1/* 2 * Marvell Wireless LAN device driver: SDIO specific definitions 3 * 4 * Copyright (C) 2011-2014, Marvell International Ltd. 5 * 6 * This software file (the "File") is distributed by Marvell International 7 * Ltd. under the terms of the GNU General Public License Version 2, June 1991 8 * (the "License"). You may use, redistribute and/or modify this File in 9 * accordance with the terms and conditions of the License, a copy of which 10 * is available by writing to the Free Software Foundation, Inc., 11 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the 12 * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt. 13 * 14 * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 16 * ARE EXPRESSLY DISCLAIMED. The License provides additional details about 17 * this warranty disclaimer. 18 */ 19 20#ifndef _MWIFIEX_SDIO_H 21#define _MWIFIEX_SDIO_H 22 23 24#include <linux/mmc/sdio.h> 25#include <linux/mmc/sdio_ids.h> 26#include <linux/mmc/sdio_func.h> 27#include <linux/mmc/card.h> 28#include <linux/mmc/host.h> 29 30#include "main.h" 31 32#define SD8786_DEFAULT_FW_NAME "mrvl/sd8786_uapsta.bin" 33#define SD8787_DEFAULT_FW_NAME "mrvl/sd8787_uapsta.bin" 34#define SD8797_DEFAULT_FW_NAME "mrvl/sd8797_uapsta.bin" 35#define SD8897_DEFAULT_FW_NAME "mrvl/sd8897_uapsta.bin" 36#define SD8887_DEFAULT_FW_NAME "mrvl/sd8887_uapsta.bin" 37#define SD8801_DEFAULT_FW_NAME "mrvl/sd8801_uapsta.bin" 38 39#define BLOCK_MODE 1 40#define BYTE_MODE 0 41 42#define REG_PORT 0 43 44#define MWIFIEX_SDIO_IO_PORT_MASK 0xfffff 45 46#define MWIFIEX_SDIO_BYTE_MODE_MASK 0x80000000 47 48#define MWIFIEX_MAX_FUNC2_REG_NUM 13 49#define MWIFIEX_SDIO_SCRATCH_SIZE 10 50 51#define SDIO_MPA_ADDR_BASE 0x1000 52#define CTRL_PORT 0 53#define CTRL_PORT_MASK 0x0001 54 55#define CMD_PORT_UPLD_INT_MASK (0x1U<<6) 56#define CMD_PORT_DNLD_INT_MASK (0x1U<<7) 57#define HOST_TERM_CMD53 (0x1U << 2) 58#define REG_PORT 0 59#define MEM_PORT 0x10000 60 61#define CMD53_NEW_MODE (0x1U << 0) 62#define CMD_PORT_RD_LEN_EN (0x1U << 2) 63#define CMD_PORT_AUTO_EN (0x1U << 0) 64#define CMD_PORT_SLCT 0x8000 65#define UP_LD_CMD_PORT_HOST_INT_STATUS (0x40U) 66#define DN_LD_CMD_PORT_HOST_INT_STATUS (0x80U) 67 68#define MWIFIEX_MP_AGGR_BUF_SIZE_16K (16384) 69#define MWIFIEX_MP_AGGR_BUF_SIZE_32K (32768) 70/* we leave one block of 256 bytes for DMA alignment*/ 71#define MWIFIEX_MP_AGGR_BUF_SIZE_MAX (65280) 72 73/* Misc. Config Register : Auto Re-enable interrupts */ 74#define AUTO_RE_ENABLE_INT BIT(4) 75 76/* Host Control Registers : Configuration */ 77#define CONFIGURATION_REG 0x00 78/* Host Control Registers : Host power up */ 79#define HOST_POWER_UP (0x1U << 1) 80 81/* Host Control Registers : Upload host interrupt mask */ 82#define UP_LD_HOST_INT_MASK (0x1U) 83/* Host Control Registers : Download host interrupt mask */ 84#define DN_LD_HOST_INT_MASK (0x2U) 85 86/* Host Control Registers : Upload host interrupt status */ 87#define UP_LD_HOST_INT_STATUS (0x1U) 88/* Host Control Registers : Download host interrupt status */ 89#define DN_LD_HOST_INT_STATUS (0x2U) 90 91/* Host Control Registers : Host interrupt status */ 92#define CARD_INT_STATUS_REG 0x28 93 94/* Card Control Registers : Card I/O ready */ 95#define CARD_IO_READY (0x1U << 3) 96/* Card Control Registers : Download card ready */ 97#define DN_LD_CARD_RDY (0x1U << 0) 98 99/* Max retry number of CMD53 write */ 100#define MAX_WRITE_IOMEM_RETRY 2 101 102/* SDIO Tx aggregation in progress ? */ 103#define MP_TX_AGGR_IN_PROGRESS(a) (a->mpa_tx.pkt_cnt > 0) 104 105/* SDIO Tx aggregation buffer room for next packet ? */ 106#define MP_TX_AGGR_BUF_HAS_ROOM(a, len) ((a->mpa_tx.buf_len+len) \ 107 <= a->mpa_tx.buf_size) 108 109/* Copy current packet (SDIO Tx aggregation buffer) to SDIO buffer */ 110#define MP_TX_AGGR_BUF_PUT(a, payload, pkt_len, port) do { \ 111 memmove(&a->mpa_tx.buf[a->mpa_tx.buf_len], \ 112 payload, pkt_len); \ 113 a->mpa_tx.buf_len += pkt_len; \ 114 if (!a->mpa_tx.pkt_cnt) \ 115 a->mpa_tx.start_port = port; \ 116 if (a->mpa_tx.start_port <= port) \ 117 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt)); \ 118 else \ 119 a->mpa_tx.ports |= (1<<(a->mpa_tx.pkt_cnt+1+ \ 120 (a->max_ports - \ 121 a->mp_end_port))); \ 122 a->mpa_tx.pkt_cnt++; \ 123} while (0) 124 125/* SDIO Tx aggregation limit ? */ 126#define MP_TX_AGGR_PKT_LIMIT_REACHED(a) \ 127 (a->mpa_tx.pkt_cnt == a->mpa_tx.pkt_aggr_limit) 128 129/* Reset SDIO Tx aggregation buffer parameters */ 130#define MP_TX_AGGR_BUF_RESET(a) do { \ 131 a->mpa_tx.pkt_cnt = 0; \ 132 a->mpa_tx.buf_len = 0; \ 133 a->mpa_tx.ports = 0; \ 134 a->mpa_tx.start_port = 0; \ 135} while (0) 136 137/* SDIO Rx aggregation limit ? */ 138#define MP_RX_AGGR_PKT_LIMIT_REACHED(a) \ 139 (a->mpa_rx.pkt_cnt == a->mpa_rx.pkt_aggr_limit) 140 141/* SDIO Rx aggregation in progress ? */ 142#define MP_RX_AGGR_IN_PROGRESS(a) (a->mpa_rx.pkt_cnt > 0) 143 144/* SDIO Rx aggregation buffer room for next packet ? */ 145#define MP_RX_AGGR_BUF_HAS_ROOM(a, rx_len) \ 146 ((a->mpa_rx.buf_len+rx_len) <= a->mpa_rx.buf_size) 147 148/* Reset SDIO Rx aggregation buffer parameters */ 149#define MP_RX_AGGR_BUF_RESET(a) do { \ 150 a->mpa_rx.pkt_cnt = 0; \ 151 a->mpa_rx.buf_len = 0; \ 152 a->mpa_rx.ports = 0; \ 153 a->mpa_rx.start_port = 0; \ 154} while (0) 155 156/* data structure for SDIO MPA TX */ 157struct mwifiex_sdio_mpa_tx { 158 /* multiport tx aggregation buffer pointer */ 159 u8 *buf; 160 u32 buf_len; 161 u32 pkt_cnt; 162 u32 ports; 163 u16 start_port; 164 u8 enabled; 165 u32 buf_size; 166 u32 pkt_aggr_limit; 167}; 168 169struct mwifiex_sdio_mpa_rx { 170 u8 *buf; 171 u32 buf_len; 172 u32 pkt_cnt; 173 u32 ports; 174 u16 start_port; 175 176 struct sk_buff **skb_arr; 177 u32 *len_arr; 178 179 u8 enabled; 180 u32 buf_size; 181 u32 pkt_aggr_limit; 182}; 183 184int mwifiex_bus_register(void); 185void mwifiex_bus_unregister(void); 186 187struct mwifiex_sdio_card_reg { 188 u8 start_rd_port; 189 u8 start_wr_port; 190 u8 base_0_reg; 191 u8 base_1_reg; 192 u8 poll_reg; 193 u8 host_int_enable; 194 u8 host_int_rsr_reg; 195 u8 host_int_status_reg; 196 u8 host_int_mask_reg; 197 u8 status_reg_0; 198 u8 status_reg_1; 199 u8 sdio_int_mask; 200 u32 data_port_mask; 201 u8 io_port_0_reg; 202 u8 io_port_1_reg; 203 u8 io_port_2_reg; 204 u8 max_mp_regs; 205 u8 rd_bitmap_l; 206 u8 rd_bitmap_u; 207 u8 rd_bitmap_1l; 208 u8 rd_bitmap_1u; 209 u8 wr_bitmap_l; 210 u8 wr_bitmap_u; 211 u8 wr_bitmap_1l; 212 u8 wr_bitmap_1u; 213 u8 rd_len_p0_l; 214 u8 rd_len_p0_u; 215 u8 card_misc_cfg_reg; 216 u8 card_cfg_2_1_reg; 217 u8 cmd_rd_len_0; 218 u8 cmd_rd_len_1; 219 u8 cmd_rd_len_2; 220 u8 cmd_rd_len_3; 221 u8 cmd_cfg_0; 222 u8 cmd_cfg_1; 223 u8 cmd_cfg_2; 224 u8 cmd_cfg_3; 225 u8 fw_dump_ctrl; 226 u8 fw_dump_start; 227 u8 fw_dump_end; 228 u8 func1_dump_reg_start; 229 u8 func1_dump_reg_end; 230 u8 func1_scratch_reg; 231 u8 func1_spec_reg_num; 232 u8 func1_spec_reg_table[MWIFIEX_MAX_FUNC2_REG_NUM]; 233}; 234 235struct sdio_mmc_card { 236 struct sdio_func *func; 237 struct mwifiex_adapter *adapter; 238 239 const char *firmware; 240 const struct mwifiex_sdio_card_reg *reg; 241 u8 max_ports; 242 u8 mp_agg_pkt_limit; 243 u16 tx_buf_size; 244 u32 mp_tx_agg_buf_size; 245 u32 mp_rx_agg_buf_size; 246 247 u32 mp_rd_bitmap; 248 u32 mp_wr_bitmap; 249 250 u16 mp_end_port; 251 u32 mp_data_port_mask; 252 253 u8 curr_rd_port; 254 u8 curr_wr_port; 255 256 u8 *mp_regs; 257 bool supports_sdio_new_mode; 258 bool has_control_mask; 259 bool can_dump_fw; 260 bool can_auto_tdls; 261 bool can_ext_scan; 262 263 struct mwifiex_sdio_mpa_tx mpa_tx; 264 struct mwifiex_sdio_mpa_rx mpa_rx; 265}; 266 267struct mwifiex_sdio_device { 268 const char *firmware; 269 const struct mwifiex_sdio_card_reg *reg; 270 u8 max_ports; 271 u8 mp_agg_pkt_limit; 272 u16 tx_buf_size; 273 u32 mp_tx_agg_buf_size; 274 u32 mp_rx_agg_buf_size; 275 bool supports_sdio_new_mode; 276 bool has_control_mask; 277 bool can_dump_fw; 278 bool can_auto_tdls; 279 bool can_ext_scan; 280}; 281 282static const struct mwifiex_sdio_card_reg mwifiex_reg_sd87xx = { 283 .start_rd_port = 1, 284 .start_wr_port = 1, 285 .base_0_reg = 0x0040, 286 .base_1_reg = 0x0041, 287 .poll_reg = 0x30, 288 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK, 289 .host_int_rsr_reg = 0x1, 290 .host_int_mask_reg = 0x02, 291 .host_int_status_reg = 0x03, 292 .status_reg_0 = 0x60, 293 .status_reg_1 = 0x61, 294 .sdio_int_mask = 0x3f, 295 .data_port_mask = 0x0000fffe, 296 .io_port_0_reg = 0x78, 297 .io_port_1_reg = 0x79, 298 .io_port_2_reg = 0x7A, 299 .max_mp_regs = 64, 300 .rd_bitmap_l = 0x04, 301 .rd_bitmap_u = 0x05, 302 .wr_bitmap_l = 0x06, 303 .wr_bitmap_u = 0x07, 304 .rd_len_p0_l = 0x08, 305 .rd_len_p0_u = 0x09, 306 .card_misc_cfg_reg = 0x6c, 307 .func1_dump_reg_start = 0x0, 308 .func1_dump_reg_end = 0x9, 309 .func1_scratch_reg = 0x60, 310 .func1_spec_reg_num = 5, 311 .func1_spec_reg_table = {0x28, 0x30, 0x34, 0x38, 0x3c}, 312}; 313 314static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8897 = { 315 .start_rd_port = 0, 316 .start_wr_port = 0, 317 .base_0_reg = 0x60, 318 .base_1_reg = 0x61, 319 .poll_reg = 0x50, 320 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 321 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 322 .host_int_rsr_reg = 0x1, 323 .host_int_status_reg = 0x03, 324 .host_int_mask_reg = 0x02, 325 .status_reg_0 = 0xc0, 326 .status_reg_1 = 0xc1, 327 .sdio_int_mask = 0xff, 328 .data_port_mask = 0xffffffff, 329 .io_port_0_reg = 0xD8, 330 .io_port_1_reg = 0xD9, 331 .io_port_2_reg = 0xDA, 332 .max_mp_regs = 184, 333 .rd_bitmap_l = 0x04, 334 .rd_bitmap_u = 0x05, 335 .rd_bitmap_1l = 0x06, 336 .rd_bitmap_1u = 0x07, 337 .wr_bitmap_l = 0x08, 338 .wr_bitmap_u = 0x09, 339 .wr_bitmap_1l = 0x0a, 340 .wr_bitmap_1u = 0x0b, 341 .rd_len_p0_l = 0x0c, 342 .rd_len_p0_u = 0x0d, 343 .card_misc_cfg_reg = 0xcc, 344 .card_cfg_2_1_reg = 0xcd, 345 .cmd_rd_len_0 = 0xb4, 346 .cmd_rd_len_1 = 0xb5, 347 .cmd_rd_len_2 = 0xb6, 348 .cmd_rd_len_3 = 0xb7, 349 .cmd_cfg_0 = 0xb8, 350 .cmd_cfg_1 = 0xb9, 351 .cmd_cfg_2 = 0xba, 352 .cmd_cfg_3 = 0xbb, 353 .fw_dump_ctrl = 0xe2, 354 .fw_dump_start = 0xe3, 355 .fw_dump_end = 0xea, 356 .func1_dump_reg_start = 0x0, 357 .func1_dump_reg_end = 0xb, 358 .func1_scratch_reg = 0xc0, 359 .func1_spec_reg_num = 8, 360 .func1_spec_reg_table = {0x4C, 0x50, 0x54, 0x55, 0x58, 361 0x59, 0x5c, 0x5d}, 362}; 363 364static const struct mwifiex_sdio_card_reg mwifiex_reg_sd8887 = { 365 .start_rd_port = 0, 366 .start_wr_port = 0, 367 .base_0_reg = 0x6C, 368 .base_1_reg = 0x6D, 369 .poll_reg = 0x5C, 370 .host_int_enable = UP_LD_HOST_INT_MASK | DN_LD_HOST_INT_MASK | 371 CMD_PORT_UPLD_INT_MASK | CMD_PORT_DNLD_INT_MASK, 372 .host_int_rsr_reg = 0x4, 373 .host_int_status_reg = 0x0C, 374 .host_int_mask_reg = 0x08, 375 .status_reg_0 = 0x90, 376 .status_reg_1 = 0x91, 377 .sdio_int_mask = 0xff, 378 .data_port_mask = 0xffffffff, 379 .io_port_0_reg = 0xE4, 380 .io_port_1_reg = 0xE5, 381 .io_port_2_reg = 0xE6, 382 .max_mp_regs = 196, 383 .rd_bitmap_l = 0x10, 384 .rd_bitmap_u = 0x11, 385 .rd_bitmap_1l = 0x12, 386 .rd_bitmap_1u = 0x13, 387 .wr_bitmap_l = 0x14, 388 .wr_bitmap_u = 0x15, 389 .wr_bitmap_1l = 0x16, 390 .wr_bitmap_1u = 0x17, 391 .rd_len_p0_l = 0x18, 392 .rd_len_p0_u = 0x19, 393 .card_misc_cfg_reg = 0xd8, 394 .card_cfg_2_1_reg = 0xd9, 395 .cmd_rd_len_0 = 0xc0, 396 .cmd_rd_len_1 = 0xc1, 397 .cmd_rd_len_2 = 0xc2, 398 .cmd_rd_len_3 = 0xc3, 399 .cmd_cfg_0 = 0xc4, 400 .cmd_cfg_1 = 0xc5, 401 .cmd_cfg_2 = 0xc6, 402 .cmd_cfg_3 = 0xc7, 403 .func1_dump_reg_start = 0x10, 404 .func1_dump_reg_end = 0x17, 405 .func1_scratch_reg = 0x90, 406 .func1_spec_reg_num = 13, 407 .func1_spec_reg_table = {0x08, 0x58, 0x5C, 0x5D, 0x60, 408 0x61, 0x62, 0x64, 0x65, 0x66, 409 0x68, 0x69, 0x6a}, 410}; 411 412static const struct mwifiex_sdio_device mwifiex_sdio_sd8786 = { 413 .firmware = SD8786_DEFAULT_FW_NAME, 414 .reg = &mwifiex_reg_sd87xx, 415 .max_ports = 16, 416 .mp_agg_pkt_limit = 8, 417 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 418 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 419 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 420 .supports_sdio_new_mode = false, 421 .has_control_mask = true, 422 .can_dump_fw = false, 423 .can_auto_tdls = false, 424 .can_ext_scan = false, 425}; 426 427static const struct mwifiex_sdio_device mwifiex_sdio_sd8787 = { 428 .firmware = SD8787_DEFAULT_FW_NAME, 429 .reg = &mwifiex_reg_sd87xx, 430 .max_ports = 16, 431 .mp_agg_pkt_limit = 8, 432 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 433 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 434 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 435 .supports_sdio_new_mode = false, 436 .has_control_mask = true, 437 .can_dump_fw = false, 438 .can_auto_tdls = false, 439 .can_ext_scan = true, 440}; 441 442static const struct mwifiex_sdio_device mwifiex_sdio_sd8797 = { 443 .firmware = SD8797_DEFAULT_FW_NAME, 444 .reg = &mwifiex_reg_sd87xx, 445 .max_ports = 16, 446 .mp_agg_pkt_limit = 8, 447 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 448 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 449 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 450 .supports_sdio_new_mode = false, 451 .has_control_mask = true, 452 .can_dump_fw = false, 453 .can_auto_tdls = false, 454 .can_ext_scan = true, 455}; 456 457static const struct mwifiex_sdio_device mwifiex_sdio_sd8897 = { 458 .firmware = SD8897_DEFAULT_FW_NAME, 459 .reg = &mwifiex_reg_sd8897, 460 .max_ports = 32, 461 .mp_agg_pkt_limit = 16, 462 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_4K, 463 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 464 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_MAX, 465 .supports_sdio_new_mode = true, 466 .has_control_mask = false, 467 .can_dump_fw = true, 468 .can_auto_tdls = false, 469 .can_ext_scan = true, 470}; 471 472static const struct mwifiex_sdio_device mwifiex_sdio_sd8887 = { 473 .firmware = SD8887_DEFAULT_FW_NAME, 474 .reg = &mwifiex_reg_sd8887, 475 .max_ports = 32, 476 .mp_agg_pkt_limit = 16, 477 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 478 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 479 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_32K, 480 .supports_sdio_new_mode = true, 481 .has_control_mask = false, 482 .can_dump_fw = false, 483 .can_auto_tdls = true, 484 .can_ext_scan = true, 485}; 486 487static const struct mwifiex_sdio_device mwifiex_sdio_sd8801 = { 488 .firmware = SD8801_DEFAULT_FW_NAME, 489 .reg = &mwifiex_reg_sd87xx, 490 .max_ports = 16, 491 .mp_agg_pkt_limit = 8, 492 .supports_sdio_new_mode = false, 493 .has_control_mask = true, 494 .tx_buf_size = MWIFIEX_TX_DATA_BUF_SIZE_2K, 495 .mp_tx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 496 .mp_rx_agg_buf_size = MWIFIEX_MP_AGGR_BUF_SIZE_16K, 497 .can_dump_fw = false, 498 .can_auto_tdls = false, 499 .can_ext_scan = true, 500}; 501 502/* 503 * .cmdrsp_complete handler 504 */ 505static inline int mwifiex_sdio_cmdrsp_complete(struct mwifiex_adapter *adapter, 506 struct sk_buff *skb) 507{ 508 dev_kfree_skb_any(skb); 509 return 0; 510} 511 512/* 513 * .event_complete handler 514 */ 515static inline int mwifiex_sdio_event_complete(struct mwifiex_adapter *adapter, 516 struct sk_buff *skb) 517{ 518 dev_kfree_skb_any(skb); 519 return 0; 520} 521 522static inline bool 523mp_rx_aggr_port_limit_reached(struct sdio_mmc_card *card) 524{ 525 u8 tmp; 526 527 if (card->curr_rd_port < card->mpa_rx.start_port) { 528 if (card->supports_sdio_new_mode) 529 tmp = card->mp_end_port >> 1; 530 else 531 tmp = card->mp_agg_pkt_limit; 532 533 if (((card->max_ports - card->mpa_rx.start_port) + 534 card->curr_rd_port) >= tmp) 535 return true; 536 } 537 538 if (!card->supports_sdio_new_mode) 539 return false; 540 541 if ((card->curr_rd_port - card->mpa_rx.start_port) >= 542 (card->mp_end_port >> 1)) 543 return true; 544 545 return false; 546} 547 548static inline bool 549mp_tx_aggr_port_limit_reached(struct sdio_mmc_card *card) 550{ 551 u16 tmp; 552 553 if (card->curr_wr_port < card->mpa_tx.start_port) { 554 if (card->supports_sdio_new_mode) 555 tmp = card->mp_end_port >> 1; 556 else 557 tmp = card->mp_agg_pkt_limit; 558 559 if (((card->max_ports - card->mpa_tx.start_port) + 560 card->curr_wr_port) >= tmp) 561 return true; 562 } 563 564 if (!card->supports_sdio_new_mode) 565 return false; 566 567 if ((card->curr_wr_port - card->mpa_tx.start_port) >= 568 (card->mp_end_port >> 1)) 569 return true; 570 571 return false; 572} 573 574/* Prepare to copy current packet from card to SDIO Rx aggregation buffer */ 575static inline void mp_rx_aggr_setup(struct sdio_mmc_card *card, 576 u16 rx_len, u8 port) 577{ 578 card->mpa_rx.buf_len += rx_len; 579 580 if (!card->mpa_rx.pkt_cnt) 581 card->mpa_rx.start_port = port; 582 583 if (card->supports_sdio_new_mode) { 584 card->mpa_rx.ports |= (1 << port); 585 } else { 586 if (card->mpa_rx.start_port <= port) 587 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt); 588 else 589 card->mpa_rx.ports |= 1 << (card->mpa_rx.pkt_cnt + 1); 590 } 591 card->mpa_rx.skb_arr[card->mpa_rx.pkt_cnt] = NULL; 592 card->mpa_rx.len_arr[card->mpa_rx.pkt_cnt] = rx_len; 593 card->mpa_rx.pkt_cnt++; 594} 595#endif /* _MWIFIEX_SDIO_H */ 596