1/****************************************************************************** 2 * 3 * This file is provided under a dual BSD/GPLv2 license. When using or 4 * redistributing this file, you may do so under either license. 5 * 6 * GPL LICENSE SUMMARY 7 * 8 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of version 2 of the GNU General Public License as 12 * published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but 15 * WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 22 * USA 23 * 24 * The full GNU General Public License is included in this distribution 25 * in the file called COPYING. 26 * 27 * Contact Information: 28 * Intel Linux Wireless <ilw@linux.intel.com> 29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 30 * 31 * BSD LICENSE 32 * 33 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved. 34 * All rights reserved. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 40 * * Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * * Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in 44 * the documentation and/or other materials provided with the 45 * distribution. 46 * * Neither the name Intel Corporation nor the names of its 47 * contributors may be used to endorse or promote products derived 48 * from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 *****************************************************************************/ 63#ifndef __iwl_fh_h__ 64#define __iwl_fh_h__ 65 66#include <linux/types.h> 67 68/****************************/ 69/* Flow Handler Definitions */ 70/****************************/ 71 72/** 73 * This I/O area is directly read/writable by driver (e.g. Linux uses writel()) 74 * Addresses are offsets from device's PCI hardware base address. 75 */ 76#define FH_MEM_LOWER_BOUND (0x1000) 77#define FH_MEM_UPPER_BOUND (0x2000) 78 79/** 80 * Keep-Warm (KW) buffer base address. 81 * 82 * Driver must allocate a 4KByte buffer that is for keeping the 83 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency 84 * DRAM access when doing Txing or Rxing. The dummy accesses prevent host 85 * from going into a power-savings mode that would cause higher DRAM latency, 86 * and possible data over/under-runs, before all Tx/Rx is complete. 87 * 88 * Driver loads FH_KW_MEM_ADDR_REG with the physical address (bits 35:4) 89 * of the buffer, which must be 4K aligned. Once this is set up, the device 90 * automatically invokes keep-warm accesses when normal accesses might not 91 * be sufficient to maintain fast DRAM response. 92 * 93 * Bit fields: 94 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned 95 */ 96#define FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C) 97 98 99/** 100 * TFD Circular Buffers Base (CBBC) addresses 101 * 102 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident 103 * circular buffers (CBs/queues) containing Transmit Frame Descriptors (TFDs) 104 * (see struct iwl_tfd_frame). These 16 pointer registers are offset by 0x04 105 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte 106 * aligned (address bits 0-7 must be 0). 107 * Later devices have 20 (5000 series) or 30 (higher) queues, but the registers 108 * for them are in different places. 109 * 110 * Bit fields in each pointer register: 111 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned 112 */ 113#define FH_MEM_CBBC_0_15_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 114#define FH_MEM_CBBC_0_15_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10) 115#define FH_MEM_CBBC_16_19_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBF0) 116#define FH_MEM_CBBC_16_19_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 117#define FH_MEM_CBBC_20_31_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xB20) 118#define FH_MEM_CBBC_20_31_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xB80) 119 120/* Find TFD CB base pointer for given queue */ 121static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl) 122{ 123 if (chnl < 16) 124 return FH_MEM_CBBC_0_15_LOWER_BOUND + 4 * chnl; 125 if (chnl < 20) 126 return FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16); 127 WARN_ON_ONCE(chnl >= 32); 128 return FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20); 129} 130 131 132/** 133 * Rx SRAM Control and Status Registers (RSCSR) 134 * 135 * These registers provide handshake between driver and device for the Rx queue 136 * (this queue handles *all* command responses, notifications, Rx data, etc. 137 * sent from uCode to host driver). Unlike Tx, there is only one Rx 138 * queue, and only one Rx DMA/FIFO channel. Also unlike Tx, which can 139 * concatenate up to 20 DRAM buffers to form a Tx frame, each Receive Buffer 140 * Descriptor (RBD) points to only one Rx Buffer (RB); there is a 1:1 141 * mapping between RBDs and RBs. 142 * 143 * Driver must allocate host DRAM memory for the following, and set the 144 * physical address of each into device registers: 145 * 146 * 1) Receive Buffer Descriptor (RBD) circular buffer (CB), typically with 256 147 * entries (although any power of 2, up to 4096, is selectable by driver). 148 * Each entry (1 dword) points to a receive buffer (RB) of consistent size 149 * (typically 4K, although 8K or 16K are also selectable by driver). 150 * Driver sets up RB size and number of RBDs in the CB via Rx config 151 * register FH_MEM_RCSR_CHNL0_CONFIG_REG. 152 * 153 * Bit fields within one RBD: 154 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned 155 * 156 * Driver sets physical address [35:8] of base of RBD circular buffer 157 * into FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0]. 158 * 159 * 2) Rx status buffer, 8 bytes, in which uCode indicates which Rx Buffers 160 * (RBs) have been filled, via a "write pointer", actually the index of 161 * the RB's corresponding RBD within the circular buffer. Driver sets 162 * physical address [35:4] into FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0]. 163 * 164 * Bit fields in lower dword of Rx status buffer (upper dword not used 165 * by driver: 166 * 31-12: Not used by driver 167 * 11- 0: Index of last filled Rx buffer descriptor 168 * (device writes, driver reads this value) 169 * 170 * As the driver prepares Receive Buffers (RBs) for device to fill, driver must 171 * enter pointers to these RBs into contiguous RBD circular buffer entries, 172 * and update the device's "write" index register, 173 * FH_RSCSR_CHNL0_RBDCB_WPTR_REG. 174 * 175 * This "write" index corresponds to the *next* RBD that the driver will make 176 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within 177 * the circular buffer. This value should initially be 0 (before preparing any 178 * RBs), should be 8 after preparing the first 8 RBs (for example), and must 179 * wrap back to 0 at the end of the circular buffer (but don't wrap before 180 * "read" index has advanced past 1! See below). 181 * NOTE: DEVICE EXPECTS THE WRITE INDEX TO BE INCREMENTED IN MULTIPLES OF 8. 182 * 183 * As the device fills RBs (referenced from contiguous RBDs within the circular 184 * buffer), it updates the Rx status buffer in host DRAM, 2) described above, 185 * to tell the driver the index of the latest filled RBD. The driver must 186 * read this "read" index from DRAM after receiving an Rx interrupt from device 187 * 188 * The driver must also internally keep track of a third index, which is the 189 * next RBD to process. When receiving an Rx interrupt, driver should process 190 * all filled but unprocessed RBs up to, but not including, the RB 191 * corresponding to the "read" index. For example, if "read" index becomes "1", 192 * driver may process the RB pointed to by RBD 0. Depending on volume of 193 * traffic, there may be many RBs to process. 194 * 195 * If read index == write index, device thinks there is no room to put new data. 196 * Due to this, the maximum number of filled RBs is 255, instead of 256. To 197 * be safe, make sure that there is a gap of at least 2 RBDs between "write" 198 * and "read" indexes; that is, make sure that there are no more than 254 199 * buffers waiting to be filled. 200 */ 201#define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0) 202#define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 203#define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND) 204 205/** 206 * Physical base address of 8-byte Rx Status buffer. 207 * Bit fields: 208 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned. 209 */ 210#define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0) 211 212/** 213 * Physical base address of Rx Buffer Descriptor Circular Buffer. 214 * Bit fields: 215 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned. 216 */ 217#define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004) 218 219/** 220 * Rx write pointer (index, really!). 221 * Bit fields: 222 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1. 223 * NOTE: For 256-entry circular buffer, use only bits [7:0]. 224 */ 225#define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008) 226#define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG) 227 228#define FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x00c) 229#define FH_RSCSR_CHNL0_RDPTR FW_RSCSR_CHNL0_RXDCB_RDPTR_REG 230 231/** 232 * Rx Config/Status Registers (RCSR) 233 * Rx Config Reg for channel 0 (only channel used) 234 * 235 * Driver must initialize FH_MEM_RCSR_CHNL0_CONFIG_REG as follows for 236 * normal operation (see bit fields). 237 * 238 * Clearing FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA. 239 * Driver should poll FH_MEM_RSSR_RX_STATUS_REG for 240 * FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (bit 24) before continuing. 241 * 242 * Bit fields: 243 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame, 244 * '10' operate normally 245 * 29-24: reserved 246 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal), 247 * min "5" for 32 RBDs, max "12" for 4096 RBDs. 248 * 19-18: reserved 249 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K, 250 * '10' 12K, '11' 16K. 251 * 15-14: reserved 252 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation) 253 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec) 254 * typical value 0x10 (about 1/2 msec) 255 * 3- 0: reserved 256 */ 257#define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00) 258#define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0) 259#define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND) 260 261#define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0) 262#define FH_MEM_RCSR_CHNL0_RBDCB_WPTR (FH_MEM_RCSR_CHNL0 + 0x8) 263#define FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (FH_MEM_RCSR_CHNL0 + 0x10) 264 265#define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */ 266#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */ 267#define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */ 268#define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */ 269#define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */ 270#define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/ 271 272#define FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20) 273#define FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4) 274#define RX_RB_TIMEOUT (0x11) 275 276#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000) 277#define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000) 278#define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000) 279 280#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000) 281#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000) 282#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000) 283#define FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000) 284 285#define FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004) 286#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000) 287#define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000) 288 289/** 290 * Rx Shared Status Registers (RSSR) 291 * 292 * After stopping Rx DMA channel (writing 0 to 293 * FH_MEM_RCSR_CHNL0_CONFIG_REG), driver must poll 294 * FH_MEM_RSSR_RX_STATUS_REG until Rx channel is idle. 295 * 296 * Bit fields: 297 * 24: 1 = Channel 0 is idle 298 * 299 * FH_MEM_RSSR_SHARED_CTRL_REG and FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV 300 * contain default values that should not be altered by the driver. 301 */ 302#define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40) 303#define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 304 305#define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND) 306#define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004) 307#define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\ 308 (FH_MEM_RSSR_LOWER_BOUND + 0x008) 309 310#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000) 311 312#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28 313#define FH_MEM_TB_MAX_LENGTH (0x00020000) 314 315/* TFDB Area - TFDs buffer table */ 316#define FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF) 317#define FH_TFDIB_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x900) 318#define FH_TFDIB_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x958) 319#define FH_TFDIB_CTRL0_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl)) 320#define FH_TFDIB_CTRL1_REG(_chnl) (FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4) 321 322/** 323 * Transmit DMA Channel Control/Status Registers (TCSR) 324 * 325 * Device has one configuration register for each of 8 Tx DMA/FIFO channels 326 * supported in hardware (don't confuse these with the 16 Tx queues in DRAM, 327 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes. 328 * 329 * To use a Tx DMA channel, driver must initialize its 330 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl) with: 331 * 332 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 333 * FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL 334 * 335 * All other bits should be 0. 336 * 337 * Bit fields: 338 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame, 339 * '10' operate normally 340 * 29- 4: Reserved, set to "0" 341 * 3: Enable internal DMA requests (1, normal operation), disable (0) 342 * 2- 0: Reserved, set to "0" 343 */ 344#define FH_TCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xD00) 345#define FH_TCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xE60) 346 347/* Find Control/Status reg for given Tx DMA/FIFO channel */ 348#define FH_TCSR_CHNL_NUM (8) 349 350/* TCSR: tx_config register values */ 351#define FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \ 352 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl)) 353#define FH_TCSR_CHNL_TX_CREDIT_REG(_chnl) \ 354 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4) 355#define FH_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \ 356 (FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8) 357 358#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000) 359#define FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001) 360 361#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000) 362#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008) 363 364#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000) 365#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000) 366#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000) 367 368#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000) 369#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000) 370#define FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000) 371 372#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000) 373#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000) 374#define FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000) 375 376#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000) 377#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000) 378#define FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003) 379 380#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20) 381#define FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12) 382 383/** 384 * Tx Shared Status Registers (TSSR) 385 * 386 * After stopping Tx DMA channel (writing 0 to 387 * FH_TCSR_CHNL_TX_CONFIG_REG(chnl)), driver must poll 388 * FH_TSSR_TX_STATUS_REG until selected Tx channel is idle 389 * (channel's buffers empty | no pending requests). 390 * 391 * Bit fields: 392 * 31-24: 1 = Channel buffers empty (channel 7:0) 393 * 23-16: 1 = No pending requests (channel 7:0) 394 */ 395#define FH_TSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xEA0) 396#define FH_TSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xEC0) 397 398#define FH_TSSR_TX_STATUS_REG (FH_TSSR_LOWER_BOUND + 0x010) 399 400/** 401 * Bit fields for TSSR(Tx Shared Status & Control) error status register: 402 * 31: Indicates an address error when accessed to internal memory 403 * uCode/driver must write "1" in order to clear this flag 404 * 30: Indicates that Host did not send the expected number of dwords to FH 405 * uCode/driver must write "1" in order to clear this flag 406 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA 407 * command was received from the scheduler while the TRB was already full 408 * with previous command 409 * uCode/driver must write "1" in order to clear this flag 410 * 7-0: Each status bit indicates a channel's TxCredit error. When an error 411 * bit is set, it indicates that the FH has received a full indication 412 * from the RTC TxFIFO and the current value of the TxCredit counter was 413 * not equal to zero. This mean that the credit mechanism was not 414 * synchronized to the TxFIFO status 415 * uCode/driver must write "1" in order to clear this flag 416 */ 417#define FH_TSSR_TX_ERROR_REG (FH_TSSR_LOWER_BOUND + 0x018) 418#define FH_TSSR_TX_MSG_CONFIG_REG (FH_TSSR_LOWER_BOUND + 0x008) 419 420#define FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16) 421 422/* Tx service channels */ 423#define FH_SRVC_CHNL (9) 424#define FH_SRVC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9C8) 425#define FH_SRVC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0) 426#define FH_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \ 427 (FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4) 428 429#define FH_TX_CHICKEN_BITS_REG (FH_MEM_LOWER_BOUND + 0xE98) 430#define FH_TX_TRB_REG(_chan) (FH_MEM_LOWER_BOUND + 0x958 + (_chan) * 4) 431 432/* Instruct FH to increment the retry count of a packet when 433 * it is brought from the memory to TX-FIFO 434 */ 435#define FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002) 436 437#define RX_QUEUE_SIZE 256 438#define RX_QUEUE_MASK 255 439#define RX_QUEUE_SIZE_LOG 8 440 441/* 442 * RX related structures and functions 443 */ 444#define RX_FREE_BUFFERS 64 445#define RX_LOW_WATERMARK 8 446 447/** 448 * struct iwl_rb_status - reserve buffer status 449 * host memory mapped FH registers 450 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed 451 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed 452 * @finished_rb_num [0:11] - Indicates the index of the current RB 453 * in which the last frame was written to 454 * @finished_fr_num [0:11] - Indicates the index of the RX Frame 455 * which was transferred 456 */ 457struct iwl_rb_status { 458 __le16 closed_rb_num; 459 __le16 closed_fr_num; 460 __le16 finished_rb_num; 461 __le16 finished_fr_nam; 462 __le32 __unused; 463} __packed; 464 465 466#define TFD_QUEUE_SIZE_MAX (256) 467#define TFD_QUEUE_SIZE_BC_DUP (64) 468#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP) 469#define IWL_TX_DMA_MASK DMA_BIT_MASK(36) 470#define IWL_NUM_OF_TBS 20 471 472static inline u8 iwl_get_dma_hi_addr(dma_addr_t addr) 473{ 474 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF; 475} 476/** 477 * struct iwl_tfd_tb transmit buffer descriptor within transmit frame descriptor 478 * 479 * This structure contains dma address and length of transmission address 480 * 481 * @lo: low [31:0] portion of the dma address of TX buffer 482 * every even is unaligned on 16 bit boundary 483 * @hi_n_len 0-3 [35:32] portion of dma 484 * 4-15 length of the tx buffer 485 */ 486struct iwl_tfd_tb { 487 __le32 lo; 488 __le16 hi_n_len; 489} __packed; 490 491/** 492 * struct iwl_tfd 493 * 494 * Transmit Frame Descriptor (TFD) 495 * 496 * @ __reserved1[3] reserved 497 * @ num_tbs 0-4 number of active tbs 498 * 5 reserved 499 * 6-7 padding (not used) 500 * @ tbs[20] transmit frame buffer descriptors 501 * @ __pad padding 502 * 503 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM. 504 * Both driver and device share these circular buffers, each of which must be 505 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes 506 * 507 * Driver must indicate the physical address of the base of each 508 * circular buffer via the FH_MEM_CBBC_QUEUE registers. 509 * 510 * Each TFD contains pointer/size information for up to 20 data buffers 511 * in host DRAM. These buffers collectively contain the (one) frame described 512 * by the TFD. Each buffer must be a single contiguous block of memory within 513 * itself, but buffers may be scattered in host DRAM. Each buffer has max size 514 * of (4K - 4). The concatenates all of a TFD's buffers into a single 515 * Tx frame, up to 8 KBytes in size. 516 * 517 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx. 518 */ 519struct iwl_tfd { 520 u8 __reserved1[3]; 521 u8 num_tbs; 522 struct iwl_tfd_tb tbs[IWL_NUM_OF_TBS]; 523 __le32 __pad; 524} __packed; 525 526/* Keep Warm Size */ 527#define IWL_KW_SIZE 0x1000 /* 4k */ 528 529/* Fixed (non-configurable) rx data from phy */ 530 531/** 532 * struct iwlagn_schedq_bc_tbl scheduler byte count table 533 * base physical address provided by SCD_DRAM_BASE_ADDR 534 * @tfd_offset 0-12 - tx command byte count 535 * 12-16 - station index 536 */ 537struct iwlagn_scd_bc_tbl { 538 __le16 tfd_offset[TFD_QUEUE_BC_SIZE]; 539} __packed; 540 541#endif /* !__iwl_fh_h__ */ 542