1/* 2 3 Broadcom B43 wireless driver 4 IEEE 802.11n PHY support 5 6 Copyright (c) 2008 Michael Buesch <m@bues.ch> 7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com> 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 2 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program; see the file COPYING. If not, write to 21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, 22 Boston, MA 02110-1301, USA. 23 24*/ 25 26#include <linux/delay.h> 27#include <linux/slab.h> 28#include <linux/types.h> 29 30#include "b43.h" 31#include "phy_n.h" 32#include "tables_nphy.h" 33#include "radio_2055.h" 34#include "radio_2056.h" 35#include "radio_2057.h" 36#include "main.h" 37#include "ppr.h" 38 39struct nphy_txgains { 40 u16 tx_lpf[2]; 41 u16 txgm[2]; 42 u16 pga[2]; 43 u16 pad[2]; 44 u16 ipa[2]; 45}; 46 47struct nphy_iqcal_params { 48 u16 tx_lpf; 49 u16 txgm; 50 u16 pga; 51 u16 pad; 52 u16 ipa; 53 u16 cal_gain; 54 u16 ncorr[5]; 55}; 56 57struct nphy_iq_est { 58 s32 iq0_prod; 59 u32 i0_pwr; 60 u32 q0_pwr; 61 s32 iq1_prod; 62 u32 i1_pwr; 63 u32 q1_pwr; 64}; 65 66enum b43_nphy_rf_sequence { 67 B43_RFSEQ_RX2TX, 68 B43_RFSEQ_TX2RX, 69 B43_RFSEQ_RESET2RX, 70 B43_RFSEQ_UPDATE_GAINH, 71 B43_RFSEQ_UPDATE_GAINL, 72 B43_RFSEQ_UPDATE_GAINU, 73}; 74 75enum n_rf_ctl_over_cmd { 76 N_RF_CTL_OVER_CMD_RXRF_PU = 0, 77 N_RF_CTL_OVER_CMD_RX_PU = 1, 78 N_RF_CTL_OVER_CMD_TX_PU = 2, 79 N_RF_CTL_OVER_CMD_RX_GAIN = 3, 80 N_RF_CTL_OVER_CMD_TX_GAIN = 4, 81}; 82 83enum n_intc_override { 84 N_INTC_OVERRIDE_OFF = 0, 85 N_INTC_OVERRIDE_TRSW = 1, 86 N_INTC_OVERRIDE_PA = 2, 87 N_INTC_OVERRIDE_EXT_LNA_PU = 3, 88 N_INTC_OVERRIDE_EXT_LNA_GAIN = 4, 89}; 90 91enum n_rssi_type { 92 N_RSSI_W1 = 0, 93 N_RSSI_W2, 94 N_RSSI_NB, 95 N_RSSI_IQ, 96 N_RSSI_TSSI_2G, 97 N_RSSI_TSSI_5G, 98 N_RSSI_TBD, 99}; 100 101enum n_rail_type { 102 N_RAIL_I = 0, 103 N_RAIL_Q = 1, 104}; 105 106static inline bool b43_nphy_ipa(struct b43_wldev *dev) 107{ 108 enum ieee80211_band band = b43_current_band(dev->wl); 109 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) || 110 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ)); 111} 112 113/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */ 114static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev) 115{ 116 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >> 117 B43_NPHY_RFSEQCA_RXEN_SHIFT; 118} 119 120/************************************************** 121 * RF (just without b43_nphy_rf_ctl_intc_override) 122 **************************************************/ 123 124/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ 125static void b43_nphy_force_rf_sequence(struct b43_wldev *dev, 126 enum b43_nphy_rf_sequence seq) 127{ 128 static const u16 trigger[] = { 129 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX, 130 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX, 131 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX, 132 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH, 133 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL, 134 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU, 135 }; 136 int i; 137 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 138 139 B43_WARN_ON(seq >= ARRAY_SIZE(trigger)); 140 141 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 142 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER); 143 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]); 144 for (i = 0; i < 200; i++) { 145 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq])) 146 goto ok; 147 msleep(1); 148 } 149 b43err(dev->wl, "RF sequence status timeout\n"); 150ok: 151 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 152} 153 154static void b43_nphy_rf_ctl_override_rev19(struct b43_wldev *dev, u16 field, 155 u16 value, u8 core, bool off, 156 u8 override_id) 157{ 158 /* TODO */ 159} 160 161/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ 162static void b43_nphy_rf_ctl_override_rev7(struct b43_wldev *dev, u16 field, 163 u16 value, u8 core, bool off, 164 u8 override) 165{ 166 struct b43_phy *phy = &dev->phy; 167 const struct nphy_rf_control_override_rev7 *e; 168 u16 en_addrs[3][2] = { 169 { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 } 170 }; 171 u16 en_addr; 172 u16 en_mask = field; 173 u16 val_addr; 174 u8 i; 175 176 if (phy->rev >= 19 || phy->rev < 3) { 177 B43_WARN_ON(1); 178 return; 179 } 180 181 /* Remember: we can get NULL! */ 182 e = b43_nphy_get_rf_ctl_over_rev7(dev, field, override); 183 184 for (i = 0; i < 2; i++) { 185 if (override >= ARRAY_SIZE(en_addrs)) { 186 b43err(dev->wl, "Invalid override value %d\n", override); 187 return; 188 } 189 en_addr = en_addrs[override][i]; 190 191 if (e) 192 val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1; 193 194 if (off) { 195 b43_phy_mask(dev, en_addr, ~en_mask); 196 if (e) /* Do it safer, better than wl */ 197 b43_phy_mask(dev, val_addr, ~e->val_mask); 198 } else { 199 if (!core || (core & (1 << i))) { 200 b43_phy_set(dev, en_addr, en_mask); 201 if (e) 202 b43_phy_maskset(dev, val_addr, ~e->val_mask, (value << e->val_shift)); 203 } 204 } 205 } 206} 207 208/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */ 209static void b43_nphy_rf_ctl_override_one_to_many(struct b43_wldev *dev, 210 enum n_rf_ctl_over_cmd cmd, 211 u16 value, u8 core, bool off) 212{ 213 struct b43_phy *phy = &dev->phy; 214 u16 tmp; 215 216 B43_WARN_ON(phy->rev < 7); 217 218 switch (cmd) { 219 case N_RF_CTL_OVER_CMD_RXRF_PU: 220 b43_nphy_rf_ctl_override_rev7(dev, 0x20, value, core, off, 1); 221 b43_nphy_rf_ctl_override_rev7(dev, 0x10, value, core, off, 1); 222 b43_nphy_rf_ctl_override_rev7(dev, 0x08, value, core, off, 1); 223 break; 224 case N_RF_CTL_OVER_CMD_RX_PU: 225 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 1); 226 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); 227 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 1); 228 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 2); 229 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 0, core, off, 1); 230 break; 231 case N_RF_CTL_OVER_CMD_TX_PU: 232 b43_nphy_rf_ctl_override_rev7(dev, 0x4, value, core, off, 0); 233 b43_nphy_rf_ctl_override_rev7(dev, 0x2, value, core, off, 1); 234 b43_nphy_rf_ctl_override_rev7(dev, 0x1, value, core, off, 2); 235 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, 1, core, off, 1); 236 break; 237 case N_RF_CTL_OVER_CMD_RX_GAIN: 238 tmp = value & 0xFF; 239 b43_nphy_rf_ctl_override_rev7(dev, 0x0800, tmp, core, off, 0); 240 tmp = value >> 8; 241 b43_nphy_rf_ctl_override_rev7(dev, 0x6000, tmp, core, off, 0); 242 break; 243 case N_RF_CTL_OVER_CMD_TX_GAIN: 244 tmp = value & 0x7FFF; 245 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, tmp, core, off, 0); 246 tmp = value >> 14; 247 b43_nphy_rf_ctl_override_rev7(dev, 0x4000, tmp, core, off, 0); 248 break; 249 } 250} 251 252/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ 253static void b43_nphy_rf_ctl_override(struct b43_wldev *dev, u16 field, 254 u16 value, u8 core, bool off) 255{ 256 int i; 257 u8 index = fls(field); 258 u8 addr, en_addr, val_addr; 259 /* we expect only one bit set */ 260 B43_WARN_ON(field & (~(1 << (index - 1)))); 261 262 if (dev->phy.rev >= 3) { 263 const struct nphy_rf_control_override_rev3 *rf_ctrl; 264 for (i = 0; i < 2; i++) { 265 if (index == 0 || index == 16) { 266 b43err(dev->wl, 267 "Unsupported RF Ctrl Override call\n"); 268 return; 269 } 270 271 rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; 272 en_addr = B43_PHY_N((i == 0) ? 273 rf_ctrl->en_addr0 : rf_ctrl->en_addr1); 274 val_addr = B43_PHY_N((i == 0) ? 275 rf_ctrl->val_addr0 : rf_ctrl->val_addr1); 276 277 if (off) { 278 b43_phy_mask(dev, en_addr, ~(field)); 279 b43_phy_mask(dev, val_addr, 280 ~(rf_ctrl->val_mask)); 281 } else { 282 if (core == 0 || ((1 << i) & core)) { 283 b43_phy_set(dev, en_addr, field); 284 b43_phy_maskset(dev, val_addr, 285 ~(rf_ctrl->val_mask), 286 (value << rf_ctrl->val_shift)); 287 } 288 } 289 } 290 } else { 291 const struct nphy_rf_control_override_rev2 *rf_ctrl; 292 if (off) { 293 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field)); 294 value = 0; 295 } else { 296 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field); 297 } 298 299 for (i = 0; i < 2; i++) { 300 if (index <= 1 || index == 16) { 301 b43err(dev->wl, 302 "Unsupported RF Ctrl Override call\n"); 303 return; 304 } 305 306 if (index == 2 || index == 10 || 307 (index >= 13 && index <= 15)) { 308 core = 1; 309 } 310 311 rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; 312 addr = B43_PHY_N((i == 0) ? 313 rf_ctrl->addr0 : rf_ctrl->addr1); 314 315 if ((1 << i) & core) 316 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask), 317 (value << rf_ctrl->shift)); 318 319 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); 320 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 321 B43_NPHY_RFCTL_CMD_START); 322 udelay(1); 323 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE); 324 } 325 } 326} 327 328static void b43_nphy_rf_ctl_intc_override_rev7(struct b43_wldev *dev, 329 enum n_intc_override intc_override, 330 u16 value, u8 core_sel) 331{ 332 u16 reg, tmp, tmp2, val; 333 int core; 334 335 /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */ 336 337 for (core = 0; core < 2; core++) { 338 if ((core_sel == 1 && core != 0) || 339 (core_sel == 2 && core != 1)) 340 continue; 341 342 reg = (core == 0) ? B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 343 344 switch (intc_override) { 345 case N_INTC_OVERRIDE_OFF: 346 b43_phy_write(dev, reg, 0); 347 b43_phy_mask(dev, 0x2ff, ~0x2000); 348 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 349 break; 350 case N_INTC_OVERRIDE_TRSW: 351 b43_phy_maskset(dev, reg, ~0xC0, value << 6); 352 b43_phy_set(dev, reg, 0x400); 353 354 b43_phy_mask(dev, 0x2ff, ~0xC000 & 0xFFFF); 355 b43_phy_set(dev, 0x2ff, 0x2000); 356 b43_phy_set(dev, 0x2ff, 0x0001); 357 break; 358 case N_INTC_OVERRIDE_PA: 359 tmp = 0x0030; 360 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 361 val = value << 5; 362 else 363 val = value << 4; 364 b43_phy_maskset(dev, reg, ~tmp, val); 365 b43_phy_set(dev, reg, 0x1000); 366 break; 367 case N_INTC_OVERRIDE_EXT_LNA_PU: 368 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 369 tmp = 0x0001; 370 tmp2 = 0x0004; 371 val = value; 372 } else { 373 tmp = 0x0004; 374 tmp2 = 0x0001; 375 val = value << 2; 376 } 377 b43_phy_maskset(dev, reg, ~tmp, val); 378 b43_phy_mask(dev, reg, ~tmp2); 379 break; 380 case N_INTC_OVERRIDE_EXT_LNA_GAIN: 381 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 382 tmp = 0x0002; 383 tmp2 = 0x0008; 384 val = value << 1; 385 } else { 386 tmp = 0x0008; 387 tmp2 = 0x0002; 388 val = value << 3; 389 } 390 b43_phy_maskset(dev, reg, ~tmp, val); 391 b43_phy_mask(dev, reg, ~tmp2); 392 break; 393 } 394 } 395} 396 397/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ 398static void b43_nphy_rf_ctl_intc_override(struct b43_wldev *dev, 399 enum n_intc_override intc_override, 400 u16 value, u8 core) 401{ 402 u8 i, j; 403 u16 reg, tmp, val; 404 405 if (dev->phy.rev >= 7) { 406 b43_nphy_rf_ctl_intc_override_rev7(dev, intc_override, value, 407 core); 408 return; 409 } 410 411 B43_WARN_ON(dev->phy.rev < 3); 412 413 for (i = 0; i < 2; i++) { 414 if ((core == 1 && i == 1) || (core == 2 && !i)) 415 continue; 416 417 reg = (i == 0) ? 418 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2; 419 b43_phy_set(dev, reg, 0x400); 420 421 switch (intc_override) { 422 case N_INTC_OVERRIDE_OFF: 423 b43_phy_write(dev, reg, 0); 424 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 425 break; 426 case N_INTC_OVERRIDE_TRSW: 427 if (!i) { 428 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1, 429 0xFC3F, (value << 6)); 430 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1, 431 0xFFFE, 1); 432 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 433 B43_NPHY_RFCTL_CMD_START); 434 for (j = 0; j < 100; j++) { 435 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) { 436 j = 0; 437 break; 438 } 439 udelay(10); 440 } 441 if (j) 442 b43err(dev->wl, 443 "intc override timeout\n"); 444 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, 445 0xFFFE); 446 } else { 447 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2, 448 0xFC3F, (value << 6)); 449 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 450 0xFFFE, 1); 451 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 452 B43_NPHY_RFCTL_CMD_RXTX); 453 for (j = 0; j < 100; j++) { 454 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) { 455 j = 0; 456 break; 457 } 458 udelay(10); 459 } 460 if (j) 461 b43err(dev->wl, 462 "intc override timeout\n"); 463 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 464 0xFFFE); 465 } 466 break; 467 case N_INTC_OVERRIDE_PA: 468 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 469 tmp = 0x0020; 470 val = value << 5; 471 } else { 472 tmp = 0x0010; 473 val = value << 4; 474 } 475 b43_phy_maskset(dev, reg, ~tmp, val); 476 break; 477 case N_INTC_OVERRIDE_EXT_LNA_PU: 478 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 479 tmp = 0x0001; 480 val = value; 481 } else { 482 tmp = 0x0004; 483 val = value << 2; 484 } 485 b43_phy_maskset(dev, reg, ~tmp, val); 486 break; 487 case N_INTC_OVERRIDE_EXT_LNA_GAIN: 488 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 489 tmp = 0x0002; 490 val = value << 1; 491 } else { 492 tmp = 0x0008; 493 val = value << 3; 494 } 495 b43_phy_maskset(dev, reg, ~tmp, val); 496 break; 497 } 498 } 499} 500 501/************************************************** 502 * Various PHY ops 503 **************************************************/ 504 505/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 506static void b43_nphy_write_clip_detection(struct b43_wldev *dev, 507 const u16 *clip_st) 508{ 509 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]); 510 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]); 511} 512 513/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ 514static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st) 515{ 516 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES); 517 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES); 518} 519 520/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ 521static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val) 522{ 523 u16 tmp; 524 525 if (dev->dev->core_rev == 16) 526 b43_mac_suspend(dev); 527 528 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL); 529 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN | 530 B43_NPHY_CLASSCTL_WAITEDEN); 531 tmp &= ~mask; 532 tmp |= (val & mask); 533 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp); 534 535 if (dev->dev->core_rev == 16) 536 b43_mac_enable(dev); 537 538 return tmp; 539} 540 541/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ 542static void b43_nphy_reset_cca(struct b43_wldev *dev) 543{ 544 u16 bbcfg; 545 546 b43_phy_force_clock(dev, 1); 547 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG); 548 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA); 549 udelay(1); 550 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA); 551 b43_phy_force_clock(dev, 0); 552 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 553} 554 555/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ 556static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable) 557{ 558 struct b43_phy *phy = &dev->phy; 559 struct b43_phy_n *nphy = phy->n; 560 561 if (enable) { 562 static const u16 clip[] = { 0xFFFF, 0xFFFF }; 563 if (nphy->deaf_count++ == 0) { 564 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0); 565 b43_nphy_classifier(dev, 0x7, 566 B43_NPHY_CLASSCTL_WAITEDEN); 567 b43_nphy_read_clip_detection(dev, nphy->clip_state); 568 b43_nphy_write_clip_detection(dev, clip); 569 } 570 b43_nphy_reset_cca(dev); 571 } else { 572 if (--nphy->deaf_count == 0) { 573 b43_nphy_classifier(dev, 0x7, nphy->classifier_state); 574 b43_nphy_write_clip_detection(dev, nphy->clip_state); 575 } 576 } 577} 578 579/* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */ 580static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) 581{ 582 if (!offset) 583 offset = b43_is_40mhz(dev) ? 0x159 : 0x154; 584 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; 585} 586 587/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ 588static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev) 589{ 590 struct b43_phy_n *nphy = dev->phy.n; 591 592 u8 i; 593 s16 tmp; 594 u16 data[4]; 595 s16 gain[2]; 596 u16 minmax[2]; 597 static const u16 lna_gain[4] = { -2, 10, 19, 25 }; 598 599 if (nphy->hang_avoid) 600 b43_nphy_stay_in_carrier_search(dev, 1); 601 602 if (nphy->gain_boost) { 603 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 604 gain[0] = 6; 605 gain[1] = 6; 606 } else { 607 tmp = 40370 - 315 * dev->phy.channel; 608 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); 609 tmp = 23242 - 224 * dev->phy.channel; 610 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); 611 } 612 } else { 613 gain[0] = 0; 614 gain[1] = 0; 615 } 616 617 for (i = 0; i < 2; i++) { 618 if (nphy->elna_gain_config) { 619 data[0] = 19 + gain[i]; 620 data[1] = 25 + gain[i]; 621 data[2] = 25 + gain[i]; 622 data[3] = 25 + gain[i]; 623 } else { 624 data[0] = lna_gain[0] + gain[i]; 625 data[1] = lna_gain[1] + gain[i]; 626 data[2] = lna_gain[2] + gain[i]; 627 data[3] = lna_gain[3] + gain[i]; 628 } 629 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data); 630 631 minmax[i] = 23 + gain[i]; 632 } 633 634 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN, 635 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT); 636 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN, 637 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT); 638 639 if (nphy->hang_avoid) 640 b43_nphy_stay_in_carrier_search(dev, 0); 641} 642 643/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ 644static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd, 645 u8 *events, u8 *delays, u8 length) 646{ 647 struct b43_phy_n *nphy = dev->phy.n; 648 u8 i; 649 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F; 650 u16 offset1 = cmd << 4; 651 u16 offset2 = offset1 + 0x80; 652 653 if (nphy->hang_avoid) 654 b43_nphy_stay_in_carrier_search(dev, true); 655 656 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events); 657 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays); 658 659 for (i = length; i < 16; i++) { 660 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end); 661 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1); 662 } 663 664 if (nphy->hang_avoid) 665 b43_nphy_stay_in_carrier_search(dev, false); 666} 667 668/************************************************** 669 * Radio 0x2057 670 **************************************************/ 671 672static void b43_radio_2057_chantab_upload(struct b43_wldev *dev, 673 const struct b43_nphy_chantabent_rev7 *e_r7, 674 const struct b43_nphy_chantabent_rev7_2g *e_r7_2g) 675{ 676 if (e_r7_2g) { 677 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); 678 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); 679 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize); 680 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); 681 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); 682 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); 683 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); 684 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); 685 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); 686 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); 687 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); 688 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); 689 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0); 690 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); 691 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); 692 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1); 693 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); 694 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); 695 696 } else { 697 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); 698 b43_radio_write(dev, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); 699 b43_radio_write(dev, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize); 700 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); 701 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); 702 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); 703 b43_radio_write(dev, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); 704 b43_radio_write(dev, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); 705 b43_radio_write(dev, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); 706 b43_radio_write(dev, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); 707 b43_radio_write(dev, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); 708 b43_radio_write(dev, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); 709 b43_radio_write(dev, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); 710 b43_radio_write(dev, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); 711 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); 712 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); 713 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); 714 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); 715 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); 716 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); 717 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); 718 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); 719 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); 720 b43_radio_write(dev, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); 721 b43_radio_write(dev, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); 722 b43_radio_write(dev, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); 723 b43_radio_write(dev, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); 724 b43_radio_write(dev, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); 725 } 726} 727 728static void b43_radio_2057_setup(struct b43_wldev *dev, 729 const struct b43_nphy_chantabent_rev7 *tabent_r7, 730 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g) 731{ 732 struct b43_phy *phy = &dev->phy; 733 734 b43_radio_2057_chantab_upload(dev, tabent_r7, tabent_r7_2g); 735 736 switch (phy->radio_rev) { 737 case 0 ... 4: 738 case 6: 739 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 740 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x3f); 741 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); 742 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); 743 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); 744 } else { 745 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1f); 746 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); 747 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x8); 748 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x8); 749 } 750 break; 751 case 9: /* e.g. PHY rev 16 */ 752 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x20); 753 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x18); 754 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 755 b43_radio_write(dev, R2057_LOGEN_PTAT_RESETS, 0x38); 756 b43_radio_write(dev, R2057_VCOBUF_IDACS, 0x0f); 757 758 if (b43_is_40mhz(dev)) { 759 /* TODO */ 760 } else { 761 b43_radio_write(dev, 762 R2057_PAD_BIAS_FILTER_BWS_CORE0, 763 0x3c); 764 b43_radio_write(dev, 765 R2057_PAD_BIAS_FILTER_BWS_CORE1, 766 0x3c); 767 } 768 } 769 break; 770 case 14: /* 2 GHz only */ 771 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_R1, 0x1b); 772 b43_radio_write(dev, R2057_CP_KPD_IDAC, 0x3f); 773 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C1, 0x1f); 774 b43_radio_write(dev, R2057_RFPLL_LOOPFILTER_C2, 0x1f); 775 break; 776 } 777 778 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 779 u16 txmix2g_tune_boost_pu = 0; 780 u16 pad2g_tune_pus = 0; 781 782 if (b43_nphy_ipa(dev)) { 783 switch (phy->radio_rev) { 784 case 9: 785 txmix2g_tune_boost_pu = 0x0041; 786 /* TODO */ 787 break; 788 case 14: 789 txmix2g_tune_boost_pu = 0x21; 790 pad2g_tune_pus = 0x23; 791 break; 792 } 793 } 794 795 if (txmix2g_tune_boost_pu) 796 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 797 txmix2g_tune_boost_pu); 798 if (pad2g_tune_pus) 799 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE0, 800 pad2g_tune_pus); 801 if (txmix2g_tune_boost_pu) 802 b43_radio_write(dev, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, 803 txmix2g_tune_boost_pu); 804 if (pad2g_tune_pus) 805 b43_radio_write(dev, R2057_PAD2G_TUNE_PUS_CORE1, 806 pad2g_tune_pus); 807 } 808 809 usleep_range(50, 100); 810 811 /* VCO calibration */ 812 b43_radio_mask(dev, R2057_RFPLL_MISC_EN, ~0x01); 813 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); 814 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x4); 815 b43_radio_set(dev, R2057_RFPLL_MISC_EN, 0x01); 816 usleep_range(300, 600); 817} 818 819/* Calibrate resistors in LPF of PLL? 820 * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal 821 */ 822static u8 b43_radio_2057_rcal(struct b43_wldev *dev) 823{ 824 struct b43_phy *phy = &dev->phy; 825 u16 saved_regs_phy[12]; 826 u16 saved_regs_phy_rf[6]; 827 u16 saved_regs_radio[2] = { }; 828 static const u16 phy_to_store[] = { 829 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2, 830 B43_NPHY_RFCTL_LUT_TRSW_LO1, B43_NPHY_RFCTL_LUT_TRSW_LO2, 831 B43_NPHY_RFCTL_RXG1, B43_NPHY_RFCTL_RXG2, 832 B43_NPHY_RFCTL_TXG1, B43_NPHY_RFCTL_TXG2, 833 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4, 834 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6, 835 }; 836 static const u16 phy_to_store_rf[] = { 837 B43_NPHY_REV3_RFCTL_OVER0, B43_NPHY_REV3_RFCTL_OVER1, 838 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4, 839 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6, 840 }; 841 u16 tmp; 842 int i; 843 844 /* Save */ 845 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) 846 saved_regs_phy[i] = b43_phy_read(dev, phy_to_store[i]); 847 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) 848 saved_regs_phy_rf[i] = b43_phy_read(dev, phy_to_store_rf[i]); 849 850 /* Set */ 851 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) 852 b43_phy_write(dev, phy_to_store[i], 0); 853 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER0, 0x07ff); 854 b43_phy_write(dev, B43_NPHY_REV3_RFCTL_OVER1, 0x07ff); 855 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x07ff); 856 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0x07ff); 857 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0x007f); 858 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0x007f); 859 860 switch (phy->radio_rev) { 861 case 5: 862 b43_phy_mask(dev, B43_NPHY_REV7_RF_CTL_OVER3, ~0x2); 863 udelay(10); 864 b43_radio_set(dev, R2057_IQTEST_SEL_PU, 0x1); 865 b43_radio_maskset(dev, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); 866 break; 867 case 9: 868 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); 869 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); 870 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); 871 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x11); 872 break; 873 case 14: 874 saved_regs_radio[0] = b43_radio_read(dev, R2057_IQTEST_SEL_PU); 875 saved_regs_radio[1] = b43_radio_read(dev, R2057v7_IQTEST_SEL_PU2); 876 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); 877 b43_phy_set(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0x2); 878 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, 0x2); 879 b43_radio_write(dev, R2057_IQTEST_SEL_PU, 0x1); 880 break; 881 } 882 883 /* Enable */ 884 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x1); 885 udelay(10); 886 887 /* Start */ 888 b43_radio_set(dev, R2057_RCAL_CONFIG, 0x2); 889 usleep_range(100, 200); 890 891 /* Stop */ 892 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x2); 893 894 /* Wait and check for result */ 895 if (!b43_radio_wait_value(dev, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { 896 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); 897 return 0; 898 } 899 tmp = b43_radio_read(dev, R2057_RCAL_STATUS) & 0x3E; 900 901 /* Disable */ 902 b43_radio_mask(dev, R2057_RCAL_CONFIG, ~0x1); 903 904 /* Restore */ 905 for (i = 0; i < ARRAY_SIZE(phy_to_store_rf); i++) 906 b43_phy_write(dev, phy_to_store_rf[i], saved_regs_phy_rf[i]); 907 for (i = 0; i < ARRAY_SIZE(phy_to_store); i++) 908 b43_phy_write(dev, phy_to_store[i], saved_regs_phy[i]); 909 910 switch (phy->radio_rev) { 911 case 0 ... 4: 912 case 6: 913 b43_radio_maskset(dev, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); 914 b43_radio_maskset(dev, R2057_BANDGAP_RCAL_TRIM, ~0xF0, 915 tmp << 2); 916 break; 917 case 5: 918 b43_radio_mask(dev, R2057_IPA2G_CASCONV_CORE0, ~0x1); 919 b43_radio_mask(dev, R2057v7_IQTEST_SEL_PU2, ~0x2); 920 break; 921 case 9: 922 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); 923 break; 924 case 14: 925 b43_radio_write(dev, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); 926 b43_radio_write(dev, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); 927 break; 928 } 929 930 return tmp & 0x3e; 931} 932 933/* Calibrate the internal RC oscillator? 934 * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal 935 */ 936static u16 b43_radio_2057_rccal(struct b43_wldev *dev) 937{ 938 struct b43_phy *phy = &dev->phy; 939 bool special = (phy->radio_rev == 3 || phy->radio_rev == 4 || 940 phy->radio_rev == 6); 941 u16 tmp; 942 943 /* Setup cal */ 944 if (special) { 945 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x61); 946 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xC0); 947 } else { 948 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x61); 949 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xE9); 950 } 951 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); 952 953 /* Start, wait, stop */ 954 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); 955 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 956 5000000)) 957 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); 958 usleep_range(35, 70); 959 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); 960 usleep_range(70, 140); 961 962 /* Setup cal */ 963 if (special) { 964 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x69); 965 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); 966 } else { 967 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x69); 968 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xD5); 969 } 970 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); 971 972 /* Start, wait, stop */ 973 usleep_range(35, 70); 974 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); 975 usleep_range(70, 140); 976 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 977 5000000)) 978 b43dbg(dev->wl, "Radio 0x2057 rccal timeout\n"); 979 usleep_range(35, 70); 980 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); 981 usleep_range(70, 140); 982 983 /* Setup cal */ 984 if (special) { 985 b43_radio_write(dev, R2057_RCCAL_MASTER, 0x73); 986 b43_radio_write(dev, R2057_RCCAL_X1, 0x28); 987 b43_radio_write(dev, R2057_RCCAL_TRC0, 0xB0); 988 } else { 989 b43_radio_write(dev, R2057v7_RCCAL_MASTER, 0x73); 990 b43_radio_write(dev, R2057_RCCAL_X1, 0x6E); 991 b43_radio_write(dev, R2057_RCCAL_TRC0, 0x99); 992 } 993 994 /* Start, wait, stop */ 995 usleep_range(35, 70); 996 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x55); 997 usleep_range(70, 140); 998 if (!b43_radio_wait_value(dev, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 999 5000000)) { 1000 b43err(dev->wl, "Radio 0x2057 rcal timeout\n"); 1001 return 0; 1002 } 1003 tmp = b43_radio_read(dev, R2057_RCCAL_DONE_OSCCAP); 1004 usleep_range(35, 70); 1005 b43_radio_write(dev, R2057_RCCAL_START_R1_Q1_P1, 0x15); 1006 usleep_range(70, 140); 1007 1008 if (special) 1009 b43_radio_mask(dev, R2057_RCCAL_MASTER, ~0x1); 1010 else 1011 b43_radio_mask(dev, R2057v7_RCCAL_MASTER, ~0x1); 1012 1013 return tmp; 1014} 1015 1016static void b43_radio_2057_init_pre(struct b43_wldev *dev) 1017{ 1018 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_CHIP0PU); 1019 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ 1020 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_OEPORFORCE); 1021 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, ~B43_NPHY_RFCTL_CMD_OEPORFORCE); 1022 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_CHIP0PU); 1023} 1024 1025static void b43_radio_2057_init_post(struct b43_wldev *dev) 1026{ 1027 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x1); 1028 1029 if (0) /* FIXME: Is this BCM43217 specific? */ 1030 b43_radio_set(dev, R2057_XTALPUOVR_PINCTRL, 0x2); 1031 1032 b43_radio_set(dev, R2057_RFPLL_MISC_CAL_RESETN, 0x78); 1033 b43_radio_set(dev, R2057_XTAL_CONFIG2, 0x80); 1034 mdelay(2); 1035 b43_radio_mask(dev, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); 1036 b43_radio_mask(dev, R2057_XTAL_CONFIG2, ~0x80); 1037 1038 if (dev->phy.do_full_init) { 1039 b43_radio_2057_rcal(dev); 1040 b43_radio_2057_rccal(dev); 1041 } 1042 b43_radio_mask(dev, R2057_RFPLL_MASTER, ~0x8); 1043} 1044 1045/* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */ 1046static void b43_radio_2057_init(struct b43_wldev *dev) 1047{ 1048 b43_radio_2057_init_pre(dev); 1049 r2057_upload_inittabs(dev); 1050 b43_radio_2057_init_post(dev); 1051} 1052 1053/************************************************** 1054 * Radio 0x2056 1055 **************************************************/ 1056 1057static void b43_chantab_radio_2056_upload(struct b43_wldev *dev, 1058 const struct b43_nphy_channeltab_entry_rev3 *e) 1059{ 1060 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); 1061 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); 1062 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); 1063 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); 1064 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); 1065 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 1066 e->radio_syn_pll_loopfilter1); 1067 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 1068 e->radio_syn_pll_loopfilter2); 1069 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3, 1070 e->radio_syn_pll_loopfilter3); 1071 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 1072 e->radio_syn_pll_loopfilter4); 1073 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5, 1074 e->radio_syn_pll_loopfilter5); 1075 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27, 1076 e->radio_syn_reserved_addr27); 1077 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28, 1078 e->radio_syn_reserved_addr28); 1079 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29, 1080 e->radio_syn_reserved_addr29); 1081 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1, 1082 e->radio_syn_logen_vcobuf1); 1083 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); 1084 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); 1085 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); 1086 1087 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE, 1088 e->radio_rx0_lnaa_tune); 1089 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE, 1090 e->radio_rx0_lnag_tune); 1091 1092 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, 1093 e->radio_tx0_intpaa_boost_tune); 1094 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, 1095 e->radio_tx0_intpag_boost_tune); 1096 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, 1097 e->radio_tx0_pada_boost_tune); 1098 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, 1099 e->radio_tx0_padg_boost_tune); 1100 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, 1101 e->radio_tx0_pgaa_boost_tune); 1102 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, 1103 e->radio_tx0_pgag_boost_tune); 1104 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, 1105 e->radio_tx0_mixa_boost_tune); 1106 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, 1107 e->radio_tx0_mixg_boost_tune); 1108 1109 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE, 1110 e->radio_rx1_lnaa_tune); 1111 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE, 1112 e->radio_rx1_lnag_tune); 1113 1114 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, 1115 e->radio_tx1_intpaa_boost_tune); 1116 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, 1117 e->radio_tx1_intpag_boost_tune); 1118 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, 1119 e->radio_tx1_pada_boost_tune); 1120 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, 1121 e->radio_tx1_padg_boost_tune); 1122 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, 1123 e->radio_tx1_pgaa_boost_tune); 1124 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, 1125 e->radio_tx1_pgag_boost_tune); 1126 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, 1127 e->radio_tx1_mixa_boost_tune); 1128 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, 1129 e->radio_tx1_mixg_boost_tune); 1130} 1131 1132/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */ 1133static void b43_radio_2056_setup(struct b43_wldev *dev, 1134 const struct b43_nphy_channeltab_entry_rev3 *e) 1135{ 1136 struct b43_phy *phy = &dev->phy; 1137 struct ssb_sprom *sprom = dev->dev->bus_sprom; 1138 enum ieee80211_band band = b43_current_band(dev->wl); 1139 u16 offset; 1140 u8 i; 1141 u16 bias, cbias; 1142 u16 pag_boost, padg_boost, pgag_boost, mixg_boost; 1143 u16 paa_boost, pada_boost, pgaa_boost, mixa_boost; 1144 bool is_pkg_fab_smic; 1145 1146 B43_WARN_ON(dev->phy.rev < 3); 1147 1148 is_pkg_fab_smic = 1149 ((dev->dev->chip_id == BCMA_CHIP_ID_BCM43224 || 1150 dev->dev->chip_id == BCMA_CHIP_ID_BCM43225 || 1151 dev->dev->chip_id == BCMA_CHIP_ID_BCM43421) && 1152 dev->dev->chip_pkg == BCMA_PKG_ID_BCM43224_FAB_SMIC); 1153 1154 b43_chantab_radio_2056_upload(dev, e); 1155 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ); 1156 1157 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && 1158 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 1159 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); 1160 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); 1161 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || 1162 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { 1163 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14); 1164 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0); 1165 } else { 1166 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B); 1167 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14); 1168 } 1169 } 1170 if (sprom->boardflags2_hi & B43_BFH2_GPLL_WAR2 && 1171 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 1172 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1f); 1173 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1f); 1174 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0b); 1175 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x20); 1176 } 1177 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR && 1178 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 1179 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F); 1180 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F); 1181 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05); 1182 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C); 1183 } 1184 1185 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) { 1186 for (i = 0; i < 2; i++) { 1187 offset = i ? B2056_TX1 : B2056_TX0; 1188 if (dev->phy.rev >= 5) { 1189 b43_radio_write(dev, 1190 offset | B2056_TX_PADG_IDAC, 0xcc); 1191 1192 if (dev->dev->chip_id == BCMA_CHIP_ID_BCM4716 || 1193 dev->dev->chip_id == BCMA_CHIP_ID_BCM47162) { 1194 bias = 0x40; 1195 cbias = 0x45; 1196 pag_boost = 0x5; 1197 pgag_boost = 0x33; 1198 mixg_boost = 0x55; 1199 } else { 1200 bias = 0x25; 1201 cbias = 0x20; 1202 if (is_pkg_fab_smic) { 1203 bias = 0x2a; 1204 cbias = 0x38; 1205 } 1206 pag_boost = 0x4; 1207 pgag_boost = 0x03; 1208 mixg_boost = 0x65; 1209 } 1210 padg_boost = 0x77; 1211 1212 b43_radio_write(dev, 1213 offset | B2056_TX_INTPAG_IMAIN_STAT, 1214 bias); 1215 b43_radio_write(dev, 1216 offset | B2056_TX_INTPAG_IAUX_STAT, 1217 bias); 1218 b43_radio_write(dev, 1219 offset | B2056_TX_INTPAG_CASCBIAS, 1220 cbias); 1221 b43_radio_write(dev, 1222 offset | B2056_TX_INTPAG_BOOST_TUNE, 1223 pag_boost); 1224 b43_radio_write(dev, 1225 offset | B2056_TX_PGAG_BOOST_TUNE, 1226 pgag_boost); 1227 b43_radio_write(dev, 1228 offset | B2056_TX_PADG_BOOST_TUNE, 1229 padg_boost); 1230 b43_radio_write(dev, 1231 offset | B2056_TX_MIXG_BOOST_TUNE, 1232 mixg_boost); 1233 } else { 1234 bias = b43_is_40mhz(dev) ? 0x40 : 0x20; 1235 b43_radio_write(dev, 1236 offset | B2056_TX_INTPAG_IMAIN_STAT, 1237 bias); 1238 b43_radio_write(dev, 1239 offset | B2056_TX_INTPAG_IAUX_STAT, 1240 bias); 1241 b43_radio_write(dev, 1242 offset | B2056_TX_INTPAG_CASCBIAS, 1243 0x30); 1244 } 1245 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee); 1246 } 1247 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) { 1248 u16 freq = phy->chandef->chan->center_freq; 1249 if (freq < 5100) { 1250 paa_boost = 0xA; 1251 pada_boost = 0x77; 1252 pgaa_boost = 0xF; 1253 mixa_boost = 0xF; 1254 } else if (freq < 5340) { 1255 paa_boost = 0x8; 1256 pada_boost = 0x77; 1257 pgaa_boost = 0xFB; 1258 mixa_boost = 0xF; 1259 } else if (freq < 5650) { 1260 paa_boost = 0x0; 1261 pada_boost = 0x77; 1262 pgaa_boost = 0xB; 1263 mixa_boost = 0xF; 1264 } else { 1265 paa_boost = 0x0; 1266 pada_boost = 0x77; 1267 if (freq != 5825) 1268 pgaa_boost = -(freq - 18) / 36 + 168; 1269 else 1270 pgaa_boost = 6; 1271 mixa_boost = 0xF; 1272 } 1273 1274 cbias = is_pkg_fab_smic ? 0x35 : 0x30; 1275 1276 for (i = 0; i < 2; i++) { 1277 offset = i ? B2056_TX1 : B2056_TX0; 1278 1279 b43_radio_write(dev, 1280 offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost); 1281 b43_radio_write(dev, 1282 offset | B2056_TX_PADA_BOOST_TUNE, pada_boost); 1283 b43_radio_write(dev, 1284 offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost); 1285 b43_radio_write(dev, 1286 offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost); 1287 b43_radio_write(dev, 1288 offset | B2056_TX_TXSPARE1, 0x30); 1289 b43_radio_write(dev, 1290 offset | B2056_TX_PA_SPARE2, 0xee); 1291 b43_radio_write(dev, 1292 offset | B2056_TX_PADA_CASCBIAS, 0x03); 1293 b43_radio_write(dev, 1294 offset | B2056_TX_INTPAA_IAUX_STAT, 0x30); 1295 b43_radio_write(dev, 1296 offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30); 1297 b43_radio_write(dev, 1298 offset | B2056_TX_INTPAA_CASCBIAS, cbias); 1299 } 1300 } 1301 1302 udelay(50); 1303 /* VCO calibration */ 1304 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00); 1305 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); 1306 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18); 1307 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38); 1308 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39); 1309 udelay(300); 1310} 1311 1312static u8 b43_radio_2056_rcal(struct b43_wldev *dev) 1313{ 1314 struct b43_phy *phy = &dev->phy; 1315 u16 mast2, tmp; 1316 1317 if (phy->rev != 3) 1318 return 0; 1319 1320 mast2 = b43_radio_read(dev, B2056_SYN_PLL_MAST2); 1321 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2 | 0x7); 1322 1323 udelay(10); 1324 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); 1325 udelay(10); 1326 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x09); 1327 1328 if (!b43_radio_wait_value(dev, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, 1329 1000000)) { 1330 b43err(dev->wl, "Radio recalibration timeout\n"); 1331 return 0; 1332 } 1333 1334 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x01); 1335 tmp = b43_radio_read(dev, B2056_SYN_RCAL_CODE_OUT); 1336 b43_radio_write(dev, B2056_SYN_RCAL_MASTER, 0x00); 1337 1338 b43_radio_write(dev, B2056_SYN_PLL_MAST2, mast2); 1339 1340 return tmp & 0x1f; 1341} 1342 1343static void b43_radio_init2056_pre(struct b43_wldev *dev) 1344{ 1345 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1346 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 1347 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ 1348 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1349 B43_NPHY_RFCTL_CMD_OEPORFORCE); 1350 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1351 ~B43_NPHY_RFCTL_CMD_OEPORFORCE); 1352 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1353 B43_NPHY_RFCTL_CMD_CHIP0PU); 1354} 1355 1356static void b43_radio_init2056_post(struct b43_wldev *dev) 1357{ 1358 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB); 1359 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2); 1360 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2); 1361 msleep(1); 1362 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2); 1363 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC); 1364 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1); 1365 if (dev->phy.do_full_init) 1366 b43_radio_2056_rcal(dev); 1367} 1368 1369/* 1370 * Initialize a Broadcom 2056 N-radio 1371 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init 1372 */ 1373static void b43_radio_init2056(struct b43_wldev *dev) 1374{ 1375 b43_radio_init2056_pre(dev); 1376 b2056_upload_inittabs(dev, 0, 0); 1377 b43_radio_init2056_post(dev); 1378} 1379 1380/************************************************** 1381 * Radio 0x2055 1382 **************************************************/ 1383 1384static void b43_chantab_radio_upload(struct b43_wldev *dev, 1385 const struct b43_nphy_channeltab_entry_rev2 *e) 1386{ 1387 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref); 1388 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); 1389 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); 1390 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail); 1391 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1392 1393 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1); 1394 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2); 1395 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1); 1396 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1); 1397 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1398 1399 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2); 1400 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); 1401 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1); 1402 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2); 1403 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1404 1405 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); 1406 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); 1407 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); 1408 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); 1409 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1410 1411 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); 1412 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); 1413 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); 1414 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); 1415 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1416 1417 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); 1418 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); 1419} 1420 1421/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ 1422static void b43_radio_2055_setup(struct b43_wldev *dev, 1423 const struct b43_nphy_channeltab_entry_rev2 *e) 1424{ 1425 B43_WARN_ON(dev->phy.rev >= 3); 1426 1427 b43_chantab_radio_upload(dev, e); 1428 udelay(50); 1429 b43_radio_write(dev, B2055_VCO_CAL10, 0x05); 1430 b43_radio_write(dev, B2055_VCO_CAL10, 0x45); 1431 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */ 1432 b43_radio_write(dev, B2055_VCO_CAL10, 0x65); 1433 udelay(300); 1434} 1435 1436static void b43_radio_init2055_pre(struct b43_wldev *dev) 1437{ 1438 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1439 ~B43_NPHY_RFCTL_CMD_PORFORCE); 1440 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1441 B43_NPHY_RFCTL_CMD_CHIP0PU | 1442 B43_NPHY_RFCTL_CMD_OEPORFORCE); 1443 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1444 B43_NPHY_RFCTL_CMD_PORFORCE); 1445} 1446 1447static void b43_radio_init2055_post(struct b43_wldev *dev) 1448{ 1449 struct b43_phy_n *nphy = dev->phy.n; 1450 struct ssb_sprom *sprom = dev->dev->bus_sprom; 1451 bool workaround = false; 1452 1453 if (sprom->revision < 4) 1454 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM 1455 && dev->dev->board_type == SSB_BOARD_CB2_4321 1456 && dev->dev->board_rev >= 0x41); 1457 else 1458 workaround = 1459 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS); 1460 1461 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3); 1462 if (workaround) { 1463 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F); 1464 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F); 1465 } 1466 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); 1467 b43_radio_write(dev, B2055_CAL_MISC, 0x3C); 1468 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE); 1469 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80); 1470 b43_radio_set(dev, B2055_CAL_MISC, 0x1); 1471 msleep(1); 1472 b43_radio_set(dev, B2055_CAL_MISC, 0x40); 1473 if (!b43_radio_wait_value(dev, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) 1474 b43err(dev->wl, "radio post init timeout\n"); 1475 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F); 1476 b43_switch_channel(dev, dev->phy.channel); 1477 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9); 1478 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9); 1479 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83); 1480 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83); 1481 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); 1482 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); 1483 if (!nphy->gain_boost) { 1484 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2); 1485 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2); 1486 } else { 1487 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD); 1488 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD); 1489 } 1490 udelay(2); 1491} 1492 1493/* 1494 * Initialize a Broadcom 2055 N-radio 1495 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init 1496 */ 1497static void b43_radio_init2055(struct b43_wldev *dev) 1498{ 1499 b43_radio_init2055_pre(dev); 1500 if (b43_status(dev) < B43_STAT_INITIALIZED) { 1501 /* Follow wl, not specs. Do not force uploading all regs */ 1502 b2055_upload_inittab(dev, 0, 0); 1503 } else { 1504 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ; 1505 b2055_upload_inittab(dev, ghz5, 0); 1506 } 1507 b43_radio_init2055_post(dev); 1508} 1509 1510/************************************************** 1511 * Samples 1512 **************************************************/ 1513 1514/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ 1515static int b43_nphy_load_samples(struct b43_wldev *dev, 1516 struct b43_c32 *samples, u16 len) { 1517 struct b43_phy_n *nphy = dev->phy.n; 1518 u16 i; 1519 u32 *data; 1520 1521 data = kzalloc(len * sizeof(u32), GFP_KERNEL); 1522 if (!data) { 1523 b43err(dev->wl, "allocation for samples loading failed\n"); 1524 return -ENOMEM; 1525 } 1526 if (nphy->hang_avoid) 1527 b43_nphy_stay_in_carrier_search(dev, 1); 1528 1529 for (i = 0; i < len; i++) { 1530 data[i] = (samples[i].i & 0x3FF << 10); 1531 data[i] |= samples[i].q & 0x3FF; 1532 } 1533 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data); 1534 1535 kfree(data); 1536 if (nphy->hang_avoid) 1537 b43_nphy_stay_in_carrier_search(dev, 0); 1538 return 0; 1539} 1540 1541/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ 1542static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max, 1543 bool test) 1544{ 1545 int i; 1546 u16 bw, len, rot, angle; 1547 struct b43_c32 *samples; 1548 1549 bw = b43_is_40mhz(dev) ? 40 : 20; 1550 len = bw << 3; 1551 1552 if (test) { 1553 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX) 1554 bw = 82; 1555 else 1556 bw = 80; 1557 1558 if (b43_is_40mhz(dev)) 1559 bw <<= 1; 1560 1561 len = bw << 1; 1562 } 1563 1564 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL); 1565 if (!samples) { 1566 b43err(dev->wl, "allocation for samples generation failed\n"); 1567 return 0; 1568 } 1569 rot = (((freq * 36) / bw) << 16) / 100; 1570 angle = 0; 1571 1572 for (i = 0; i < len; i++) { 1573 samples[i] = b43_cordic(angle); 1574 angle += rot; 1575 samples[i].q = CORDIC_CONVERT(samples[i].q * max); 1576 samples[i].i = CORDIC_CONVERT(samples[i].i * max); 1577 } 1578 1579 i = b43_nphy_load_samples(dev, samples, len); 1580 kfree(samples); 1581 return (i < 0) ? 0 : len; 1582} 1583 1584/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ 1585static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops, 1586 u16 wait, bool iqmode, bool dac_test, 1587 bool modify_bbmult) 1588{ 1589 struct b43_phy *phy = &dev->phy; 1590 struct b43_phy_n *nphy = dev->phy.n; 1591 int i; 1592 u16 seq_mode; 1593 u32 tmp; 1594 1595 b43_nphy_stay_in_carrier_search(dev, true); 1596 1597 if (phy->rev >= 7) { 1598 bool lpf_bw3, lpf_bw4; 1599 1600 lpf_bw3 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER3) & 0x80; 1601 lpf_bw4 = b43_phy_read(dev, B43_NPHY_REV7_RF_CTL_OVER4) & 0x80; 1602 1603 if (lpf_bw3 || lpf_bw4) { 1604 /* TODO */ 1605 } else { 1606 u16 value = b43_nphy_read_lpf_ctl(dev, 0); 1607 if (phy->rev >= 19) 1608 b43_nphy_rf_ctl_override_rev19(dev, 0x80, value, 1609 0, false, 1); 1610 else 1611 b43_nphy_rf_ctl_override_rev7(dev, 0x80, value, 1612 0, false, 1); 1613 nphy->lpf_bw_overrode_for_sample_play = true; 1614 } 1615 } 1616 1617 if ((nphy->bb_mult_save & 0x80000000) == 0) { 1618 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87)); 1619 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; 1620 } 1621 1622 if (modify_bbmult) { 1623 tmp = !b43_is_40mhz(dev) ? 0x6464 : 0x4747; 1624 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 1625 } 1626 1627 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1)); 1628 1629 if (loops != 0xFFFF) 1630 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1)); 1631 else 1632 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops); 1633 1634 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait); 1635 1636 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE); 1637 1638 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER); 1639 if (iqmode) { 1640 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 1641 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000); 1642 } else { 1643 tmp = dac_test ? 5 : 1; 1644 b43_phy_write(dev, B43_NPHY_SAMP_CMD, tmp); 1645 } 1646 for (i = 0; i < 100; i++) { 1647 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) { 1648 i = 0; 1649 break; 1650 } 1651 udelay(10); 1652 } 1653 if (i) 1654 b43err(dev->wl, "run samples timeout\n"); 1655 1656 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode); 1657 1658 b43_nphy_stay_in_carrier_search(dev, false); 1659} 1660 1661/************************************************** 1662 * RSSI 1663 **************************************************/ 1664 1665/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ 1666static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale, 1667 s8 offset, u8 core, 1668 enum n_rail_type rail, 1669 enum n_rssi_type rssi_type) 1670{ 1671 u16 tmp; 1672 bool core1or5 = (core == 1) || (core == 5); 1673 bool core2or5 = (core == 2) || (core == 5); 1674 1675 offset = clamp_val(offset, -32, 31); 1676 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); 1677 1678 switch (rssi_type) { 1679 case N_RSSI_NB: 1680 if (core1or5 && rail == N_RAIL_I) 1681 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp); 1682 if (core1or5 && rail == N_RAIL_Q) 1683 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp); 1684 if (core2or5 && rail == N_RAIL_I) 1685 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp); 1686 if (core2or5 && rail == N_RAIL_Q) 1687 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp); 1688 break; 1689 case N_RSSI_W1: 1690 if (core1or5 && rail == N_RAIL_I) 1691 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp); 1692 if (core1or5 && rail == N_RAIL_Q) 1693 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp); 1694 if (core2or5 && rail == N_RAIL_I) 1695 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp); 1696 if (core2or5 && rail == N_RAIL_Q) 1697 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp); 1698 break; 1699 case N_RSSI_W2: 1700 if (core1or5 && rail == N_RAIL_I) 1701 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp); 1702 if (core1or5 && rail == N_RAIL_Q) 1703 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp); 1704 if (core2or5 && rail == N_RAIL_I) 1705 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp); 1706 if (core2or5 && rail == N_RAIL_Q) 1707 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp); 1708 break; 1709 case N_RSSI_TBD: 1710 if (core1or5 && rail == N_RAIL_I) 1711 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp); 1712 if (core1or5 && rail == N_RAIL_Q) 1713 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp); 1714 if (core2or5 && rail == N_RAIL_I) 1715 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp); 1716 if (core2or5 && rail == N_RAIL_Q) 1717 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp); 1718 break; 1719 case N_RSSI_IQ: 1720 if (core1or5 && rail == N_RAIL_I) 1721 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp); 1722 if (core1or5 && rail == N_RAIL_Q) 1723 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp); 1724 if (core2or5 && rail == N_RAIL_I) 1725 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp); 1726 if (core2or5 && rail == N_RAIL_Q) 1727 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp); 1728 break; 1729 case N_RSSI_TSSI_2G: 1730 if (core1or5) 1731 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp); 1732 if (core2or5) 1733 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp); 1734 break; 1735 case N_RSSI_TSSI_5G: 1736 if (core1or5) 1737 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp); 1738 if (core2or5) 1739 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp); 1740 break; 1741 } 1742} 1743 1744static void b43_nphy_rssi_select_rev19(struct b43_wldev *dev, u8 code, 1745 enum n_rssi_type rssi_type) 1746{ 1747 /* TODO */ 1748} 1749 1750static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, 1751 enum n_rssi_type rssi_type) 1752{ 1753 u8 i; 1754 u16 reg, val; 1755 1756 if (code == 0) { 1757 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF); 1758 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF); 1759 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF); 1760 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF); 1761 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF); 1762 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF); 1763 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); 1764 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); 1765 } else { 1766 for (i = 0; i < 2; i++) { 1767 if ((code == 1 && i == 1) || (code == 2 && !i)) 1768 continue; 1769 1770 reg = (i == 0) ? 1771 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER; 1772 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200); 1773 1774 if (rssi_type == N_RSSI_W1 || 1775 rssi_type == N_RSSI_W2 || 1776 rssi_type == N_RSSI_NB) { 1777 reg = (i == 0) ? 1778 B43_NPHY_AFECTL_C1 : 1779 B43_NPHY_AFECTL_C2; 1780 b43_phy_maskset(dev, reg, 0xFCFF, 0); 1781 1782 reg = (i == 0) ? 1783 B43_NPHY_RFCTL_LUT_TRSW_UP1 : 1784 B43_NPHY_RFCTL_LUT_TRSW_UP2; 1785 b43_phy_maskset(dev, reg, 0xFFC3, 0); 1786 1787 if (rssi_type == N_RSSI_W1) 1788 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8; 1789 else if (rssi_type == N_RSSI_W2) 1790 val = 16; 1791 else 1792 val = 32; 1793 b43_phy_set(dev, reg, val); 1794 1795 reg = (i == 0) ? 1796 B43_NPHY_TXF_40CO_B1S0 : 1797 B43_NPHY_TXF_40CO_B32S1; 1798 b43_phy_set(dev, reg, 0x0020); 1799 } else { 1800 if (rssi_type == N_RSSI_TBD) 1801 val = 0x0100; 1802 else if (rssi_type == N_RSSI_IQ) 1803 val = 0x0200; 1804 else 1805 val = 0x0300; 1806 1807 reg = (i == 0) ? 1808 B43_NPHY_AFECTL_C1 : 1809 B43_NPHY_AFECTL_C2; 1810 1811 b43_phy_maskset(dev, reg, 0xFCFF, val); 1812 b43_phy_maskset(dev, reg, 0xF3FF, val << 2); 1813 1814 if (rssi_type != N_RSSI_IQ && 1815 rssi_type != N_RSSI_TBD) { 1816 enum ieee80211_band band = 1817 b43_current_band(dev->wl); 1818 1819 if (dev->phy.rev < 7) { 1820 if (b43_nphy_ipa(dev)) 1821 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; 1822 else 1823 val = 0x11; 1824 reg = (i == 0) ? B2056_TX0 : B2056_TX1; 1825 reg |= B2056_TX_TX_SSI_MUX; 1826 b43_radio_write(dev, reg, val); 1827 } 1828 1829 reg = (i == 0) ? 1830 B43_NPHY_AFECTL_OVER1 : 1831 B43_NPHY_AFECTL_OVER; 1832 b43_phy_set(dev, reg, 0x0200); 1833 } 1834 } 1835 } 1836 } 1837} 1838 1839static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, 1840 enum n_rssi_type rssi_type) 1841{ 1842 u16 val; 1843 bool rssi_w1_w2_nb = false; 1844 1845 switch (rssi_type) { 1846 case N_RSSI_W1: 1847 case N_RSSI_W2: 1848 case N_RSSI_NB: 1849 val = 0; 1850 rssi_w1_w2_nb = true; 1851 break; 1852 case N_RSSI_TBD: 1853 val = 1; 1854 break; 1855 case N_RSSI_IQ: 1856 val = 2; 1857 break; 1858 default: 1859 val = 3; 1860 } 1861 1862 val = (val << 12) | (val << 14); 1863 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val); 1864 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val); 1865 1866 if (rssi_w1_w2_nb) { 1867 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF, 1868 (rssi_type + 1) << 4); 1869 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF, 1870 (rssi_type + 1) << 4); 1871 } 1872 1873 if (code == 0) { 1874 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000); 1875 if (rssi_w1_w2_nb) { 1876 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1877 ~(B43_NPHY_RFCTL_CMD_RXEN | 1878 B43_NPHY_RFCTL_CMD_CORESEL)); 1879 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 1880 ~(0x1 << 12 | 1881 0x1 << 5 | 1882 0x1 << 1 | 1883 0x1)); 1884 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 1885 ~B43_NPHY_RFCTL_CMD_START); 1886 udelay(20); 1887 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 1888 } 1889 } else { 1890 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000); 1891 if (rssi_w1_w2_nb) { 1892 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 1893 ~(B43_NPHY_RFCTL_CMD_RXEN | 1894 B43_NPHY_RFCTL_CMD_CORESEL), 1895 (B43_NPHY_RFCTL_CMD_RXEN | 1896 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT)); 1897 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 1898 (0x1 << 12 | 1899 0x1 << 5 | 1900 0x1 << 1 | 1901 0x1)); 1902 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, 1903 B43_NPHY_RFCTL_CMD_START); 1904 udelay(20); 1905 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 1906 } 1907 } 1908} 1909 1910/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ 1911static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, 1912 enum n_rssi_type type) 1913{ 1914 if (dev->phy.rev >= 19) 1915 b43_nphy_rssi_select_rev19(dev, code, type); 1916 else if (dev->phy.rev >= 3) 1917 b43_nphy_rev3_rssi_select(dev, code, type); 1918 else 1919 b43_nphy_rev2_rssi_select(dev, code, type); 1920} 1921 1922/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ 1923static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, 1924 enum n_rssi_type rssi_type, u8 *buf) 1925{ 1926 int i; 1927 for (i = 0; i < 2; i++) { 1928 if (rssi_type == N_RSSI_NB) { 1929 if (i == 0) { 1930 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, 1931 0xFC, buf[0]); 1932 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1933 0xFC, buf[1]); 1934 } else { 1935 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, 1936 0xFC, buf[2 * i]); 1937 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1938 0xFC, buf[2 * i + 1]); 1939 } 1940 } else { 1941 if (i == 0) 1942 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, 1943 0xF3, buf[0] << 2); 1944 else 1945 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5, 1946 0xF3, buf[2 * i + 1] << 2); 1947 } 1948 } 1949} 1950 1951/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ 1952static int b43_nphy_poll_rssi(struct b43_wldev *dev, enum n_rssi_type rssi_type, 1953 s32 *buf, u8 nsamp) 1954{ 1955 int i; 1956 int out; 1957 u16 save_regs_phy[9]; 1958 u16 s[2]; 1959 1960 /* TODO: rev7+ is treated like rev3+, what about rev19+? */ 1961 1962 if (dev->phy.rev >= 3) { 1963 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 1964 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 1965 save_regs_phy[2] = b43_phy_read(dev, 1966 B43_NPHY_RFCTL_LUT_TRSW_UP1); 1967 save_regs_phy[3] = b43_phy_read(dev, 1968 B43_NPHY_RFCTL_LUT_TRSW_UP2); 1969 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 1970 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 1971 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0); 1972 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1); 1973 save_regs_phy[8] = 0; 1974 } else { 1975 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 1976 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 1977 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 1978 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD); 1979 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 1980 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 1981 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 1982 save_regs_phy[7] = 0; 1983 save_regs_phy[8] = 0; 1984 } 1985 1986 b43_nphy_rssi_select(dev, 5, rssi_type); 1987 1988 if (dev->phy.rev < 2) { 1989 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); 1990 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5); 1991 } 1992 1993 for (i = 0; i < 4; i++) 1994 buf[i] = 0; 1995 1996 for (i = 0; i < nsamp; i++) { 1997 if (dev->phy.rev < 2) { 1998 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); 1999 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); 2000 } else { 2001 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); 2002 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2); 2003 } 2004 2005 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; 2006 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; 2007 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2; 2008 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; 2009 } 2010 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | 2011 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); 2012 2013 if (dev->phy.rev < 2) 2014 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); 2015 2016 if (dev->phy.rev >= 3) { 2017 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); 2018 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); 2019 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 2020 save_regs_phy[2]); 2021 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 2022 save_regs_phy[3]); 2023 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); 2024 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); 2025 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); 2026 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); 2027 } else { 2028 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); 2029 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); 2030 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); 2031 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); 2032 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); 2033 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); 2034 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); 2035 } 2036 2037 return out; 2038} 2039 2040/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ 2041static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) 2042{ 2043 struct b43_phy *phy = &dev->phy; 2044 struct b43_phy_n *nphy = dev->phy.n; 2045 2046 u16 saved_regs_phy_rfctl[2]; 2047 u16 saved_regs_phy[22]; 2048 u16 regs_to_store_rev3[] = { 2049 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER, 2050 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2, 2051 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER, 2052 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1, 2053 B43_NPHY_RFCTL_CMD, 2054 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2, 2055 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2 2056 }; 2057 u16 regs_to_store_rev7[] = { 2058 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER, 2059 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2, 2060 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER, 2061 B43_NPHY_REV7_RF_CTL_OVER3, B43_NPHY_REV7_RF_CTL_OVER4, 2062 B43_NPHY_REV7_RF_CTL_OVER5, B43_NPHY_REV7_RF_CTL_OVER6, 2063 0x2ff, 2064 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1, 2065 B43_NPHY_RFCTL_CMD, 2066 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2, 2067 B43_NPHY_REV7_RF_CTL_MISC_REG3, B43_NPHY_REV7_RF_CTL_MISC_REG4, 2068 B43_NPHY_REV7_RF_CTL_MISC_REG5, B43_NPHY_REV7_RF_CTL_MISC_REG6, 2069 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2 2070 }; 2071 u16 *regs_to_store; 2072 int regs_amount; 2073 2074 u16 class; 2075 2076 u16 clip_state[2]; 2077 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; 2078 2079 u8 vcm_final = 0; 2080 s32 offset[4]; 2081 s32 results[8][4] = { }; 2082 s32 results_min[4] = { }; 2083 s32 poll_results[4] = { }; 2084 2085 u16 *rssical_radio_regs = NULL; 2086 u16 *rssical_phy_regs = NULL; 2087 2088 u16 r; /* routing */ 2089 u8 rx_core_state; 2090 int core, i, j, vcm; 2091 2092 if (dev->phy.rev >= 7) { 2093 regs_to_store = regs_to_store_rev7; 2094 regs_amount = ARRAY_SIZE(regs_to_store_rev7); 2095 } else { 2096 regs_to_store = regs_to_store_rev3; 2097 regs_amount = ARRAY_SIZE(regs_to_store_rev3); 2098 } 2099 BUG_ON(regs_amount > ARRAY_SIZE(saved_regs_phy)); 2100 2101 class = b43_nphy_classifier(dev, 0, 0); 2102 b43_nphy_classifier(dev, 7, 4); 2103 b43_nphy_read_clip_detection(dev, clip_state); 2104 b43_nphy_write_clip_detection(dev, clip_off); 2105 2106 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2107 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2108 for (i = 0; i < regs_amount; i++) 2109 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]); 2110 2111 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_OFF, 0, 7); 2112 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 1, 7); 2113 2114 if (dev->phy.rev >= 7) { 2115 b43_nphy_rf_ctl_override_one_to_many(dev, 2116 N_RF_CTL_OVER_CMD_RXRF_PU, 2117 0, 0, false); 2118 b43_nphy_rf_ctl_override_one_to_many(dev, 2119 N_RF_CTL_OVER_CMD_RX_PU, 2120 1, 0, false); 2121 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 1, 0, false, 0); 2122 b43_nphy_rf_ctl_override_rev7(dev, 0x40, 1, 0, false, 0); 2123 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2124 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 0, 0, false, 2125 0); 2126 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 1, 0, false, 2127 0); 2128 } else { 2129 b43_nphy_rf_ctl_override_rev7(dev, 0x10, 0, 0, false, 2130 0); 2131 b43_nphy_rf_ctl_override_rev7(dev, 0x20, 1, 0, false, 2132 0); 2133 } 2134 } else { 2135 b43_nphy_rf_ctl_override(dev, 0x1, 0, 0, false); 2136 b43_nphy_rf_ctl_override(dev, 0x2, 1, 0, false); 2137 b43_nphy_rf_ctl_override(dev, 0x80, 1, 0, false); 2138 b43_nphy_rf_ctl_override(dev, 0x40, 1, 0, false); 2139 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 2140 b43_nphy_rf_ctl_override(dev, 0x20, 0, 0, false); 2141 b43_nphy_rf_ctl_override(dev, 0x10, 1, 0, false); 2142 } else { 2143 b43_nphy_rf_ctl_override(dev, 0x10, 0, 0, false); 2144 b43_nphy_rf_ctl_override(dev, 0x20, 1, 0, false); 2145 } 2146 } 2147 2148 rx_core_state = b43_nphy_get_rx_core_state(dev); 2149 for (core = 0; core < 2; core++) { 2150 if (!(rx_core_state & (1 << core))) 2151 continue; 2152 r = core ? B2056_RX1 : B2056_RX0; 2153 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_I, 2154 N_RSSI_NB); 2155 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, N_RAIL_Q, 2156 N_RSSI_NB); 2157 2158 /* Grab RSSI results for every possible VCM */ 2159 for (vcm = 0; vcm < 8; vcm++) { 2160 if (dev->phy.rev >= 7) 2161 b43_radio_maskset(dev, 2162 core ? R2057_NB_MASTER_CORE1 : 2163 R2057_NB_MASTER_CORE0, 2164 ~R2057_VCM_MASK, vcm); 2165 else 2166 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 2167 0xE3, vcm << 2); 2168 b43_nphy_poll_rssi(dev, N_RSSI_NB, results[vcm], 8); 2169 } 2170 2171 /* Find out which VCM got the best results */ 2172 for (i = 0; i < 4; i += 2) { 2173 s32 currd; 2174 s32 mind = 0x100000; 2175 s32 minpoll = 249; 2176 u8 minvcm = 0; 2177 if (2 * core != i) 2178 continue; 2179 for (vcm = 0; vcm < 8; vcm++) { 2180 currd = results[vcm][i] * results[vcm][i] + 2181 results[vcm][i + 1] * results[vcm][i]; 2182 if (currd < mind) { 2183 mind = currd; 2184 minvcm = vcm; 2185 } 2186 if (results[vcm][i] < minpoll) 2187 minpoll = results[vcm][i]; 2188 } 2189 vcm_final = minvcm; 2190 results_min[i] = minpoll; 2191 } 2192 2193 /* Select the best VCM */ 2194 if (dev->phy.rev >= 7) 2195 b43_radio_maskset(dev, 2196 core ? R2057_NB_MASTER_CORE1 : 2197 R2057_NB_MASTER_CORE0, 2198 ~R2057_VCM_MASK, vcm); 2199 else 2200 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 2201 0xE3, vcm_final << 2); 2202 2203 for (i = 0; i < 4; i++) { 2204 if (core != i / 2) 2205 continue; 2206 offset[i] = -results[vcm_final][i]; 2207 if (offset[i] < 0) 2208 offset[i] = -((abs(offset[i]) + 4) / 8); 2209 else 2210 offset[i] = (offset[i] + 4) / 8; 2211 if (results_min[i] == 248) 2212 offset[i] = -32; 2213 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2214 (i / 2 == 0) ? 1 : 2, 2215 (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q, 2216 N_RSSI_NB); 2217 } 2218 } 2219 2220 for (core = 0; core < 2; core++) { 2221 if (!(rx_core_state & (1 << core))) 2222 continue; 2223 for (i = 0; i < 2; i++) { 2224 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 2225 N_RAIL_I, i); 2226 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 2227 N_RAIL_Q, i); 2228 b43_nphy_poll_rssi(dev, i, poll_results, 8); 2229 for (j = 0; j < 4; j++) { 2230 if (j / 2 == core) { 2231 offset[j] = 232 - poll_results[j]; 2232 if (offset[j] < 0) 2233 offset[j] = -(abs(offset[j] + 4) / 8); 2234 else 2235 offset[j] = (offset[j] + 4) / 8; 2236 b43_nphy_scale_offset_rssi(dev, 0, 2237 offset[2 * core], core + 1, j % 2, i); 2238 } 2239 } 2240 } 2241 } 2242 2243 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); 2244 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); 2245 2246 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 2247 2248 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1); 2249 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START); 2250 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1); 2251 2252 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1); 2253 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX); 2254 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1); 2255 2256 for (i = 0; i < regs_amount; i++) 2257 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]); 2258 2259 /* Store for future configuration */ 2260 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2261 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; 2262 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; 2263 } else { 2264 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 2265 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 2266 } 2267 if (dev->phy.rev >= 7) { 2268 rssical_radio_regs[0] = b43_radio_read(dev, 2269 R2057_NB_MASTER_CORE0); 2270 rssical_radio_regs[1] = b43_radio_read(dev, 2271 R2057_NB_MASTER_CORE1); 2272 } else { 2273 rssical_radio_regs[0] = b43_radio_read(dev, B2056_RX0 | 2274 B2056_RX_RSSI_MISC); 2275 rssical_radio_regs[1] = b43_radio_read(dev, B2056_RX1 | 2276 B2056_RX_RSSI_MISC); 2277 } 2278 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z); 2279 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z); 2280 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z); 2281 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z); 2282 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X); 2283 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X); 2284 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X); 2285 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X); 2286 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y); 2287 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y); 2288 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y); 2289 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y); 2290 2291 /* Remember for which channel we store configuration */ 2292 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 2293 nphy->rssical_chanspec_2G.center_freq = phy->chandef->chan->center_freq; 2294 else 2295 nphy->rssical_chanspec_5G.center_freq = phy->chandef->chan->center_freq; 2296 2297 /* End of calibration, restore configuration */ 2298 b43_nphy_classifier(dev, 7, class); 2299 b43_nphy_write_clip_detection(dev, clip_state); 2300} 2301 2302/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ 2303static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type) 2304{ 2305 int i, j, vcm; 2306 u8 state[4]; 2307 u8 code, val; 2308 u16 class, override; 2309 u8 regs_save_radio[2]; 2310 u16 regs_save_phy[2]; 2311 2312 s32 offset[4]; 2313 u8 core; 2314 u8 rail; 2315 2316 u16 clip_state[2]; 2317 u16 clip_off[2] = { 0xFFFF, 0xFFFF }; 2318 s32 results_min[4] = { }; 2319 u8 vcm_final[4] = { }; 2320 s32 results[4][4] = { }; 2321 s32 miniq[4][2] = { }; 2322 2323 if (type == N_RSSI_NB) { 2324 code = 0; 2325 val = 6; 2326 } else if (type == N_RSSI_W1 || type == N_RSSI_W2) { 2327 code = 25; 2328 val = 4; 2329 } else { 2330 B43_WARN_ON(1); 2331 return; 2332 } 2333 2334 class = b43_nphy_classifier(dev, 0, 0); 2335 b43_nphy_classifier(dev, 7, 4); 2336 b43_nphy_read_clip_detection(dev, clip_state); 2337 b43_nphy_write_clip_detection(dev, clip_off); 2338 2339 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 2340 override = 0x140; 2341 else 2342 override = 0x110; 2343 2344 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 2345 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX); 2346 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 2347 b43_radio_write(dev, B2055_C1_PD_RXTX, val); 2348 2349 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 2350 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX); 2351 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 2352 b43_radio_write(dev, B2055_C2_PD_RXTX, val); 2353 2354 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07; 2355 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07; 2356 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 2357 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 2358 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07; 2359 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07; 2360 2361 b43_nphy_rssi_select(dev, 5, type); 2362 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); 2363 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_Q, type); 2364 2365 for (vcm = 0; vcm < 4; vcm++) { 2366 u8 tmp[4]; 2367 for (j = 0; j < 4; j++) 2368 tmp[j] = vcm; 2369 if (type != N_RSSI_W2) 2370 b43_nphy_set_rssi_2055_vcm(dev, type, tmp); 2371 b43_nphy_poll_rssi(dev, type, results[vcm], 8); 2372 if (type == N_RSSI_W1 || type == N_RSSI_W2) 2373 for (j = 0; j < 2; j++) 2374 miniq[vcm][j] = min(results[vcm][2 * j], 2375 results[vcm][2 * j + 1]); 2376 } 2377 2378 for (i = 0; i < 4; i++) { 2379 s32 mind = 0x100000; 2380 u8 minvcm = 0; 2381 s32 minpoll = 249; 2382 s32 currd; 2383 for (vcm = 0; vcm < 4; vcm++) { 2384 if (type == N_RSSI_NB) 2385 currd = abs(results[vcm][i] - code * 8); 2386 else 2387 currd = abs(miniq[vcm][i / 2] - code * 8); 2388 2389 if (currd < mind) { 2390 mind = currd; 2391 minvcm = vcm; 2392 } 2393 2394 if (results[vcm][i] < minpoll) 2395 minpoll = results[vcm][i]; 2396 } 2397 results_min[i] = minpoll; 2398 vcm_final[i] = minvcm; 2399 } 2400 2401 if (type != N_RSSI_W2) 2402 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); 2403 2404 for (i = 0; i < 4; i++) { 2405 offset[i] = (code * 8) - results[vcm_final[i]][i]; 2406 2407 if (offset[i] < 0) 2408 offset[i] = -((abs(offset[i]) + 4) / 8); 2409 else 2410 offset[i] = (offset[i] + 4) / 8; 2411 2412 if (results_min[i] == 248) 2413 offset[i] = code - 32; 2414 2415 core = (i / 2) ? 2 : 1; 2416 rail = (i % 2) ? N_RAIL_Q : N_RAIL_I; 2417 2418 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, 2419 type); 2420 } 2421 2422 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); 2423 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); 2424 2425 switch (state[2]) { 2426 case 1: 2427 b43_nphy_rssi_select(dev, 1, N_RSSI_NB); 2428 break; 2429 case 4: 2430 b43_nphy_rssi_select(dev, 1, N_RSSI_W1); 2431 break; 2432 case 2: 2433 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); 2434 break; 2435 default: 2436 b43_nphy_rssi_select(dev, 1, N_RSSI_W2); 2437 break; 2438 } 2439 2440 switch (state[3]) { 2441 case 1: 2442 b43_nphy_rssi_select(dev, 2, N_RSSI_NB); 2443 break; 2444 case 4: 2445 b43_nphy_rssi_select(dev, 2, N_RSSI_W1); 2446 break; 2447 default: 2448 b43_nphy_rssi_select(dev, 2, N_RSSI_W2); 2449 break; 2450 } 2451 2452 b43_nphy_rssi_select(dev, 0, type); 2453 2454 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 2455 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 2456 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 2457 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 2458 2459 b43_nphy_classifier(dev, 7, class); 2460 b43_nphy_write_clip_detection(dev, clip_state); 2461 /* Specs don't say about reset here, but it makes wl and b43 dumps 2462 identical, it really seems wl performs this */ 2463 b43_nphy_reset_cca(dev); 2464} 2465 2466/* 2467 * RSSI Calibration 2468 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal 2469 */ 2470static void b43_nphy_rssi_cal(struct b43_wldev *dev) 2471{ 2472 if (dev->phy.rev >= 19) { 2473 /* TODO */ 2474 } else if (dev->phy.rev >= 3) { 2475 b43_nphy_rev3_rssi_cal(dev); 2476 } else { 2477 b43_nphy_rev2_rssi_cal(dev, N_RSSI_NB); 2478 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W1); 2479 b43_nphy_rev2_rssi_cal(dev, N_RSSI_W2); 2480 } 2481} 2482 2483/************************************************** 2484 * Workarounds 2485 **************************************************/ 2486 2487static void b43_nphy_gain_ctl_workarounds_rev19(struct b43_wldev *dev) 2488{ 2489 /* TODO */ 2490} 2491 2492static void b43_nphy_gain_ctl_workarounds_rev7(struct b43_wldev *dev) 2493{ 2494 struct b43_phy *phy = &dev->phy; 2495 2496 switch (phy->rev) { 2497 /* TODO */ 2498 } 2499} 2500 2501static void b43_nphy_gain_ctl_workarounds_rev3(struct b43_wldev *dev) 2502{ 2503 struct ssb_sprom *sprom = dev->dev->bus_sprom; 2504 2505 bool ghz5; 2506 bool ext_lna; 2507 u16 rssi_gain; 2508 struct nphy_gain_ctl_workaround_entry *e; 2509 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; 2510 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; 2511 2512 /* Prepare values */ 2513 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL) 2514 & B43_NPHY_BANDCTL_5GHZ; 2515 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ : 2516 sprom->boardflags_lo & B43_BFL_EXTLNA; 2517 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna); 2518 if (ghz5 && dev->phy.rev >= 5) 2519 rssi_gain = 0x90; 2520 else 2521 rssi_gain = 0x50; 2522 2523 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); 2524 2525 /* Set Clip 2 detect */ 2526 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); 2527 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); 2528 2529 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, 2530 0x17); 2531 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, 2532 0x17); 2533 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); 2534 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); 2535 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); 2536 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); 2537 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN, 2538 rssi_gain); 2539 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN, 2540 rssi_gain); 2541 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, 2542 0x17); 2543 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, 2544 0x17); 2545 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); 2546 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); 2547 2548 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); 2549 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain); 2550 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); 2551 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain); 2552 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); 2553 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db); 2554 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits); 2555 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits); 2556 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain); 2557 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain); 2558 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); 2559 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); 2560 2561 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain); 2562 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain); 2563 2564 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, 2565 e->rfseq_init); 2566 2567 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); 2568 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); 2569 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); 2570 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); 2571 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); 2572 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); 2573 2574 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); 2575 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); 2576 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); 2577 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); 2578 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); 2579 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 2580 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip); 2581 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 2582 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip); 2583 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); 2584} 2585 2586static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev) 2587{ 2588 struct b43_phy_n *nphy = dev->phy.n; 2589 2590 u8 i, j; 2591 u8 code; 2592 u16 tmp; 2593 u8 rfseq_events[3] = { 6, 8, 7 }; 2594 u8 rfseq_delays[3] = { 10, 30, 1 }; 2595 2596 /* Set Clip 2 detect */ 2597 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT); 2598 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT); 2599 2600 /* Set narrowband clip threshold */ 2601 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); 2602 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); 2603 2604 if (!b43_is_40mhz(dev)) { 2605 /* Set dwell lengths */ 2606 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); 2607 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); 2608 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009); 2609 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009); 2610 } 2611 2612 /* Set wideband clip 2 threshold */ 2613 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 2614 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21); 2615 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 2616 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21); 2617 2618 if (!b43_is_40mhz(dev)) { 2619 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, 2620 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); 2621 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, 2622 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); 2623 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, 2624 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); 2625 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, 2626 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); 2627 } 2628 2629 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); 2630 2631 if (nphy->gain_boost) { 2632 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && 2633 b43_is_40mhz(dev)) 2634 code = 4; 2635 else 2636 code = 5; 2637 } else { 2638 code = b43_is_40mhz(dev) ? 6 : 7; 2639 } 2640 2641 /* Set HPVGA2 index */ 2642 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2, 2643 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT); 2644 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2, 2645 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT); 2646 2647 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 2648 /* specs say about 2 loops, but wl does 4 */ 2649 for (i = 0; i < 4; i++) 2650 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); 2651 2652 b43_nphy_adjust_lna_gain_table(dev); 2653 2654 if (nphy->elna_gain_config) { 2655 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); 2656 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 2657 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2658 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2659 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2660 2661 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); 2662 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); 2663 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2664 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2665 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); 2666 2667 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); 2668 /* specs say about 2 loops, but wl does 4 */ 2669 for (i = 0; i < 4; i++) 2670 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 2671 (code << 8 | 0x74)); 2672 } 2673 2674 if (dev->phy.rev == 2) { 2675 for (i = 0; i < 4; i++) { 2676 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 2677 (0x0400 * i) + 0x0020); 2678 for (j = 0; j < 21; j++) { 2679 tmp = j * (i < 2 ? 3 : 1); 2680 b43_phy_write(dev, 2681 B43_NPHY_TABLE_DATALO, tmp); 2682 } 2683 } 2684 } 2685 2686 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3); 2687 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, 2688 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, 2689 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); 2690 2691 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 2692 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); 2693} 2694 2695/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ 2696static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) 2697{ 2698 if (dev->phy.rev >= 19) 2699 b43_nphy_gain_ctl_workarounds_rev19(dev); 2700 else if (dev->phy.rev >= 7) 2701 b43_nphy_gain_ctl_workarounds_rev7(dev); 2702 else if (dev->phy.rev >= 3) 2703 b43_nphy_gain_ctl_workarounds_rev3(dev); 2704 else 2705 b43_nphy_gain_ctl_workarounds_rev1_2(dev); 2706} 2707 2708static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev) 2709{ 2710 struct ssb_sprom *sprom = dev->dev->bus_sprom; 2711 struct b43_phy *phy = &dev->phy; 2712 2713 /* TX to RX */ 2714 u8 tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, }; 2715 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, }; 2716 /* RX to TX */ 2717 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, 2718 0x1F }; 2719 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; 2720 2721 static const u16 ntab7_15e_16e[] = { 0, 0x10f, 0x10f }; 2722 u8 ntab7_138_146[] = { 0x11, 0x11 }; 2723 u8 ntab7_133[] = { 0x77, 0x11, 0x11 }; 2724 2725 u16 lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2]; 2726 u16 bcap_val; 2727 s16 bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2]; 2728 u16 scap_val; 2729 s16 scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2]; 2730 bool rccal_ovrd = false; 2731 2732 u16 bias, conv, filt; 2733 2734 u32 noise_tbl[2]; 2735 2736 u32 tmp32; 2737 u8 core; 2738 2739 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); 2740 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01b3); 2741 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); 2742 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016e); 2743 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00cd); 2744 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); 2745 2746 if (phy->rev == 7) { 2747 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 0x10); 2748 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0xFF80, 0x0020); 2749 b43_phy_maskset(dev, B43_NPHY_FREQGAIN0, 0x80FF, 0x2700); 2750 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0xFF80, 0x002E); 2751 b43_phy_maskset(dev, B43_NPHY_FREQGAIN1, 0x80FF, 0x3300); 2752 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0xFF80, 0x0037); 2753 b43_phy_maskset(dev, B43_NPHY_FREQGAIN2, 0x80FF, 0x3A00); 2754 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0xFF80, 0x003C); 2755 b43_phy_maskset(dev, B43_NPHY_FREQGAIN3, 0x80FF, 0x3E00); 2756 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0xFF80, 0x003E); 2757 b43_phy_maskset(dev, B43_NPHY_FREQGAIN4, 0x80FF, 0x3F00); 2758 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0xFF80, 0x0040); 2759 b43_phy_maskset(dev, B43_NPHY_FREQGAIN5, 0x80FF, 0x4000); 2760 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0xFF80, 0x0040); 2761 b43_phy_maskset(dev, B43_NPHY_FREQGAIN6, 0x80FF, 0x4000); 2762 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0xFF80, 0x0040); 2763 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); 2764 } 2765 2766 if (phy->rev >= 16) { 2767 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x7ff); 2768 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x7ff); 2769 } else if (phy->rev <= 8) { 2770 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0); 2771 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0); 2772 } 2773 2774 if (phy->rev >= 16) 2775 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0xa0); 2776 else if (phy->rev >= 8) 2777 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); 2778 2779 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 2); 2780 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 2); 2781 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 2782 tmp32 &= 0xffffff; 2783 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); 2784 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x15d), 3, ntab7_15e_16e); 2785 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x16d), 3, ntab7_15e_16e); 2786 2787 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 2788 ARRAY_SIZE(tx2rx_events)); 2789 if (b43_nphy_ipa(dev)) 2790 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 2791 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 2792 2793 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); 2794 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); 2795 2796 for (core = 0; core < 2; core++) { 2797 lpf_ofdm_20mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x154 + core * 0x10); 2798 lpf_ofdm_40mhz[core] = b43_nphy_read_lpf_ctl(dev, 0x159 + core * 0x10); 2799 lpf_11b[core] = b43_nphy_read_lpf_ctl(dev, 0x152 + core * 0x10); 2800 } 2801 2802 bcap_val = b43_radio_read(dev, R2057_RCCAL_BCAP_VAL); 2803 scap_val = b43_radio_read(dev, R2057_RCCAL_SCAP_VAL); 2804 2805 if (b43_nphy_ipa(dev)) { 2806 bool ghz2 = b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ; 2807 2808 switch (phy->radio_rev) { 2809 case 5: 2810 /* Check radio version (to be 0) by PHY rev for now */ 2811 if (phy->rev == 8 && b43_is_40mhz(dev)) { 2812 for (core = 0; core < 2; core++) { 2813 scap_val_11b[core] = scap_val; 2814 bcap_val_11b[core] = bcap_val; 2815 scap_val_11n_20[core] = scap_val; 2816 bcap_val_11n_20[core] = bcap_val; 2817 scap_val_11n_40[core] = 0xc; 2818 bcap_val_11n_40[core] = 0xc; 2819 } 2820 2821 rccal_ovrd = true; 2822 } 2823 if (phy->rev == 9) { 2824 /* TODO: Radio version 1 (e.g. BCM5357B0) */ 2825 } 2826 break; 2827 case 7: 2828 case 8: 2829 for (core = 0; core < 2; core++) { 2830 scap_val_11b[core] = scap_val; 2831 bcap_val_11b[core] = bcap_val; 2832 lpf_ofdm_20mhz[core] = 4; 2833 lpf_11b[core] = 1; 2834 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2835 scap_val_11n_20[core] = 0xc; 2836 bcap_val_11n_20[core] = 0xc; 2837 scap_val_11n_40[core] = 0xa; 2838 bcap_val_11n_40[core] = 0xa; 2839 } else { 2840 scap_val_11n_20[core] = 0x14; 2841 bcap_val_11n_20[core] = 0x14; 2842 scap_val_11n_40[core] = 0xf; 2843 bcap_val_11n_40[core] = 0xf; 2844 } 2845 } 2846 2847 rccal_ovrd = true; 2848 break; 2849 case 9: 2850 for (core = 0; core < 2; core++) { 2851 bcap_val_11b[core] = bcap_val; 2852 scap_val_11b[core] = scap_val; 2853 lpf_11b[core] = 1; 2854 2855 if (ghz2) { 2856 bcap_val_11n_20[core] = bcap_val + 13; 2857 scap_val_11n_20[core] = scap_val + 15; 2858 } else { 2859 bcap_val_11n_20[core] = bcap_val + 14; 2860 scap_val_11n_20[core] = scap_val + 15; 2861 } 2862 lpf_ofdm_20mhz[core] = 4; 2863 2864 if (ghz2) { 2865 bcap_val_11n_40[core] = bcap_val - 7; 2866 scap_val_11n_40[core] = scap_val - 5; 2867 } else { 2868 bcap_val_11n_40[core] = bcap_val + 2; 2869 scap_val_11n_40[core] = scap_val + 4; 2870 } 2871 lpf_ofdm_40mhz[core] = 4; 2872 } 2873 2874 rccal_ovrd = true; 2875 break; 2876 case 14: 2877 for (core = 0; core < 2; core++) { 2878 bcap_val_11b[core] = bcap_val; 2879 scap_val_11b[core] = scap_val; 2880 lpf_11b[core] = 1; 2881 } 2882 2883 bcap_val_11n_20[0] = bcap_val + 20; 2884 scap_val_11n_20[0] = scap_val + 20; 2885 lpf_ofdm_20mhz[0] = 3; 2886 2887 bcap_val_11n_20[1] = bcap_val + 16; 2888 scap_val_11n_20[1] = scap_val + 16; 2889 lpf_ofdm_20mhz[1] = 3; 2890 2891 bcap_val_11n_40[0] = bcap_val + 20; 2892 scap_val_11n_40[0] = scap_val + 20; 2893 lpf_ofdm_40mhz[0] = 4; 2894 2895 bcap_val_11n_40[1] = bcap_val + 10; 2896 scap_val_11n_40[1] = scap_val + 10; 2897 lpf_ofdm_40mhz[1] = 4; 2898 2899 rccal_ovrd = true; 2900 break; 2901 } 2902 } else { 2903 if (phy->radio_rev == 5) { 2904 for (core = 0; core < 2; core++) { 2905 lpf_ofdm_20mhz[core] = 1; 2906 lpf_ofdm_40mhz[core] = 3; 2907 scap_val_11b[core] = scap_val; 2908 bcap_val_11b[core] = bcap_val; 2909 scap_val_11n_20[core] = 0x11; 2910 scap_val_11n_40[core] = 0x11; 2911 bcap_val_11n_20[core] = 0x13; 2912 bcap_val_11n_40[core] = 0x13; 2913 } 2914 2915 rccal_ovrd = true; 2916 } 2917 } 2918 if (rccal_ovrd) { 2919 u16 rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2]; 2920 u8 rx2tx_lut_extra = 1; 2921 2922 for (core = 0; core < 2; core++) { 2923 bcap_val_11b[core] = clamp_val(bcap_val_11b[core], 0, 0x1f); 2924 scap_val_11b[core] = clamp_val(scap_val_11b[core], 0, 0x1f); 2925 bcap_val_11n_20[core] = clamp_val(bcap_val_11n_20[core], 0, 0x1f); 2926 scap_val_11n_20[core] = clamp_val(scap_val_11n_20[core], 0, 0x1f); 2927 bcap_val_11n_40[core] = clamp_val(bcap_val_11n_40[core], 0, 0x1f); 2928 scap_val_11n_40[core] = clamp_val(scap_val_11n_40[core], 0, 0x1f); 2929 2930 rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) | 2931 (bcap_val_11b[core] << 8) | 2932 (scap_val_11b[core] << 3) | 2933 lpf_11b[core]; 2934 rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) | 2935 (bcap_val_11n_20[core] << 8) | 2936 (scap_val_11n_20[core] << 3) | 2937 lpf_ofdm_20mhz[core]; 2938 rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) | 2939 (bcap_val_11n_40[core] << 8) | 2940 (scap_val_11n_40[core] << 3) | 2941 lpf_ofdm_40mhz[core]; 2942 } 2943 2944 for (core = 0; core < 2; core++) { 2945 b43_ntab_write(dev, B43_NTAB16(7, 0x152 + core * 16), 2946 rx2tx_lut_20_11b[core]); 2947 b43_ntab_write(dev, B43_NTAB16(7, 0x153 + core * 16), 2948 rx2tx_lut_20_11n[core]); 2949 b43_ntab_write(dev, B43_NTAB16(7, 0x154 + core * 16), 2950 rx2tx_lut_20_11n[core]); 2951 b43_ntab_write(dev, B43_NTAB16(7, 0x155 + core * 16), 2952 rx2tx_lut_40_11n[core]); 2953 b43_ntab_write(dev, B43_NTAB16(7, 0x156 + core * 16), 2954 rx2tx_lut_40_11n[core]); 2955 b43_ntab_write(dev, B43_NTAB16(7, 0x157 + core * 16), 2956 rx2tx_lut_40_11n[core]); 2957 b43_ntab_write(dev, B43_NTAB16(7, 0x158 + core * 16), 2958 rx2tx_lut_40_11n[core]); 2959 b43_ntab_write(dev, B43_NTAB16(7, 0x159 + core * 16), 2960 rx2tx_lut_40_11n[core]); 2961 } 2962 } 2963 2964 b43_phy_write(dev, 0x32F, 0x3); 2965 2966 if (phy->radio_rev == 4 || phy->radio_rev == 6) 2967 b43_nphy_rf_ctl_override_rev7(dev, 4, 1, 3, false, 0); 2968 2969 if (phy->radio_rev == 3 || phy->radio_rev == 4 || phy->radio_rev == 6) { 2970 if (sprom->revision && 2971 sprom->boardflags2_hi & B43_BFH2_IPALVLSHIFT_3P3) { 2972 b43_radio_write(dev, 0x5, 0x05); 2973 b43_radio_write(dev, 0x6, 0x30); 2974 b43_radio_write(dev, 0x7, 0x00); 2975 b43_radio_set(dev, 0x4f, 0x1); 2976 b43_radio_set(dev, 0xd4, 0x1); 2977 bias = 0x1f; 2978 conv = 0x6f; 2979 filt = 0xaa; 2980 } else { 2981 bias = 0x2b; 2982 conv = 0x7f; 2983 filt = 0xee; 2984 } 2985 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 2986 for (core = 0; core < 2; core++) { 2987 if (core == 0) { 2988 b43_radio_write(dev, 0x5F, bias); 2989 b43_radio_write(dev, 0x64, conv); 2990 b43_radio_write(dev, 0x66, filt); 2991 } else { 2992 b43_radio_write(dev, 0xE8, bias); 2993 b43_radio_write(dev, 0xE9, conv); 2994 b43_radio_write(dev, 0xEB, filt); 2995 } 2996 } 2997 } 2998 } 2999 3000 if (b43_nphy_ipa(dev)) { 3001 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 3002 if (phy->radio_rev == 3 || phy->radio_rev == 4 || 3003 phy->radio_rev == 6) { 3004 for (core = 0; core < 2; core++) { 3005 if (core == 0) 3006 b43_radio_write(dev, 0x51, 3007 0x7f); 3008 else 3009 b43_radio_write(dev, 0xd6, 3010 0x7f); 3011 } 3012 } 3013 switch (phy->radio_rev) { 3014 case 3: 3015 for (core = 0; core < 2; core++) { 3016 if (core == 0) { 3017 b43_radio_write(dev, 0x64, 3018 0x13); 3019 b43_radio_write(dev, 0x5F, 3020 0x1F); 3021 b43_radio_write(dev, 0x66, 3022 0xEE); 3023 b43_radio_write(dev, 0x59, 3024 0x8A); 3025 b43_radio_write(dev, 0x80, 3026 0x3E); 3027 } else { 3028 b43_radio_write(dev, 0x69, 3029 0x13); 3030 b43_radio_write(dev, 0xE8, 3031 0x1F); 3032 b43_radio_write(dev, 0xEB, 3033 0xEE); 3034 b43_radio_write(dev, 0xDE, 3035 0x8A); 3036 b43_radio_write(dev, 0x105, 3037 0x3E); 3038 } 3039 } 3040 break; 3041 case 7: 3042 case 8: 3043 if (!b43_is_40mhz(dev)) { 3044 b43_radio_write(dev, 0x5F, 0x14); 3045 b43_radio_write(dev, 0xE8, 0x12); 3046 } else { 3047 b43_radio_write(dev, 0x5F, 0x16); 3048 b43_radio_write(dev, 0xE8, 0x16); 3049 } 3050 break; 3051 case 14: 3052 for (core = 0; core < 2; core++) { 3053 int o = core ? 0x85 : 0; 3054 3055 b43_radio_write(dev, o + R2057_IPA2G_CASCONV_CORE0, 0x13); 3056 b43_radio_write(dev, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); 3057 b43_radio_write(dev, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); 3058 b43_radio_write(dev, o + R2057_PAD2G_IDACS_CORE0, 0x88); 3059 b43_radio_write(dev, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); 3060 b43_radio_write(dev, o + R2057_IPA2G_IMAIN_CORE0, 0x16); 3061 b43_radio_write(dev, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); 3062 b43_radio_write(dev, o + R2057_BACKUP1_CORE0, 0x10); 3063 } 3064 break; 3065 } 3066 } else { 3067 u16 freq = phy->chandef->chan->center_freq; 3068 if ((freq >= 5180 && freq <= 5230) || 3069 (freq >= 5745 && freq <= 5805)) { 3070 b43_radio_write(dev, 0x7D, 0xFF); 3071 b43_radio_write(dev, 0xFE, 0xFF); 3072 } 3073 } 3074 } else { 3075 if (phy->radio_rev != 5) { 3076 for (core = 0; core < 2; core++) { 3077 if (core == 0) { 3078 b43_radio_write(dev, 0x5c, 0x61); 3079 b43_radio_write(dev, 0x51, 0x70); 3080 } else { 3081 b43_radio_write(dev, 0xe1, 0x61); 3082 b43_radio_write(dev, 0xd6, 0x70); 3083 } 3084 } 3085 } 3086 } 3087 3088 if (phy->radio_rev == 4) { 3089 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0x20); 3090 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0x20); 3091 for (core = 0; core < 2; core++) { 3092 if (core == 0) { 3093 b43_radio_write(dev, 0x1a1, 0x00); 3094 b43_radio_write(dev, 0x1a2, 0x3f); 3095 b43_radio_write(dev, 0x1a6, 0x3f); 3096 } else { 3097 b43_radio_write(dev, 0x1a7, 0x00); 3098 b43_radio_write(dev, 0x1ab, 0x3f); 3099 b43_radio_write(dev, 0x1ac, 0x3f); 3100 } 3101 } 3102 } else { 3103 b43_phy_set(dev, B43_NPHY_AFECTL_C1, 0x4); 3104 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x4); 3105 b43_phy_set(dev, B43_NPHY_AFECTL_C2, 0x4); 3106 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4); 3107 3108 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x1); 3109 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x1); 3110 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x1); 3111 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x1); 3112 b43_ntab_write(dev, B43_NTAB16(8, 0x05), 0); 3113 b43_ntab_write(dev, B43_NTAB16(8, 0x15), 0); 3114 3115 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x4); 3116 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x4); 3117 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x4); 3118 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4); 3119 } 3120 3121 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, 0x2); 3122 3123 b43_ntab_write(dev, B43_NTAB32(16, 0x100), 20); 3124 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x138), 2, ntab7_138_146); 3125 b43_ntab_write(dev, B43_NTAB16(7, 0x141), 0x77); 3126 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x133), 3, ntab7_133); 3127 b43_ntab_write_bulk(dev, B43_NTAB8(7, 0x146), 2, ntab7_138_146); 3128 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); 3129 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); 3130 3131 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x02), 1, noise_tbl); 3132 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; 3133 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x02), 2, noise_tbl); 3134 3135 b43_ntab_read_bulk(dev, B43_NTAB32(16, 0x7E), 1, noise_tbl); 3136 noise_tbl[1] = b43_is_40mhz(dev) ? 0x14D : 0x18D; 3137 b43_ntab_write_bulk(dev, B43_NTAB32(16, 0x7E), 2, noise_tbl); 3138 3139 b43_nphy_gain_ctl_workarounds(dev); 3140 3141 /* TODO 3142 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, 3143 aux_adc_vmid_rev7_core0); 3144 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, 3145 aux_adc_vmid_rev7_core1); 3146 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0C), 4, 3147 aux_adc_gain_rev7); 3148 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1C), 4, 3149 aux_adc_gain_rev7); 3150 */ 3151} 3152 3153static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) 3154{ 3155 struct b43_phy_n *nphy = dev->phy.n; 3156 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3157 3158 /* TX to RX */ 3159 u8 tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F }; 3160 u8 tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 }; 3161 /* RX to TX */ 3162 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, 3163 0x1F }; 3164 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; 3165 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; 3166 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 }; 3167 3168 u16 vmids[5][4] = { 3169 { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */ 3170 { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */ 3171 { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */ 3172 { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */ 3173 { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */ 3174 }; 3175 u16 gains[5][4] = { 3176 { 0x02, 0x02, 0x02, 0x00, }, /* 0 */ 3177 { 0x02, 0x02, 0x02, 0x02, }, /* 1 */ 3178 { 0x02, 0x02, 0x02, 0x04, }, /* 2 */ 3179 { 0x02, 0x02, 0x02, 0x00, }, /* 3 */ 3180 { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */ 3181 }; 3182 u16 *vmid, *gain; 3183 3184 u8 pdet_range; 3185 u16 tmp16; 3186 u32 tmp32; 3187 3188 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8); 3189 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8); 3190 3191 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 3192 tmp32 &= 0xffffff; 3193 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32); 3194 3195 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); 3196 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); 3197 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); 3198 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); 3199 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); 3200 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); 3201 3202 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); 3203 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); 3204 3205 /* TX to RX */ 3206 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 3207 ARRAY_SIZE(tx2rx_events)); 3208 3209 /* RX to TX */ 3210 if (b43_nphy_ipa(dev)) 3211 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 3212 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 3213 if (nphy->hw_phyrxchain != 3 && 3214 nphy->hw_phyrxchain != nphy->hw_phytxchain) { 3215 if (b43_nphy_ipa(dev)) { 3216 rx2tx_delays[5] = 59; 3217 rx2tx_delays[6] = 1; 3218 rx2tx_events[7] = 0x1F; 3219 } 3220 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events, rx2tx_delays, 3221 ARRAY_SIZE(rx2tx_events)); 3222 } 3223 3224 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 3225 0x2 : 0x9C40; 3226 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); 3227 3228 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); 3229 3230 if (!b43_is_40mhz(dev)) { 3231 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); 3232 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); 3233 } else { 3234 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x14D); 3235 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x14D); 3236 } 3237 3238 b43_nphy_gain_ctl_workarounds(dev); 3239 3240 b43_ntab_write(dev, B43_NTAB16(8, 0), 2); 3241 b43_ntab_write(dev, B43_NTAB16(8, 16), 2); 3242 3243 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3244 pdet_range = sprom->fem.ghz2.pdet_range; 3245 else 3246 pdet_range = sprom->fem.ghz5.pdet_range; 3247 vmid = vmids[min_t(u16, pdet_range, 4)]; 3248 gain = gains[min_t(u16, pdet_range, 4)]; 3249 switch (pdet_range) { 3250 case 3: 3251 if (!(dev->phy.rev >= 4 && 3252 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) 3253 break; 3254 /* FALL THROUGH */ 3255 case 0: 3256 case 1: 3257 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); 3258 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); 3259 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); 3260 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); 3261 break; 3262 case 2: 3263 if (dev->phy.rev >= 6) { 3264 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3265 vmid[3] = 0x94; 3266 else 3267 vmid[3] = 0x8e; 3268 gain[3] = 3; 3269 } else if (dev->phy.rev == 5) { 3270 vmid[3] = 0x84; 3271 gain[3] = 2; 3272 } 3273 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); 3274 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); 3275 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); 3276 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); 3277 break; 3278 case 4: 3279 case 5: 3280 if (b43_current_band(dev->wl) != IEEE80211_BAND_2GHZ) { 3281 if (pdet_range == 4) { 3282 vmid[3] = 0x8e; 3283 tmp16 = 0x96; 3284 gain[3] = 0x2; 3285 } else { 3286 vmid[3] = 0x89; 3287 tmp16 = 0x89; 3288 gain[3] = 0; 3289 } 3290 } else { 3291 if (pdet_range == 4) { 3292 vmid[3] = 0x89; 3293 tmp16 = 0x8b; 3294 gain[3] = 0x2; 3295 } else { 3296 vmid[3] = 0x74; 3297 tmp16 = 0x70; 3298 gain[3] = 0; 3299 } 3300 } 3301 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x08), 4, vmid); 3302 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x0c), 4, gain); 3303 vmid[3] = tmp16; 3304 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x18), 4, vmid); 3305 b43_ntab_write_bulk(dev, B43_NTAB16(8, 0x1c), 4, gain); 3306 break; 3307 } 3308 3309 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); 3310 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); 3311 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); 3312 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); 3313 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); 3314 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); 3315 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); 3316 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); 3317 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); 3318 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); 3319 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); 3320 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); 3321 3322 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ 3323 3324 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR && 3325 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || 3326 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && 3327 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) 3328 tmp32 = 0x00088888; 3329 else 3330 tmp32 = 0x88888888; 3331 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); 3332 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); 3333 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); 3334 3335 if (dev->phy.rev == 4 && 3336 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 3337 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, 3338 0x70); 3339 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, 3340 0x70); 3341 } 3342 3343 /* Dropped probably-always-true condition */ 3344 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); 3345 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); 3346 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); 3347 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); 3348 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); 3349 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); 3350 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); 3351 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); 3352 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); 3353 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); 3354 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); 3355 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); 3356 3357 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) 3358 ; /* TODO: 0x0080000000000000 HF */ 3359} 3360 3361static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) 3362{ 3363 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3364 struct b43_phy *phy = &dev->phy; 3365 struct b43_phy_n *nphy = phy->n; 3366 3367 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; 3368 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; 3369 3370 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; 3371 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; 3372 3373 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 3374 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93) { 3375 delays1[0] = 0x1; 3376 delays1[5] = 0x14; 3377 } 3378 3379 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && 3380 nphy->band5g_pwrgain) { 3381 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); 3382 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); 3383 } else { 3384 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8); 3385 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8); 3386 } 3387 3388 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); 3389 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); 3390 if (dev->phy.rev < 3) { 3391 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); 3392 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); 3393 } 3394 3395 if (dev->phy.rev < 2) { 3396 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); 3397 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); 3398 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); 3399 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); 3400 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); 3401 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); 3402 } 3403 3404 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 3405 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 3406 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 3407 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 3408 3409 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7); 3410 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7); 3411 3412 b43_nphy_gain_ctl_workarounds(dev); 3413 3414 if (dev->phy.rev < 2) { 3415 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2) 3416 b43_hf_write(dev, b43_hf_read(dev) | 3417 B43_HF_MLADVW); 3418 } else if (dev->phy.rev == 2) { 3419 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0); 3420 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0); 3421 } 3422 3423 if (dev->phy.rev < 2) 3424 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL, 3425 ~B43_NPHY_SCRAM_SIGCTL_SCM); 3426 3427 /* Set phase track alpha and beta */ 3428 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125); 3429 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3); 3430 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105); 3431 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E); 3432 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD); 3433 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20); 3434 3435 if (dev->phy.rev < 3) { 3436 b43_phy_mask(dev, B43_NPHY_PIL_DW1, 3437 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF); 3438 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5); 3439 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4); 3440 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00); 3441 } 3442 3443 if (dev->phy.rev == 2) 3444 b43_phy_set(dev, B43_NPHY_FINERX2_CGC, 3445 B43_NPHY_FINERX2_CGC_DECGC); 3446} 3447 3448/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ 3449static void b43_nphy_workarounds(struct b43_wldev *dev) 3450{ 3451 struct b43_phy *phy = &dev->phy; 3452 struct b43_phy_n *nphy = phy->n; 3453 3454 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 3455 b43_nphy_classifier(dev, 1, 0); 3456 else 3457 b43_nphy_classifier(dev, 1, 1); 3458 3459 if (nphy->hang_avoid) 3460 b43_nphy_stay_in_carrier_search(dev, 1); 3461 3462 b43_phy_set(dev, B43_NPHY_IQFLIP, 3463 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); 3464 3465 /* TODO: rev19+ */ 3466 if (dev->phy.rev >= 7) 3467 b43_nphy_workarounds_rev7plus(dev); 3468 else if (dev->phy.rev >= 3) 3469 b43_nphy_workarounds_rev3plus(dev); 3470 else 3471 b43_nphy_workarounds_rev1_2(dev); 3472 3473 if (nphy->hang_avoid) 3474 b43_nphy_stay_in_carrier_search(dev, 0); 3475} 3476 3477/************************************************** 3478 * Tx/Rx common 3479 **************************************************/ 3480 3481/* 3482 * Transmits a known value for LO calibration 3483 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone 3484 */ 3485static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val, 3486 bool iqmode, bool dac_test, bool modify_bbmult) 3487{ 3488 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test); 3489 if (samp == 0) 3490 return -1; 3491 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test, 3492 modify_bbmult); 3493 return 0; 3494} 3495 3496/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ 3497static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) 3498{ 3499 struct b43_phy_n *nphy = dev->phy.n; 3500 3501 bool override = false; 3502 u16 chain = 0x33; 3503 3504 if (nphy->txrx_chain == 0) { 3505 chain = 0x11; 3506 override = true; 3507 } else if (nphy->txrx_chain == 1) { 3508 chain = 0x22; 3509 override = true; 3510 } 3511 3512 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 3513 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), 3514 chain); 3515 3516 if (override) 3517 b43_phy_set(dev, B43_NPHY_RFSEQMODE, 3518 B43_NPHY_RFSEQMODE_CAOVER); 3519 else 3520 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 3521 ~B43_NPHY_RFSEQMODE_CAOVER); 3522} 3523 3524/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ 3525static void b43_nphy_stop_playback(struct b43_wldev *dev) 3526{ 3527 struct b43_phy *phy = &dev->phy; 3528 struct b43_phy_n *nphy = dev->phy.n; 3529 u16 tmp; 3530 3531 if (nphy->hang_avoid) 3532 b43_nphy_stay_in_carrier_search(dev, 1); 3533 3534 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT); 3535 if (tmp & 0x1) 3536 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP); 3537 else if (tmp & 0x2) 3538 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); 3539 3540 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); 3541 3542 if (nphy->bb_mult_save & 0x80000000) { 3543 tmp = nphy->bb_mult_save & 0xFFFF; 3544 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); 3545 nphy->bb_mult_save = 0; 3546 } 3547 3548 if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) { 3549 if (phy->rev >= 19) 3550 b43_nphy_rf_ctl_override_rev19(dev, 0x80, 0, 0, true, 3551 1); 3552 else 3553 b43_nphy_rf_ctl_override_rev7(dev, 0x80, 0, 0, true, 1); 3554 nphy->lpf_bw_overrode_for_sample_play = false; 3555 } 3556 3557 if (nphy->hang_avoid) 3558 b43_nphy_stay_in_carrier_search(dev, 0); 3559} 3560 3561/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ 3562static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core, 3563 struct nphy_txgains target, 3564 struct nphy_iqcal_params *params) 3565{ 3566 struct b43_phy *phy = &dev->phy; 3567 int i, j, indx; 3568 u16 gain; 3569 3570 if (dev->phy.rev >= 3) { 3571 params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */ 3572 params->txgm = target.txgm[core]; 3573 params->pga = target.pga[core]; 3574 params->pad = target.pad[core]; 3575 params->ipa = target.ipa[core]; 3576 if (phy->rev >= 19) { 3577 /* TODO */ 3578 } else if (phy->rev >= 7) { 3579 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15); 3580 } else { 3581 params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa); 3582 } 3583 for (j = 0; j < 5; j++) 3584 params->ncorr[j] = 0x79; 3585 } else { 3586 gain = (target.pad[core]) | (target.pga[core] << 4) | 3587 (target.txgm[core] << 8); 3588 3589 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 3590 1 : 0; 3591 for (i = 0; i < 9; i++) 3592 if (tbl_iqcal_gainparams[indx][i][0] == gain) 3593 break; 3594 i = min(i, 8); 3595 3596 params->txgm = tbl_iqcal_gainparams[indx][i][1]; 3597 params->pga = tbl_iqcal_gainparams[indx][i][2]; 3598 params->pad = tbl_iqcal_gainparams[indx][i][3]; 3599 params->cal_gain = (params->txgm << 7) | (params->pga << 4) | 3600 (params->pad << 2); 3601 for (j = 0; j < 4; j++) 3602 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; 3603 } 3604} 3605 3606/************************************************** 3607 * Tx and Rx 3608 **************************************************/ 3609 3610/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */ 3611static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) 3612{ 3613 struct b43_phy *phy = &dev->phy; 3614 struct b43_phy_n *nphy = dev->phy.n; 3615 u8 i; 3616 u16 bmask, val, tmp; 3617 enum ieee80211_band band = b43_current_band(dev->wl); 3618 3619 if (nphy->hang_avoid) 3620 b43_nphy_stay_in_carrier_search(dev, 1); 3621 3622 nphy->txpwrctrl = enable; 3623 if (!enable) { 3624 if (dev->phy.rev >= 3 && 3625 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) & 3626 (B43_NPHY_TXPCTL_CMD_COEFF | 3627 B43_NPHY_TXPCTL_CMD_HWPCTLEN | 3628 B43_NPHY_TXPCTL_CMD_PCTLEN))) { 3629 /* We disable enabled TX pwr ctl, save it's state */ 3630 nphy->tx_pwr_idx[0] = b43_phy_read(dev, 3631 B43_NPHY_C1_TXPCTL_STAT) & 0x7f; 3632 nphy->tx_pwr_idx[1] = b43_phy_read(dev, 3633 B43_NPHY_C2_TXPCTL_STAT) & 0x7f; 3634 } 3635 3636 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840); 3637 for (i = 0; i < 84; i++) 3638 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); 3639 3640 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40); 3641 for (i = 0; i < 84; i++) 3642 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0); 3643 3644 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; 3645 if (dev->phy.rev >= 3) 3646 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN; 3647 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp); 3648 3649 if (dev->phy.rev >= 3) { 3650 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); 3651 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); 3652 } else { 3653 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); 3654 } 3655 3656 if (dev->phy.rev == 2) 3657 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3658 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53); 3659 else if (dev->phy.rev < 2) 3660 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3661 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); 3662 3663 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) 3664 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); 3665 } else { 3666 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, 3667 nphy->adj_pwr_tbl); 3668 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, 3669 nphy->adj_pwr_tbl); 3670 3671 bmask = B43_NPHY_TXPCTL_CMD_COEFF | 3672 B43_NPHY_TXPCTL_CMD_HWPCTLEN; 3673 /* wl does useless check for "enable" param here */ 3674 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; 3675 if (dev->phy.rev >= 3) { 3676 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN; 3677 if (val) 3678 val |= B43_NPHY_TXPCTL_CMD_PCTLEN; 3679 } 3680 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val); 3681 3682 if (band == IEEE80211_BAND_5GHZ) { 3683 if (phy->rev >= 19) { 3684 /* TODO */ 3685 } else if (phy->rev >= 7) { 3686 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3687 ~B43_NPHY_TXPCTL_CMD_INIT, 3688 0x32); 3689 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, 3690 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 3691 0x32); 3692 } else { 3693 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3694 ~B43_NPHY_TXPCTL_CMD_INIT, 3695 0x64); 3696 if (phy->rev > 1) 3697 b43_phy_maskset(dev, 3698 B43_NPHY_TXPCTL_INIT, 3699 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 3700 0x64); 3701 } 3702 } 3703 3704 if (dev->phy.rev >= 3) { 3705 if (nphy->tx_pwr_idx[0] != 128 && 3706 nphy->tx_pwr_idx[1] != 128) { 3707 /* Recover TX pwr ctl state */ 3708 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 3709 ~B43_NPHY_TXPCTL_CMD_INIT, 3710 nphy->tx_pwr_idx[0]); 3711 if (dev->phy.rev > 1) 3712 b43_phy_maskset(dev, 3713 B43_NPHY_TXPCTL_INIT, 3714 ~0xff, nphy->tx_pwr_idx[1]); 3715 } 3716 } 3717 3718 if (phy->rev >= 7) { 3719 /* TODO */ 3720 } 3721 3722 if (dev->phy.rev >= 3) { 3723 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); 3724 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); 3725 } else { 3726 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); 3727 } 3728 3729 if (dev->phy.rev == 2) 3730 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); 3731 else if (dev->phy.rev < 2) 3732 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); 3733 3734 if (dev->phy.rev < 2 && b43_is_40mhz(dev)) 3735 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); 3736 3737 if (b43_nphy_ipa(dev)) { 3738 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); 3739 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); 3740 } 3741 } 3742 3743 if (nphy->hang_avoid) 3744 b43_nphy_stay_in_carrier_search(dev, 0); 3745} 3746 3747/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */ 3748static void b43_nphy_tx_power_fix(struct b43_wldev *dev) 3749{ 3750 struct b43_phy *phy = &dev->phy; 3751 struct b43_phy_n *nphy = dev->phy.n; 3752 struct ssb_sprom *sprom = dev->dev->bus_sprom; 3753 3754 u8 txpi[2], bbmult, i; 3755 u16 tmp, radio_gain, dac_gain; 3756 u16 freq = phy->chandef->chan->center_freq; 3757 u32 txgain; 3758 /* u32 gaintbl; rev3+ */ 3759 3760 if (nphy->hang_avoid) 3761 b43_nphy_stay_in_carrier_search(dev, 1); 3762 3763 /* TODO: rev19+ */ 3764 if (dev->phy.rev >= 7) { 3765 txpi[0] = txpi[1] = 30; 3766 } else if (dev->phy.rev >= 3) { 3767 txpi[0] = 40; 3768 txpi[1] = 40; 3769 } else if (sprom->revision < 4) { 3770 txpi[0] = 72; 3771 txpi[1] = 72; 3772 } else { 3773 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 3774 txpi[0] = sprom->txpid2g[0]; 3775 txpi[1] = sprom->txpid2g[1]; 3776 } else if (freq >= 4900 && freq < 5100) { 3777 txpi[0] = sprom->txpid5gl[0]; 3778 txpi[1] = sprom->txpid5gl[1]; 3779 } else if (freq >= 5100 && freq < 5500) { 3780 txpi[0] = sprom->txpid5g[0]; 3781 txpi[1] = sprom->txpid5g[1]; 3782 } else if (freq >= 5500) { 3783 txpi[0] = sprom->txpid5gh[0]; 3784 txpi[1] = sprom->txpid5gh[1]; 3785 } else { 3786 txpi[0] = 91; 3787 txpi[1] = 91; 3788 } 3789 } 3790 if (dev->phy.rev < 7 && 3791 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100)) 3792 txpi[0] = txpi[1] = 91; 3793 3794 /* 3795 for (i = 0; i < 2; i++) { 3796 nphy->txpwrindex[i].index_internal = txpi[i]; 3797 nphy->txpwrindex[i].index_internal_save = txpi[i]; 3798 } 3799 */ 3800 3801 for (i = 0; i < 2; i++) { 3802 const u32 *table = b43_nphy_get_tx_gain_table(dev); 3803 3804 if (!table) 3805 break; 3806 txgain = *(table + txpi[i]); 3807 3808 if (dev->phy.rev >= 3) 3809 radio_gain = (txgain >> 16) & 0x1FFFF; 3810 else 3811 radio_gain = (txgain >> 16) & 0x1FFF; 3812 3813 if (dev->phy.rev >= 7) 3814 dac_gain = (txgain >> 8) & 0x7; 3815 else 3816 dac_gain = (txgain >> 8) & 0x3F; 3817 bbmult = txgain & 0xFF; 3818 3819 if (dev->phy.rev >= 3) { 3820 if (i == 0) 3821 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); 3822 else 3823 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); 3824 } else { 3825 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); 3826 } 3827 3828 if (i == 0) 3829 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); 3830 else 3831 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); 3832 3833 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); 3834 3835 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); 3836 if (i == 0) 3837 tmp = (tmp & 0x00FF) | (bbmult << 8); 3838 else 3839 tmp = (tmp & 0xFF00) | bbmult; 3840 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp); 3841 3842 if (b43_nphy_ipa(dev)) { 3843 u32 tmp32; 3844 u16 reg = (i == 0) ? 3845 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1; 3846 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, 3847 576 + txpi[i])); 3848 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4); 3849 b43_phy_set(dev, reg, 0x4); 3850 } 3851 } 3852 3853 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); 3854 3855 if (nphy->hang_avoid) 3856 b43_nphy_stay_in_carrier_search(dev, 0); 3857} 3858 3859static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev) 3860{ 3861 struct b43_phy *phy = &dev->phy; 3862 3863 u8 core; 3864 u16 r; /* routing */ 3865 3866 if (phy->rev >= 19) { 3867 /* TODO */ 3868 } else if (phy->rev >= 7) { 3869 for (core = 0; core < 2; core++) { 3870 r = core ? 0x190 : 0x170; 3871 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 3872 b43_radio_write(dev, r + 0x5, 0x5); 3873 b43_radio_write(dev, r + 0x9, 0xE); 3874 if (phy->rev != 5) 3875 b43_radio_write(dev, r + 0xA, 0); 3876 if (phy->rev != 7) 3877 b43_radio_write(dev, r + 0xB, 1); 3878 else 3879 b43_radio_write(dev, r + 0xB, 0x31); 3880 } else { 3881 b43_radio_write(dev, r + 0x5, 0x9); 3882 b43_radio_write(dev, r + 0x9, 0xC); 3883 b43_radio_write(dev, r + 0xB, 0x0); 3884 if (phy->rev != 5) 3885 b43_radio_write(dev, r + 0xA, 1); 3886 else 3887 b43_radio_write(dev, r + 0xA, 0x31); 3888 } 3889 b43_radio_write(dev, r + 0x6, 0); 3890 b43_radio_write(dev, r + 0x7, 0); 3891 b43_radio_write(dev, r + 0x8, 3); 3892 b43_radio_write(dev, r + 0xC, 0); 3893 } 3894 } else { 3895 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 3896 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128); 3897 else 3898 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80); 3899 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0); 3900 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29); 3901 3902 for (core = 0; core < 2; core++) { 3903 r = core ? B2056_TX1 : B2056_TX0; 3904 3905 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0); 3906 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0); 3907 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3); 3908 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0); 3909 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8); 3910 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0); 3911 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0); 3912 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 3913 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, 3914 0x5); 3915 if (phy->rev != 5) 3916 b43_radio_write(dev, r | B2056_TX_TSSIA, 3917 0x00); 3918 if (phy->rev >= 5) 3919 b43_radio_write(dev, r | B2056_TX_TSSIG, 3920 0x31); 3921 else 3922 b43_radio_write(dev, r | B2056_TX_TSSIG, 3923 0x11); 3924 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, 3925 0xE); 3926 } else { 3927 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER, 3928 0x9); 3929 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31); 3930 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0); 3931 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX, 3932 0xC); 3933 } 3934 } 3935 } 3936} 3937 3938/* 3939 * Stop radio and transmit known signal. Then check received signal strength to 3940 * get TSSI (Transmit Signal Strength Indicator). 3941 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi 3942 */ 3943static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev) 3944{ 3945 struct b43_phy *phy = &dev->phy; 3946 struct b43_phy_n *nphy = dev->phy.n; 3947 3948 u32 tmp; 3949 s32 rssi[4] = { }; 3950 3951 if (phy->chandef->chan->flags & IEEE80211_CHAN_NO_IR) 3952 return; 3953 3954 if (b43_nphy_ipa(dev)) 3955 b43_nphy_ipa_internal_tssi_setup(dev); 3956 3957 if (phy->rev >= 19) 3958 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, false, 0); 3959 else if (phy->rev >= 7) 3960 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, false, 0); 3961 else if (phy->rev >= 3) 3962 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, false); 3963 3964 b43_nphy_stop_playback(dev); 3965 b43_nphy_tx_tone(dev, 4000, 0, false, false, false); 3966 udelay(20); 3967 tmp = b43_nphy_poll_rssi(dev, N_RSSI_TSSI_2G, rssi, 1); 3968 b43_nphy_stop_playback(dev); 3969 3970 b43_nphy_rssi_select(dev, 0, N_RSSI_W1); 3971 3972 if (phy->rev >= 19) 3973 b43_nphy_rf_ctl_override_rev19(dev, 0x1000, 0, 3, true, 0); 3974 else if (phy->rev >= 7) 3975 b43_nphy_rf_ctl_override_rev7(dev, 0x1000, 0, 3, true, 0); 3976 else if (phy->rev >= 3) 3977 b43_nphy_rf_ctl_override(dev, 0x2000, 0, 3, true); 3978 3979 if (phy->rev >= 19) { 3980 /* TODO */ 3981 return; 3982 } else if (phy->rev >= 3) { 3983 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; 3984 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF; 3985 } else { 3986 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF; 3987 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF; 3988 } 3989 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF; 3990 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF; 3991} 3992 3993/* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */ 3994static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev) 3995{ 3996 struct b43_phy_n *nphy = dev->phy.n; 3997 3998 u8 idx, delta; 3999 u8 i, stf_mode; 4000 4001 /* Array adj_pwr_tbl corresponds to the hardware table. It consists of 4002 * 21 groups, each containing 4 entries. 4003 * 4004 * First group has entries for CCK modulation. 4005 * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM). 4006 * 4007 * Group 0 is for CCK 4008 * Groups 1..4 use BPSK (group per coding rate) 4009 * Groups 5..8 use QPSK (group per coding rate) 4010 * Groups 9..12 use 16-QAM (group per coding rate) 4011 * Groups 13..16 use 64-QAM (group per coding rate) 4012 * Groups 17..20 are unknown 4013 */ 4014 4015 for (i = 0; i < 4; i++) 4016 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i]; 4017 4018 for (stf_mode = 0; stf_mode < 4; stf_mode++) { 4019 delta = 0; 4020 switch (stf_mode) { 4021 case 0: 4022 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) { 4023 idx = 68; 4024 } else { 4025 delta = 1; 4026 idx = b43_is_40mhz(dev) ? 52 : 4; 4027 } 4028 break; 4029 case 1: 4030 idx = b43_is_40mhz(dev) ? 76 : 28; 4031 break; 4032 case 2: 4033 idx = b43_is_40mhz(dev) ? 84 : 36; 4034 break; 4035 case 3: 4036 idx = b43_is_40mhz(dev) ? 92 : 44; 4037 break; 4038 } 4039 4040 for (i = 0; i < 20; i++) { 4041 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] = 4042 nphy->tx_power_offset[idx]; 4043 if (i == 0) 4044 idx += delta; 4045 if (i == 14) 4046 idx += 1 - delta; 4047 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 || 4048 i == 13) 4049 idx += 1; 4050 } 4051 } 4052} 4053 4054/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */ 4055static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev) 4056{ 4057 struct b43_phy *phy = &dev->phy; 4058 struct b43_phy_n *nphy = dev->phy.n; 4059 struct ssb_sprom *sprom = dev->dev->bus_sprom; 4060 4061 s16 a1[2], b0[2], b1[2]; 4062 u8 idle[2]; 4063 u8 ppr_max; 4064 s8 target[2]; 4065 s32 num, den, pwr; 4066 u32 regval[64]; 4067 4068 u16 freq = phy->chandef->chan->center_freq; 4069 u16 tmp; 4070 u16 r; /* routing */ 4071 u8 i, c; 4072 4073 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { 4074 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); 4075 b43_read32(dev, B43_MMIO_MACCTL); 4076 udelay(1); 4077 } 4078 4079 if (nphy->hang_avoid) 4080 b43_nphy_stay_in_carrier_search(dev, true); 4081 4082 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN); 4083 if (dev->phy.rev >= 3) 4084 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, 4085 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF); 4086 else 4087 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD, 4088 B43_NPHY_TXPCTL_CMD_PCTLEN); 4089 4090 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) 4091 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); 4092 4093 if (sprom->revision < 4) { 4094 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g; 4095 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g; 4096 target[0] = target[1] = 52; 4097 a1[0] = a1[1] = -424; 4098 b0[0] = b0[1] = 5612; 4099 b1[0] = b1[1] = -1393; 4100 } else { 4101 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 4102 for (c = 0; c < 2; c++) { 4103 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g; 4104 target[c] = sprom->core_pwr_info[c].maxpwr_2g; 4105 a1[c] = sprom->core_pwr_info[c].pa_2g[0]; 4106 b0[c] = sprom->core_pwr_info[c].pa_2g[1]; 4107 b1[c] = sprom->core_pwr_info[c].pa_2g[2]; 4108 } 4109 } else if (freq >= 4900 && freq < 5100) { 4110 for (c = 0; c < 2; c++) { 4111 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; 4112 target[c] = sprom->core_pwr_info[c].maxpwr_5gl; 4113 a1[c] = sprom->core_pwr_info[c].pa_5gl[0]; 4114 b0[c] = sprom->core_pwr_info[c].pa_5gl[1]; 4115 b1[c] = sprom->core_pwr_info[c].pa_5gl[2]; 4116 } 4117 } else if (freq >= 5100 && freq < 5500) { 4118 for (c = 0; c < 2; c++) { 4119 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; 4120 target[c] = sprom->core_pwr_info[c].maxpwr_5g; 4121 a1[c] = sprom->core_pwr_info[c].pa_5g[0]; 4122 b0[c] = sprom->core_pwr_info[c].pa_5g[1]; 4123 b1[c] = sprom->core_pwr_info[c].pa_5g[2]; 4124 } 4125 } else if (freq >= 5500) { 4126 for (c = 0; c < 2; c++) { 4127 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; 4128 target[c] = sprom->core_pwr_info[c].maxpwr_5gh; 4129 a1[c] = sprom->core_pwr_info[c].pa_5gh[0]; 4130 b0[c] = sprom->core_pwr_info[c].pa_5gh[1]; 4131 b1[c] = sprom->core_pwr_info[c].pa_5gh[2]; 4132 } 4133 } else { 4134 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g; 4135 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g; 4136 target[0] = target[1] = 52; 4137 a1[0] = a1[1] = -424; 4138 b0[0] = b0[1] = 5612; 4139 b1[0] = b1[1] = -1393; 4140 } 4141 } 4142 4143 ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr); 4144 if (ppr_max) { 4145 target[0] = ppr_max; 4146 target[1] = ppr_max; 4147 } 4148 4149 if (dev->phy.rev >= 3) { 4150 if (sprom->fem.ghz2.tssipos) 4151 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000); 4152 if (dev->phy.rev >= 7) { 4153 for (c = 0; c < 2; c++) { 4154 r = c ? 0x190 : 0x170; 4155 if (b43_nphy_ipa(dev)) 4156 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC); 4157 } 4158 } else { 4159 if (b43_nphy_ipa(dev)) { 4160 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE; 4161 b43_radio_write(dev, 4162 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp); 4163 b43_radio_write(dev, 4164 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp); 4165 } else { 4166 b43_radio_write(dev, 4167 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11); 4168 b43_radio_write(dev, 4169 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11); 4170 } 4171 } 4172 } 4173 4174 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { 4175 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000); 4176 b43_read32(dev, B43_MMIO_MACCTL); 4177 udelay(1); 4178 } 4179 4180 if (phy->rev >= 19) { 4181 /* TODO */ 4182 } else if (phy->rev >= 7) { 4183 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 4184 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19); 4185 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, 4186 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19); 4187 } else { 4188 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, 4189 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40); 4190 if (dev->phy.rev > 1) 4191 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, 4192 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40); 4193 } 4194 4195 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) 4196 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0); 4197 4198 b43_phy_write(dev, B43_NPHY_TXPCTL_N, 4199 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT | 4200 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT); 4201 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI, 4202 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT | 4203 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT | 4204 B43_NPHY_TXPCTL_ITSSI_BINF); 4205 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR, 4206 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT | 4207 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT); 4208 4209 for (c = 0; c < 2; c++) { 4210 for (i = 0; i < 64; i++) { 4211 num = 8 * (16 * b0[c] + b1[c] * i); 4212 den = 32768 + a1[c] * i; 4213 pwr = max((4 * num + den / 2) / den, -8); 4214 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1))) 4215 pwr = max(pwr, target[c] + 1); 4216 regval[i] = pwr; 4217 } 4218 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval); 4219 } 4220 4221 b43_nphy_tx_prepare_adjusted_power_table(dev); 4222 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); 4223 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); 4224 4225 if (nphy->hang_avoid) 4226 b43_nphy_stay_in_carrier_search(dev, false); 4227} 4228 4229static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) 4230{ 4231 struct b43_phy *phy = &dev->phy; 4232 4233 const u32 *table = NULL; 4234 u32 rfpwr_offset; 4235 u8 pga_gain, pad_gain; 4236 int i; 4237 const s16 *uninitialized_var(rf_pwr_offset_table); 4238 4239 table = b43_nphy_get_tx_gain_table(dev); 4240 if (!table) 4241 return; 4242 4243 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table); 4244 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table); 4245 4246 if (phy->rev < 3) 4247 return; 4248 4249#if 0 4250 nphy->gmval = (table[0] >> 16) & 0x7000; 4251#endif 4252 4253 if (phy->rev >= 19) { 4254 return; 4255 } else if (phy->rev >= 7) { 4256 rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev); 4257 if (!rf_pwr_offset_table) 4258 return; 4259 /* TODO: Enable this once we have gains configured */ 4260 return; 4261 } 4262 4263 for (i = 0; i < 128; i++) { 4264 if (phy->rev >= 19) { 4265 /* TODO */ 4266 return; 4267 } else if (phy->rev >= 7) { 4268 pga_gain = (table[i] >> 24) & 0xf; 4269 pad_gain = (table[i] >> 19) & 0x1f; 4270 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 4271 rfpwr_offset = rf_pwr_offset_table[pad_gain]; 4272 else 4273 rfpwr_offset = rf_pwr_offset_table[pga_gain]; 4274 } else { 4275 pga_gain = (table[i] >> 24) & 0xF; 4276 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 4277 rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; 4278 else 4279 rfpwr_offset = 0; /* FIXME */ 4280 } 4281 4282 b43_ntab_write(dev, B43_NTAB32(26, 576 + i), rfpwr_offset); 4283 b43_ntab_write(dev, B43_NTAB32(27, 576 + i), rfpwr_offset); 4284 } 4285} 4286 4287/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ 4288static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) 4289{ 4290 struct b43_phy_n *nphy = dev->phy.n; 4291 enum ieee80211_band band; 4292 u16 tmp; 4293 4294 if (!enable) { 4295 nphy->rfctrl_intc1_save = b43_phy_read(dev, 4296 B43_NPHY_RFCTL_INTC1); 4297 nphy->rfctrl_intc2_save = b43_phy_read(dev, 4298 B43_NPHY_RFCTL_INTC2); 4299 band = b43_current_band(dev->wl); 4300 if (dev->phy.rev >= 7) { 4301 tmp = 0x1480; 4302 } else if (dev->phy.rev >= 3) { 4303 if (band == IEEE80211_BAND_5GHZ) 4304 tmp = 0x600; 4305 else 4306 tmp = 0x480; 4307 } else { 4308 if (band == IEEE80211_BAND_5GHZ) 4309 tmp = 0x180; 4310 else 4311 tmp = 0x120; 4312 } 4313 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 4314 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 4315 } else { 4316 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 4317 nphy->rfctrl_intc1_save); 4318 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 4319 nphy->rfctrl_intc2_save); 4320 } 4321} 4322 4323/* 4324 * TX low-pass filter bandwidth setup 4325 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw 4326 */ 4327static void b43_nphy_tx_lpf_bw(struct b43_wldev *dev) 4328{ 4329 u16 tmp; 4330 4331 if (dev->phy.rev < 3 || dev->phy.rev >= 7) 4332 return; 4333 4334 if (b43_nphy_ipa(dev)) 4335 tmp = b43_is_40mhz(dev) ? 5 : 4; 4336 else 4337 tmp = b43_is_40mhz(dev) ? 3 : 1; 4338 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, 4339 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); 4340 4341 if (b43_nphy_ipa(dev)) { 4342 tmp = b43_is_40mhz(dev) ? 4 : 1; 4343 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, 4344 (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); 4345 } 4346} 4347 4348/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ 4349static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, 4350 u16 samps, u8 time, bool wait) 4351{ 4352 int i; 4353 u16 tmp; 4354 4355 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps); 4356 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time); 4357 if (wait) 4358 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE); 4359 else 4360 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE); 4361 4362 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); 4363 4364 for (i = 1000; i; i--) { 4365 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); 4366 if (!(tmp & B43_NPHY_IQEST_CMD_START)) { 4367 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) | 4368 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0); 4369 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) | 4370 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0); 4371 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) | 4372 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0); 4373 4374 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | 4375 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); 4376 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | 4377 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); 4378 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | 4379 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); 4380 return; 4381 } 4382 udelay(10); 4383 } 4384 memset(est, 0, sizeof(*est)); 4385} 4386 4387/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ 4388static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, 4389 struct b43_phy_n_iq_comp *pcomp) 4390{ 4391 if (write) { 4392 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0); 4393 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0); 4394 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1); 4395 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1); 4396 } else { 4397 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0); 4398 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0); 4399 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1); 4400 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1); 4401 } 4402} 4403 4404#if 0 4405/* Ready but not used anywhere */ 4406/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ 4407static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core) 4408{ 4409 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 4410 4411 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); 4412 if (core == 0) { 4413 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); 4414 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 4415 } else { 4416 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 4417 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 4418 } 4419 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]); 4420 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]); 4421 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]); 4422 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]); 4423 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]); 4424 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]); 4425 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 4426 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 4427} 4428 4429/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ 4430static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) 4431{ 4432 u8 rxval, txval; 4433 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 4434 4435 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 4436 if (core == 0) { 4437 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 4438 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 4439 } else { 4440 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 4441 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 4442 } 4443 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 4444 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 4445 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1); 4446 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2); 4447 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1); 4448 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER); 4449 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 4450 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 4451 4452 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 4453 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 4454 4455 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 4456 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 4457 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 4458 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 4459 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT)); 4460 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 4461 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT)); 4462 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS, 4463 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT)); 4464 4465 if (core == 0) { 4466 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); 4467 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); 4468 } else { 4469 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); 4470 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); 4471 } 4472 4473 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 0, 3); 4474 b43_nphy_rf_ctl_override(dev, 8, 0, 3, false); 4475 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 4476 4477 if (core == 0) { 4478 rxval = 1; 4479 txval = 8; 4480 } else { 4481 rxval = 4; 4482 txval = 2; 4483 } 4484 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, rxval, 4485 core + 1); 4486 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, txval, 4487 2 - core); 4488} 4489#endif 4490 4491/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ 4492static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask) 4493{ 4494 int i; 4495 s32 iq; 4496 u32 ii; 4497 u32 qq; 4498 int iq_nbits, qq_nbits; 4499 int arsh, brsh; 4500 u16 tmp, a, b; 4501 4502 struct nphy_iq_est est; 4503 struct b43_phy_n_iq_comp old; 4504 struct b43_phy_n_iq_comp new = { }; 4505 bool error = false; 4506 4507 if (mask == 0) 4508 return; 4509 4510 b43_nphy_rx_iq_coeffs(dev, false, &old); 4511 b43_nphy_rx_iq_coeffs(dev, true, &new); 4512 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); 4513 new = old; 4514 4515 for (i = 0; i < 2; i++) { 4516 if (i == 0 && (mask & 1)) { 4517 iq = est.iq0_prod; 4518 ii = est.i0_pwr; 4519 qq = est.q0_pwr; 4520 } else if (i == 1 && (mask & 2)) { 4521 iq = est.iq1_prod; 4522 ii = est.i1_pwr; 4523 qq = est.q1_pwr; 4524 } else { 4525 continue; 4526 } 4527 4528 if (ii + qq < 2) { 4529 error = true; 4530 break; 4531 } 4532 4533 iq_nbits = fls(abs(iq)); 4534 qq_nbits = fls(qq); 4535 4536 arsh = iq_nbits - 20; 4537 if (arsh >= 0) { 4538 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); 4539 tmp = ii >> arsh; 4540 } else { 4541 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); 4542 tmp = ii << -arsh; 4543 } 4544 if (tmp == 0) { 4545 error = true; 4546 break; 4547 } 4548 a /= tmp; 4549 4550 brsh = qq_nbits - 11; 4551 if (brsh >= 0) { 4552 b = (qq << (31 - qq_nbits)); 4553 tmp = ii >> brsh; 4554 } else { 4555 b = (qq << (31 - qq_nbits)); 4556 tmp = ii << -brsh; 4557 } 4558 if (tmp == 0) { 4559 error = true; 4560 break; 4561 } 4562 b = int_sqrt(b / tmp - a * a) - (1 << 10); 4563 4564 if (i == 0 && (mask & 0x1)) { 4565 if (dev->phy.rev >= 3) { 4566 new.a0 = a & 0x3FF; 4567 new.b0 = b & 0x3FF; 4568 } else { 4569 new.a0 = b & 0x3FF; 4570 new.b0 = a & 0x3FF; 4571 } 4572 } else if (i == 1 && (mask & 0x2)) { 4573 if (dev->phy.rev >= 3) { 4574 new.a1 = a & 0x3FF; 4575 new.b1 = b & 0x3FF; 4576 } else { 4577 new.a1 = b & 0x3FF; 4578 new.b1 = a & 0x3FF; 4579 } 4580 } 4581 } 4582 4583 if (error) 4584 new = old; 4585 4586 b43_nphy_rx_iq_coeffs(dev, true, &new); 4587} 4588 4589/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ 4590static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) 4591{ 4592 u16 array[4]; 4593 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array); 4594 4595 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]); 4596 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]); 4597 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]); 4598 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]); 4599} 4600 4601/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ 4602static void b43_nphy_spur_workaround(struct b43_wldev *dev) 4603{ 4604 struct b43_phy_n *nphy = dev->phy.n; 4605 4606 u8 channel = dev->phy.channel; 4607 int tone[2] = { 57, 58 }; 4608 u32 noise[2] = { 0x3FF, 0x3FF }; 4609 4610 B43_WARN_ON(dev->phy.rev < 3); 4611 4612 if (nphy->hang_avoid) 4613 b43_nphy_stay_in_carrier_search(dev, 1); 4614 4615 if (nphy->gband_spurwar_en) { 4616 /* TODO: N PHY Adjust Analog Pfbw (7) */ 4617 if (channel == 11 && b43_is_40mhz(dev)) 4618 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ 4619 else 4620 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 4621 /* TODO: N PHY Adjust CRS Min Power (0x1E) */ 4622 } 4623 4624 if (nphy->aband_spurwar_en) { 4625 if (channel == 54) { 4626 tone[0] = 0x20; 4627 noise[0] = 0x25F; 4628 } else if (channel == 38 || channel == 102 || channel == 118) { 4629 if (0 /* FIXME */) { 4630 tone[0] = 0x20; 4631 noise[0] = 0x21F; 4632 } else { 4633 tone[0] = 0; 4634 noise[0] = 0; 4635 } 4636 } else if (channel == 134) { 4637 tone[0] = 0x20; 4638 noise[0] = 0x21F; 4639 } else if (channel == 151) { 4640 tone[0] = 0x10; 4641 noise[0] = 0x23F; 4642 } else if (channel == 153 || channel == 161) { 4643 tone[0] = 0x30; 4644 noise[0] = 0x23F; 4645 } else { 4646 tone[0] = 0; 4647 noise[0] = 0; 4648 } 4649 4650 if (!tone[0] && !noise[0]) 4651 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ 4652 else 4653 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 4654 } 4655 4656 if (nphy->hang_avoid) 4657 b43_nphy_stay_in_carrier_search(dev, 0); 4658} 4659 4660/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ 4661static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev) 4662{ 4663 struct b43_phy_n *nphy = dev->phy.n; 4664 int i, j; 4665 u32 tmp; 4666 u32 cur_real, cur_imag, real_part, imag_part; 4667 4668 u16 buffer[7]; 4669 4670 if (nphy->hang_avoid) 4671 b43_nphy_stay_in_carrier_search(dev, true); 4672 4673 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 4674 4675 for (i = 0; i < 2; i++) { 4676 tmp = ((buffer[i * 2] & 0x3FF) << 10) | 4677 (buffer[i * 2 + 1] & 0x3FF); 4678 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 4679 (((i + 26) << 10) | 320)); 4680 for (j = 0; j < 128; j++) { 4681 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 4682 ((tmp >> 16) & 0xFFFF)); 4683 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 4684 (tmp & 0xFFFF)); 4685 } 4686 } 4687 4688 for (i = 0; i < 2; i++) { 4689 tmp = buffer[5 + i]; 4690 real_part = (tmp >> 8) & 0xFF; 4691 imag_part = (tmp & 0xFF); 4692 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 4693 (((i + 26) << 10) | 448)); 4694 4695 if (dev->phy.rev >= 3) { 4696 cur_real = real_part; 4697 cur_imag = imag_part; 4698 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); 4699 } 4700 4701 for (j = 0; j < 128; j++) { 4702 if (dev->phy.rev < 3) { 4703 cur_real = (real_part * loscale[j] + 128) >> 8; 4704 cur_imag = (imag_part * loscale[j] + 128) >> 8; 4705 tmp = ((cur_real & 0xFF) << 8) | 4706 (cur_imag & 0xFF); 4707 } 4708 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI, 4709 ((tmp >> 16) & 0xFFFF)); 4710 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 4711 (tmp & 0xFFFF)); 4712 } 4713 } 4714 4715 if (dev->phy.rev >= 3) { 4716 b43_shm_write16(dev, B43_SHM_SHARED, 4717 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); 4718 b43_shm_write16(dev, B43_SHM_SHARED, 4719 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); 4720 } 4721 4722 if (nphy->hang_avoid) 4723 b43_nphy_stay_in_carrier_search(dev, false); 4724} 4725 4726/* 4727 * Restore RSSI Calibration 4728 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal 4729 */ 4730static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev) 4731{ 4732 struct b43_phy_n *nphy = dev->phy.n; 4733 4734 u16 *rssical_radio_regs = NULL; 4735 u16 *rssical_phy_regs = NULL; 4736 4737 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 4738 if (!nphy->rssical_chanspec_2G.center_freq) 4739 return; 4740 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; 4741 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; 4742 } else { 4743 if (!nphy->rssical_chanspec_5G.center_freq) 4744 return; 4745 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; 4746 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; 4747 } 4748 4749 if (dev->phy.rev >= 19) { 4750 /* TODO */ 4751 } else if (dev->phy.rev >= 7) { 4752 b43_radio_maskset(dev, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, 4753 rssical_radio_regs[0]); 4754 b43_radio_maskset(dev, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, 4755 rssical_radio_regs[1]); 4756 } else { 4757 b43_radio_maskset(dev, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, 4758 rssical_radio_regs[0]); 4759 b43_radio_maskset(dev, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, 4760 rssical_radio_regs[1]); 4761 } 4762 4763 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); 4764 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); 4765 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); 4766 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); 4767 4768 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); 4769 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); 4770 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); 4771 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); 4772 4773 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); 4774 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); 4775 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); 4776 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); 4777} 4778 4779static void b43_nphy_tx_cal_radio_setup_rev19(struct b43_wldev *dev) 4780{ 4781 /* TODO */ 4782} 4783 4784static void b43_nphy_tx_cal_radio_setup_rev7(struct b43_wldev *dev) 4785{ 4786 struct b43_phy *phy = &dev->phy; 4787 struct b43_phy_n *nphy = dev->phy.n; 4788 u16 *save = nphy->tx_rx_cal_radio_saveregs; 4789 int core, off; 4790 u16 r, tmp; 4791 4792 for (core = 0; core < 2; core++) { 4793 r = core ? 0x20 : 0; 4794 off = core * 11; 4795 4796 save[off + 0] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MASTER); 4797 save[off + 1] = b43_radio_read(dev, r + R2057_TX0_IQCAL_VCM_HG); 4798 save[off + 2] = b43_radio_read(dev, r + R2057_TX0_IQCAL_IDAC); 4799 save[off + 3] = b43_radio_read(dev, r + R2057_TX0_TSSI_VCM); 4800 save[off + 4] = 0; 4801 save[off + 5] = b43_radio_read(dev, r + R2057_TX0_TX_SSI_MUX); 4802 if (phy->radio_rev != 5) 4803 save[off + 6] = b43_radio_read(dev, r + R2057_TX0_TSSIA); 4804 save[off + 7] = b43_radio_read(dev, r + R2057_TX0_TSSIG); 4805 save[off + 8] = b43_radio_read(dev, r + R2057_TX0_TSSI_MISC1); 4806 4807 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 4808 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0xA); 4809 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); 4810 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); 4811 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); 4812 b43_radio_write(dev, r + R2057_TX0_TSSIG, 0); 4813 if (nphy->use_int_tx_iq_lo_cal) { 4814 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x4); 4815 tmp = true ? 0x31 : 0x21; /* TODO */ 4816 b43_radio_write(dev, r + R2057_TX0_TSSIA, tmp); 4817 } 4818 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0x00); 4819 } else { 4820 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MASTER, 0x6); 4821 b43_radio_write(dev, r + R2057_TX0_IQCAL_VCM_HG, 0x43); 4822 b43_radio_write(dev, r + R2057_TX0_IQCAL_IDAC, 0x55); 4823 b43_radio_write(dev, r + R2057_TX0_TSSI_VCM, 0); 4824 4825 if (phy->radio_rev != 5) 4826 b43_radio_write(dev, r + R2057_TX0_TSSIA, 0); 4827 if (nphy->use_int_tx_iq_lo_cal) { 4828 b43_radio_write(dev, r + R2057_TX0_TX_SSI_MUX, 0x6); 4829 tmp = true ? 0x31 : 0x21; /* TODO */ 4830 b43_radio_write(dev, r + R2057_TX0_TSSIG, tmp); 4831 } 4832 b43_radio_write(dev, r + R2057_TX0_TSSI_MISC1, 0); 4833 } 4834 } 4835} 4836 4837/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ 4838static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev) 4839{ 4840 struct b43_phy *phy = &dev->phy; 4841 struct b43_phy_n *nphy = dev->phy.n; 4842 u16 *save = nphy->tx_rx_cal_radio_saveregs; 4843 u16 tmp; 4844 u8 offset, i; 4845 4846 if (phy->rev >= 19) { 4847 b43_nphy_tx_cal_radio_setup_rev19(dev); 4848 } else if (phy->rev >= 7) { 4849 b43_nphy_tx_cal_radio_setup_rev7(dev); 4850 } else if (phy->rev >= 3) { 4851 for (i = 0; i < 2; i++) { 4852 tmp = (i == 0) ? 0x2000 : 0x3000; 4853 offset = i * 11; 4854 4855 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL); 4856 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL); 4857 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS); 4858 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS); 4859 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS); 4860 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV); 4861 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1); 4862 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2); 4863 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL); 4864 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC); 4865 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1); 4866 4867 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 4868 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 4869 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); 4870 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); 4871 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); 4872 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); 4873 if (nphy->ipa5g_on) { 4874 b43_radio_write(dev, tmp | B2055_PADDRV, 4); 4875 b43_radio_write(dev, tmp | B2055_XOCTL1, 1); 4876 } else { 4877 b43_radio_write(dev, tmp | B2055_PADDRV, 0); 4878 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F); 4879 } 4880 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); 4881 } else { 4882 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06); 4883 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40); 4884 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55); 4885 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0); 4886 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0); 4887 b43_radio_write(dev, tmp | B2055_XOCTL1, 0); 4888 if (nphy->ipa2g_on) { 4889 b43_radio_write(dev, tmp | B2055_PADDRV, 6); 4890 b43_radio_write(dev, tmp | B2055_XOCTL2, 4891 (dev->phy.rev < 5) ? 0x11 : 0x01); 4892 } else { 4893 b43_radio_write(dev, tmp | B2055_PADDRV, 0); 4894 b43_radio_write(dev, tmp | B2055_XOCTL2, 0); 4895 } 4896 } 4897 b43_radio_write(dev, tmp | B2055_XOREGUL, 0); 4898 b43_radio_write(dev, tmp | B2055_XOMISC, 0); 4899 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0); 4900 } 4901 } else { 4902 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1); 4903 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 4904 4905 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2); 4906 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 4907 4908 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1); 4909 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 4910 4911 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2); 4912 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 4913 4914 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX); 4915 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX); 4916 4917 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 4918 B43_NPHY_BANDCTL_5GHZ)) { 4919 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04); 4920 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04); 4921 } else { 4922 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20); 4923 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20); 4924 } 4925 4926 if (dev->phy.rev < 2) { 4927 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20); 4928 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20); 4929 } else { 4930 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20); 4931 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20); 4932 } 4933 } 4934} 4935 4936/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ 4937static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core) 4938{ 4939 struct b43_phy_n *nphy = dev->phy.n; 4940 int i; 4941 u16 scale, entry; 4942 4943 u16 tmp = nphy->txcal_bbmult; 4944 if (core == 0) 4945 tmp >>= 8; 4946 tmp &= 0xff; 4947 4948 for (i = 0; i < 18; i++) { 4949 scale = (ladder_lo[i].percent * tmp) / 100; 4950 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; 4951 b43_ntab_write(dev, B43_NTAB16(15, i), entry); 4952 4953 scale = (ladder_iq[i].percent * tmp) / 100; 4954 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; 4955 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry); 4956 } 4957} 4958 4959static void b43_nphy_pa_set_tx_dig_filter(struct b43_wldev *dev, u16 offset, 4960 const s16 *filter) 4961{ 4962 int i; 4963 4964 offset = B43_PHY_N(offset); 4965 4966 for (i = 0; i < 15; i++, offset++) 4967 b43_phy_write(dev, offset, filter[i]); 4968} 4969 4970/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ 4971static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev) 4972{ 4973 b43_nphy_pa_set_tx_dig_filter(dev, 0x2C5, 4974 tbl_tx_filter_coef_rev4[2]); 4975} 4976 4977/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ 4978static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev) 4979{ 4980 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */ 4981 static const u16 offset[] = { 0x186, 0x195, 0x2C5 }; 4982 static const s16 dig_filter_phy_rev16[] = { 4983 -375, 136, -407, 208, -1527, 4984 956, 93, 186, 93, 230, 4985 -44, 230, 201, -191, 201, 4986 }; 4987 int i; 4988 4989 for (i = 0; i < 3; i++) 4990 b43_nphy_pa_set_tx_dig_filter(dev, offset[i], 4991 tbl_tx_filter_coef_rev4[i]); 4992 4993 /* Verified with BCM43227 and BCM43228 */ 4994 if (dev->phy.rev == 16) 4995 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); 4996 4997 /* Verified with BCM43131 and BCM43217 */ 4998 if (dev->phy.rev == 17) { 4999 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, dig_filter_phy_rev16); 5000 b43_nphy_pa_set_tx_dig_filter(dev, 0x195, 5001 tbl_tx_filter_coef_rev4[1]); 5002 } 5003 5004 if (b43_is_40mhz(dev)) { 5005 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, 5006 tbl_tx_filter_coef_rev4[3]); 5007 } else { 5008 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 5009 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, 5010 tbl_tx_filter_coef_rev4[5]); 5011 if (dev->phy.channel == 14) 5012 b43_nphy_pa_set_tx_dig_filter(dev, 0x186, 5013 tbl_tx_filter_coef_rev4[6]); 5014 } 5015} 5016 5017/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ 5018static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev) 5019{ 5020 struct b43_phy_n *nphy = dev->phy.n; 5021 5022 u16 curr_gain[2]; 5023 struct nphy_txgains target; 5024 const u32 *table = NULL; 5025 5026 if (!nphy->txpwrctrl) { 5027 int i; 5028 5029 if (nphy->hang_avoid) 5030 b43_nphy_stay_in_carrier_search(dev, true); 5031 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain); 5032 if (nphy->hang_avoid) 5033 b43_nphy_stay_in_carrier_search(dev, false); 5034 5035 for (i = 0; i < 2; ++i) { 5036 if (dev->phy.rev >= 7) { 5037 target.ipa[i] = curr_gain[i] & 0x0007; 5038 target.pad[i] = (curr_gain[i] & 0x00F8) >> 3; 5039 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 5040 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 5041 target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15; 5042 } else if (dev->phy.rev >= 3) { 5043 target.ipa[i] = curr_gain[i] & 0x000F; 5044 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; 5045 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; 5046 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; 5047 } else { 5048 target.ipa[i] = curr_gain[i] & 0x0003; 5049 target.pad[i] = (curr_gain[i] & 0x000C) >> 2; 5050 target.pga[i] = (curr_gain[i] & 0x0070) >> 4; 5051 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; 5052 } 5053 } 5054 } else { 5055 int i; 5056 u16 index[2]; 5057 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) & 5058 B43_NPHY_TXPCTL_STAT_BIDX) >> 5059 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 5060 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) & 5061 B43_NPHY_TXPCTL_STAT_BIDX) >> 5062 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT; 5063 5064 for (i = 0; i < 2; ++i) { 5065 table = b43_nphy_get_tx_gain_table(dev); 5066 if (!table) 5067 break; 5068 5069 if (dev->phy.rev >= 7) { 5070 target.ipa[i] = (table[index[i]] >> 16) & 0x7; 5071 target.pad[i] = (table[index[i]] >> 19) & 0x1F; 5072 target.pga[i] = (table[index[i]] >> 24) & 0xF; 5073 target.txgm[i] = (table[index[i]] >> 28) & 0x7; 5074 target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1; 5075 } else if (dev->phy.rev >= 3) { 5076 target.ipa[i] = (table[index[i]] >> 16) & 0xF; 5077 target.pad[i] = (table[index[i]] >> 20) & 0xF; 5078 target.pga[i] = (table[index[i]] >> 24) & 0xF; 5079 target.txgm[i] = (table[index[i]] >> 28) & 0xF; 5080 } else { 5081 target.ipa[i] = (table[index[i]] >> 16) & 0x3; 5082 target.pad[i] = (table[index[i]] >> 18) & 0x3; 5083 target.pga[i] = (table[index[i]] >> 20) & 0x7; 5084 target.txgm[i] = (table[index[i]] >> 23) & 0x7; 5085 } 5086 } 5087 } 5088 5089 return target; 5090} 5091 5092/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ 5093static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev) 5094{ 5095 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 5096 5097 if (dev->phy.rev >= 3) { 5098 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]); 5099 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); 5100 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); 5101 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]); 5102 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]); 5103 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]); 5104 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]); 5105 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]); 5106 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]); 5107 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]); 5108 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]); 5109 b43_nphy_reset_cca(dev); 5110 } else { 5111 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]); 5112 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]); 5113 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); 5114 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]); 5115 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]); 5116 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]); 5117 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]); 5118 } 5119} 5120 5121/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ 5122static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev) 5123{ 5124 struct b43_phy *phy = &dev->phy; 5125 struct b43_phy_n *nphy = dev->phy.n; 5126 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; 5127 u16 tmp; 5128 5129 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 5130 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); 5131 if (dev->phy.rev >= 3) { 5132 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); 5133 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); 5134 5135 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); 5136 regs[2] = tmp; 5137 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600); 5138 5139 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 5140 regs[3] = tmp; 5141 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600); 5142 5143 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG); 5144 b43_phy_mask(dev, B43_NPHY_BBCFG, 5145 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); 5146 5147 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3)); 5148 regs[5] = tmp; 5149 b43_ntab_write(dev, B43_NTAB16(8, 3), 0); 5150 5151 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19)); 5152 regs[6] = tmp; 5153 b43_ntab_write(dev, B43_NTAB16(8, 19), 0); 5154 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 5155 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 5156 5157 if (!nphy->use_int_tx_iq_lo_cal) 5158 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 5159 1, 3); 5160 else 5161 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_PA, 5162 0, 3); 5163 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 2, 1); 5164 b43_nphy_rf_ctl_intc_override(dev, N_INTC_OVERRIDE_TRSW, 8, 2); 5165 5166 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0); 5167 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1); 5168 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); 5169 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); 5170 5171 tmp = b43_nphy_read_lpf_ctl(dev, 0); 5172 if (phy->rev >= 19) 5173 b43_nphy_rf_ctl_override_rev19(dev, 0x80, tmp, 0, false, 5174 1); 5175 else if (phy->rev >= 7) 5176 b43_nphy_rf_ctl_override_rev7(dev, 0x80, tmp, 0, false, 5177 1); 5178 5179 if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) { 5180 if (phy->rev >= 19) { 5181 b43_nphy_rf_ctl_override_rev19(dev, 0x8, 0, 0x3, 5182 false, 0); 5183 } else if (phy->rev >= 8) { 5184 b43_nphy_rf_ctl_override_rev7(dev, 0x8, 0, 0x3, 5185 false, 0); 5186 } else if (phy->rev == 7) { 5187 b43_radio_maskset(dev, R2057_OVR_REG0, 1 << 4, 1 << 4); 5188 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 5189 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); 5190 b43_radio_maskset(dev, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); 5191 } else { 5192 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); 5193 b43_radio_maskset(dev, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); 5194 } 5195 } 5196 } 5197 } else { 5198 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000); 5199 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000); 5200 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 5201 regs[2] = tmp; 5202 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000); 5203 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2)); 5204 regs[3] = tmp; 5205 tmp |= 0x2000; 5206 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp); 5207 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18)); 5208 regs[4] = tmp; 5209 tmp |= 0x2000; 5210 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp); 5211 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 5212 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 5213 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) 5214 tmp = 0x0180; 5215 else 5216 tmp = 0x0120; 5217 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp); 5218 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); 5219 } 5220} 5221 5222/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ 5223static void b43_nphy_save_cal(struct b43_wldev *dev) 5224{ 5225 struct b43_phy *phy = &dev->phy; 5226 struct b43_phy_n *nphy = dev->phy.n; 5227 5228 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 5229 u16 *txcal_radio_regs = NULL; 5230 struct b43_chanspec *iqcal_chanspec; 5231 u16 *table = NULL; 5232 5233 if (nphy->hang_avoid) 5234 b43_nphy_stay_in_carrier_search(dev, 1); 5235 5236 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 5237 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 5238 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 5239 iqcal_chanspec = &nphy->iqcal_chanspec_2G; 5240 table = nphy->cal_cache.txcal_coeffs_2G; 5241 } else { 5242 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 5243 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 5244 iqcal_chanspec = &nphy->iqcal_chanspec_5G; 5245 table = nphy->cal_cache.txcal_coeffs_5G; 5246 } 5247 5248 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs); 5249 /* TODO use some definitions */ 5250 if (phy->rev >= 19) { 5251 /* TODO */ 5252 } else if (phy->rev >= 7) { 5253 txcal_radio_regs[0] = b43_radio_read(dev, 5254 R2057_TX0_LOFT_FINE_I); 5255 txcal_radio_regs[1] = b43_radio_read(dev, 5256 R2057_TX0_LOFT_FINE_Q); 5257 txcal_radio_regs[4] = b43_radio_read(dev, 5258 R2057_TX0_LOFT_COARSE_I); 5259 txcal_radio_regs[5] = b43_radio_read(dev, 5260 R2057_TX0_LOFT_COARSE_Q); 5261 txcal_radio_regs[2] = b43_radio_read(dev, 5262 R2057_TX1_LOFT_FINE_I); 5263 txcal_radio_regs[3] = b43_radio_read(dev, 5264 R2057_TX1_LOFT_FINE_Q); 5265 txcal_radio_regs[6] = b43_radio_read(dev, 5266 R2057_TX1_LOFT_COARSE_I); 5267 txcal_radio_regs[7] = b43_radio_read(dev, 5268 R2057_TX1_LOFT_COARSE_Q); 5269 } else if (phy->rev >= 3) { 5270 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021); 5271 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022); 5272 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021); 5273 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022); 5274 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023); 5275 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024); 5276 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023); 5277 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024); 5278 } else { 5279 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B); 5280 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA); 5281 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D); 5282 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC); 5283 } 5284 iqcal_chanspec->center_freq = dev->phy.chandef->chan->center_freq; 5285 iqcal_chanspec->channel_type = 5286 cfg80211_get_chandef_type(dev->phy.chandef); 5287 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table); 5288 5289 if (nphy->hang_avoid) 5290 b43_nphy_stay_in_carrier_search(dev, 0); 5291} 5292 5293/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ 5294static void b43_nphy_restore_cal(struct b43_wldev *dev) 5295{ 5296 struct b43_phy *phy = &dev->phy; 5297 struct b43_phy_n *nphy = dev->phy.n; 5298 5299 u16 coef[4]; 5300 u16 *loft = NULL; 5301 u16 *table = NULL; 5302 5303 int i; 5304 u16 *txcal_radio_regs = NULL; 5305 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL; 5306 5307 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 5308 if (!nphy->iqcal_chanspec_2G.center_freq) 5309 return; 5310 table = nphy->cal_cache.txcal_coeffs_2G; 5311 loft = &nphy->cal_cache.txcal_coeffs_2G[5]; 5312 } else { 5313 if (!nphy->iqcal_chanspec_5G.center_freq) 5314 return; 5315 table = nphy->cal_cache.txcal_coeffs_5G; 5316 loft = &nphy->cal_cache.txcal_coeffs_5G[5]; 5317 } 5318 5319 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table); 5320 5321 for (i = 0; i < 4; i++) { 5322 if (dev->phy.rev >= 3) 5323 table[i] = coef[i]; 5324 else 5325 coef[i] = 0; 5326 } 5327 5328 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef); 5329 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft); 5330 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft); 5331 5332 if (dev->phy.rev < 2) 5333 b43_nphy_tx_iq_workaround(dev); 5334 5335 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 5336 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; 5337 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; 5338 } else { 5339 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; 5340 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; 5341 } 5342 5343 /* TODO use some definitions */ 5344 if (phy->rev >= 19) { 5345 /* TODO */ 5346 } else if (phy->rev >= 7) { 5347 b43_radio_write(dev, R2057_TX0_LOFT_FINE_I, 5348 txcal_radio_regs[0]); 5349 b43_radio_write(dev, R2057_TX0_LOFT_FINE_Q, 5350 txcal_radio_regs[1]); 5351 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_I, 5352 txcal_radio_regs[4]); 5353 b43_radio_write(dev, R2057_TX0_LOFT_COARSE_Q, 5354 txcal_radio_regs[5]); 5355 b43_radio_write(dev, R2057_TX1_LOFT_FINE_I, 5356 txcal_radio_regs[2]); 5357 b43_radio_write(dev, R2057_TX1_LOFT_FINE_Q, 5358 txcal_radio_regs[3]); 5359 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_I, 5360 txcal_radio_regs[6]); 5361 b43_radio_write(dev, R2057_TX1_LOFT_COARSE_Q, 5362 txcal_radio_regs[7]); 5363 } else if (phy->rev >= 3) { 5364 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]); 5365 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]); 5366 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]); 5367 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]); 5368 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]); 5369 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]); 5370 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]); 5371 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]); 5372 } else { 5373 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]); 5374 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]); 5375 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]); 5376 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]); 5377 } 5378 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs); 5379} 5380 5381/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ 5382static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev, 5383 struct nphy_txgains target, 5384 bool full, bool mphase) 5385{ 5386 struct b43_phy *phy = &dev->phy; 5387 struct b43_phy_n *nphy = dev->phy.n; 5388 int i; 5389 int error = 0; 5390 int freq; 5391 bool avoid = false; 5392 u8 length; 5393 u16 tmp, core, type, count, max, numb, last = 0, cmd; 5394 const u16 *table; 5395 bool phy6or5x; 5396 5397 u16 buffer[11]; 5398 u16 diq_start = 0; 5399 u16 save[2]; 5400 u16 gain[2]; 5401 struct nphy_iqcal_params params[2]; 5402 bool updated[2] = { }; 5403 5404 b43_nphy_stay_in_carrier_search(dev, true); 5405 5406 if (dev->phy.rev >= 4) { 5407 avoid = nphy->hang_avoid; 5408 nphy->hang_avoid = false; 5409 } 5410 5411 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 5412 5413 for (i = 0; i < 2; i++) { 5414 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]); 5415 gain[i] = params[i].cal_gain; 5416 } 5417 5418 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain); 5419 5420 b43_nphy_tx_cal_radio_setup(dev); 5421 b43_nphy_tx_cal_phy_setup(dev); 5422 5423 phy6or5x = dev->phy.rev >= 6 || 5424 (dev->phy.rev == 5 && nphy->ipa2g_on && 5425 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); 5426 if (phy6or5x) { 5427 if (b43_is_40mhz(dev)) { 5428 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 5429 tbl_tx_iqlo_cal_loft_ladder_40); 5430 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 5431 tbl_tx_iqlo_cal_iqimb_ladder_40); 5432 } else { 5433 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 5434 tbl_tx_iqlo_cal_loft_ladder_20); 5435 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 5436 tbl_tx_iqlo_cal_iqimb_ladder_20); 5437 } 5438 } 5439 5440 if (phy->rev >= 19) { 5441 /* TODO */ 5442 } else if (phy->rev >= 7) { 5443 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); 5444 } else { 5445 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); 5446 } 5447 5448 if (!b43_is_40mhz(dev)) 5449 freq = 2500; 5450 else 5451 freq = 5000; 5452 5453 if (nphy->mphase_cal_phase_id > 2) 5454 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8, 5455 0xFFFF, 0, true, false, false); 5456 else 5457 error = b43_nphy_tx_tone(dev, freq, 250, true, false, false); 5458 5459 if (error == 0) { 5460 if (nphy->mphase_cal_phase_id > 2) { 5461 table = nphy->mphase_txcal_bestcoeffs; 5462 length = 11; 5463 if (dev->phy.rev < 3) 5464 length -= 2; 5465 } else { 5466 if (!full && nphy->txiqlocal_coeffsvalid) { 5467 table = nphy->txiqlocal_bestc; 5468 length = 11; 5469 if (dev->phy.rev < 3) 5470 length -= 2; 5471 } else { 5472 full = true; 5473 if (dev->phy.rev >= 3) { 5474 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; 5475 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; 5476 } else { 5477 table = tbl_tx_iqlo_cal_startcoefs; 5478 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS; 5479 } 5480 } 5481 } 5482 5483 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table); 5484 5485 if (full) { 5486 if (dev->phy.rev >= 3) 5487 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; 5488 else 5489 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; 5490 } else { 5491 if (dev->phy.rev >= 3) 5492 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; 5493 else 5494 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL; 5495 } 5496 5497 if (mphase) { 5498 count = nphy->mphase_txcal_cmdidx; 5499 numb = min(max, 5500 (u16)(count + nphy->mphase_txcal_numcmds)); 5501 } else { 5502 count = 0; 5503 numb = max; 5504 } 5505 5506 for (; count < numb; count++) { 5507 if (full) { 5508 if (dev->phy.rev >= 3) 5509 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; 5510 else 5511 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; 5512 } else { 5513 if (dev->phy.rev >= 3) 5514 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; 5515 else 5516 cmd = tbl_tx_iqlo_cal_cmds_recal[count]; 5517 } 5518 5519 core = (cmd & 0x3000) >> 12; 5520 type = (cmd & 0x0F00) >> 8; 5521 5522 if (phy6or5x && updated[core] == 0) { 5523 b43_nphy_update_tx_cal_ladder(dev, core); 5524 updated[core] = true; 5525 } 5526 5527 tmp = (params[core].ncorr[type] << 8) | 0x66; 5528 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp); 5529 5530 if (type == 1 || type == 3 || type == 4) { 5531 buffer[0] = b43_ntab_read(dev, 5532 B43_NTAB16(15, 69 + core)); 5533 diq_start = buffer[0]; 5534 buffer[0] = 0; 5535 b43_ntab_write(dev, B43_NTAB16(15, 69 + core), 5536 0); 5537 } 5538 5539 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd); 5540 for (i = 0; i < 2000; i++) { 5541 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD); 5542 if (tmp & 0xC000) 5543 break; 5544 udelay(10); 5545 } 5546 5547 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 5548 buffer); 5549 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, 5550 buffer); 5551 5552 if (type == 1 || type == 3 || type == 4) 5553 buffer[0] = diq_start; 5554 } 5555 5556 if (mphase) 5557 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; 5558 5559 last = (dev->phy.rev < 3) ? 6 : 7; 5560 5561 if (!mphase || nphy->mphase_cal_phase_id == last) { 5562 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer); 5563 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer); 5564 if (dev->phy.rev < 3) { 5565 buffer[0] = 0; 5566 buffer[1] = 0; 5567 buffer[2] = 0; 5568 buffer[3] = 0; 5569 } 5570 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 5571 buffer); 5572 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2, 5573 buffer); 5574 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 5575 buffer); 5576 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 5577 buffer); 5578 length = 11; 5579 if (dev->phy.rev < 3) 5580 length -= 2; 5581 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 5582 nphy->txiqlocal_bestc); 5583 nphy->txiqlocal_coeffsvalid = true; 5584 nphy->txiqlocal_chanspec.center_freq = 5585 phy->chandef->chan->center_freq; 5586 nphy->txiqlocal_chanspec.channel_type = 5587 cfg80211_get_chandef_type(phy->chandef); 5588 } else { 5589 length = 11; 5590 if (dev->phy.rev < 3) 5591 length -= 2; 5592 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length, 5593 nphy->mphase_txcal_bestcoeffs); 5594 } 5595 5596 b43_nphy_stop_playback(dev); 5597 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0); 5598 } 5599 5600 b43_nphy_tx_cal_phy_cleanup(dev); 5601 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save); 5602 5603 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) 5604 b43_nphy_tx_iq_workaround(dev); 5605 5606 if (dev->phy.rev >= 4) 5607 nphy->hang_avoid = avoid; 5608 5609 b43_nphy_stay_in_carrier_search(dev, false); 5610 5611 return error; 5612} 5613 5614/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ 5615static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev) 5616{ 5617 struct b43_phy_n *nphy = dev->phy.n; 5618 u8 i; 5619 u16 buffer[7]; 5620 bool equal = true; 5621 5622 if (!nphy->txiqlocal_coeffsvalid || 5623 nphy->txiqlocal_chanspec.center_freq != dev->phy.chandef->chan->center_freq || 5624 nphy->txiqlocal_chanspec.channel_type != cfg80211_get_chandef_type(dev->phy.chandef)) 5625 return; 5626 5627 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer); 5628 for (i = 0; i < 4; i++) { 5629 if (buffer[i] != nphy->txiqlocal_bestc[i]) { 5630 equal = false; 5631 break; 5632 } 5633 } 5634 5635 if (!equal) { 5636 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, 5637 nphy->txiqlocal_bestc); 5638 for (i = 0; i < 4; i++) 5639 buffer[i] = 0; 5640 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, 5641 buffer); 5642 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, 5643 &nphy->txiqlocal_bestc[5]); 5644 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, 5645 &nphy->txiqlocal_bestc[5]); 5646 } 5647} 5648 5649/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ 5650static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, 5651 struct nphy_txgains target, u8 type, bool debug) 5652{ 5653 struct b43_phy_n *nphy = dev->phy.n; 5654 int i, j, index; 5655 u8 rfctl[2]; 5656 u8 afectl_core; 5657 u16 tmp[6]; 5658 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna; 5659 u32 real, imag; 5660 enum ieee80211_band band; 5661 5662 u8 use; 5663 u16 cur_hpf; 5664 u16 lna[3] = { 3, 3, 1 }; 5665 u16 hpf1[3] = { 7, 2, 0 }; 5666 u16 hpf2[3] = { 2, 0, 0 }; 5667 u32 power[3] = { }; 5668 u16 gain_save[2]; 5669 u16 cal_gain[2]; 5670 struct nphy_iqcal_params cal_params[2]; 5671 struct nphy_iq_est est; 5672 int ret = 0; 5673 bool playtone = true; 5674 int desired = 13; 5675 5676 b43_nphy_stay_in_carrier_search(dev, 1); 5677 5678 if (dev->phy.rev < 2) 5679 b43_nphy_reapply_tx_cal_coeffs(dev); 5680 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 5681 for (i = 0; i < 2; i++) { 5682 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]); 5683 cal_gain[i] = cal_params[i].cal_gain; 5684 } 5685 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain); 5686 5687 for (i = 0; i < 2; i++) { 5688 if (i == 0) { 5689 rfctl[0] = B43_NPHY_RFCTL_INTC1; 5690 rfctl[1] = B43_NPHY_RFCTL_INTC2; 5691 afectl_core = B43_NPHY_AFECTL_C1; 5692 } else { 5693 rfctl[0] = B43_NPHY_RFCTL_INTC2; 5694 rfctl[1] = B43_NPHY_RFCTL_INTC1; 5695 afectl_core = B43_NPHY_AFECTL_C2; 5696 } 5697 5698 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA); 5699 tmp[2] = b43_phy_read(dev, afectl_core); 5700 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); 5701 tmp[4] = b43_phy_read(dev, rfctl[0]); 5702 tmp[5] = b43_phy_read(dev, rfctl[1]); 5703 5704 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, 5705 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF, 5706 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT)); 5707 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN, 5708 (1 - i)); 5709 b43_phy_set(dev, afectl_core, 0x0006); 5710 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006); 5711 5712 band = b43_current_band(dev->wl); 5713 5714 if (nphy->rxcalparams & 0xFF000000) { 5715 if (band == IEEE80211_BAND_5GHZ) 5716 b43_phy_write(dev, rfctl[0], 0x140); 5717 else 5718 b43_phy_write(dev, rfctl[0], 0x110); 5719 } else { 5720 if (band == IEEE80211_BAND_5GHZ) 5721 b43_phy_write(dev, rfctl[0], 0x180); 5722 else 5723 b43_phy_write(dev, rfctl[0], 0x120); 5724 } 5725 5726 if (band == IEEE80211_BAND_5GHZ) 5727 b43_phy_write(dev, rfctl[1], 0x148); 5728 else 5729 b43_phy_write(dev, rfctl[1], 0x114); 5730 5731 if (nphy->rxcalparams & 0x10000) { 5732 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC, 5733 (i + 1)); 5734 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC, 5735 (2 - i)); 5736 } 5737 5738 for (j = 0; j < 4; j++) { 5739 if (j < 3) { 5740 cur_lna = lna[j]; 5741 cur_hpf1 = hpf1[j]; 5742 cur_hpf2 = hpf2[j]; 5743 } else { 5744 if (power[1] > 10000) { 5745 use = 1; 5746 cur_hpf = cur_hpf1; 5747 index = 2; 5748 } else { 5749 if (power[0] > 10000) { 5750 use = 1; 5751 cur_hpf = cur_hpf1; 5752 index = 1; 5753 } else { 5754 index = 0; 5755 use = 2; 5756 cur_hpf = cur_hpf2; 5757 } 5758 } 5759 cur_lna = lna[index]; 5760 cur_hpf1 = hpf1[index]; 5761 cur_hpf2 = hpf2[index]; 5762 cur_hpf += desired - hweight32(power[index]); 5763 cur_hpf = clamp_val(cur_hpf, 0, 10); 5764 if (use == 1) 5765 cur_hpf1 = cur_hpf; 5766 else 5767 cur_hpf2 = cur_hpf; 5768 } 5769 5770 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | 5771 (cur_lna << 2)); 5772 b43_nphy_rf_ctl_override(dev, 0x400, tmp[0], 3, 5773 false); 5774 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 5775 b43_nphy_stop_playback(dev); 5776 5777 if (playtone) { 5778 ret = b43_nphy_tx_tone(dev, 4000, 5779 (nphy->rxcalparams & 0xFFFF), 5780 false, false, true); 5781 playtone = false; 5782 } else { 5783 b43_nphy_run_samples(dev, 160, 0xFFFF, 0, false, 5784 false, true); 5785 } 5786 5787 if (ret == 0) { 5788 if (j < 3) { 5789 b43_nphy_rx_iq_est(dev, &est, 1024, 32, 5790 false); 5791 if (i == 0) { 5792 real = est.i0_pwr; 5793 imag = est.q0_pwr; 5794 } else { 5795 real = est.i1_pwr; 5796 imag = est.q1_pwr; 5797 } 5798 power[i] = ((real + imag) / 1024) + 1; 5799 } else { 5800 b43_nphy_calc_rx_iq_comp(dev, 1 << i); 5801 } 5802 b43_nphy_stop_playback(dev); 5803 } 5804 5805 if (ret != 0) 5806 break; 5807 } 5808 5809 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC); 5810 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC); 5811 b43_phy_write(dev, rfctl[1], tmp[5]); 5812 b43_phy_write(dev, rfctl[0], tmp[4]); 5813 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]); 5814 b43_phy_write(dev, afectl_core, tmp[2]); 5815 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]); 5816 5817 if (ret != 0) 5818 break; 5819 } 5820 5821 b43_nphy_rf_ctl_override(dev, 0x400, 0, 3, true); 5822 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 5823 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save); 5824 5825 b43_nphy_stay_in_carrier_search(dev, 0); 5826 5827 return ret; 5828} 5829 5830static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev, 5831 struct nphy_txgains target, u8 type, bool debug) 5832{ 5833 return -1; 5834} 5835 5836/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ 5837static int b43_nphy_cal_rx_iq(struct b43_wldev *dev, 5838 struct nphy_txgains target, u8 type, bool debug) 5839{ 5840 if (dev->phy.rev >= 7) 5841 type = 0; 5842 5843 if (dev->phy.rev >= 3) 5844 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug); 5845 else 5846 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug); 5847} 5848 5849/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ 5850static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask) 5851{ 5852 struct b43_phy *phy = &dev->phy; 5853 struct b43_phy_n *nphy = phy->n; 5854 /* u16 buf[16]; it's rev3+ */ 5855 5856 nphy->phyrxchain = mask; 5857 5858 if (0 /* FIXME clk */) 5859 return; 5860 5861 b43_mac_suspend(dev); 5862 5863 if (nphy->hang_avoid) 5864 b43_nphy_stay_in_carrier_search(dev, true); 5865 5866 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN, 5867 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT); 5868 5869 if ((mask & 0x3) != 0x3) { 5870 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1); 5871 if (dev->phy.rev >= 3) { 5872 /* TODO */ 5873 } 5874 } else { 5875 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E); 5876 if (dev->phy.rev >= 3) { 5877 /* TODO */ 5878 } 5879 } 5880 5881 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 5882 5883 if (nphy->hang_avoid) 5884 b43_nphy_stay_in_carrier_search(dev, false); 5885 5886 b43_mac_enable(dev); 5887} 5888 5889static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, 5890 bool ignore_tssi) 5891{ 5892 struct b43_phy *phy = &dev->phy; 5893 struct b43_phy_n *nphy = dev->phy.n; 5894 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; 5895 struct b43_ppr *ppr = &nphy->tx_pwr_max_ppr; 5896 u8 max; /* qdBm */ 5897 bool tx_pwr_state; 5898 5899 if (nphy->tx_pwr_last_recalc_freq == channel->center_freq && 5900 nphy->tx_pwr_last_recalc_limit == phy->desired_txpower) 5901 return B43_TXPWR_RES_DONE; 5902 5903 /* Make sure we have a clean PPR */ 5904 b43_ppr_clear(dev, ppr); 5905 5906 /* HW limitations */ 5907 b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G); 5908 5909 /* Regulatory & user settings */ 5910 max = INT_TO_Q52(phy->chandef->chan->max_power); 5911 if (phy->desired_txpower) 5912 max = min_t(u8, max, INT_TO_Q52(phy->desired_txpower)); 5913 b43_ppr_apply_max(dev, ppr, max); 5914 if (b43_debug(dev, B43_DBG_XMITPOWER)) 5915 b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n", 5916 Q52_ARG(b43_ppr_get_max(dev, ppr))); 5917 5918 /* TODO: Enable this once we get gains working */ 5919#if 0 5920 /* Some extra gains */ 5921 hw_gain = 6; /* N-PHY specific */ 5922 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 5923 hw_gain += sprom->antenna_gain.a0; 5924 else 5925 hw_gain += sprom->antenna_gain.a1; 5926 b43_ppr_add(dev, ppr, -hw_gain); 5927#endif 5928 5929 /* Make sure we didn't go too low */ 5930 b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8)); 5931 5932 /* Apply */ 5933 tx_pwr_state = nphy->txpwrctrl; 5934 b43_mac_suspend(dev); 5935 b43_nphy_tx_power_ctl_setup(dev); 5936 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) { 5937 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK); 5938 b43_read32(dev, B43_MMIO_MACCTL); 5939 udelay(1); 5940 } 5941 b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl); 5942 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) 5943 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0); 5944 b43_mac_enable(dev); 5945 5946 nphy->tx_pwr_last_recalc_freq = channel->center_freq; 5947 nphy->tx_pwr_last_recalc_limit = phy->desired_txpower; 5948 5949 return B43_TXPWR_RES_DONE; 5950} 5951 5952/************************************************** 5953 * N-PHY init 5954 **************************************************/ 5955 5956/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ 5957static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) 5958{ 5959 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); 5960 5961 mimocfg |= B43_NPHY_MIMOCFG_AUTO; 5962 if (preamble == 1) 5963 mimocfg |= B43_NPHY_MIMOCFG_GFMIX; 5964 else 5965 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; 5966 5967 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); 5968} 5969 5970/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */ 5971static void b43_nphy_bphy_init(struct b43_wldev *dev) 5972{ 5973 unsigned int i; 5974 u16 val; 5975 5976 val = 0x1E1F; 5977 for (i = 0; i < 16; i++) { 5978 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); 5979 val -= 0x202; 5980 } 5981 val = 0x3E3F; 5982 for (i = 0; i < 16; i++) { 5983 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val); 5984 val -= 0x202; 5985 } 5986 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668); 5987} 5988 5989/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ 5990static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init) 5991{ 5992 if (dev->phy.rev >= 7) 5993 return; 5994 5995 if (dev->phy.rev >= 3) { 5996 if (!init) 5997 return; 5998 if (0 /* FIXME */) { 5999 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); 6000 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222); 6001 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144); 6002 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188); 6003 } 6004 } else { 6005 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0); 6006 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0); 6007 6008 switch (dev->dev->bus_type) { 6009#ifdef CONFIG_B43_BCMA 6010 case B43_BUS_BCMA: 6011 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc, 6012 0xFC00, 0xFC00); 6013 break; 6014#endif 6015#ifdef CONFIG_B43_SSB 6016 case B43_BUS_SSB: 6017 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco, 6018 0xFC00, 0xFC00); 6019 break; 6020#endif 6021 } 6022 6023 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0); 6024 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00); 6025 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF), 6026 0); 6027 6028 if (init) { 6029 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); 6030 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); 6031 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); 6032 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); 6033 } 6034 } 6035} 6036 6037/* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */ 6038static int b43_phy_initn(struct b43_wldev *dev) 6039{ 6040 struct ssb_sprom *sprom = dev->dev->bus_sprom; 6041 struct b43_phy *phy = &dev->phy; 6042 struct b43_phy_n *nphy = phy->n; 6043 u8 tx_pwr_state; 6044 struct nphy_txgains target; 6045 u16 tmp; 6046 enum ieee80211_band tmp2; 6047 bool do_rssi_cal; 6048 6049 u16 clip[2]; 6050 bool do_cal = false; 6051 6052 if ((dev->phy.rev >= 3) && 6053 (sprom->boardflags_lo & B43_BFL_EXTLNA) && 6054 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) { 6055 switch (dev->dev->bus_type) { 6056#ifdef CONFIG_B43_BCMA 6057 case B43_BUS_BCMA: 6058 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc, 6059 BCMA_CC_CHIPCTL, 0x40); 6060 break; 6061#endif 6062#ifdef CONFIG_B43_SSB 6063 case B43_BUS_SSB: 6064 chipco_set32(&dev->dev->sdev->bus->chipco, 6065 SSB_CHIPCO_CHIPCTL, 0x40); 6066 break; 6067#endif 6068 } 6069 } 6070 nphy->use_int_tx_iq_lo_cal = b43_nphy_ipa(dev) || 6071 phy->rev >= 7 || 6072 (phy->rev >= 5 && 6073 sprom->boardflags2_hi & B43_BFH2_INTERNDET_TXIQCAL); 6074 nphy->deaf_count = 0; 6075 b43_nphy_tables_init(dev); 6076 nphy->crsminpwr_adjusted = false; 6077 nphy->noisevars_adjusted = false; 6078 6079 /* Clear all overrides */ 6080 if (dev->phy.rev >= 3) { 6081 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0); 6082 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 6083 if (phy->rev >= 7) { 6084 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER3, 0); 6085 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER4, 0); 6086 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER5, 0); 6087 b43_phy_write(dev, B43_NPHY_REV7_RF_CTL_OVER6, 0); 6088 } 6089 if (phy->rev >= 19) { 6090 /* TODO */ 6091 } 6092 6093 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0); 6094 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0); 6095 } else { 6096 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0); 6097 } 6098 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0); 6099 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0); 6100 if (dev->phy.rev < 6) { 6101 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0); 6102 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0); 6103 } 6104 b43_phy_mask(dev, B43_NPHY_RFSEQMODE, 6105 ~(B43_NPHY_RFSEQMODE_CAOVER | 6106 B43_NPHY_RFSEQMODE_TROVER)); 6107 if (dev->phy.rev >= 3) 6108 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0); 6109 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0); 6110 6111 if (dev->phy.rev <= 2) { 6112 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40; 6113 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 6114 ~B43_NPHY_BPHY_CTL3_SCALE, 6115 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT); 6116 } 6117 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); 6118 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); 6119 6120 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD || 6121 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && 6122 dev->dev->board_type == BCMA_BOARD_TYPE_BCM943224M93)) 6123 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0); 6124 else 6125 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8); 6126 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8); 6127 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); 6128 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30); 6129 6130 if (phy->rev < 8) 6131 b43_nphy_update_mimo_config(dev, nphy->preamble_override); 6132 6133 b43_nphy_update_txrx_chain(dev); 6134 6135 if (phy->rev < 2) { 6136 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8); 6137 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4); 6138 } 6139 6140 tmp2 = b43_current_band(dev->wl); 6141 if (b43_nphy_ipa(dev)) { 6142 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1); 6143 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F, 6144 nphy->papd_epsilon_offset[0] << 7); 6145 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1); 6146 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F, 6147 nphy->papd_epsilon_offset[1] << 7); 6148 b43_nphy_int_pa_set_tx_dig_filters(dev); 6149 } else if (phy->rev >= 5) { 6150 b43_nphy_ext_pa_set_tx_dig_filters(dev); 6151 } 6152 6153 b43_nphy_workarounds(dev); 6154 6155 /* Reset CCA, in init code it differs a little from standard way */ 6156 b43_phy_force_clock(dev, 1); 6157 tmp = b43_phy_read(dev, B43_NPHY_BBCFG); 6158 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA); 6159 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA); 6160 b43_phy_force_clock(dev, 0); 6161 6162 b43_mac_phy_clock_set(dev, true); 6163 6164 if (phy->rev < 7) { 6165 b43_nphy_pa_override(dev, false); 6166 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX); 6167 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX); 6168 b43_nphy_pa_override(dev, true); 6169 } 6170 6171 b43_nphy_classifier(dev, 0, 0); 6172 b43_nphy_read_clip_detection(dev, clip); 6173 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 6174 b43_nphy_bphy_init(dev); 6175 6176 tx_pwr_state = nphy->txpwrctrl; 6177 b43_nphy_tx_power_ctrl(dev, false); 6178 b43_nphy_tx_power_fix(dev); 6179 b43_nphy_tx_power_ctl_idle_tssi(dev); 6180 b43_nphy_tx_power_ctl_setup(dev); 6181 b43_nphy_tx_gain_table_upload(dev); 6182 6183 if (nphy->phyrxchain != 3) 6184 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain); 6185 if (nphy->mphase_cal_phase_id > 0) 6186 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ 6187 6188 do_rssi_cal = false; 6189 if (phy->rev >= 3) { 6190 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 6191 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq; 6192 else 6193 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq; 6194 6195 if (do_rssi_cal) 6196 b43_nphy_rssi_cal(dev); 6197 else 6198 b43_nphy_restore_rssi_cal(dev); 6199 } else { 6200 b43_nphy_rssi_cal(dev); 6201 } 6202 6203 if (!((nphy->measure_hold & 0x6) != 0)) { 6204 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 6205 do_cal = !nphy->iqcal_chanspec_2G.center_freq; 6206 else 6207 do_cal = !nphy->iqcal_chanspec_5G.center_freq; 6208 6209 if (nphy->mute) 6210 do_cal = false; 6211 6212 if (do_cal) { 6213 target = b43_nphy_get_tx_gains(dev); 6214 6215 if (nphy->antsel_type == 2) 6216 b43_nphy_superswitch_init(dev, true); 6217 if (nphy->perical != 2) { 6218 b43_nphy_rssi_cal(dev); 6219 if (phy->rev >= 3) { 6220 nphy->cal_orig_pwr_idx[0] = 6221 nphy->txpwrindex[0].index_internal; 6222 nphy->cal_orig_pwr_idx[1] = 6223 nphy->txpwrindex[1].index_internal; 6224 /* TODO N PHY Pre Calibrate TX Gain */ 6225 target = b43_nphy_get_tx_gains(dev); 6226 } 6227 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) 6228 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0) 6229 b43_nphy_save_cal(dev); 6230 } else if (nphy->mphase_cal_phase_id == 0) 6231 ;/* N PHY Periodic Calibration with arg 3 */ 6232 } else { 6233 b43_nphy_restore_cal(dev); 6234 } 6235 } 6236 6237 b43_nphy_tx_pwr_ctrl_coef_setup(dev); 6238 b43_nphy_tx_power_ctrl(dev, tx_pwr_state); 6239 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015); 6240 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320); 6241 if (phy->rev >= 3 && phy->rev <= 6) 6242 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); 6243 b43_nphy_tx_lpf_bw(dev); 6244 if (phy->rev >= 3) 6245 b43_nphy_spur_workaround(dev); 6246 6247 return 0; 6248} 6249 6250/************************************************** 6251 * Channel switching ops. 6252 **************************************************/ 6253 6254static void b43_chantab_phy_upload(struct b43_wldev *dev, 6255 const struct b43_phy_n_sfo_cfg *e) 6256{ 6257 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); 6258 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2); 6259 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3); 6260 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4); 6261 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5); 6262 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6); 6263} 6264 6265/* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */ 6266static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid) 6267{ 6268 switch (dev->dev->bus_type) { 6269#ifdef CONFIG_B43_BCMA 6270 case B43_BUS_BCMA: 6271 bcma_pmu_spuravoid_pllupdate(&dev->dev->bdev->bus->drv_cc, 6272 avoid); 6273 break; 6274#endif 6275#ifdef CONFIG_B43_SSB 6276 case B43_BUS_SSB: 6277 ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco, 6278 avoid); 6279 break; 6280#endif 6281 } 6282} 6283 6284/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ 6285static void b43_nphy_channel_setup(struct b43_wldev *dev, 6286 const struct b43_phy_n_sfo_cfg *e, 6287 struct ieee80211_channel *new_channel) 6288{ 6289 struct b43_phy *phy = &dev->phy; 6290 struct b43_phy_n *nphy = dev->phy.n; 6291 int ch = new_channel->hw_value; 6292 u16 tmp16; 6293 6294 if (new_channel->band == IEEE80211_BAND_5GHZ) { 6295 /* Switch to 2 GHz for a moment to access B43_PHY_B_BBCFG */ 6296 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); 6297 6298 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); 6299 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); 6300 /* Put BPHY in the reset */ 6301 b43_phy_set(dev, B43_PHY_B_BBCFG, 6302 B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX); 6303 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); 6304 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ); 6305 } else if (new_channel->band == IEEE80211_BAND_2GHZ) { 6306 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ); 6307 tmp16 = b43_read16(dev, B43_MMIO_PSM_PHY_HDR); 6308 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16 | 4); 6309 /* Take BPHY out of the reset */ 6310 b43_phy_mask(dev, B43_PHY_B_BBCFG, 6311 (u16)~(B43_PHY_B_BBCFG_RSTCCA | B43_PHY_B_BBCFG_RSTRX)); 6312 b43_write16(dev, B43_MMIO_PSM_PHY_HDR, tmp16); 6313 } 6314 6315 b43_chantab_phy_upload(dev, e); 6316 6317 if (new_channel->hw_value == 14) { 6318 b43_nphy_classifier(dev, 2, 0); 6319 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800); 6320 } else { 6321 b43_nphy_classifier(dev, 2, 2); 6322 if (new_channel->band == IEEE80211_BAND_2GHZ) 6323 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840); 6324 } 6325 6326 if (!nphy->txpwrctrl) 6327 b43_nphy_tx_power_fix(dev); 6328 6329 if (dev->phy.rev < 3) 6330 b43_nphy_adjust_lna_gain_table(dev); 6331 6332 b43_nphy_tx_lpf_bw(dev); 6333 6334 if (dev->phy.rev >= 3 && 6335 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) { 6336 u8 spuravoid = 0; 6337 6338 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) { 6339 spuravoid = 1; 6340 } else if (phy->rev >= 19) { 6341 /* TODO */ 6342 } else if (phy->rev >= 18) { 6343 /* TODO */ 6344 } else if (phy->rev >= 17) { 6345 /* TODO: Off for channels 1-11, but check 12-14! */ 6346 } else if (phy->rev >= 16) { 6347 /* TODO: Off for 2 GHz, but check 5 GHz! */ 6348 } else if (phy->rev >= 7) { 6349 if (!b43_is_40mhz(dev)) { /* 20MHz */ 6350 if (ch == 13 || ch == 14 || ch == 153) 6351 spuravoid = 1; 6352 } else { /* 40 MHz */ 6353 if (ch == 54) 6354 spuravoid = 1; 6355 } 6356 } else { 6357 if (!b43_is_40mhz(dev)) { /* 20MHz */ 6358 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14) 6359 spuravoid = 1; 6360 } else { /* 40MHz */ 6361 if (nphy->aband_spurwar_en && 6362 (ch == 38 || ch == 102 || ch == 118)) 6363 spuravoid = dev->dev->chip_id == 0x4716; 6364 } 6365 } 6366 6367 b43_nphy_pmu_spur_avoid(dev, spuravoid); 6368 6369 b43_mac_switch_freq(dev, spuravoid); 6370 6371 if (dev->phy.rev == 3 || dev->phy.rev == 4) 6372 b43_wireless_core_phy_pll_reset(dev); 6373 6374 if (spuravoid) 6375 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX); 6376 else 6377 b43_phy_mask(dev, B43_NPHY_BBCFG, 6378 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF); 6379 6380 b43_nphy_reset_cca(dev); 6381 6382 /* wl sets useless phy_isspuravoid here */ 6383 } 6384 6385 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830); 6386 6387 if (phy->rev >= 3) 6388 b43_nphy_spur_workaround(dev); 6389} 6390 6391/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ 6392static int b43_nphy_set_channel(struct b43_wldev *dev, 6393 struct ieee80211_channel *channel, 6394 enum nl80211_channel_type channel_type) 6395{ 6396 struct b43_phy *phy = &dev->phy; 6397 6398 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL; 6399 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL; 6400 const struct b43_nphy_chantabent_rev7 *tabent_r7 = NULL; 6401 const struct b43_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL; 6402 6403 u8 tmp; 6404 6405 if (phy->rev >= 19) { 6406 return -ESRCH; 6407 /* TODO */ 6408 } else if (phy->rev >= 7) { 6409 r2057_get_chantabent_rev7(dev, channel->center_freq, 6410 &tabent_r7, &tabent_r7_2g); 6411 if (!tabent_r7 && !tabent_r7_2g) 6412 return -ESRCH; 6413 } else if (phy->rev >= 3) { 6414 tabent_r3 = b43_nphy_get_chantabent_rev3(dev, 6415 channel->center_freq); 6416 if (!tabent_r3) 6417 return -ESRCH; 6418 } else { 6419 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, 6420 channel->hw_value); 6421 if (!tabent_r2) 6422 return -ESRCH; 6423 } 6424 6425 /* Channel is set later in common code, but we need to set it on our 6426 own to let this function's subcalls work properly. */ 6427 phy->channel = channel->hw_value; 6428 6429#if 0 6430 if (b43_channel_type_is_40mhz(phy->channel_type) != 6431 b43_channel_type_is_40mhz(channel_type)) 6432 ; /* TODO: BMAC BW Set (channel_type) */ 6433#endif 6434 6435 if (channel_type == NL80211_CHAN_HT40PLUS) { 6436 b43_phy_set(dev, B43_NPHY_RXCTL, B43_NPHY_RXCTL_BSELU20); 6437 if (phy->rev >= 7) 6438 b43_phy_set(dev, 0x310, 0x8000); 6439 } else if (channel_type == NL80211_CHAN_HT40MINUS) { 6440 b43_phy_mask(dev, B43_NPHY_RXCTL, ~B43_NPHY_RXCTL_BSELU20); 6441 if (phy->rev >= 7) 6442 b43_phy_mask(dev, 0x310, (u16)~0x8000); 6443 } 6444 6445 if (phy->rev >= 19) { 6446 /* TODO */ 6447 } else if (phy->rev >= 7) { 6448 const struct b43_phy_n_sfo_cfg *phy_regs = tabent_r7 ? 6449 &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs); 6450 6451 if (phy->radio_rev <= 4 || phy->radio_rev == 6) { 6452 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 2 : 0; 6453 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE0, ~2, tmp); 6454 b43_radio_maskset(dev, R2057_TIA_CONFIG_CORE1, ~2, tmp); 6455 } 6456 6457 b43_radio_2057_setup(dev, tabent_r7, tabent_r7_2g); 6458 b43_nphy_channel_setup(dev, phy_regs, channel); 6459 } else if (phy->rev >= 3) { 6460 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0; 6461 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp); 6462 b43_radio_2056_setup(dev, tabent_r3); 6463 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel); 6464 } else { 6465 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050; 6466 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp); 6467 b43_radio_2055_setup(dev, tabent_r2); 6468 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel); 6469 } 6470 6471 return 0; 6472} 6473 6474/************************************************** 6475 * Basic PHY ops. 6476 **************************************************/ 6477 6478static int b43_nphy_op_allocate(struct b43_wldev *dev) 6479{ 6480 struct b43_phy_n *nphy; 6481 6482 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL); 6483 if (!nphy) 6484 return -ENOMEM; 6485 6486 dev->phy.n = nphy; 6487 6488 return 0; 6489} 6490 6491static void b43_nphy_op_prepare_structs(struct b43_wldev *dev) 6492{ 6493 struct b43_phy *phy = &dev->phy; 6494 struct b43_phy_n *nphy = phy->n; 6495 struct ssb_sprom *sprom = dev->dev->bus_sprom; 6496 6497 memset(nphy, 0, sizeof(*nphy)); 6498 6499 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4); 6500 nphy->spur_avoid = (phy->rev >= 3) ? 6501 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE; 6502 nphy->gain_boost = true; /* this way we follow wl, assume it is true */ 6503 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ 6504 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */ 6505 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ 6506 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is 6507 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */ 6508 nphy->tx_pwr_idx[0] = 128; 6509 nphy->tx_pwr_idx[1] = 128; 6510 6511 /* Hardware TX power control and 5GHz power gain */ 6512 nphy->txpwrctrl = false; 6513 nphy->pwg_gain_5ghz = false; 6514 if (dev->phy.rev >= 3 || 6515 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE && 6516 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) { 6517 nphy->txpwrctrl = true; 6518 nphy->pwg_gain_5ghz = true; 6519 } else if (sprom->revision >= 4) { 6520 if (dev->phy.rev >= 2 && 6521 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) { 6522 nphy->txpwrctrl = true; 6523#ifdef CONFIG_B43_SSB 6524 if (dev->dev->bus_type == B43_BUS_SSB && 6525 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) { 6526 struct pci_dev *pdev = 6527 dev->dev->sdev->bus->host_pci; 6528 if (pdev->device == 0x4328 || 6529 pdev->device == 0x432a) 6530 nphy->pwg_gain_5ghz = true; 6531 } 6532#endif 6533 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) { 6534 nphy->pwg_gain_5ghz = true; 6535 } 6536 } 6537 6538 if (dev->phy.rev >= 3) { 6539 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2; 6540 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2; 6541 } 6542} 6543 6544static void b43_nphy_op_free(struct b43_wldev *dev) 6545{ 6546 struct b43_phy *phy = &dev->phy; 6547 struct b43_phy_n *nphy = phy->n; 6548 6549 kfree(nphy); 6550 phy->n = NULL; 6551} 6552 6553static int b43_nphy_op_init(struct b43_wldev *dev) 6554{ 6555 return b43_phy_initn(dev); 6556} 6557 6558static inline void check_phyreg(struct b43_wldev *dev, u16 offset) 6559{ 6560#if B43_DEBUG 6561 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) { 6562 /* OFDM registers are onnly available on A/G-PHYs */ 6563 b43err(dev->wl, "Invalid OFDM PHY access at " 6564 "0x%04X on N-PHY\n", offset); 6565 dump_stack(); 6566 } 6567 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) { 6568 /* Ext-G registers are only available on G-PHYs */ 6569 b43err(dev->wl, "Invalid EXT-G PHY access at " 6570 "0x%04X on N-PHY\n", offset); 6571 dump_stack(); 6572 } 6573#endif /* B43_DEBUG */ 6574} 6575 6576static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask, 6577 u16 set) 6578{ 6579 check_phyreg(dev, reg); 6580 b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg); 6581 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set); 6582 dev->phy.writes_counter = 1; 6583} 6584 6585static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg) 6586{ 6587 /* Register 1 is a 32-bit register. */ 6588 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); 6589 6590 if (dev->phy.rev >= 7) 6591 reg |= 0x200; /* Radio 0x2057 */ 6592 else 6593 reg |= 0x100; 6594 6595 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); 6596 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW); 6597} 6598 6599static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value) 6600{ 6601 /* Register 1 is a 32-bit register. */ 6602 B43_WARN_ON(dev->phy.rev < 7 && reg == 1); 6603 6604 b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg); 6605 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value); 6606} 6607 6608/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ 6609static void b43_nphy_op_software_rfkill(struct b43_wldev *dev, 6610 bool blocked) 6611{ 6612 struct b43_phy *phy = &dev->phy; 6613 6614 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED) 6615 b43err(dev->wl, "MAC not suspended\n"); 6616 6617 if (blocked) { 6618 if (phy->rev >= 19) { 6619 /* TODO */ 6620 } else if (phy->rev >= 8) { 6621 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 6622 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 6623 } else if (phy->rev >= 7) { 6624 /* Nothing needed */ 6625 } else if (phy->rev >= 3) { 6626 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD, 6627 ~B43_NPHY_RFCTL_CMD_CHIP0PU); 6628 6629 b43_radio_mask(dev, 0x09, ~0x2); 6630 6631 b43_radio_write(dev, 0x204D, 0); 6632 b43_radio_write(dev, 0x2053, 0); 6633 b43_radio_write(dev, 0x2058, 0); 6634 b43_radio_write(dev, 0x205E, 0); 6635 b43_radio_mask(dev, 0x2062, ~0xF0); 6636 b43_radio_write(dev, 0x2064, 0); 6637 6638 b43_radio_write(dev, 0x304D, 0); 6639 b43_radio_write(dev, 0x3053, 0); 6640 b43_radio_write(dev, 0x3058, 0); 6641 b43_radio_write(dev, 0x305E, 0); 6642 b43_radio_mask(dev, 0x3062, ~0xF0); 6643 b43_radio_write(dev, 0x3064, 0); 6644 } 6645 } else { 6646 if (phy->rev >= 19) { 6647 /* TODO */ 6648 } else if (phy->rev >= 7) { 6649 if (!dev->phy.radio_on) 6650 b43_radio_2057_init(dev); 6651 b43_switch_channel(dev, dev->phy.channel); 6652 } else if (phy->rev >= 3) { 6653 if (!dev->phy.radio_on) 6654 b43_radio_init2056(dev); 6655 b43_switch_channel(dev, dev->phy.channel); 6656 } else { 6657 b43_radio_init2055(dev); 6658 } 6659 } 6660} 6661 6662/* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */ 6663static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on) 6664{ 6665 struct b43_phy *phy = &dev->phy; 6666 u16 override = on ? 0x0 : 0x7FFF; 6667 u16 core = on ? 0xD : 0x00FD; 6668 6669 if (phy->rev >= 19) { 6670 /* TODO */ 6671 } else if (phy->rev >= 3) { 6672 if (on) { 6673 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); 6674 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); 6675 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); 6676 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); 6677 } else { 6678 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override); 6679 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core); 6680 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); 6681 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core); 6682 } 6683 } else { 6684 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override); 6685 } 6686} 6687 6688static int b43_nphy_op_switch_channel(struct b43_wldev *dev, 6689 unsigned int new_channel) 6690{ 6691 struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan; 6692 enum nl80211_channel_type channel_type = 6693 cfg80211_get_chandef_type(&dev->wl->hw->conf.chandef); 6694 6695 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) { 6696 if ((new_channel < 1) || (new_channel > 14)) 6697 return -EINVAL; 6698 } else { 6699 if (new_channel > 200) 6700 return -EINVAL; 6701 } 6702 6703 return b43_nphy_set_channel(dev, channel, channel_type); 6704} 6705 6706static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev) 6707{ 6708 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) 6709 return 1; 6710 return 36; 6711} 6712 6713const struct b43_phy_operations b43_phyops_n = { 6714 .allocate = b43_nphy_op_allocate, 6715 .free = b43_nphy_op_free, 6716 .prepare_structs = b43_nphy_op_prepare_structs, 6717 .init = b43_nphy_op_init, 6718 .phy_maskset = b43_nphy_op_maskset, 6719 .radio_read = b43_nphy_op_radio_read, 6720 .radio_write = b43_nphy_op_radio_write, 6721 .software_rfkill = b43_nphy_op_software_rfkill, 6722 .switch_analog = b43_nphy_op_switch_analog, 6723 .switch_channel = b43_nphy_op_switch_channel, 6724 .get_default_chan = b43_nphy_op_get_default_chan, 6725 .recalc_txpower = b43_nphy_op_recalc_txpower, 6726}; 6727