1/* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef DEBUG_H 18#define DEBUG_H 19 20#include "hw.h" 21#include "dfs_debug.h" 22 23struct ath_txq; 24struct ath_buf; 25struct fft_sample_tlv; 26 27#ifdef CONFIG_ATH9K_DEBUGFS 28#define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++ 29#define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++) 30#define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++ 31#define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++ 32#define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++; 33#else 34#define TX_STAT_INC(q, c) do { } while (0) 35#define RX_STAT_INC(c) 36#define RESET_STAT_INC(sc, type) do { } while (0) 37#define ANT_STAT_INC(i, c) do { } while (0) 38#define ANT_LNA_INC(i, c) do { } while (0) 39#endif 40 41enum ath_reset_type { 42 RESET_TYPE_BB_HANG, 43 RESET_TYPE_BB_WATCHDOG, 44 RESET_TYPE_FATAL_INT, 45 RESET_TYPE_TX_ERROR, 46 RESET_TYPE_TX_GTT, 47 RESET_TYPE_TX_HANG, 48 RESET_TYPE_PLL_HANG, 49 RESET_TYPE_MAC_HANG, 50 RESET_TYPE_BEACON_STUCK, 51 RESET_TYPE_MCI, 52 RESET_TYPE_CALIBRATION, 53 __RESET_TYPE_MAX 54}; 55 56#ifdef CONFIG_ATH9K_DEBUGFS 57 58/** 59 * struct ath_interrupt_stats - Contains statistics about interrupts 60 * @total: Total no. of interrupts generated so far 61 * @rxok: RX with no errors 62 * @rxlp: RX with low priority RX 63 * @rxhp: RX with high priority, uapsd only 64 * @rxeol: RX with no more RXDESC available 65 * @rxorn: RX FIFO overrun 66 * @txok: TX completed at the requested rate 67 * @txurn: TX FIFO underrun 68 * @mib: MIB regs reaching its threshold 69 * @rxphyerr: RX with phy errors 70 * @rx_keycache_miss: RX with key cache misses 71 * @swba: Software Beacon Alert 72 * @bmiss: Beacon Miss 73 * @bnr: Beacon Not Ready 74 * @cst: Carrier Sense TImeout 75 * @gtt: Global TX Timeout 76 * @tim: RX beacon TIM occurrence 77 * @cabend: RX End of CAB traffic 78 * @dtimsync: DTIM sync lossage 79 * @dtim: RX Beacon with DTIM 80 * @bb_watchdog: Baseband watchdog 81 * @tsfoor: TSF out of range, indicates that the corrected TSF received 82 * from a beacon differs from the PCU's internal TSF by more than a 83 * (programmable) threshold 84 * @local_timeout: Internal bus timeout. 85 * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets 86 * @gen_timer: Generic hardware timer interrupt 87 */ 88struct ath_interrupt_stats { 89 u32 total; 90 u32 rxok; 91 u32 rxlp; 92 u32 rxhp; 93 u32 rxeol; 94 u32 rxorn; 95 u32 txok; 96 u32 txeol; 97 u32 txurn; 98 u32 mib; 99 u32 rxphyerr; 100 u32 rx_keycache_miss; 101 u32 swba; 102 u32 bmiss; 103 u32 bnr; 104 u32 cst; 105 u32 gtt; 106 u32 tim; 107 u32 cabend; 108 u32 dtimsync; 109 u32 dtim; 110 u32 bb_watchdog; 111 u32 tsfoor; 112 u32 mci; 113 u32 gen_timer; 114 115 /* Sync-cause stats */ 116 u32 sync_cause_all; 117 u32 sync_rtc_irq; 118 u32 sync_mac_irq; 119 u32 eeprom_illegal_access; 120 u32 apb_timeout; 121 u32 pci_mode_conflict; 122 u32 host1_fatal; 123 u32 host1_perr; 124 u32 trcv_fifo_perr; 125 u32 radm_cpl_ep; 126 u32 radm_cpl_dllp_abort; 127 u32 radm_cpl_tlp_abort; 128 u32 radm_cpl_ecrc_err; 129 u32 radm_cpl_timeout; 130 u32 local_timeout; 131 u32 pm_access; 132 u32 mac_awake; 133 u32 mac_asleep; 134 u32 mac_sleep_access; 135}; 136 137 138/** 139 * struct ath_tx_stats - Statistics about TX 140 * @tx_pkts_all: No. of total frames transmitted, including ones that 141 may have had errors. 142 * @tx_bytes_all: No. of total bytes transmitted, including ones that 143 may have had errors. 144 * @queued: Total MPDUs (non-aggr) queued 145 * @completed: Total MPDUs (non-aggr) completed 146 * @a_aggr: Total no. of aggregates queued 147 * @a_queued_hw: Total AMPDUs queued to hardware 148 * @a_queued_sw: Total AMPDUs queued to software queues 149 * @a_completed: Total AMPDUs completed 150 * @a_retries: No. of AMPDUs retried (SW) 151 * @a_xretries: No. of AMPDUs dropped due to xretries 152 * @txerr_filtered: No. of frames with TXERR_FILT flag set. 153 * @fifo_underrun: FIFO underrun occurrences 154 Valid only for: 155 - non-aggregate condition. 156 - first packet of aggregate. 157 * @xtxop: No. of frames filtered because of TXOP limit 158 * @timer_exp: Transmit timer expiry 159 * @desc_cfg_err: Descriptor configuration errors 160 * @data_urn: TX data underrun errors 161 * @delim_urn: TX delimiter underrun errors 162 * @puttxbuf: Number of times hardware was given txbuf to write. 163 * @txstart: Number of times hardware was told to start tx. 164 * @txprocdesc: Number of times tx descriptor was processed 165 * @txfailed: Out-of-memory or other errors in xmit path. 166 */ 167struct ath_tx_stats { 168 u32 tx_pkts_all; 169 u32 tx_bytes_all; 170 u32 queued; 171 u32 completed; 172 u32 xretries; 173 u32 a_aggr; 174 u32 a_queued_hw; 175 u32 a_queued_sw; 176 u32 a_completed; 177 u32 a_retries; 178 u32 a_xretries; 179 u32 txerr_filtered; 180 u32 fifo_underrun; 181 u32 xtxop; 182 u32 timer_exp; 183 u32 desc_cfg_err; 184 u32 data_underrun; 185 u32 delim_underrun; 186 u32 puttxbuf; 187 u32 txstart; 188 u32 txprocdesc; 189 u32 txfailed; 190}; 191 192/* 193 * Various utility macros to print TX/Queue counters. 194 */ 195#define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum 196#define TXSTATS sc->debug.stats.txstats 197#define PR(str, elem) \ 198 do { \ 199 seq_printf(file, "%s%13u%11u%10u%10u\n", str, \ 200 TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\ 201 TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\ 202 TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\ 203 TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \ 204 } while(0) 205 206struct ath_rx_rate_stats { 207 struct { 208 u32 ht20_cnt; 209 u32 ht40_cnt; 210 u32 sgi_cnt; 211 u32 lgi_cnt; 212 } ht_stats[24]; 213 214 struct { 215 u32 ofdm_cnt; 216 } ofdm_stats[8]; 217 218 struct { 219 u32 cck_lp_cnt; 220 u32 cck_sp_cnt; 221 } cck_stats[4]; 222}; 223 224#define ANT_MAIN 0 225#define ANT_ALT 1 226 227struct ath_antenna_stats { 228 u32 recv_cnt; 229 u32 rssi_avg; 230 u32 lna_recv_cnt[4]; 231 u32 lna_attempt_cnt[4]; 232}; 233 234struct ath_stats { 235 struct ath_interrupt_stats istats; 236 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES]; 237 struct ath_rx_stats rxstats; 238 struct ath_dfs_stats dfs_stats; 239 struct ath_antenna_stats ant_stats[2]; 240 u32 reset[__RESET_TYPE_MAX]; 241}; 242 243struct ath9k_debug { 244 struct dentry *debugfs_phy; 245 u32 regidx; 246 struct ath_stats stats; 247}; 248 249int ath9k_init_debug(struct ath_hw *ah); 250void ath9k_deinit_debug(struct ath_softc *sc); 251 252void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 253void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf, 254 struct ath_tx_status *ts, struct ath_txq *txq, 255 unsigned int flags); 256void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs); 257int ath9k_get_et_sset_count(struct ieee80211_hw *hw, 258 struct ieee80211_vif *vif, int sset); 259void ath9k_get_et_stats(struct ieee80211_hw *hw, 260 struct ieee80211_vif *vif, 261 struct ethtool_stats *stats, u64 *data); 262void ath9k_get_et_strings(struct ieee80211_hw *hw, 263 struct ieee80211_vif *vif, 264 u32 sset, u8 *data); 265void ath9k_sta_add_debugfs(struct ieee80211_hw *hw, 266 struct ieee80211_vif *vif, 267 struct ieee80211_sta *sta, 268 struct dentry *dir); 269void ath9k_debug_stat_ant(struct ath_softc *sc, 270 struct ath_hw_antcomb_conf *div_ant_conf, 271 int main_rssi_avg, int alt_rssi_avg); 272void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause); 273 274#else 275 276static inline int ath9k_init_debug(struct ath_hw *ah) 277{ 278 return 0; 279} 280 281static inline void ath9k_deinit_debug(struct ath_softc *sc) 282{ 283} 284static inline void ath_debug_stat_interrupt(struct ath_softc *sc, 285 enum ath9k_int status) 286{ 287} 288static inline void ath_debug_stat_tx(struct ath_softc *sc, 289 struct ath_buf *bf, 290 struct ath_tx_status *ts, 291 struct ath_txq *txq, 292 unsigned int flags) 293{ 294} 295static inline void ath_debug_stat_rx(struct ath_softc *sc, 296 struct ath_rx_status *rs) 297{ 298} 299static inline void ath9k_debug_stat_ant(struct ath_softc *sc, 300 struct ath_hw_antcomb_conf *div_ant_conf, 301 int main_rssi_avg, int alt_rssi_avg) 302{ 303 304} 305 306static inline void 307ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause) 308{ 309} 310 311#endif /* CONFIG_ATH9K_DEBUGFS */ 312 313#ifdef CONFIG_ATH9K_STATION_STATISTICS 314void ath_debug_rate_stats(struct ath_softc *sc, 315 struct ath_rx_status *rs, 316 struct sk_buff *skb); 317#else 318static inline void ath_debug_rate_stats(struct ath_softc *sc, 319 struct ath_rx_status *rs, 320 struct sk_buff *skb) 321{ 322} 323#endif /* CONFIG_ATH9K_STATION_STATISTICS */ 324 325#endif /* DEBUG_H */ 326