1/* 2 * wanXL serial card driver for Linux 3 * host part 4 * 5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of version 2 of the GNU General Public License 9 * as published by the Free Software Foundation. 10 * 11 * Status: 12 * - Only DTE (external clock) support with NRZ and NRZI encodings 13 * - wanXL100 will require minor driver modifications, no access to hw 14 */ 15 16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/slab.h> 21#include <linux/sched.h> 22#include <linux/types.h> 23#include <linux/fcntl.h> 24#include <linux/string.h> 25#include <linux/errno.h> 26#include <linux/init.h> 27#include <linux/interrupt.h> 28#include <linux/ioport.h> 29#include <linux/netdevice.h> 30#include <linux/hdlc.h> 31#include <linux/pci.h> 32#include <linux/dma-mapping.h> 33#include <linux/delay.h> 34#include <asm/io.h> 35 36#include "wanxl.h" 37 38static const char* version = "wanXL serial card driver version: 0.48"; 39 40#define PLX_CTL_RESET 0x40000000 /* adapter reset */ 41 42#undef DEBUG_PKT 43#undef DEBUG_PCI 44 45/* MAILBOX #1 - PUTS COMMANDS */ 46#define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */ 47#ifdef __LITTLE_ENDIAN 48#define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */ 49#else 50#define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */ 51#endif 52 53/* MAILBOX #2 - DRAM SIZE */ 54#define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */ 55 56 57struct port { 58 struct net_device *dev; 59 struct card *card; 60 spinlock_t lock; /* for wanxl_xmit */ 61 int node; /* physical port #0 - 3 */ 62 unsigned int clock_type; 63 int tx_in, tx_out; 64 struct sk_buff *tx_skbs[TX_BUFFERS]; 65}; 66 67 68struct card_status { 69 desc_t rx_descs[RX_QUEUE_LENGTH]; 70 port_status_t port_status[4]; 71}; 72 73 74struct card { 75 int n_ports; /* 1, 2 or 4 ports */ 76 u8 irq; 77 78 u8 __iomem *plx; /* PLX PCI9060 virtual base address */ 79 struct pci_dev *pdev; /* for pci_name(pdev) */ 80 int rx_in; 81 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH]; 82 struct card_status *status; /* shared between host and card */ 83 dma_addr_t status_address; 84 struct port ports[0]; /* 1 - 4 port structures follow */ 85}; 86 87 88 89static inline struct port *dev_to_port(struct net_device *dev) 90{ 91 return (struct port *)dev_to_hdlc(dev)->priv; 92} 93 94 95static inline port_status_t *get_status(struct port *port) 96{ 97 return &port->card->status->port_status[port->node]; 98} 99 100 101#ifdef DEBUG_PCI 102static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr, 103 size_t size, int direction) 104{ 105 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction); 106 if (addr + size > 0x100000000LL) 107 pr_crit("%s: pci_map_single() returned memory at 0x%llx!\n", 108 pci_name(pdev), (unsigned long long)addr); 109 return addr; 110} 111 112#undef pci_map_single 113#define pci_map_single pci_map_single_debug 114#endif 115 116 117/* Cable and/or personality module change interrupt service */ 118static inline void wanxl_cable_intr(struct port *port) 119{ 120 u32 value = get_status(port)->cable; 121 int valid = 1; 122 const char *cable, *pm, *dte = "", *dsr = "", *dcd = ""; 123 124 switch(value & 0x7) { 125 case STATUS_CABLE_V35: cable = "V.35"; break; 126 case STATUS_CABLE_X21: cable = "X.21"; break; 127 case STATUS_CABLE_V24: cable = "V.24"; break; 128 case STATUS_CABLE_EIA530: cable = "EIA530"; break; 129 case STATUS_CABLE_NONE: cable = "no"; break; 130 default: cable = "invalid"; 131 } 132 133 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) { 134 case STATUS_CABLE_V35: pm = "V.35"; break; 135 case STATUS_CABLE_X21: pm = "X.21"; break; 136 case STATUS_CABLE_V24: pm = "V.24"; break; 137 case STATUS_CABLE_EIA530: pm = "EIA530"; break; 138 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break; 139 default: pm = "invalid personality"; valid = 0; 140 } 141 142 if (valid) { 143 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) { 144 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" : 145 ", DSR off"; 146 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" : 147 ", carrier off"; 148 } 149 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE"; 150 } 151 netdev_info(port->dev, "%s%s module, %s cable%s%s\n", 152 pm, dte, cable, dsr, dcd); 153 154 if (value & STATUS_CABLE_DCD) 155 netif_carrier_on(port->dev); 156 else 157 netif_carrier_off(port->dev); 158} 159 160 161 162/* Transmit complete interrupt service */ 163static inline void wanxl_tx_intr(struct port *port) 164{ 165 struct net_device *dev = port->dev; 166 while (1) { 167 desc_t *desc = &get_status(port)->tx_descs[port->tx_in]; 168 struct sk_buff *skb = port->tx_skbs[port->tx_in]; 169 170 switch (desc->stat) { 171 case PACKET_FULL: 172 case PACKET_EMPTY: 173 netif_wake_queue(dev); 174 return; 175 176 case PACKET_UNDERRUN: 177 dev->stats.tx_errors++; 178 dev->stats.tx_fifo_errors++; 179 break; 180 181 default: 182 dev->stats.tx_packets++; 183 dev->stats.tx_bytes += skb->len; 184 } 185 desc->stat = PACKET_EMPTY; /* Free descriptor */ 186 pci_unmap_single(port->card->pdev, desc->address, skb->len, 187 PCI_DMA_TODEVICE); 188 dev_kfree_skb_irq(skb); 189 port->tx_in = (port->tx_in + 1) % TX_BUFFERS; 190 } 191} 192 193 194 195/* Receive complete interrupt service */ 196static inline void wanxl_rx_intr(struct card *card) 197{ 198 desc_t *desc; 199 while (desc = &card->status->rx_descs[card->rx_in], 200 desc->stat != PACKET_EMPTY) { 201 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports) 202 pr_crit("%s: received packet for nonexistent port\n", 203 pci_name(card->pdev)); 204 else { 205 struct sk_buff *skb = card->rx_skbs[card->rx_in]; 206 struct port *port = &card->ports[desc->stat & 207 PACKET_PORT_MASK]; 208 struct net_device *dev = port->dev; 209 210 if (!skb) 211 dev->stats.rx_dropped++; 212 else { 213 pci_unmap_single(card->pdev, desc->address, 214 BUFFER_LENGTH, 215 PCI_DMA_FROMDEVICE); 216 skb_put(skb, desc->length); 217 218#ifdef DEBUG_PKT 219 printk(KERN_DEBUG "%s RX(%i):", dev->name, 220 skb->len); 221 debug_frame(skb); 222#endif 223 dev->stats.rx_packets++; 224 dev->stats.rx_bytes += skb->len; 225 skb->protocol = hdlc_type_trans(skb, dev); 226 netif_rx(skb); 227 skb = NULL; 228 } 229 230 if (!skb) { 231 skb = dev_alloc_skb(BUFFER_LENGTH); 232 desc->address = skb ? 233 pci_map_single(card->pdev, skb->data, 234 BUFFER_LENGTH, 235 PCI_DMA_FROMDEVICE) : 0; 236 card->rx_skbs[card->rx_in] = skb; 237 } 238 } 239 desc->stat = PACKET_EMPTY; /* Free descriptor */ 240 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH; 241 } 242} 243 244 245 246static irqreturn_t wanxl_intr(int irq, void* dev_id) 247{ 248 struct card *card = dev_id; 249 int i; 250 u32 stat; 251 int handled = 0; 252 253 254 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) { 255 handled = 1; 256 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD); 257 258 for (i = 0; i < card->n_ports; i++) { 259 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i))) 260 wanxl_tx_intr(&card->ports[i]); 261 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i))) 262 wanxl_cable_intr(&card->ports[i]); 263 } 264 if (stat & (1 << DOORBELL_FROM_CARD_RX)) 265 wanxl_rx_intr(card); 266 } 267 268 return IRQ_RETVAL(handled); 269} 270 271 272 273static netdev_tx_t wanxl_xmit(struct sk_buff *skb, struct net_device *dev) 274{ 275 struct port *port = dev_to_port(dev); 276 desc_t *desc; 277 278 spin_lock(&port->lock); 279 280 desc = &get_status(port)->tx_descs[port->tx_out]; 281 if (desc->stat != PACKET_EMPTY) { 282 /* should never happen - previous xmit should stop queue */ 283#ifdef DEBUG_PKT 284 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); 285#endif 286 netif_stop_queue(dev); 287 spin_unlock(&port->lock); 288 return NETDEV_TX_BUSY; /* request packet to be queued */ 289 } 290 291#ifdef DEBUG_PKT 292 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 293 debug_frame(skb); 294#endif 295 296 port->tx_skbs[port->tx_out] = skb; 297 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len, 298 PCI_DMA_TODEVICE); 299 desc->length = skb->len; 300 desc->stat = PACKET_FULL; 301 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node), 302 port->card->plx + PLX_DOORBELL_TO_CARD); 303 304 port->tx_out = (port->tx_out + 1) % TX_BUFFERS; 305 306 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) { 307 netif_stop_queue(dev); 308#ifdef DEBUG_PKT 309 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name); 310#endif 311 } 312 313 spin_unlock(&port->lock); 314 return NETDEV_TX_OK; 315} 316 317 318 319static int wanxl_attach(struct net_device *dev, unsigned short encoding, 320 unsigned short parity) 321{ 322 struct port *port = dev_to_port(dev); 323 324 if (encoding != ENCODING_NRZ && 325 encoding != ENCODING_NRZI) 326 return -EINVAL; 327 328 if (parity != PARITY_NONE && 329 parity != PARITY_CRC32_PR1_CCITT && 330 parity != PARITY_CRC16_PR1_CCITT && 331 parity != PARITY_CRC32_PR0_CCITT && 332 parity != PARITY_CRC16_PR0_CCITT) 333 return -EINVAL; 334 335 get_status(port)->encoding = encoding; 336 get_status(port)->parity = parity; 337 return 0; 338} 339 340 341 342static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 343{ 344 const size_t size = sizeof(sync_serial_settings); 345 sync_serial_settings line; 346 struct port *port = dev_to_port(dev); 347 348 if (cmd != SIOCWANDEV) 349 return hdlc_ioctl(dev, ifr, cmd); 350 351 switch (ifr->ifr_settings.type) { 352 case IF_GET_IFACE: 353 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; 354 if (ifr->ifr_settings.size < size) { 355 ifr->ifr_settings.size = size; /* data size wanted */ 356 return -ENOBUFS; 357 } 358 memset(&line, 0, sizeof(line)); 359 line.clock_type = get_status(port)->clocking; 360 line.clock_rate = 0; 361 line.loopback = 0; 362 363 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size)) 364 return -EFAULT; 365 return 0; 366 367 case IF_IFACE_SYNC_SERIAL: 368 if (!capable(CAP_NET_ADMIN)) 369 return -EPERM; 370 if (dev->flags & IFF_UP) 371 return -EBUSY; 372 373 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync, 374 size)) 375 return -EFAULT; 376 377 if (line.clock_type != CLOCK_EXT && 378 line.clock_type != CLOCK_TXFROMRX) 379 return -EINVAL; /* No such clock setting */ 380 381 if (line.loopback != 0) 382 return -EINVAL; 383 384 get_status(port)->clocking = line.clock_type; 385 return 0; 386 387 default: 388 return hdlc_ioctl(dev, ifr, cmd); 389 } 390} 391 392 393 394static int wanxl_open(struct net_device *dev) 395{ 396 struct port *port = dev_to_port(dev); 397 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD; 398 unsigned long timeout; 399 int i; 400 401 if (get_status(port)->open) { 402 netdev_err(dev, "port already open\n"); 403 return -EIO; 404 } 405 if ((i = hdlc_open(dev)) != 0) 406 return i; 407 408 port->tx_in = port->tx_out = 0; 409 for (i = 0; i < TX_BUFFERS; i++) 410 get_status(port)->tx_descs[i].stat = PACKET_EMPTY; 411 /* signal the card */ 412 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr); 413 414 timeout = jiffies + HZ; 415 do { 416 if (get_status(port)->open) { 417 netif_start_queue(dev); 418 return 0; 419 } 420 } while (time_after(timeout, jiffies)); 421 422 netdev_err(dev, "unable to open port\n"); 423 /* ask the card to close the port, should it be still alive */ 424 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr); 425 return -EFAULT; 426} 427 428 429 430static int wanxl_close(struct net_device *dev) 431{ 432 struct port *port = dev_to_port(dev); 433 unsigned long timeout; 434 int i; 435 436 hdlc_close(dev); 437 /* signal the card */ 438 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), 439 port->card->plx + PLX_DOORBELL_TO_CARD); 440 441 timeout = jiffies + HZ; 442 do { 443 if (!get_status(port)->open) 444 break; 445 } while (time_after(timeout, jiffies)); 446 447 if (get_status(port)->open) 448 netdev_err(dev, "unable to close port\n"); 449 450 netif_stop_queue(dev); 451 452 for (i = 0; i < TX_BUFFERS; i++) { 453 desc_t *desc = &get_status(port)->tx_descs[i]; 454 455 if (desc->stat != PACKET_EMPTY) { 456 desc->stat = PACKET_EMPTY; 457 pci_unmap_single(port->card->pdev, desc->address, 458 port->tx_skbs[i]->len, 459 PCI_DMA_TODEVICE); 460 dev_kfree_skb(port->tx_skbs[i]); 461 } 462 } 463 return 0; 464} 465 466 467 468static struct net_device_stats *wanxl_get_stats(struct net_device *dev) 469{ 470 struct port *port = dev_to_port(dev); 471 472 dev->stats.rx_over_errors = get_status(port)->rx_overruns; 473 dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors; 474 dev->stats.rx_errors = dev->stats.rx_over_errors + 475 dev->stats.rx_frame_errors; 476 return &dev->stats; 477} 478 479 480 481static int wanxl_puts_command(struct card *card, u32 cmd) 482{ 483 unsigned long timeout = jiffies + 5 * HZ; 484 485 writel(cmd, card->plx + PLX_MAILBOX_1); 486 do { 487 if (readl(card->plx + PLX_MAILBOX_1) == 0) 488 return 0; 489 490 schedule(); 491 }while (time_after(timeout, jiffies)); 492 493 return -1; 494} 495 496 497 498static void wanxl_reset(struct card *card) 499{ 500 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET; 501 502 writel(0x80, card->plx + PLX_MAILBOX_0); 503 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL); 504 readl(card->plx + PLX_CONTROL); /* wait for posted write */ 505 udelay(1); 506 writel(old_value, card->plx + PLX_CONTROL); 507 readl(card->plx + PLX_CONTROL); /* wait for posted write */ 508} 509 510 511 512static void wanxl_pci_remove_one(struct pci_dev *pdev) 513{ 514 struct card *card = pci_get_drvdata(pdev); 515 int i; 516 517 for (i = 0; i < card->n_ports; i++) { 518 unregister_hdlc_device(card->ports[i].dev); 519 free_netdev(card->ports[i].dev); 520 } 521 522 /* unregister and free all host resources */ 523 if (card->irq) 524 free_irq(card->irq, card); 525 526 wanxl_reset(card); 527 528 for (i = 0; i < RX_QUEUE_LENGTH; i++) 529 if (card->rx_skbs[i]) { 530 pci_unmap_single(card->pdev, 531 card->status->rx_descs[i].address, 532 BUFFER_LENGTH, PCI_DMA_FROMDEVICE); 533 dev_kfree_skb(card->rx_skbs[i]); 534 } 535 536 if (card->plx) 537 iounmap(card->plx); 538 539 if (card->status) 540 pci_free_consistent(pdev, sizeof(struct card_status), 541 card->status, card->status_address); 542 543 pci_release_regions(pdev); 544 pci_disable_device(pdev); 545 kfree(card); 546} 547 548 549#include "wanxlfw.inc" 550 551static const struct net_device_ops wanxl_ops = { 552 .ndo_open = wanxl_open, 553 .ndo_stop = wanxl_close, 554 .ndo_change_mtu = hdlc_change_mtu, 555 .ndo_start_xmit = hdlc_start_xmit, 556 .ndo_do_ioctl = wanxl_ioctl, 557 .ndo_get_stats = wanxl_get_stats, 558}; 559 560static int wanxl_pci_init_one(struct pci_dev *pdev, 561 const struct pci_device_id *ent) 562{ 563 struct card *card; 564 u32 ramsize, stat; 565 unsigned long timeout; 566 u32 plx_phy; /* PLX PCI base address */ 567 u32 mem_phy; /* memory PCI base addr */ 568 u8 __iomem *mem; /* memory virtual base addr */ 569 int i, ports, alloc_size; 570 571#ifndef MODULE 572 pr_info_once("%s\n", version); 573#endif 574 575 i = pci_enable_device(pdev); 576 if (i) 577 return i; 578 579 /* QUICC can only access first 256 MB of host RAM directly, 580 but PLX9060 DMA does 32-bits for actual packet data transfers */ 581 582 /* FIXME when PCI/DMA subsystems are fixed. 583 We set both dma_mask and consistent_dma_mask to 28 bits 584 and pray pci_alloc_consistent() will use this info. It should 585 work on most platforms */ 586 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(28)) || 587 pci_set_dma_mask(pdev, DMA_BIT_MASK(28))) { 588 pr_err("No usable DMA configuration\n"); 589 return -EIO; 590 } 591 592 i = pci_request_regions(pdev, "wanXL"); 593 if (i) { 594 pci_disable_device(pdev); 595 return i; 596 } 597 598 switch (pdev->device) { 599 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break; 600 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break; 601 default: ports = 4; 602 } 603 604 alloc_size = sizeof(struct card) + ports * sizeof(struct port); 605 card = kzalloc(alloc_size, GFP_KERNEL); 606 if (card == NULL) { 607 pci_release_regions(pdev); 608 pci_disable_device(pdev); 609 return -ENOBUFS; 610 } 611 612 pci_set_drvdata(pdev, card); 613 card->pdev = pdev; 614 615 card->status = pci_alloc_consistent(pdev, 616 sizeof(struct card_status), 617 &card->status_address); 618 if (card->status == NULL) { 619 wanxl_pci_remove_one(pdev); 620 return -ENOBUFS; 621 } 622 623#ifdef DEBUG_PCI 624 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory" 625 " at 0x%LX\n", pci_name(pdev), 626 (unsigned long long)card->status_address); 627#endif 628 629 /* FIXME when PCI/DMA subsystems are fixed. 630 We set both dma_mask and consistent_dma_mask back to 32 bits 631 to indicate the card can do 32-bit DMA addressing */ 632 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) || 633 pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 634 pr_err("No usable DMA configuration\n"); 635 wanxl_pci_remove_one(pdev); 636 return -EIO; 637 } 638 639 /* set up PLX mapping */ 640 plx_phy = pci_resource_start(pdev, 0); 641 642 card->plx = ioremap_nocache(plx_phy, 0x70); 643 if (!card->plx) { 644 pr_err("ioremap() failed\n"); 645 wanxl_pci_remove_one(pdev); 646 return -EFAULT; 647 } 648 649#if RESET_WHILE_LOADING 650 wanxl_reset(card); 651#endif 652 653 timeout = jiffies + 20 * HZ; 654 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) { 655 if (time_before(timeout, jiffies)) { 656 pr_warn("%s: timeout waiting for PUTS to complete\n", 657 pci_name(pdev)); 658 wanxl_pci_remove_one(pdev); 659 return -ENODEV; 660 } 661 662 switch(stat & 0xC0) { 663 case 0x00: /* hmm - PUTS completed with non-zero code? */ 664 case 0x80: /* PUTS still testing the hardware */ 665 break; 666 667 default: 668 pr_warn("%s: PUTS test 0x%X failed\n", 669 pci_name(pdev), stat & 0x30); 670 wanxl_pci_remove_one(pdev); 671 return -ENODEV; 672 } 673 674 schedule(); 675 } 676 677 /* get on-board memory size (PUTS detects no more than 4 MB) */ 678 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK; 679 680 /* set up on-board RAM mapping */ 681 mem_phy = pci_resource_start(pdev, 2); 682 683 684 /* sanity check the board's reported memory size */ 685 if (ramsize < BUFFERS_ADDR + 686 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) { 687 pr_warn("%s: no enough on-board RAM (%u bytes detected, %u bytes required)\n", 688 pci_name(pdev), ramsize, 689 BUFFERS_ADDR + 690 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports); 691 wanxl_pci_remove_one(pdev); 692 return -ENODEV; 693 } 694 695 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) { 696 pr_warn("%s: unable to Set Byte Swap Mode\n", pci_name(pdev)); 697 wanxl_pci_remove_one(pdev); 698 return -ENODEV; 699 } 700 701 for (i = 0; i < RX_QUEUE_LENGTH; i++) { 702 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH); 703 card->rx_skbs[i] = skb; 704 if (skb) 705 card->status->rx_descs[i].address = 706 pci_map_single(card->pdev, skb->data, 707 BUFFER_LENGTH, 708 PCI_DMA_FROMDEVICE); 709 } 710 711 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware)); 712 if (!mem) { 713 pr_err("ioremap() failed\n"); 714 wanxl_pci_remove_one(pdev); 715 return -EFAULT; 716 } 717 718 for (i = 0; i < sizeof(firmware); i += 4) 719 writel(ntohl(*(__be32*)(firmware + i)), mem + PDM_OFFSET + i); 720 721 for (i = 0; i < ports; i++) 722 writel(card->status_address + 723 (void *)&card->status->port_status[i] - 724 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4); 725 writel(card->status_address, mem + PDM_OFFSET + 20); 726 writel(PDM_OFFSET, mem); 727 iounmap(mem); 728 729 writel(0, card->plx + PLX_MAILBOX_5); 730 731 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) { 732 pr_warn("%s: unable to Abort and Jump\n", pci_name(pdev)); 733 wanxl_pci_remove_one(pdev); 734 return -ENODEV; 735 } 736 737 stat = 0; 738 timeout = jiffies + 5 * HZ; 739 do { 740 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0) 741 break; 742 schedule(); 743 }while (time_after(timeout, jiffies)); 744 745 if (!stat) { 746 pr_warn("%s: timeout while initializing card firmware\n", 747 pci_name(pdev)); 748 wanxl_pci_remove_one(pdev); 749 return -ENODEV; 750 } 751 752#if DETECT_RAM 753 ramsize = stat; 754#endif 755 756 pr_info("%s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n", 757 pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq); 758 759 /* Allocate IRQ */ 760 if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) { 761 pr_warn("%s: could not allocate IRQ%i\n", 762 pci_name(pdev), pdev->irq); 763 wanxl_pci_remove_one(pdev); 764 return -EBUSY; 765 } 766 card->irq = pdev->irq; 767 768 for (i = 0; i < ports; i++) { 769 hdlc_device *hdlc; 770 struct port *port = &card->ports[i]; 771 struct net_device *dev = alloc_hdlcdev(port); 772 if (!dev) { 773 pr_err("%s: unable to allocate memory\n", 774 pci_name(pdev)); 775 wanxl_pci_remove_one(pdev); 776 return -ENOMEM; 777 } 778 779 port->dev = dev; 780 hdlc = dev_to_hdlc(dev); 781 spin_lock_init(&port->lock); 782 dev->tx_queue_len = 50; 783 dev->netdev_ops = &wanxl_ops; 784 hdlc->attach = wanxl_attach; 785 hdlc->xmit = wanxl_xmit; 786 port->card = card; 787 port->node = i; 788 get_status(port)->clocking = CLOCK_EXT; 789 if (register_hdlc_device(dev)) { 790 pr_err("%s: unable to register hdlc device\n", 791 pci_name(pdev)); 792 free_netdev(dev); 793 wanxl_pci_remove_one(pdev); 794 return -ENOBUFS; 795 } 796 card->n_ports++; 797 } 798 799 pr_info("%s: port", pci_name(pdev)); 800 for (i = 0; i < ports; i++) 801 pr_cont("%s #%i: %s", 802 i ? "," : "", i, card->ports[i].dev->name); 803 pr_cont("\n"); 804 805 for (i = 0; i < ports; i++) 806 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/ 807 808 return 0; 809} 810 811static const struct pci_device_id wanxl_pci_tbl[] = { 812 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID, 813 PCI_ANY_ID, 0, 0, 0 }, 814 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID, 815 PCI_ANY_ID, 0, 0, 0 }, 816 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID, 817 PCI_ANY_ID, 0, 0, 0 }, 818 { 0, } 819}; 820 821 822static struct pci_driver wanxl_pci_driver = { 823 .name = "wanXL", 824 .id_table = wanxl_pci_tbl, 825 .probe = wanxl_pci_init_one, 826 .remove = wanxl_pci_remove_one, 827}; 828 829 830static int __init wanxl_init_module(void) 831{ 832#ifdef MODULE 833 pr_info("%s\n", version); 834#endif 835 return pci_register_driver(&wanxl_pci_driver); 836} 837 838static void __exit wanxl_cleanup_module(void) 839{ 840 pci_unregister_driver(&wanxl_pci_driver); 841} 842 843 844MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); 845MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver"); 846MODULE_LICENSE("GPL v2"); 847MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl); 848 849module_init(wanxl_init_module); 850module_exit(wanxl_cleanup_module); 851