1/* 2 * Hitachi (now Renesas) SCA-II HD64572 driver for Linux 3 * 4 * Copyright (C) 1998-2008 Krzysztof Halasa <khc@pm.waw.pl> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License 8 * as published by the Free Software Foundation. 9 * 10 * Source of information: HD64572 SCA-II User's Manual 11 * 12 * We use the following SCA memory map: 13 * 14 * Packet buffer descriptor rings - starting from card->rambase: 15 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring 16 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring 17 * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used) 18 * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used) 19 * 20 * Packet data buffers - starting from card->rambase + buff_offset: 21 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers 22 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers 23 * rx_ring_buffers * HDLC_MAX_MRU = logical channel #0 RX buffers (if used) 24 * tx_ring_buffers * HDLC_MAX_MRU = logical channel #0 TX buffers (if used) 25 */ 26 27#include <linux/bitops.h> 28#include <linux/errno.h> 29#include <linux/fcntl.h> 30#include <linux/hdlc.h> 31#include <linux/in.h> 32#include <linux/interrupt.h> 33#include <linux/ioport.h> 34#include <linux/jiffies.h> 35#include <linux/kernel.h> 36#include <linux/module.h> 37#include <linux/netdevice.h> 38#include <linux/skbuff.h> 39#include <linux/string.h> 40#include <linux/types.h> 41#include <asm/io.h> 42#include <asm/uaccess.h> 43#include "hd64572.h" 44 45#define NAPI_WEIGHT 16 46 47#define get_msci(port) (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) 48#define get_dmac_rx(port) (port->chan ? DMAC1RX_OFFSET : DMAC0RX_OFFSET) 49#define get_dmac_tx(port) (port->chan ? DMAC1TX_OFFSET : DMAC0TX_OFFSET) 50 51#define sca_in(reg, card) readb(card->scabase + (reg)) 52#define sca_out(value, reg, card) writeb(value, card->scabase + (reg)) 53#define sca_inw(reg, card) readw(card->scabase + (reg)) 54#define sca_outw(value, reg, card) writew(value, card->scabase + (reg)) 55#define sca_inl(reg, card) readl(card->scabase + (reg)) 56#define sca_outl(value, reg, card) writel(value, card->scabase + (reg)) 57 58static int sca_poll(struct napi_struct *napi, int budget); 59 60static inline port_t* dev_to_port(struct net_device *dev) 61{ 62 return dev_to_hdlc(dev)->priv; 63} 64 65static inline void enable_intr(port_t *port) 66{ 67 /* enable DMIB and MSCI RXINTA interrupts */ 68 sca_outl(sca_inl(IER0, port->card) | 69 (port->chan ? 0x08002200 : 0x00080022), IER0, port->card); 70} 71 72static inline void disable_intr(port_t *port) 73{ 74 sca_outl(sca_inl(IER0, port->card) & 75 (port->chan ? 0x00FF00FF : 0xFF00FF00), IER0, port->card); 76} 77 78static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit) 79{ 80 u16 rx_buffs = port->card->rx_ring_buffers; 81 u16 tx_buffs = port->card->tx_ring_buffers; 82 83 desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc. 84 return port->chan * (rx_buffs + tx_buffs) + transmit * rx_buffs + desc; 85} 86 87 88static inline u16 desc_offset(port_t *port, u16 desc, int transmit) 89{ 90 /* Descriptor offset always fits in 16 bits */ 91 return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc); 92} 93 94 95static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc, 96 int transmit) 97{ 98 return (pkt_desc __iomem *)(port->card->rambase + 99 desc_offset(port, desc, transmit)); 100} 101 102 103static inline u32 buffer_offset(port_t *port, u16 desc, int transmit) 104{ 105 return port->card->buff_offset + 106 desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU; 107} 108 109 110static inline void sca_set_carrier(port_t *port) 111{ 112 if (!(sca_in(get_msci(port) + ST3, port->card) & ST3_DCD)) { 113#ifdef DEBUG_LINK 114 printk(KERN_DEBUG "%s: sca_set_carrier on\n", 115 port->netdev.name); 116#endif 117 netif_carrier_on(port->netdev); 118 } else { 119#ifdef DEBUG_LINK 120 printk(KERN_DEBUG "%s: sca_set_carrier off\n", 121 port->netdev.name); 122#endif 123 netif_carrier_off(port->netdev); 124 } 125} 126 127 128static void sca_init_port(port_t *port) 129{ 130 card_t *card = port->card; 131 u16 dmac_rx = get_dmac_rx(port), dmac_tx = get_dmac_tx(port); 132 int transmit, i; 133 134 port->rxin = 0; 135 port->txin = 0; 136 port->txlast = 0; 137 138 for (transmit = 0; transmit < 2; transmit++) { 139 u16 buffs = transmit ? card->tx_ring_buffers 140 : card->rx_ring_buffers; 141 142 for (i = 0; i < buffs; i++) { 143 pkt_desc __iomem *desc = desc_address(port, i, transmit); 144 u16 chain_off = desc_offset(port, i + 1, transmit); 145 u32 buff_off = buffer_offset(port, i, transmit); 146 147 writel(chain_off, &desc->cp); 148 writel(buff_off, &desc->bp); 149 writew(0, &desc->len); 150 writeb(0, &desc->stat); 151 } 152 } 153 154 /* DMA disable - to halt state */ 155 sca_out(0, DSR_RX(port->chan), card); 156 sca_out(0, DSR_TX(port->chan), card); 157 158 /* software ABORT - to initial state */ 159 sca_out(DCR_ABORT, DCR_RX(port->chan), card); 160 sca_out(DCR_ABORT, DCR_TX(port->chan), card); 161 162 /* current desc addr */ 163 sca_outl(desc_offset(port, 0, 0), dmac_rx + CDAL, card); 164 sca_outl(desc_offset(port, card->tx_ring_buffers - 1, 0), 165 dmac_rx + EDAL, card); 166 sca_outl(desc_offset(port, 0, 1), dmac_tx + CDAL, card); 167 sca_outl(desc_offset(port, 0, 1), dmac_tx + EDAL, card); 168 169 /* clear frame end interrupt counter */ 170 sca_out(DCR_CLEAR_EOF, DCR_RX(port->chan), card); 171 sca_out(DCR_CLEAR_EOF, DCR_TX(port->chan), card); 172 173 /* Receive */ 174 sca_outw(HDLC_MAX_MRU, dmac_rx + BFLL, card); /* set buffer length */ 175 sca_out(0x14, DMR_RX(port->chan), card); /* Chain mode, Multi-frame */ 176 sca_out(DIR_EOME, DIR_RX(port->chan), card); /* enable interrupts */ 177 sca_out(DSR_DE, DSR_RX(port->chan), card); /* DMA enable */ 178 179 /* Transmit */ 180 sca_out(0x14, DMR_TX(port->chan), card); /* Chain mode, Multi-frame */ 181 sca_out(DIR_EOME, DIR_TX(port->chan), card); /* enable interrupts */ 182 183 sca_set_carrier(port); 184 netif_napi_add(port->netdev, &port->napi, sca_poll, NAPI_WEIGHT); 185} 186 187 188/* MSCI interrupt service */ 189static inline void sca_msci_intr(port_t *port) 190{ 191 u16 msci = get_msci(port); 192 card_t* card = port->card; 193 194 if (sca_in(msci + ST1, card) & ST1_CDCD) { 195 /* Reset MSCI CDCD status bit */ 196 sca_out(ST1_CDCD, msci + ST1, card); 197 sca_set_carrier(port); 198 } 199} 200 201 202static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc, 203 u16 rxin) 204{ 205 struct net_device *dev = port->netdev; 206 struct sk_buff *skb; 207 u16 len; 208 u32 buff; 209 210 len = readw(&desc->len); 211 skb = dev_alloc_skb(len); 212 if (!skb) { 213 dev->stats.rx_dropped++; 214 return; 215 } 216 217 buff = buffer_offset(port, rxin, 0); 218 memcpy_fromio(skb->data, card->rambase + buff, len); 219 220 skb_put(skb, len); 221#ifdef DEBUG_PKT 222 printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len); 223 debug_frame(skb); 224#endif 225 dev->stats.rx_packets++; 226 dev->stats.rx_bytes += skb->len; 227 skb->protocol = hdlc_type_trans(skb, dev); 228 netif_receive_skb(skb); 229} 230 231 232/* Receive DMA service */ 233static inline int sca_rx_done(port_t *port, int budget) 234{ 235 struct net_device *dev = port->netdev; 236 u16 dmac = get_dmac_rx(port); 237 card_t *card = port->card; 238 u8 stat = sca_in(DSR_RX(port->chan), card); /* read DMA Status */ 239 int received = 0; 240 241 /* Reset DSR status bits */ 242 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 243 DSR_RX(port->chan), card); 244 245 if (stat & DSR_BOF) 246 /* Dropped one or more frames */ 247 dev->stats.rx_over_errors++; 248 249 while (received < budget) { 250 u32 desc_off = desc_offset(port, port->rxin, 0); 251 pkt_desc __iomem *desc; 252 u32 cda = sca_inl(dmac + CDAL, card); 253 254 if ((cda >= desc_off) && (cda < desc_off + sizeof(pkt_desc))) 255 break; /* No frame received */ 256 257 desc = desc_address(port, port->rxin, 0); 258 stat = readb(&desc->stat); 259 if (!(stat & ST_RX_EOM)) 260 port->rxpart = 1; /* partial frame received */ 261 else if ((stat & ST_ERROR_MASK) || port->rxpart) { 262 dev->stats.rx_errors++; 263 if (stat & ST_RX_OVERRUN) 264 dev->stats.rx_fifo_errors++; 265 else if ((stat & (ST_RX_SHORT | ST_RX_ABORT | 266 ST_RX_RESBIT)) || port->rxpart) 267 dev->stats.rx_frame_errors++; 268 else if (stat & ST_RX_CRC) 269 dev->stats.rx_crc_errors++; 270 if (stat & ST_RX_EOM) 271 port->rxpart = 0; /* received last fragment */ 272 } else { 273 sca_rx(card, port, desc, port->rxin); 274 received++; 275 } 276 277 /* Set new error descriptor address */ 278 sca_outl(desc_off, dmac + EDAL, card); 279 port->rxin = (port->rxin + 1) % card->rx_ring_buffers; 280 } 281 282 /* make sure RX DMA is enabled */ 283 sca_out(DSR_DE, DSR_RX(port->chan), card); 284 return received; 285} 286 287 288/* Transmit DMA service */ 289static inline void sca_tx_done(port_t *port) 290{ 291 struct net_device *dev = port->netdev; 292 card_t* card = port->card; 293 u8 stat; 294 unsigned count = 0; 295 296 spin_lock(&port->lock); 297 298 stat = sca_in(DSR_TX(port->chan), card); /* read DMA Status */ 299 300 /* Reset DSR status bits */ 301 sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE, 302 DSR_TX(port->chan), card); 303 304 while (1) { 305 pkt_desc __iomem *desc = desc_address(port, port->txlast, 1); 306 u8 stat = readb(&desc->stat); 307 308 if (!(stat & ST_TX_OWNRSHP)) 309 break; /* not yet transmitted */ 310 if (stat & ST_TX_UNDRRUN) { 311 dev->stats.tx_errors++; 312 dev->stats.tx_fifo_errors++; 313 } else { 314 dev->stats.tx_packets++; 315 dev->stats.tx_bytes += readw(&desc->len); 316 } 317 writeb(0, &desc->stat); /* Free descriptor */ 318 count++; 319 port->txlast = (port->txlast + 1) % card->tx_ring_buffers; 320 } 321 322 if (count) 323 netif_wake_queue(dev); 324 spin_unlock(&port->lock); 325} 326 327 328static int sca_poll(struct napi_struct *napi, int budget) 329{ 330 port_t *port = container_of(napi, port_t, napi); 331 u32 isr0 = sca_inl(ISR0, port->card); 332 int received = 0; 333 334 if (isr0 & (port->chan ? 0x08000000 : 0x00080000)) 335 sca_msci_intr(port); 336 337 if (isr0 & (port->chan ? 0x00002000 : 0x00000020)) 338 sca_tx_done(port); 339 340 if (isr0 & (port->chan ? 0x00000200 : 0x00000002)) 341 received = sca_rx_done(port, budget); 342 343 if (received < budget) { 344 napi_complete(napi); 345 enable_intr(port); 346 } 347 348 return received; 349} 350 351static irqreturn_t sca_intr(int irq, void *dev_id) 352{ 353 card_t *card = dev_id; 354 u32 isr0 = sca_inl(ISR0, card); 355 int i, handled = 0; 356 357 for (i = 0; i < 2; i++) { 358 port_t *port = get_port(card, i); 359 if (port && (isr0 & (i ? 0x08002200 : 0x00080022))) { 360 handled = 1; 361 disable_intr(port); 362 napi_schedule(&port->napi); 363 } 364 } 365 366 return IRQ_RETVAL(handled); 367} 368 369 370static void sca_set_port(port_t *port) 371{ 372 card_t* card = port->card; 373 u16 msci = get_msci(port); 374 u8 md2 = sca_in(msci + MD2, card); 375 unsigned int tmc, br = 10, brv = 1024; 376 377 378 if (port->settings.clock_rate > 0) { 379 /* Try lower br for better accuracy*/ 380 do { 381 br--; 382 brv >>= 1; /* brv = 2^9 = 512 max in specs */ 383 384 /* Baud Rate = CLOCK_BASE / TMC / 2^BR */ 385 tmc = CLOCK_BASE / brv / port->settings.clock_rate; 386 }while (br > 1 && tmc <= 128); 387 388 if (tmc < 1) { 389 tmc = 1; 390 br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */ 391 brv = 1; 392 } else if (tmc > 255) 393 tmc = 256; /* tmc=0 means 256 - low baud rates */ 394 395 port->settings.clock_rate = CLOCK_BASE / brv / tmc; 396 } else { 397 br = 9; /* Minimum clock rate */ 398 tmc = 256; /* 8bit = 0 */ 399 port->settings.clock_rate = CLOCK_BASE / (256 * 512); 400 } 401 402 port->rxs = (port->rxs & ~CLK_BRG_MASK) | br; 403 port->txs = (port->txs & ~CLK_BRG_MASK) | br; 404 port->tmc = tmc; 405 406 /* baud divisor - time constant*/ 407 sca_out(port->tmc, msci + TMCR, card); 408 sca_out(port->tmc, msci + TMCT, card); 409 410 /* Set BRG bits */ 411 sca_out(port->rxs, msci + RXS, card); 412 sca_out(port->txs, msci + TXS, card); 413 414 if (port->settings.loopback) 415 md2 |= MD2_LOOPBACK; 416 else 417 md2 &= ~MD2_LOOPBACK; 418 419 sca_out(md2, msci + MD2, card); 420 421} 422 423 424static void sca_open(struct net_device *dev) 425{ 426 port_t *port = dev_to_port(dev); 427 card_t* card = port->card; 428 u16 msci = get_msci(port); 429 u8 md0, md2; 430 431 switch(port->encoding) { 432 case ENCODING_NRZ: md2 = MD2_NRZ; break; 433 case ENCODING_NRZI: md2 = MD2_NRZI; break; 434 case ENCODING_FM_MARK: md2 = MD2_FM_MARK; break; 435 case ENCODING_FM_SPACE: md2 = MD2_FM_SPACE; break; 436 default: md2 = MD2_MANCHESTER; 437 } 438 439 if (port->settings.loopback) 440 md2 |= MD2_LOOPBACK; 441 442 switch(port->parity) { 443 case PARITY_CRC16_PR0: md0 = MD0_HDLC | MD0_CRC_16_0; break; 444 case PARITY_CRC16_PR1: md0 = MD0_HDLC | MD0_CRC_16; break; 445 case PARITY_CRC32_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU32; break; 446 case PARITY_CRC16_PR1_CCITT: md0 = MD0_HDLC | MD0_CRC_ITU; break; 447 default: md0 = MD0_HDLC | MD0_CRC_NONE; 448 } 449 450 sca_out(CMD_RESET, msci + CMD, card); 451 sca_out(md0, msci + MD0, card); 452 sca_out(0x00, msci + MD1, card); /* no address field check */ 453 sca_out(md2, msci + MD2, card); 454 sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */ 455 /* Skip the rest of underrun frame */ 456 sca_out(CTL_IDLE | CTL_URCT | CTL_URSKP, msci + CTL, card); 457 sca_out(0x0F, msci + RNR, card); /* +1=RX DMA activation condition */ 458 sca_out(0x3C, msci + TFS, card); /* +1 = TX start */ 459 sca_out(0x38, msci + TCR, card); /* =Critical TX DMA activ condition */ 460 sca_out(0x38, msci + TNR0, card); /* =TX DMA activation condition */ 461 sca_out(0x3F, msci + TNR1, card); /* +1=TX DMA deactivation condition*/ 462 463/* We're using the following interrupts: 464 - RXINTA (DCD changes only) 465 - DMIB (EOM - single frame transfer complete) 466*/ 467 sca_outl(IE0_RXINTA | IE0_CDCD, msci + IE0, card); 468 469 sca_out(port->tmc, msci + TMCR, card); 470 sca_out(port->tmc, msci + TMCT, card); 471 sca_out(port->rxs, msci + RXS, card); 472 sca_out(port->txs, msci + TXS, card); 473 sca_out(CMD_TX_ENABLE, msci + CMD, card); 474 sca_out(CMD_RX_ENABLE, msci + CMD, card); 475 476 sca_set_carrier(port); 477 enable_intr(port); 478 napi_enable(&port->napi); 479 netif_start_queue(dev); 480} 481 482 483static void sca_close(struct net_device *dev) 484{ 485 port_t *port = dev_to_port(dev); 486 487 /* reset channel */ 488 sca_out(CMD_RESET, get_msci(port) + CMD, port->card); 489 disable_intr(port); 490 napi_disable(&port->napi); 491 netif_stop_queue(dev); 492} 493 494 495static int sca_attach(struct net_device *dev, unsigned short encoding, 496 unsigned short parity) 497{ 498 if (encoding != ENCODING_NRZ && 499 encoding != ENCODING_NRZI && 500 encoding != ENCODING_FM_MARK && 501 encoding != ENCODING_FM_SPACE && 502 encoding != ENCODING_MANCHESTER) 503 return -EINVAL; 504 505 if (parity != PARITY_NONE && 506 parity != PARITY_CRC16_PR0 && 507 parity != PARITY_CRC16_PR1 && 508 parity != PARITY_CRC32_PR1_CCITT && 509 parity != PARITY_CRC16_PR1_CCITT) 510 return -EINVAL; 511 512 dev_to_port(dev)->encoding = encoding; 513 dev_to_port(dev)->parity = parity; 514 return 0; 515} 516 517 518#ifdef DEBUG_RINGS 519static void sca_dump_rings(struct net_device *dev) 520{ 521 port_t *port = dev_to_port(dev); 522 card_t *card = port->card; 523 u16 cnt; 524 525 printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive", 526 sca_inl(get_dmac_rx(port) + CDAL, card), 527 sca_inl(get_dmac_rx(port) + EDAL, card), 528 sca_in(DSR_RX(port->chan), card), port->rxin, 529 sca_in(DSR_RX(port->chan), card) & DSR_DE ? "" : "in"); 530 for (cnt = 0; cnt < port->card->rx_ring_buffers; cnt++) 531 pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat))); 532 pr_cont("\n"); 533 534 printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u " 535 "last=%u %sactive", 536 sca_inl(get_dmac_tx(port) + CDAL, card), 537 sca_inl(get_dmac_tx(port) + EDAL, card), 538 sca_in(DSR_TX(port->chan), card), port->txin, port->txlast, 539 sca_in(DSR_TX(port->chan), card) & DSR_DE ? "" : "in"); 540 541 for (cnt = 0; cnt < port->card->tx_ring_buffers; cnt++) 542 pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat))); 543 pr_cont("\n"); 544 545 printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x," 546 " ST: %02x %02x %02x %02x %02x, FST: %02x CST: %02x %02x\n", 547 sca_in(get_msci(port) + MD0, card), 548 sca_in(get_msci(port) + MD1, card), 549 sca_in(get_msci(port) + MD2, card), 550 sca_in(get_msci(port) + ST0, card), 551 sca_in(get_msci(port) + ST1, card), 552 sca_in(get_msci(port) + ST2, card), 553 sca_in(get_msci(port) + ST3, card), 554 sca_in(get_msci(port) + ST4, card), 555 sca_in(get_msci(port) + FST, card), 556 sca_in(get_msci(port) + CST0, card), 557 sca_in(get_msci(port) + CST1, card)); 558 559 printk(KERN_DEBUG "ILAR: %02x ISR: %08x %08x\n", sca_in(ILAR, card), 560 sca_inl(ISR0, card), sca_inl(ISR1, card)); 561} 562#endif /* DEBUG_RINGS */ 563 564 565static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev) 566{ 567 port_t *port = dev_to_port(dev); 568 card_t *card = port->card; 569 pkt_desc __iomem *desc; 570 u32 buff, len; 571 572 spin_lock_irq(&port->lock); 573 574 desc = desc_address(port, port->txin + 1, 1); 575 BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */ 576 577#ifdef DEBUG_PKT 578 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len); 579 debug_frame(skb); 580#endif 581 582 desc = desc_address(port, port->txin, 1); 583 buff = buffer_offset(port, port->txin, 1); 584 len = skb->len; 585 memcpy_toio(card->rambase + buff, skb->data, len); 586 587 writew(len, &desc->len); 588 writeb(ST_TX_EOM, &desc->stat); 589 590 port->txin = (port->txin + 1) % card->tx_ring_buffers; 591 sca_outl(desc_offset(port, port->txin, 1), 592 get_dmac_tx(port) + EDAL, card); 593 594 sca_out(DSR_DE, DSR_TX(port->chan), card); /* Enable TX DMA */ 595 596 desc = desc_address(port, port->txin + 1, 1); 597 if (readb(&desc->stat)) /* allow 1 packet gap */ 598 netif_stop_queue(dev); 599 600 spin_unlock_irq(&port->lock); 601 602 dev_kfree_skb(skb); 603 return NETDEV_TX_OK; 604} 605 606 607static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize) 608{ 609 /* Round RAM size to 32 bits, fill from end to start */ 610 u32 i = ramsize &= ~3; 611 612 do { 613 i -= 4; 614 writel(i ^ 0x12345678, rambase + i); 615 } while (i > 0); 616 617 for (i = 0; i < ramsize ; i += 4) { 618 if (readl(rambase + i) != (i ^ 0x12345678)) 619 break; 620 } 621 622 return i; 623} 624 625 626static void sca_init(card_t *card, int wait_states) 627{ 628 sca_out(wait_states, WCRL, card); /* Wait Control */ 629 sca_out(wait_states, WCRM, card); 630 sca_out(wait_states, WCRH, card); 631 632 sca_out(0, DMER, card); /* DMA Master disable */ 633 sca_out(0x03, PCR, card); /* DMA priority */ 634 sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */ 635 sca_out(0, DSR_TX(0), card); 636 sca_out(0, DSR_RX(1), card); 637 sca_out(0, DSR_TX(1), card); 638 sca_out(DMER_DME, DMER, card); /* DMA Master enable */ 639} 640