1/**************************************************************************** 2 * Driver for Solarflare network controllers and boards 3 * Copyright 2012-2013 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10#include "net_driver.h" 11#include "ef10_regs.h" 12#include "io.h" 13#include "mcdi.h" 14#include "mcdi_pcol.h" 15#include "nic.h" 16#include "workarounds.h" 17#include "selftest.h" 18#include <linux/in.h> 19#include <linux/jhash.h> 20#include <linux/wait.h> 21#include <linux/workqueue.h> 22 23/* Hardware control for EF10 architecture including 'Huntington'. */ 24 25#define EFX_EF10_DRVGEN_EV 7 26enum { 27 EFX_EF10_TEST = 1, 28 EFX_EF10_REFILL, 29}; 30 31/* The reserved RSS context value */ 32#define EFX_EF10_RSS_CONTEXT_INVALID 0xffffffff 33 34/* The filter table(s) are managed by firmware and we have write-only 35 * access. When removing filters we must identify them to the 36 * firmware by a 64-bit handle, but this is too wide for Linux kernel 37 * interfaces (32-bit for RX NFC, 16-bit for RFS). Also, we need to 38 * be able to tell in advance whether a requested insertion will 39 * replace an existing filter. Therefore we maintain a software hash 40 * table, which should be at least as large as the hardware hash 41 * table. 42 * 43 * Huntington has a single 8K filter table shared between all filter 44 * types and both ports. 45 */ 46#define HUNT_FILTER_TBL_ROWS 8192 47 48struct efx_ef10_filter_table { 49/* The RX match field masks supported by this fw & hw, in order of priority */ 50 enum efx_filter_match_flags rx_match_flags[ 51 MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM]; 52 unsigned int rx_match_count; 53 54 struct { 55 unsigned long spec; /* pointer to spec plus flag bits */ 56/* BUSY flag indicates that an update is in progress. AUTO_OLD is 57 * used to mark and sweep MAC filters for the device address lists. 58 */ 59#define EFX_EF10_FILTER_FLAG_BUSY 1UL 60#define EFX_EF10_FILTER_FLAG_AUTO_OLD 2UL 61#define EFX_EF10_FILTER_FLAGS 3UL 62 u64 handle; /* firmware handle */ 63 } *entry; 64 wait_queue_head_t waitq; 65/* Shadow of net_device address lists, guarded by mac_lock */ 66#define EFX_EF10_FILTER_DEV_UC_MAX 32 67#define EFX_EF10_FILTER_DEV_MC_MAX 256 68 struct { 69 u8 addr[ETH_ALEN]; 70 u16 id; 71 } dev_uc_list[EFX_EF10_FILTER_DEV_UC_MAX], 72 dev_mc_list[EFX_EF10_FILTER_DEV_MC_MAX]; 73 int dev_uc_count; /* negative for PROMISC */ 74 int dev_mc_count; /* negative for PROMISC/ALLMULTI */ 75}; 76 77/* An arbitrary search limit for the software hash table */ 78#define EFX_EF10_FILTER_SEARCH_LIMIT 200 79 80static void efx_ef10_rx_push_rss_config(struct efx_nic *efx); 81static void efx_ef10_rx_free_indir_table(struct efx_nic *efx); 82static void efx_ef10_filter_table_remove(struct efx_nic *efx); 83 84static int efx_ef10_get_warm_boot_count(struct efx_nic *efx) 85{ 86 efx_dword_t reg; 87 88 efx_readd(efx, ®, ER_DZ_BIU_MC_SFT_STATUS); 89 return EFX_DWORD_FIELD(reg, EFX_WORD_1) == 0xb007 ? 90 EFX_DWORD_FIELD(reg, EFX_WORD_0) : -EIO; 91} 92 93static unsigned int efx_ef10_mem_map_size(struct efx_nic *efx) 94{ 95 return resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]); 96} 97 98static int efx_ef10_init_datapath_caps(struct efx_nic *efx) 99{ 100 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CAPABILITIES_OUT_LEN); 101 struct efx_ef10_nic_data *nic_data = efx->nic_data; 102 size_t outlen; 103 int rc; 104 105 BUILD_BUG_ON(MC_CMD_GET_CAPABILITIES_IN_LEN != 0); 106 107 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CAPABILITIES, NULL, 0, 108 outbuf, sizeof(outbuf), &outlen); 109 if (rc) 110 return rc; 111 if (outlen < sizeof(outbuf)) { 112 netif_err(efx, drv, efx->net_dev, 113 "unable to read datapath firmware capabilities\n"); 114 return -EIO; 115 } 116 117 nic_data->datapath_caps = 118 MCDI_DWORD(outbuf, GET_CAPABILITIES_OUT_FLAGS1); 119 120 if (!(nic_data->datapath_caps & 121 (1 << MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN))) { 122 netif_err(efx, drv, efx->net_dev, 123 "current firmware does not support TSO\n"); 124 return -ENODEV; 125 } 126 127 if (!(nic_data->datapath_caps & 128 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN))) { 129 netif_err(efx, probe, efx->net_dev, 130 "current firmware does not support an RX prefix\n"); 131 return -ENODEV; 132 } 133 134 return 0; 135} 136 137static int efx_ef10_get_sysclk_freq(struct efx_nic *efx) 138{ 139 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_CLOCK_OUT_LEN); 140 int rc; 141 142 rc = efx_mcdi_rpc(efx, MC_CMD_GET_CLOCK, NULL, 0, 143 outbuf, sizeof(outbuf), NULL); 144 if (rc) 145 return rc; 146 rc = MCDI_DWORD(outbuf, GET_CLOCK_OUT_SYS_FREQ); 147 return rc > 0 ? rc : -ERANGE; 148} 149 150static int efx_ef10_get_mac_address(struct efx_nic *efx, u8 *mac_address) 151{ 152 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_MAC_ADDRESSES_OUT_LEN); 153 size_t outlen; 154 int rc; 155 156 BUILD_BUG_ON(MC_CMD_GET_MAC_ADDRESSES_IN_LEN != 0); 157 158 rc = efx_mcdi_rpc(efx, MC_CMD_GET_MAC_ADDRESSES, NULL, 0, 159 outbuf, sizeof(outbuf), &outlen); 160 if (rc) 161 return rc; 162 if (outlen < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) 163 return -EIO; 164 165 ether_addr_copy(mac_address, 166 MCDI_PTR(outbuf, GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE)); 167 return 0; 168} 169 170static int efx_ef10_probe(struct efx_nic *efx) 171{ 172 struct efx_ef10_nic_data *nic_data; 173 int i, rc; 174 175 /* We can have one VI for each 8K region. However, until we 176 * use TX option descriptors we need two TX queues per channel. 177 */ 178 efx->max_channels = 179 min_t(unsigned int, 180 EFX_MAX_CHANNELS, 181 resource_size(&efx->pci_dev->resource[EFX_MEM_BAR]) / 182 (EFX_VI_PAGE_SIZE * EFX_TXQ_TYPES)); 183 if (WARN_ON(efx->max_channels == 0)) 184 return -EIO; 185 186 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); 187 if (!nic_data) 188 return -ENOMEM; 189 efx->nic_data = nic_data; 190 191 rc = efx_nic_alloc_buffer(efx, &nic_data->mcdi_buf, 192 8 + MCDI_CTL_SDU_LEN_MAX_V2, GFP_KERNEL); 193 if (rc) 194 goto fail1; 195 196 /* Get the MC's warm boot count. In case it's rebooting right 197 * now, be prepared to retry. 198 */ 199 i = 0; 200 for (;;) { 201 rc = efx_ef10_get_warm_boot_count(efx); 202 if (rc >= 0) 203 break; 204 if (++i == 5) 205 goto fail2; 206 ssleep(1); 207 } 208 nic_data->warm_boot_count = rc; 209 210 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 211 212 /* In case we're recovering from a crash (kexec), we want to 213 * cancel any outstanding request by the previous user of this 214 * function. We send a special message using the least 215 * significant bits of the 'high' (doorbell) register. 216 */ 217 _efx_writed(efx, cpu_to_le32(1), ER_DZ_MC_DB_HWRD); 218 219 rc = efx_mcdi_init(efx); 220 if (rc) 221 goto fail2; 222 223 /* Reset (most) configuration for this function */ 224 rc = efx_mcdi_reset(efx, RESET_TYPE_ALL); 225 if (rc) 226 goto fail3; 227 228 /* Enable event logging */ 229 rc = efx_mcdi_log_ctrl(efx, true, false, 0); 230 if (rc) 231 goto fail3; 232 233 rc = efx_ef10_init_datapath_caps(efx); 234 if (rc < 0) 235 goto fail3; 236 237 efx->rx_packet_len_offset = 238 ES_DZ_RX_PREFIX_PKTLEN_OFST - ES_DZ_RX_PREFIX_SIZE; 239 240 rc = efx_mcdi_port_get_number(efx); 241 if (rc < 0) 242 goto fail3; 243 efx->port_num = rc; 244 245 rc = efx_ef10_get_mac_address(efx, efx->net_dev->perm_addr); 246 if (rc) 247 goto fail3; 248 249 rc = efx_ef10_get_sysclk_freq(efx); 250 if (rc < 0) 251 goto fail3; 252 efx->timer_quantum_ns = 1536000 / rc; /* 1536 cycles */ 253 254 /* Check whether firmware supports bug 35388 workaround */ 255 rc = efx_mcdi_set_workaround(efx, MC_CMD_WORKAROUND_BUG35388, true); 256 if (rc == 0) 257 nic_data->workaround_35388 = true; 258 else if (rc != -ENOSYS && rc != -ENOENT) 259 goto fail3; 260 netif_dbg(efx, probe, efx->net_dev, 261 "workaround for bug 35388 is %sabled\n", 262 nic_data->workaround_35388 ? "en" : "dis"); 263 264 rc = efx_mcdi_mon_probe(efx); 265 if (rc) 266 goto fail3; 267 268 efx_ptp_probe(efx, NULL); 269 270 return 0; 271 272fail3: 273 efx_mcdi_fini(efx); 274fail2: 275 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 276fail1: 277 kfree(nic_data); 278 efx->nic_data = NULL; 279 return rc; 280} 281 282static int efx_ef10_free_vis(struct efx_nic *efx) 283{ 284 MCDI_DECLARE_BUF_OUT_OR_ERR(outbuf, 0); 285 size_t outlen; 286 int rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FREE_VIS, NULL, 0, 287 outbuf, sizeof(outbuf), &outlen); 288 289 /* -EALREADY means nothing to free, so ignore */ 290 if (rc == -EALREADY) 291 rc = 0; 292 if (rc) 293 efx_mcdi_display_error(efx, MC_CMD_FREE_VIS, 0, outbuf, outlen, 294 rc); 295 return rc; 296} 297 298#ifdef EFX_USE_PIO 299 300static void efx_ef10_free_piobufs(struct efx_nic *efx) 301{ 302 struct efx_ef10_nic_data *nic_data = efx->nic_data; 303 MCDI_DECLARE_BUF(inbuf, MC_CMD_FREE_PIOBUF_IN_LEN); 304 unsigned int i; 305 int rc; 306 307 BUILD_BUG_ON(MC_CMD_FREE_PIOBUF_OUT_LEN != 0); 308 309 for (i = 0; i < nic_data->n_piobufs; i++) { 310 MCDI_SET_DWORD(inbuf, FREE_PIOBUF_IN_PIOBUF_HANDLE, 311 nic_data->piobuf_handle[i]); 312 rc = efx_mcdi_rpc(efx, MC_CMD_FREE_PIOBUF, inbuf, sizeof(inbuf), 313 NULL, 0, NULL); 314 WARN_ON(rc); 315 } 316 317 nic_data->n_piobufs = 0; 318} 319 320static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 321{ 322 struct efx_ef10_nic_data *nic_data = efx->nic_data; 323 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_PIOBUF_OUT_LEN); 324 unsigned int i; 325 size_t outlen; 326 int rc = 0; 327 328 BUILD_BUG_ON(MC_CMD_ALLOC_PIOBUF_IN_LEN != 0); 329 330 for (i = 0; i < n; i++) { 331 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_PIOBUF, NULL, 0, 332 outbuf, sizeof(outbuf), &outlen); 333 if (rc) 334 break; 335 if (outlen < MC_CMD_ALLOC_PIOBUF_OUT_LEN) { 336 rc = -EIO; 337 break; 338 } 339 nic_data->piobuf_handle[i] = 340 MCDI_DWORD(outbuf, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE); 341 netif_dbg(efx, probe, efx->net_dev, 342 "allocated PIO buffer %u handle %x\n", i, 343 nic_data->piobuf_handle[i]); 344 } 345 346 nic_data->n_piobufs = i; 347 if (rc) 348 efx_ef10_free_piobufs(efx); 349 return rc; 350} 351 352static int efx_ef10_link_piobufs(struct efx_nic *efx) 353{ 354 struct efx_ef10_nic_data *nic_data = efx->nic_data; 355 MCDI_DECLARE_BUF(inbuf, 356 max(MC_CMD_LINK_PIOBUF_IN_LEN, 357 MC_CMD_UNLINK_PIOBUF_IN_LEN)); 358 struct efx_channel *channel; 359 struct efx_tx_queue *tx_queue; 360 unsigned int offset, index; 361 int rc; 362 363 BUILD_BUG_ON(MC_CMD_LINK_PIOBUF_OUT_LEN != 0); 364 BUILD_BUG_ON(MC_CMD_UNLINK_PIOBUF_OUT_LEN != 0); 365 366 /* Link a buffer to each VI in the write-combining mapping */ 367 for (index = 0; index < nic_data->n_piobufs; ++index) { 368 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_PIOBUF_HANDLE, 369 nic_data->piobuf_handle[index]); 370 MCDI_SET_DWORD(inbuf, LINK_PIOBUF_IN_TXQ_INSTANCE, 371 nic_data->pio_write_vi_base + index); 372 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 373 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 374 NULL, 0, NULL); 375 if (rc) { 376 netif_err(efx, drv, efx->net_dev, 377 "failed to link VI %u to PIO buffer %u (%d)\n", 378 nic_data->pio_write_vi_base + index, index, 379 rc); 380 goto fail; 381 } 382 netif_dbg(efx, probe, efx->net_dev, 383 "linked VI %u to PIO buffer %u\n", 384 nic_data->pio_write_vi_base + index, index); 385 } 386 387 /* Link a buffer to each TX queue */ 388 efx_for_each_channel(channel, efx) { 389 efx_for_each_channel_tx_queue(tx_queue, channel) { 390 /* We assign the PIO buffers to queues in 391 * reverse order to allow for the following 392 * special case. 393 */ 394 offset = ((efx->tx_channel_offset + efx->n_tx_channels - 395 tx_queue->channel->channel - 1) * 396 efx_piobuf_size); 397 index = offset / ER_DZ_TX_PIOBUF_SIZE; 398 offset = offset % ER_DZ_TX_PIOBUF_SIZE; 399 400 /* When the host page size is 4K, the first 401 * host page in the WC mapping may be within 402 * the same VI page as the last TX queue. We 403 * can only link one buffer to each VI. 404 */ 405 if (tx_queue->queue == nic_data->pio_write_vi_base) { 406 BUG_ON(index != 0); 407 rc = 0; 408 } else { 409 MCDI_SET_DWORD(inbuf, 410 LINK_PIOBUF_IN_PIOBUF_HANDLE, 411 nic_data->piobuf_handle[index]); 412 MCDI_SET_DWORD(inbuf, 413 LINK_PIOBUF_IN_TXQ_INSTANCE, 414 tx_queue->queue); 415 rc = efx_mcdi_rpc(efx, MC_CMD_LINK_PIOBUF, 416 inbuf, MC_CMD_LINK_PIOBUF_IN_LEN, 417 NULL, 0, NULL); 418 } 419 420 if (rc) { 421 /* This is non-fatal; the TX path just 422 * won't use PIO for this queue 423 */ 424 netif_err(efx, drv, efx->net_dev, 425 "failed to link VI %u to PIO buffer %u (%d)\n", 426 tx_queue->queue, index, rc); 427 tx_queue->piobuf = NULL; 428 } else { 429 tx_queue->piobuf = 430 nic_data->pio_write_base + 431 index * EFX_VI_PAGE_SIZE + offset; 432 tx_queue->piobuf_offset = offset; 433 netif_dbg(efx, probe, efx->net_dev, 434 "linked VI %u to PIO buffer %u offset %x addr %p\n", 435 tx_queue->queue, index, 436 tx_queue->piobuf_offset, 437 tx_queue->piobuf); 438 } 439 } 440 } 441 442 return 0; 443 444fail: 445 while (index--) { 446 MCDI_SET_DWORD(inbuf, UNLINK_PIOBUF_IN_TXQ_INSTANCE, 447 nic_data->pio_write_vi_base + index); 448 efx_mcdi_rpc(efx, MC_CMD_UNLINK_PIOBUF, 449 inbuf, MC_CMD_UNLINK_PIOBUF_IN_LEN, 450 NULL, 0, NULL); 451 } 452 return rc; 453} 454 455#else /* !EFX_USE_PIO */ 456 457static int efx_ef10_alloc_piobufs(struct efx_nic *efx, unsigned int n) 458{ 459 return n == 0 ? 0 : -ENOBUFS; 460} 461 462static int efx_ef10_link_piobufs(struct efx_nic *efx) 463{ 464 return 0; 465} 466 467static void efx_ef10_free_piobufs(struct efx_nic *efx) 468{ 469} 470 471#endif /* EFX_USE_PIO */ 472 473static void efx_ef10_remove(struct efx_nic *efx) 474{ 475 struct efx_ef10_nic_data *nic_data = efx->nic_data; 476 int rc; 477 478 efx_ptp_remove(efx); 479 480 efx_mcdi_mon_remove(efx); 481 482 efx_ef10_rx_free_indir_table(efx); 483 484 if (nic_data->wc_membase) 485 iounmap(nic_data->wc_membase); 486 487 rc = efx_ef10_free_vis(efx); 488 WARN_ON(rc != 0); 489 490 if (!nic_data->must_restore_piobufs) 491 efx_ef10_free_piobufs(efx); 492 493 efx_mcdi_fini(efx); 494 efx_nic_free_buffer(efx, &nic_data->mcdi_buf); 495 kfree(nic_data); 496} 497 498static int efx_ef10_alloc_vis(struct efx_nic *efx, 499 unsigned int min_vis, unsigned int max_vis) 500{ 501 MCDI_DECLARE_BUF(inbuf, MC_CMD_ALLOC_VIS_IN_LEN); 502 MCDI_DECLARE_BUF(outbuf, MC_CMD_ALLOC_VIS_OUT_LEN); 503 struct efx_ef10_nic_data *nic_data = efx->nic_data; 504 size_t outlen; 505 int rc; 506 507 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MIN_VI_COUNT, min_vis); 508 MCDI_SET_DWORD(inbuf, ALLOC_VIS_IN_MAX_VI_COUNT, max_vis); 509 rc = efx_mcdi_rpc(efx, MC_CMD_ALLOC_VIS, inbuf, sizeof(inbuf), 510 outbuf, sizeof(outbuf), &outlen); 511 if (rc != 0) 512 return rc; 513 514 if (outlen < MC_CMD_ALLOC_VIS_OUT_LEN) 515 return -EIO; 516 517 netif_dbg(efx, drv, efx->net_dev, "base VI is A0x%03x\n", 518 MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE)); 519 520 nic_data->vi_base = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_BASE); 521 nic_data->n_allocated_vis = MCDI_DWORD(outbuf, ALLOC_VIS_OUT_VI_COUNT); 522 return 0; 523} 524 525/* Note that the failure path of this function does not free 526 * resources, as this will be done by efx_ef10_remove(). 527 */ 528static int efx_ef10_dimension_resources(struct efx_nic *efx) 529{ 530 struct efx_ef10_nic_data *nic_data = efx->nic_data; 531 unsigned int uc_mem_map_size, wc_mem_map_size; 532 unsigned int min_vis, pio_write_vi_base, max_vis; 533 void __iomem *membase; 534 int rc; 535 536 min_vis = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES); 537 538#ifdef EFX_USE_PIO 539 /* Try to allocate PIO buffers if wanted and if the full 540 * number of PIO buffers would be sufficient to allocate one 541 * copy-buffer per TX channel. Failure is non-fatal, as there 542 * are only a small number of PIO buffers shared between all 543 * functions of the controller. 544 */ 545 if (efx_piobuf_size != 0 && 546 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size * EF10_TX_PIOBUF_COUNT >= 547 efx->n_tx_channels) { 548 unsigned int n_piobufs = 549 DIV_ROUND_UP(efx->n_tx_channels, 550 ER_DZ_TX_PIOBUF_SIZE / efx_piobuf_size); 551 552 rc = efx_ef10_alloc_piobufs(efx, n_piobufs); 553 if (rc) 554 netif_err(efx, probe, efx->net_dev, 555 "failed to allocate PIO buffers (%d)\n", rc); 556 else 557 netif_dbg(efx, probe, efx->net_dev, 558 "allocated %u PIO buffers\n", n_piobufs); 559 } 560#else 561 nic_data->n_piobufs = 0; 562#endif 563 564 /* PIO buffers should be mapped with write-combining enabled, 565 * and we want to make single UC and WC mappings rather than 566 * several of each (in fact that's the only option if host 567 * page size is >4K). So we may allocate some extra VIs just 568 * for writing PIO buffers through. 569 * 570 * The UC mapping contains (min_vis - 1) complete VIs and the 571 * first half of the next VI. Then the WC mapping begins with 572 * the second half of this last VI. 573 */ 574 uc_mem_map_size = PAGE_ALIGN((min_vis - 1) * EFX_VI_PAGE_SIZE + 575 ER_DZ_TX_PIOBUF); 576 if (nic_data->n_piobufs) { 577 /* pio_write_vi_base rounds down to give the number of complete 578 * VIs inside the UC mapping. 579 */ 580 pio_write_vi_base = uc_mem_map_size / EFX_VI_PAGE_SIZE; 581 wc_mem_map_size = (PAGE_ALIGN((pio_write_vi_base + 582 nic_data->n_piobufs) * 583 EFX_VI_PAGE_SIZE) - 584 uc_mem_map_size); 585 max_vis = pio_write_vi_base + nic_data->n_piobufs; 586 } else { 587 pio_write_vi_base = 0; 588 wc_mem_map_size = 0; 589 max_vis = min_vis; 590 } 591 592 /* In case the last attached driver failed to free VIs, do it now */ 593 rc = efx_ef10_free_vis(efx); 594 if (rc != 0) 595 return rc; 596 597 rc = efx_ef10_alloc_vis(efx, min_vis, max_vis); 598 if (rc != 0) 599 return rc; 600 601 /* If we didn't get enough VIs to map all the PIO buffers, free the 602 * PIO buffers 603 */ 604 if (nic_data->n_piobufs && 605 nic_data->n_allocated_vis < 606 pio_write_vi_base + nic_data->n_piobufs) { 607 netif_dbg(efx, probe, efx->net_dev, 608 "%u VIs are not sufficient to map %u PIO buffers\n", 609 nic_data->n_allocated_vis, nic_data->n_piobufs); 610 efx_ef10_free_piobufs(efx); 611 } 612 613 /* Shrink the original UC mapping of the memory BAR */ 614 membase = ioremap_nocache(efx->membase_phys, uc_mem_map_size); 615 if (!membase) { 616 netif_err(efx, probe, efx->net_dev, 617 "could not shrink memory BAR to %x\n", 618 uc_mem_map_size); 619 return -ENOMEM; 620 } 621 iounmap(efx->membase); 622 efx->membase = membase; 623 624 /* Set up the WC mapping if needed */ 625 if (wc_mem_map_size) { 626 nic_data->wc_membase = ioremap_wc(efx->membase_phys + 627 uc_mem_map_size, 628 wc_mem_map_size); 629 if (!nic_data->wc_membase) { 630 netif_err(efx, probe, efx->net_dev, 631 "could not allocate WC mapping of size %x\n", 632 wc_mem_map_size); 633 return -ENOMEM; 634 } 635 nic_data->pio_write_vi_base = pio_write_vi_base; 636 nic_data->pio_write_base = 637 nic_data->wc_membase + 638 (pio_write_vi_base * EFX_VI_PAGE_SIZE + ER_DZ_TX_PIOBUF - 639 uc_mem_map_size); 640 641 rc = efx_ef10_link_piobufs(efx); 642 if (rc) 643 efx_ef10_free_piobufs(efx); 644 } 645 646 netif_dbg(efx, probe, efx->net_dev, 647 "memory BAR at %pa (virtual %p+%x UC, %p+%x WC)\n", 648 &efx->membase_phys, efx->membase, uc_mem_map_size, 649 nic_data->wc_membase, wc_mem_map_size); 650 651 return 0; 652} 653 654static int efx_ef10_init_nic(struct efx_nic *efx) 655{ 656 struct efx_ef10_nic_data *nic_data = efx->nic_data; 657 int rc; 658 659 if (nic_data->must_check_datapath_caps) { 660 rc = efx_ef10_init_datapath_caps(efx); 661 if (rc) 662 return rc; 663 nic_data->must_check_datapath_caps = false; 664 } 665 666 if (nic_data->must_realloc_vis) { 667 /* We cannot let the number of VIs change now */ 668 rc = efx_ef10_alloc_vis(efx, nic_data->n_allocated_vis, 669 nic_data->n_allocated_vis); 670 if (rc) 671 return rc; 672 nic_data->must_realloc_vis = false; 673 } 674 675 if (nic_data->must_restore_piobufs && nic_data->n_piobufs) { 676 rc = efx_ef10_alloc_piobufs(efx, nic_data->n_piobufs); 677 if (rc == 0) { 678 rc = efx_ef10_link_piobufs(efx); 679 if (rc) 680 efx_ef10_free_piobufs(efx); 681 } 682 683 /* Log an error on failure, but this is non-fatal */ 684 if (rc) 685 netif_err(efx, drv, efx->net_dev, 686 "failed to restore PIO buffers (%d)\n", rc); 687 nic_data->must_restore_piobufs = false; 688 } 689 690 efx_ef10_rx_push_rss_config(efx); 691 return 0; 692} 693 694static void efx_ef10_reset_mc_allocations(struct efx_nic *efx) 695{ 696 struct efx_ef10_nic_data *nic_data = efx->nic_data; 697 698 /* All our allocations have been reset */ 699 nic_data->must_realloc_vis = true; 700 nic_data->must_restore_filters = true; 701 nic_data->must_restore_piobufs = true; 702 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 703} 704 705static int efx_ef10_map_reset_flags(u32 *flags) 706{ 707 enum { 708 EF10_RESET_PORT = ((ETH_RESET_MAC | ETH_RESET_PHY) << 709 ETH_RESET_SHARED_SHIFT), 710 EF10_RESET_MC = ((ETH_RESET_DMA | ETH_RESET_FILTER | 711 ETH_RESET_OFFLOAD | ETH_RESET_MAC | 712 ETH_RESET_PHY | ETH_RESET_MGMT) << 713 ETH_RESET_SHARED_SHIFT) 714 }; 715 716 /* We assume for now that our PCI function is permitted to 717 * reset everything. 718 */ 719 720 if ((*flags & EF10_RESET_MC) == EF10_RESET_MC) { 721 *flags &= ~EF10_RESET_MC; 722 return RESET_TYPE_WORLD; 723 } 724 725 if ((*flags & EF10_RESET_PORT) == EF10_RESET_PORT) { 726 *flags &= ~EF10_RESET_PORT; 727 return RESET_TYPE_ALL; 728 } 729 730 /* no invisible reset implemented */ 731 732 return -EINVAL; 733} 734 735static int efx_ef10_reset(struct efx_nic *efx, enum reset_type reset_type) 736{ 737 int rc = efx_mcdi_reset(efx, reset_type); 738 739 /* If it was a port reset, trigger reallocation of MC resources. 740 * Note that on an MC reset nothing needs to be done now because we'll 741 * detect the MC reset later and handle it then. 742 * For an FLR, we never get an MC reset event, but the MC has reset all 743 * resources assigned to us, so we have to trigger reallocation now. 744 */ 745 if ((reset_type == RESET_TYPE_ALL || 746 reset_type == RESET_TYPE_MCDI_TIMEOUT) && !rc) 747 efx_ef10_reset_mc_allocations(efx); 748 return rc; 749} 750 751#define EF10_DMA_STAT(ext_name, mcdi_name) \ 752 [EF10_STAT_ ## ext_name] = \ 753 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 754#define EF10_DMA_INVIS_STAT(int_name, mcdi_name) \ 755 [EF10_STAT_ ## int_name] = \ 756 { NULL, 64, 8 * MC_CMD_MAC_ ## mcdi_name } 757#define EF10_OTHER_STAT(ext_name) \ 758 [EF10_STAT_ ## ext_name] = { #ext_name, 0, 0 } 759#define GENERIC_SW_STAT(ext_name) \ 760 [GENERIC_STAT_ ## ext_name] = { #ext_name, 0, 0 } 761 762static const struct efx_hw_stat_desc efx_ef10_stat_desc[EF10_STAT_COUNT] = { 763 EF10_DMA_STAT(tx_bytes, TX_BYTES), 764 EF10_DMA_STAT(tx_packets, TX_PKTS), 765 EF10_DMA_STAT(tx_pause, TX_PAUSE_PKTS), 766 EF10_DMA_STAT(tx_control, TX_CONTROL_PKTS), 767 EF10_DMA_STAT(tx_unicast, TX_UNICAST_PKTS), 768 EF10_DMA_STAT(tx_multicast, TX_MULTICAST_PKTS), 769 EF10_DMA_STAT(tx_broadcast, TX_BROADCAST_PKTS), 770 EF10_DMA_STAT(tx_lt64, TX_LT64_PKTS), 771 EF10_DMA_STAT(tx_64, TX_64_PKTS), 772 EF10_DMA_STAT(tx_65_to_127, TX_65_TO_127_PKTS), 773 EF10_DMA_STAT(tx_128_to_255, TX_128_TO_255_PKTS), 774 EF10_DMA_STAT(tx_256_to_511, TX_256_TO_511_PKTS), 775 EF10_DMA_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS), 776 EF10_DMA_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS), 777 EF10_DMA_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS), 778 EF10_DMA_STAT(rx_bytes, RX_BYTES), 779 EF10_DMA_INVIS_STAT(rx_bytes_minus_good_bytes, RX_BAD_BYTES), 780 EF10_OTHER_STAT(rx_good_bytes), 781 EF10_OTHER_STAT(rx_bad_bytes), 782 EF10_DMA_STAT(rx_packets, RX_PKTS), 783 EF10_DMA_STAT(rx_good, RX_GOOD_PKTS), 784 EF10_DMA_STAT(rx_bad, RX_BAD_FCS_PKTS), 785 EF10_DMA_STAT(rx_pause, RX_PAUSE_PKTS), 786 EF10_DMA_STAT(rx_control, RX_CONTROL_PKTS), 787 EF10_DMA_STAT(rx_unicast, RX_UNICAST_PKTS), 788 EF10_DMA_STAT(rx_multicast, RX_MULTICAST_PKTS), 789 EF10_DMA_STAT(rx_broadcast, RX_BROADCAST_PKTS), 790 EF10_DMA_STAT(rx_lt64, RX_UNDERSIZE_PKTS), 791 EF10_DMA_STAT(rx_64, RX_64_PKTS), 792 EF10_DMA_STAT(rx_65_to_127, RX_65_TO_127_PKTS), 793 EF10_DMA_STAT(rx_128_to_255, RX_128_TO_255_PKTS), 794 EF10_DMA_STAT(rx_256_to_511, RX_256_TO_511_PKTS), 795 EF10_DMA_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS), 796 EF10_DMA_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS), 797 EF10_DMA_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS), 798 EF10_DMA_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS), 799 EF10_DMA_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS), 800 EF10_DMA_STAT(rx_overflow, RX_OVERFLOW_PKTS), 801 EF10_DMA_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS), 802 EF10_DMA_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS), 803 EF10_DMA_STAT(rx_nodesc_drops, RX_NODESC_DROPS), 804 GENERIC_SW_STAT(rx_nodesc_trunc), 805 GENERIC_SW_STAT(rx_noskb_drops), 806 EF10_DMA_STAT(rx_pm_trunc_bb_overflow, PM_TRUNC_BB_OVERFLOW), 807 EF10_DMA_STAT(rx_pm_discard_bb_overflow, PM_DISCARD_BB_OVERFLOW), 808 EF10_DMA_STAT(rx_pm_trunc_vfifo_full, PM_TRUNC_VFIFO_FULL), 809 EF10_DMA_STAT(rx_pm_discard_vfifo_full, PM_DISCARD_VFIFO_FULL), 810 EF10_DMA_STAT(rx_pm_trunc_qbb, PM_TRUNC_QBB), 811 EF10_DMA_STAT(rx_pm_discard_qbb, PM_DISCARD_QBB), 812 EF10_DMA_STAT(rx_pm_discard_mapping, PM_DISCARD_MAPPING), 813 EF10_DMA_STAT(rx_dp_q_disabled_packets, RXDP_Q_DISABLED_PKTS), 814 EF10_DMA_STAT(rx_dp_di_dropped_packets, RXDP_DI_DROPPED_PKTS), 815 EF10_DMA_STAT(rx_dp_streaming_packets, RXDP_STREAMING_PKTS), 816 EF10_DMA_STAT(rx_dp_hlb_fetch, RXDP_EMERGENCY_FETCH_CONDITIONS), 817 EF10_DMA_STAT(rx_dp_hlb_wait, RXDP_EMERGENCY_WAIT_CONDITIONS), 818}; 819 820#define HUNT_COMMON_STAT_MASK ((1ULL << EF10_STAT_tx_bytes) | \ 821 (1ULL << EF10_STAT_tx_packets) | \ 822 (1ULL << EF10_STAT_tx_pause) | \ 823 (1ULL << EF10_STAT_tx_unicast) | \ 824 (1ULL << EF10_STAT_tx_multicast) | \ 825 (1ULL << EF10_STAT_tx_broadcast) | \ 826 (1ULL << EF10_STAT_rx_bytes) | \ 827 (1ULL << EF10_STAT_rx_bytes_minus_good_bytes) | \ 828 (1ULL << EF10_STAT_rx_good_bytes) | \ 829 (1ULL << EF10_STAT_rx_bad_bytes) | \ 830 (1ULL << EF10_STAT_rx_packets) | \ 831 (1ULL << EF10_STAT_rx_good) | \ 832 (1ULL << EF10_STAT_rx_bad) | \ 833 (1ULL << EF10_STAT_rx_pause) | \ 834 (1ULL << EF10_STAT_rx_control) | \ 835 (1ULL << EF10_STAT_rx_unicast) | \ 836 (1ULL << EF10_STAT_rx_multicast) | \ 837 (1ULL << EF10_STAT_rx_broadcast) | \ 838 (1ULL << EF10_STAT_rx_lt64) | \ 839 (1ULL << EF10_STAT_rx_64) | \ 840 (1ULL << EF10_STAT_rx_65_to_127) | \ 841 (1ULL << EF10_STAT_rx_128_to_255) | \ 842 (1ULL << EF10_STAT_rx_256_to_511) | \ 843 (1ULL << EF10_STAT_rx_512_to_1023) | \ 844 (1ULL << EF10_STAT_rx_1024_to_15xx) | \ 845 (1ULL << EF10_STAT_rx_15xx_to_jumbo) | \ 846 (1ULL << EF10_STAT_rx_gtjumbo) | \ 847 (1ULL << EF10_STAT_rx_bad_gtjumbo) | \ 848 (1ULL << EF10_STAT_rx_overflow) | \ 849 (1ULL << EF10_STAT_rx_nodesc_drops) | \ 850 (1ULL << GENERIC_STAT_rx_nodesc_trunc) | \ 851 (1ULL << GENERIC_STAT_rx_noskb_drops)) 852 853/* These statistics are only provided by the 10G MAC. For a 10G/40G 854 * switchable port we do not expose these because they might not 855 * include all the packets they should. 856 */ 857#define HUNT_10G_ONLY_STAT_MASK ((1ULL << EF10_STAT_tx_control) | \ 858 (1ULL << EF10_STAT_tx_lt64) | \ 859 (1ULL << EF10_STAT_tx_64) | \ 860 (1ULL << EF10_STAT_tx_65_to_127) | \ 861 (1ULL << EF10_STAT_tx_128_to_255) | \ 862 (1ULL << EF10_STAT_tx_256_to_511) | \ 863 (1ULL << EF10_STAT_tx_512_to_1023) | \ 864 (1ULL << EF10_STAT_tx_1024_to_15xx) | \ 865 (1ULL << EF10_STAT_tx_15xx_to_jumbo)) 866 867/* These statistics are only provided by the 40G MAC. For a 10G/40G 868 * switchable port we do expose these because the errors will otherwise 869 * be silent. 870 */ 871#define HUNT_40G_EXTRA_STAT_MASK ((1ULL << EF10_STAT_rx_align_error) | \ 872 (1ULL << EF10_STAT_rx_length_error)) 873 874/* These statistics are only provided if the firmware supports the 875 * capability PM_AND_RXDP_COUNTERS. 876 */ 877#define HUNT_PM_AND_RXDP_STAT_MASK ( \ 878 (1ULL << EF10_STAT_rx_pm_trunc_bb_overflow) | \ 879 (1ULL << EF10_STAT_rx_pm_discard_bb_overflow) | \ 880 (1ULL << EF10_STAT_rx_pm_trunc_vfifo_full) | \ 881 (1ULL << EF10_STAT_rx_pm_discard_vfifo_full) | \ 882 (1ULL << EF10_STAT_rx_pm_trunc_qbb) | \ 883 (1ULL << EF10_STAT_rx_pm_discard_qbb) | \ 884 (1ULL << EF10_STAT_rx_pm_discard_mapping) | \ 885 (1ULL << EF10_STAT_rx_dp_q_disabled_packets) | \ 886 (1ULL << EF10_STAT_rx_dp_di_dropped_packets) | \ 887 (1ULL << EF10_STAT_rx_dp_streaming_packets) | \ 888 (1ULL << EF10_STAT_rx_dp_hlb_fetch) | \ 889 (1ULL << EF10_STAT_rx_dp_hlb_wait)) 890 891static u64 efx_ef10_raw_stat_mask(struct efx_nic *efx) 892{ 893 u64 raw_mask = HUNT_COMMON_STAT_MASK; 894 u32 port_caps = efx_mcdi_phy_get_caps(efx); 895 struct efx_ef10_nic_data *nic_data = efx->nic_data; 896 897 if (port_caps & (1 << MC_CMD_PHY_CAP_40000FDX_LBN)) 898 raw_mask |= HUNT_40G_EXTRA_STAT_MASK; 899 else 900 raw_mask |= HUNT_10G_ONLY_STAT_MASK; 901 902 if (nic_data->datapath_caps & 903 (1 << MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN)) 904 raw_mask |= HUNT_PM_AND_RXDP_STAT_MASK; 905 906 return raw_mask; 907} 908 909static void efx_ef10_get_stat_mask(struct efx_nic *efx, unsigned long *mask) 910{ 911 u64 raw_mask = efx_ef10_raw_stat_mask(efx); 912 913#if BITS_PER_LONG == 64 914 mask[0] = raw_mask; 915#else 916 mask[0] = raw_mask & 0xffffffff; 917 mask[1] = raw_mask >> 32; 918#endif 919} 920 921static size_t efx_ef10_describe_stats(struct efx_nic *efx, u8 *names) 922{ 923 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 924 925 efx_ef10_get_stat_mask(efx, mask); 926 return efx_nic_describe_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, 927 mask, names); 928} 929 930static int efx_ef10_try_update_nic_stats(struct efx_nic *efx) 931{ 932 struct efx_ef10_nic_data *nic_data = efx->nic_data; 933 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 934 __le64 generation_start, generation_end; 935 u64 *stats = nic_data->stats; 936 __le64 *dma_stats; 937 938 efx_ef10_get_stat_mask(efx, mask); 939 940 dma_stats = efx->stats_buffer.addr; 941 nic_data = efx->nic_data; 942 943 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END]; 944 if (generation_end == EFX_MC_STATS_GENERATION_INVALID) 945 return 0; 946 rmb(); 947 efx_nic_update_stats(efx_ef10_stat_desc, EF10_STAT_COUNT, mask, 948 stats, efx->stats_buffer.addr, false); 949 rmb(); 950 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START]; 951 if (generation_end != generation_start) 952 return -EAGAIN; 953 954 /* Update derived statistics */ 955 efx_nic_fix_nodesc_drop_stat(efx, &stats[EF10_STAT_rx_nodesc_drops]); 956 stats[EF10_STAT_rx_good_bytes] = 957 stats[EF10_STAT_rx_bytes] - 958 stats[EF10_STAT_rx_bytes_minus_good_bytes]; 959 efx_update_diff_stat(&stats[EF10_STAT_rx_bad_bytes], 960 stats[EF10_STAT_rx_bytes_minus_good_bytes]); 961 efx_update_sw_stats(efx, stats); 962 return 0; 963} 964 965 966static size_t efx_ef10_update_stats(struct efx_nic *efx, u64 *full_stats, 967 struct rtnl_link_stats64 *core_stats) 968{ 969 DECLARE_BITMAP(mask, EF10_STAT_COUNT); 970 struct efx_ef10_nic_data *nic_data = efx->nic_data; 971 u64 *stats = nic_data->stats; 972 size_t stats_count = 0, index; 973 int retry; 974 975 efx_ef10_get_stat_mask(efx, mask); 976 977 /* If we're unlucky enough to read statistics during the DMA, wait 978 * up to 10ms for it to finish (typically takes <500us) 979 */ 980 for (retry = 0; retry < 100; ++retry) { 981 if (efx_ef10_try_update_nic_stats(efx) == 0) 982 break; 983 udelay(100); 984 } 985 986 if (full_stats) { 987 for_each_set_bit(index, mask, EF10_STAT_COUNT) { 988 if (efx_ef10_stat_desc[index].name) { 989 *full_stats++ = stats[index]; 990 ++stats_count; 991 } 992 } 993 } 994 995 if (core_stats) { 996 core_stats->rx_packets = stats[EF10_STAT_rx_packets]; 997 core_stats->tx_packets = stats[EF10_STAT_tx_packets]; 998 core_stats->rx_bytes = stats[EF10_STAT_rx_bytes]; 999 core_stats->tx_bytes = stats[EF10_STAT_tx_bytes]; 1000 core_stats->rx_dropped = stats[EF10_STAT_rx_nodesc_drops] + 1001 stats[GENERIC_STAT_rx_nodesc_trunc] + 1002 stats[GENERIC_STAT_rx_noskb_drops]; 1003 core_stats->multicast = stats[EF10_STAT_rx_multicast]; 1004 core_stats->rx_length_errors = 1005 stats[EF10_STAT_rx_gtjumbo] + 1006 stats[EF10_STAT_rx_length_error]; 1007 core_stats->rx_crc_errors = stats[EF10_STAT_rx_bad]; 1008 core_stats->rx_frame_errors = stats[EF10_STAT_rx_align_error]; 1009 core_stats->rx_fifo_errors = stats[EF10_STAT_rx_overflow]; 1010 core_stats->rx_errors = (core_stats->rx_length_errors + 1011 core_stats->rx_crc_errors + 1012 core_stats->rx_frame_errors); 1013 } 1014 1015 return stats_count; 1016} 1017 1018static void efx_ef10_push_irq_moderation(struct efx_channel *channel) 1019{ 1020 struct efx_nic *efx = channel->efx; 1021 unsigned int mode, value; 1022 efx_dword_t timer_cmd; 1023 1024 if (channel->irq_moderation) { 1025 mode = 3; 1026 value = channel->irq_moderation - 1; 1027 } else { 1028 mode = 0; 1029 value = 0; 1030 } 1031 1032 if (EFX_EF10_WORKAROUND_35388(efx)) { 1033 EFX_POPULATE_DWORD_3(timer_cmd, ERF_DD_EVQ_IND_TIMER_FLAGS, 1034 EFE_DD_EVQ_IND_TIMER_FLAGS, 1035 ERF_DD_EVQ_IND_TIMER_MODE, mode, 1036 ERF_DD_EVQ_IND_TIMER_VAL, value); 1037 efx_writed_page(efx, &timer_cmd, ER_DD_EVQ_INDIRECT, 1038 channel->channel); 1039 } else { 1040 EFX_POPULATE_DWORD_2(timer_cmd, ERF_DZ_TC_TIMER_MODE, mode, 1041 ERF_DZ_TC_TIMER_VAL, value); 1042 efx_writed_page(efx, &timer_cmd, ER_DZ_EVQ_TMR, 1043 channel->channel); 1044 } 1045} 1046 1047static void efx_ef10_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) 1048{ 1049 wol->supported = 0; 1050 wol->wolopts = 0; 1051 memset(&wol->sopass, 0, sizeof(wol->sopass)); 1052} 1053 1054static int efx_ef10_set_wol(struct efx_nic *efx, u32 type) 1055{ 1056 if (type != 0) 1057 return -EINVAL; 1058 return 0; 1059} 1060 1061static void efx_ef10_mcdi_request(struct efx_nic *efx, 1062 const efx_dword_t *hdr, size_t hdr_len, 1063 const efx_dword_t *sdu, size_t sdu_len) 1064{ 1065 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1066 u8 *pdu = nic_data->mcdi_buf.addr; 1067 1068 memcpy(pdu, hdr, hdr_len); 1069 memcpy(pdu + hdr_len, sdu, sdu_len); 1070 wmb(); 1071 1072 /* The hardware provides 'low' and 'high' (doorbell) registers 1073 * for passing the 64-bit address of an MCDI request to 1074 * firmware. However the dwords are swapped by firmware. The 1075 * least significant bits of the doorbell are then 0 for all 1076 * MCDI requests due to alignment. 1077 */ 1078 _efx_writed(efx, cpu_to_le32((u64)nic_data->mcdi_buf.dma_addr >> 32), 1079 ER_DZ_MC_DB_LWRD); 1080 _efx_writed(efx, cpu_to_le32((u32)nic_data->mcdi_buf.dma_addr), 1081 ER_DZ_MC_DB_HWRD); 1082} 1083 1084static bool efx_ef10_mcdi_poll_response(struct efx_nic *efx) 1085{ 1086 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1087 const efx_dword_t hdr = *(const efx_dword_t *)nic_data->mcdi_buf.addr; 1088 1089 rmb(); 1090 return EFX_DWORD_FIELD(hdr, MCDI_HEADER_RESPONSE); 1091} 1092 1093static void 1094efx_ef10_mcdi_read_response(struct efx_nic *efx, efx_dword_t *outbuf, 1095 size_t offset, size_t outlen) 1096{ 1097 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1098 const u8 *pdu = nic_data->mcdi_buf.addr; 1099 1100 memcpy(outbuf, pdu + offset, outlen); 1101} 1102 1103static int efx_ef10_mcdi_poll_reboot(struct efx_nic *efx) 1104{ 1105 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1106 int rc; 1107 1108 rc = efx_ef10_get_warm_boot_count(efx); 1109 if (rc < 0) { 1110 /* The firmware is presumably in the process of 1111 * rebooting. However, we are supposed to report each 1112 * reboot just once, so we must only do that once we 1113 * can read and store the updated warm boot count. 1114 */ 1115 return 0; 1116 } 1117 1118 if (rc == nic_data->warm_boot_count) 1119 return 0; 1120 1121 nic_data->warm_boot_count = rc; 1122 1123 /* All our allocations have been reset */ 1124 efx_ef10_reset_mc_allocations(efx); 1125 1126 /* The datapath firmware might have been changed */ 1127 nic_data->must_check_datapath_caps = true; 1128 1129 /* MAC statistics have been cleared on the NIC; clear the local 1130 * statistic that we update with efx_update_diff_stat(). 1131 */ 1132 nic_data->stats[EF10_STAT_rx_bad_bytes] = 0; 1133 1134 return -EIO; 1135} 1136 1137/* Handle an MSI interrupt 1138 * 1139 * Handle an MSI hardware interrupt. This routine schedules event 1140 * queue processing. No interrupt acknowledgement cycle is necessary. 1141 * Also, we never need to check that the interrupt is for us, since 1142 * MSI interrupts cannot be shared. 1143 */ 1144static irqreturn_t efx_ef10_msi_interrupt(int irq, void *dev_id) 1145{ 1146 struct efx_msi_context *context = dev_id; 1147 struct efx_nic *efx = context->efx; 1148 1149 netif_vdbg(efx, intr, efx->net_dev, 1150 "IRQ %d on CPU %d\n", irq, raw_smp_processor_id()); 1151 1152 if (likely(ACCESS_ONCE(efx->irq_soft_enabled))) { 1153 /* Note test interrupts */ 1154 if (context->index == efx->irq_level) 1155 efx->last_irq_cpu = raw_smp_processor_id(); 1156 1157 /* Schedule processing of the channel */ 1158 efx_schedule_channel_irq(efx->channel[context->index]); 1159 } 1160 1161 return IRQ_HANDLED; 1162} 1163 1164static irqreturn_t efx_ef10_legacy_interrupt(int irq, void *dev_id) 1165{ 1166 struct efx_nic *efx = dev_id; 1167 bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled); 1168 struct efx_channel *channel; 1169 efx_dword_t reg; 1170 u32 queues; 1171 1172 /* Read the ISR which also ACKs the interrupts */ 1173 efx_readd(efx, ®, ER_DZ_BIU_INT_ISR); 1174 queues = EFX_DWORD_FIELD(reg, ERF_DZ_ISR_REG); 1175 1176 if (queues == 0) 1177 return IRQ_NONE; 1178 1179 if (likely(soft_enabled)) { 1180 /* Note test interrupts */ 1181 if (queues & (1U << efx->irq_level)) 1182 efx->last_irq_cpu = raw_smp_processor_id(); 1183 1184 efx_for_each_channel(channel, efx) { 1185 if (queues & 1) 1186 efx_schedule_channel_irq(channel); 1187 queues >>= 1; 1188 } 1189 } 1190 1191 netif_vdbg(efx, intr, efx->net_dev, 1192 "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", 1193 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); 1194 1195 return IRQ_HANDLED; 1196} 1197 1198static void efx_ef10_irq_test_generate(struct efx_nic *efx) 1199{ 1200 MCDI_DECLARE_BUF(inbuf, MC_CMD_TRIGGER_INTERRUPT_IN_LEN); 1201 1202 BUILD_BUG_ON(MC_CMD_TRIGGER_INTERRUPT_OUT_LEN != 0); 1203 1204 MCDI_SET_DWORD(inbuf, TRIGGER_INTERRUPT_IN_INTR_LEVEL, efx->irq_level); 1205 (void) efx_mcdi_rpc(efx, MC_CMD_TRIGGER_INTERRUPT, 1206 inbuf, sizeof(inbuf), NULL, 0, NULL); 1207} 1208 1209static int efx_ef10_tx_probe(struct efx_tx_queue *tx_queue) 1210{ 1211 return efx_nic_alloc_buffer(tx_queue->efx, &tx_queue->txd.buf, 1212 (tx_queue->ptr_mask + 1) * 1213 sizeof(efx_qword_t), 1214 GFP_KERNEL); 1215} 1216 1217/* This writes to the TX_DESC_WPTR and also pushes data */ 1218static inline void efx_ef10_push_tx_desc(struct efx_tx_queue *tx_queue, 1219 const efx_qword_t *txd) 1220{ 1221 unsigned int write_ptr; 1222 efx_oword_t reg; 1223 1224 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1225 EFX_POPULATE_OWORD_1(reg, ERF_DZ_TX_DESC_WPTR, write_ptr); 1226 reg.qword[0] = *txd; 1227 efx_writeo_page(tx_queue->efx, ®, 1228 ER_DZ_TX_DESC_UPD, tx_queue->queue); 1229} 1230 1231static void efx_ef10_tx_init(struct efx_tx_queue *tx_queue) 1232{ 1233 MCDI_DECLARE_BUF(inbuf, MC_CMD_INIT_TXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1234 EFX_BUF_SIZE)); 1235 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_TXQ_OUT_LEN); 1236 bool csum_offload = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD; 1237 size_t entries = tx_queue->txd.buf.len / EFX_BUF_SIZE; 1238 struct efx_channel *channel = tx_queue->channel; 1239 struct efx_nic *efx = tx_queue->efx; 1240 size_t inlen, outlen; 1241 dma_addr_t dma_addr; 1242 efx_qword_t *txd; 1243 int rc; 1244 int i; 1245 1246 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_SIZE, tx_queue->ptr_mask + 1); 1247 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_TARGET_EVQ, channel->channel); 1248 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_LABEL, tx_queue->queue); 1249 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_INSTANCE, tx_queue->queue); 1250 MCDI_POPULATE_DWORD_2(inbuf, INIT_TXQ_IN_FLAGS, 1251 INIT_TXQ_IN_FLAG_IP_CSUM_DIS, !csum_offload, 1252 INIT_TXQ_IN_FLAG_TCP_CSUM_DIS, !csum_offload); 1253 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_OWNER_ID, 0); 1254 MCDI_SET_DWORD(inbuf, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1255 1256 dma_addr = tx_queue->txd.buf.dma_addr; 1257 1258 netif_dbg(efx, hw, efx->net_dev, "pushing TXQ %d. %zu entries (%llx)\n", 1259 tx_queue->queue, entries, (u64)dma_addr); 1260 1261 for (i = 0; i < entries; ++i) { 1262 MCDI_SET_ARRAY_QWORD(inbuf, INIT_TXQ_IN_DMA_ADDR, i, dma_addr); 1263 dma_addr += EFX_BUF_SIZE; 1264 } 1265 1266 inlen = MC_CMD_INIT_TXQ_IN_LEN(entries); 1267 1268 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_TXQ, inbuf, inlen, 1269 outbuf, sizeof(outbuf), &outlen); 1270 if (rc) 1271 goto fail; 1272 1273 /* A previous user of this TX queue might have set us up the 1274 * bomb by writing a descriptor to the TX push collector but 1275 * not the doorbell. (Each collector belongs to a port, not a 1276 * queue or function, so cannot easily be reset.) We must 1277 * attempt to push a no-op descriptor in its place. 1278 */ 1279 tx_queue->buffer[0].flags = EFX_TX_BUF_OPTION; 1280 tx_queue->insert_count = 1; 1281 txd = efx_tx_desc(tx_queue, 0); 1282 EFX_POPULATE_QWORD_4(*txd, 1283 ESF_DZ_TX_DESC_IS_OPT, true, 1284 ESF_DZ_TX_OPTION_TYPE, 1285 ESE_DZ_TX_OPTION_DESC_CRC_CSUM, 1286 ESF_DZ_TX_OPTION_UDP_TCP_CSUM, csum_offload, 1287 ESF_DZ_TX_OPTION_IP_CSUM, csum_offload); 1288 tx_queue->write_count = 1; 1289 wmb(); 1290 efx_ef10_push_tx_desc(tx_queue, txd); 1291 1292 return; 1293 1294fail: 1295 netdev_WARN(efx->net_dev, "failed to initialise TXQ %d\n", 1296 tx_queue->queue); 1297} 1298 1299static void efx_ef10_tx_fini(struct efx_tx_queue *tx_queue) 1300{ 1301 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_TXQ_IN_LEN); 1302 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_TXQ_OUT_LEN); 1303 struct efx_nic *efx = tx_queue->efx; 1304 size_t outlen; 1305 int rc; 1306 1307 MCDI_SET_DWORD(inbuf, FINI_TXQ_IN_INSTANCE, 1308 tx_queue->queue); 1309 1310 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_TXQ, inbuf, sizeof(inbuf), 1311 outbuf, sizeof(outbuf), &outlen); 1312 1313 if (rc && rc != -EALREADY) 1314 goto fail; 1315 1316 return; 1317 1318fail: 1319 efx_mcdi_display_error(efx, MC_CMD_FINI_TXQ, MC_CMD_FINI_TXQ_IN_LEN, 1320 outbuf, outlen, rc); 1321} 1322 1323static void efx_ef10_tx_remove(struct efx_tx_queue *tx_queue) 1324{ 1325 efx_nic_free_buffer(tx_queue->efx, &tx_queue->txd.buf); 1326} 1327 1328/* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ 1329static inline void efx_ef10_notify_tx_desc(struct efx_tx_queue *tx_queue) 1330{ 1331 unsigned int write_ptr; 1332 efx_dword_t reg; 1333 1334 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1335 EFX_POPULATE_DWORD_1(reg, ERF_DZ_TX_DESC_WPTR_DWORD, write_ptr); 1336 efx_writed_page(tx_queue->efx, ®, 1337 ER_DZ_TX_DESC_UPD_DWORD, tx_queue->queue); 1338} 1339 1340static void efx_ef10_tx_write(struct efx_tx_queue *tx_queue) 1341{ 1342 unsigned int old_write_count = tx_queue->write_count; 1343 struct efx_tx_buffer *buffer; 1344 unsigned int write_ptr; 1345 efx_qword_t *txd; 1346 1347 tx_queue->xmit_more_available = false; 1348 if (unlikely(tx_queue->write_count == tx_queue->insert_count)) 1349 return; 1350 1351 do { 1352 write_ptr = tx_queue->write_count & tx_queue->ptr_mask; 1353 buffer = &tx_queue->buffer[write_ptr]; 1354 txd = efx_tx_desc(tx_queue, write_ptr); 1355 ++tx_queue->write_count; 1356 1357 /* Create TX descriptor ring entry */ 1358 if (buffer->flags & EFX_TX_BUF_OPTION) { 1359 *txd = buffer->option; 1360 } else { 1361 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1); 1362 EFX_POPULATE_QWORD_3( 1363 *txd, 1364 ESF_DZ_TX_KER_CONT, 1365 buffer->flags & EFX_TX_BUF_CONT, 1366 ESF_DZ_TX_KER_BYTE_CNT, buffer->len, 1367 ESF_DZ_TX_KER_BUF_ADDR, buffer->dma_addr); 1368 } 1369 } while (tx_queue->write_count != tx_queue->insert_count); 1370 1371 wmb(); /* Ensure descriptors are written before they are fetched */ 1372 1373 if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) { 1374 txd = efx_tx_desc(tx_queue, 1375 old_write_count & tx_queue->ptr_mask); 1376 efx_ef10_push_tx_desc(tx_queue, txd); 1377 ++tx_queue->pushes; 1378 } else { 1379 efx_ef10_notify_tx_desc(tx_queue); 1380 } 1381} 1382 1383static int efx_ef10_alloc_rss_context(struct efx_nic *efx, u32 *context) 1384{ 1385 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN); 1386 MCDI_DECLARE_BUF(outbuf, MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN); 1387 size_t outlen; 1388 int rc; 1389 1390 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID, 1391 EVB_PORT_ID_ASSIGNED); 1392 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_TYPE, 1393 MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE); 1394 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_ALLOC_IN_NUM_QUEUES, 1395 EFX_MAX_CHANNELS); 1396 1397 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_ALLOC, inbuf, sizeof(inbuf), 1398 outbuf, sizeof(outbuf), &outlen); 1399 if (rc != 0) 1400 return rc; 1401 1402 if (outlen < MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN) 1403 return -EIO; 1404 1405 *context = MCDI_DWORD(outbuf, RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID); 1406 1407 return 0; 1408} 1409 1410static void efx_ef10_free_rss_context(struct efx_nic *efx, u32 context) 1411{ 1412 MCDI_DECLARE_BUF(inbuf, MC_CMD_RSS_CONTEXT_FREE_IN_LEN); 1413 int rc; 1414 1415 MCDI_SET_DWORD(inbuf, RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID, 1416 context); 1417 1418 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_FREE, inbuf, sizeof(inbuf), 1419 NULL, 0, NULL); 1420 WARN_ON(rc != 0); 1421} 1422 1423static int efx_ef10_populate_rss_table(struct efx_nic *efx, u32 context) 1424{ 1425 MCDI_DECLARE_BUF(tablebuf, MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN); 1426 MCDI_DECLARE_BUF(keybuf, MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN); 1427 int i, rc; 1428 1429 MCDI_SET_DWORD(tablebuf, RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID, 1430 context); 1431 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) != 1432 MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN); 1433 1434 for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); ++i) 1435 MCDI_PTR(tablebuf, 1436 RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE)[i] = 1437 (u8) efx->rx_indir_table[i]; 1438 1439 rc = efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_TABLE, tablebuf, 1440 sizeof(tablebuf), NULL, 0, NULL); 1441 if (rc != 0) 1442 return rc; 1443 1444 MCDI_SET_DWORD(keybuf, RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID, 1445 context); 1446 BUILD_BUG_ON(ARRAY_SIZE(efx->rx_hash_key) != 1447 MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN); 1448 for (i = 0; i < ARRAY_SIZE(efx->rx_hash_key); ++i) 1449 MCDI_PTR(keybuf, RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY)[i] = 1450 efx->rx_hash_key[i]; 1451 1452 return efx_mcdi_rpc(efx, MC_CMD_RSS_CONTEXT_SET_KEY, keybuf, 1453 sizeof(keybuf), NULL, 0, NULL); 1454} 1455 1456static void efx_ef10_rx_free_indir_table(struct efx_nic *efx) 1457{ 1458 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1459 1460 if (nic_data->rx_rss_context != EFX_EF10_RSS_CONTEXT_INVALID) 1461 efx_ef10_free_rss_context(efx, nic_data->rx_rss_context); 1462 nic_data->rx_rss_context = EFX_EF10_RSS_CONTEXT_INVALID; 1463} 1464 1465static void efx_ef10_rx_push_rss_config(struct efx_nic *efx) 1466{ 1467 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1468 int rc; 1469 1470 netif_dbg(efx, drv, efx->net_dev, "pushing RSS config\n"); 1471 1472 if (nic_data->rx_rss_context == EFX_EF10_RSS_CONTEXT_INVALID) { 1473 rc = efx_ef10_alloc_rss_context(efx, &nic_data->rx_rss_context); 1474 if (rc != 0) 1475 goto fail; 1476 } 1477 1478 rc = efx_ef10_populate_rss_table(efx, nic_data->rx_rss_context); 1479 if (rc != 0) 1480 goto fail; 1481 1482 return; 1483 1484fail: 1485 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 1486} 1487 1488static int efx_ef10_rx_probe(struct efx_rx_queue *rx_queue) 1489{ 1490 return efx_nic_alloc_buffer(rx_queue->efx, &rx_queue->rxd.buf, 1491 (rx_queue->ptr_mask + 1) * 1492 sizeof(efx_qword_t), 1493 GFP_KERNEL); 1494} 1495 1496static void efx_ef10_rx_init(struct efx_rx_queue *rx_queue) 1497{ 1498 MCDI_DECLARE_BUF(inbuf, 1499 MC_CMD_INIT_RXQ_IN_LEN(EFX_MAX_DMAQ_SIZE * 8 / 1500 EFX_BUF_SIZE)); 1501 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_RXQ_OUT_LEN); 1502 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 1503 size_t entries = rx_queue->rxd.buf.len / EFX_BUF_SIZE; 1504 struct efx_nic *efx = rx_queue->efx; 1505 size_t inlen, outlen; 1506 dma_addr_t dma_addr; 1507 int rc; 1508 int i; 1509 1510 rx_queue->scatter_n = 0; 1511 rx_queue->scatter_len = 0; 1512 1513 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_SIZE, rx_queue->ptr_mask + 1); 1514 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_TARGET_EVQ, channel->channel); 1515 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_LABEL, efx_rx_queue_index(rx_queue)); 1516 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_INSTANCE, 1517 efx_rx_queue_index(rx_queue)); 1518 MCDI_POPULATE_DWORD_2(inbuf, INIT_RXQ_IN_FLAGS, 1519 INIT_RXQ_IN_FLAG_PREFIX, 1, 1520 INIT_RXQ_IN_FLAG_TIMESTAMP, 1); 1521 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_OWNER_ID, 0); 1522 MCDI_SET_DWORD(inbuf, INIT_RXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 1523 1524 dma_addr = rx_queue->rxd.buf.dma_addr; 1525 1526 netif_dbg(efx, hw, efx->net_dev, "pushing RXQ %d. %zu entries (%llx)\n", 1527 efx_rx_queue_index(rx_queue), entries, (u64)dma_addr); 1528 1529 for (i = 0; i < entries; ++i) { 1530 MCDI_SET_ARRAY_QWORD(inbuf, INIT_RXQ_IN_DMA_ADDR, i, dma_addr); 1531 dma_addr += EFX_BUF_SIZE; 1532 } 1533 1534 inlen = MC_CMD_INIT_RXQ_IN_LEN(entries); 1535 1536 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_RXQ, inbuf, inlen, 1537 outbuf, sizeof(outbuf), &outlen); 1538 if (rc) 1539 netdev_WARN(efx->net_dev, "failed to initialise RXQ %d\n", 1540 efx_rx_queue_index(rx_queue)); 1541} 1542 1543static void efx_ef10_rx_fini(struct efx_rx_queue *rx_queue) 1544{ 1545 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_RXQ_IN_LEN); 1546 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_RXQ_OUT_LEN); 1547 struct efx_nic *efx = rx_queue->efx; 1548 size_t outlen; 1549 int rc; 1550 1551 MCDI_SET_DWORD(inbuf, FINI_RXQ_IN_INSTANCE, 1552 efx_rx_queue_index(rx_queue)); 1553 1554 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_RXQ, inbuf, sizeof(inbuf), 1555 outbuf, sizeof(outbuf), &outlen); 1556 1557 if (rc && rc != -EALREADY) 1558 goto fail; 1559 1560 return; 1561 1562fail: 1563 efx_mcdi_display_error(efx, MC_CMD_FINI_RXQ, MC_CMD_FINI_RXQ_IN_LEN, 1564 outbuf, outlen, rc); 1565} 1566 1567static void efx_ef10_rx_remove(struct efx_rx_queue *rx_queue) 1568{ 1569 efx_nic_free_buffer(rx_queue->efx, &rx_queue->rxd.buf); 1570} 1571 1572/* This creates an entry in the RX descriptor queue */ 1573static inline void 1574efx_ef10_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) 1575{ 1576 struct efx_rx_buffer *rx_buf; 1577 efx_qword_t *rxd; 1578 1579 rxd = efx_rx_desc(rx_queue, index); 1580 rx_buf = efx_rx_buffer(rx_queue, index); 1581 EFX_POPULATE_QWORD_2(*rxd, 1582 ESF_DZ_RX_KER_BYTE_CNT, rx_buf->len, 1583 ESF_DZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); 1584} 1585 1586static void efx_ef10_rx_write(struct efx_rx_queue *rx_queue) 1587{ 1588 struct efx_nic *efx = rx_queue->efx; 1589 unsigned int write_count; 1590 efx_dword_t reg; 1591 1592 /* Firmware requires that RX_DESC_WPTR be a multiple of 8 */ 1593 write_count = rx_queue->added_count & ~7; 1594 if (rx_queue->notified_count == write_count) 1595 return; 1596 1597 do 1598 efx_ef10_build_rx_desc( 1599 rx_queue, 1600 rx_queue->notified_count & rx_queue->ptr_mask); 1601 while (++rx_queue->notified_count != write_count); 1602 1603 wmb(); 1604 EFX_POPULATE_DWORD_1(reg, ERF_DZ_RX_DESC_WPTR, 1605 write_count & rx_queue->ptr_mask); 1606 efx_writed_page(efx, ®, ER_DZ_RX_DESC_UPD, 1607 efx_rx_queue_index(rx_queue)); 1608} 1609 1610static efx_mcdi_async_completer efx_ef10_rx_defer_refill_complete; 1611 1612static void efx_ef10_rx_defer_refill(struct efx_rx_queue *rx_queue) 1613{ 1614 struct efx_channel *channel = efx_rx_queue_channel(rx_queue); 1615 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 1616 efx_qword_t event; 1617 1618 EFX_POPULATE_QWORD_2(event, 1619 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 1620 ESF_DZ_EV_DATA, EFX_EF10_REFILL); 1621 1622 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 1623 1624 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 1625 * already swapped the data to little-endian order. 1626 */ 1627 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 1628 sizeof(efx_qword_t)); 1629 1630 efx_mcdi_rpc_async(channel->efx, MC_CMD_DRIVER_EVENT, 1631 inbuf, sizeof(inbuf), 0, 1632 efx_ef10_rx_defer_refill_complete, 0); 1633} 1634 1635static void 1636efx_ef10_rx_defer_refill_complete(struct efx_nic *efx, unsigned long cookie, 1637 int rc, efx_dword_t *outbuf, 1638 size_t outlen_actual) 1639{ 1640 /* nothing to do */ 1641} 1642 1643static int efx_ef10_ev_probe(struct efx_channel *channel) 1644{ 1645 return efx_nic_alloc_buffer(channel->efx, &channel->eventq.buf, 1646 (channel->eventq_mask + 1) * 1647 sizeof(efx_qword_t), 1648 GFP_KERNEL); 1649} 1650 1651static int efx_ef10_ev_init(struct efx_channel *channel) 1652{ 1653 MCDI_DECLARE_BUF(inbuf, 1654 MC_CMD_INIT_EVQ_IN_LEN(EFX_MAX_EVQ_SIZE * 8 / 1655 EFX_BUF_SIZE)); 1656 MCDI_DECLARE_BUF(outbuf, MC_CMD_INIT_EVQ_OUT_LEN); 1657 size_t entries = channel->eventq.buf.len / EFX_BUF_SIZE; 1658 struct efx_nic *efx = channel->efx; 1659 struct efx_ef10_nic_data *nic_data; 1660 bool supports_rx_merge; 1661 size_t inlen, outlen; 1662 dma_addr_t dma_addr; 1663 int rc; 1664 int i; 1665 1666 nic_data = efx->nic_data; 1667 supports_rx_merge = 1668 !!(nic_data->datapath_caps & 1669 1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN); 1670 1671 /* Fill event queue with all ones (i.e. empty events) */ 1672 memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len); 1673 1674 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_SIZE, channel->eventq_mask + 1); 1675 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_INSTANCE, channel->channel); 1676 /* INIT_EVQ expects index in vector table, not absolute */ 1677 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_IRQ_NUM, channel->channel); 1678 MCDI_POPULATE_DWORD_4(inbuf, INIT_EVQ_IN_FLAGS, 1679 INIT_EVQ_IN_FLAG_INTERRUPTING, 1, 1680 INIT_EVQ_IN_FLAG_RX_MERGE, 1, 1681 INIT_EVQ_IN_FLAG_TX_MERGE, 1, 1682 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_merge); 1683 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_MODE, 1684 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS); 1685 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_LOAD, 0); 1686 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_TMR_RELOAD, 0); 1687 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_MODE, 1688 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS); 1689 MCDI_SET_DWORD(inbuf, INIT_EVQ_IN_COUNT_THRSHLD, 0); 1690 1691 dma_addr = channel->eventq.buf.dma_addr; 1692 for (i = 0; i < entries; ++i) { 1693 MCDI_SET_ARRAY_QWORD(inbuf, INIT_EVQ_IN_DMA_ADDR, i, dma_addr); 1694 dma_addr += EFX_BUF_SIZE; 1695 } 1696 1697 inlen = MC_CMD_INIT_EVQ_IN_LEN(entries); 1698 1699 rc = efx_mcdi_rpc(efx, MC_CMD_INIT_EVQ, inbuf, inlen, 1700 outbuf, sizeof(outbuf), &outlen); 1701 /* IRQ return is ignored */ 1702 return rc; 1703} 1704 1705static void efx_ef10_ev_fini(struct efx_channel *channel) 1706{ 1707 MCDI_DECLARE_BUF(inbuf, MC_CMD_FINI_EVQ_IN_LEN); 1708 MCDI_DECLARE_BUF(outbuf, MC_CMD_FINI_EVQ_OUT_LEN); 1709 struct efx_nic *efx = channel->efx; 1710 size_t outlen; 1711 int rc; 1712 1713 MCDI_SET_DWORD(inbuf, FINI_EVQ_IN_INSTANCE, channel->channel); 1714 1715 rc = efx_mcdi_rpc_quiet(efx, MC_CMD_FINI_EVQ, inbuf, sizeof(inbuf), 1716 outbuf, sizeof(outbuf), &outlen); 1717 1718 if (rc && rc != -EALREADY) 1719 goto fail; 1720 1721 return; 1722 1723fail: 1724 efx_mcdi_display_error(efx, MC_CMD_FINI_EVQ, MC_CMD_FINI_EVQ_IN_LEN, 1725 outbuf, outlen, rc); 1726} 1727 1728static void efx_ef10_ev_remove(struct efx_channel *channel) 1729{ 1730 efx_nic_free_buffer(channel->efx, &channel->eventq.buf); 1731} 1732 1733static void efx_ef10_handle_rx_wrong_queue(struct efx_rx_queue *rx_queue, 1734 unsigned int rx_queue_label) 1735{ 1736 struct efx_nic *efx = rx_queue->efx; 1737 1738 netif_info(efx, hw, efx->net_dev, 1739 "rx event arrived on queue %d labeled as queue %u\n", 1740 efx_rx_queue_index(rx_queue), rx_queue_label); 1741 1742 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 1743} 1744 1745static void 1746efx_ef10_handle_rx_bad_lbits(struct efx_rx_queue *rx_queue, 1747 unsigned int actual, unsigned int expected) 1748{ 1749 unsigned int dropped = (actual - expected) & rx_queue->ptr_mask; 1750 struct efx_nic *efx = rx_queue->efx; 1751 1752 netif_info(efx, hw, efx->net_dev, 1753 "dropped %d events (index=%d expected=%d)\n", 1754 dropped, actual, expected); 1755 1756 efx_schedule_reset(efx, RESET_TYPE_DISABLE); 1757} 1758 1759/* partially received RX was aborted. clean up. */ 1760static void efx_ef10_handle_rx_abort(struct efx_rx_queue *rx_queue) 1761{ 1762 unsigned int rx_desc_ptr; 1763 1764 netif_dbg(rx_queue->efx, hw, rx_queue->efx->net_dev, 1765 "scattered RX aborted (dropping %u buffers)\n", 1766 rx_queue->scatter_n); 1767 1768 rx_desc_ptr = rx_queue->removed_count & rx_queue->ptr_mask; 1769 1770 efx_rx_packet(rx_queue, rx_desc_ptr, rx_queue->scatter_n, 1771 0, EFX_RX_PKT_DISCARD); 1772 1773 rx_queue->removed_count += rx_queue->scatter_n; 1774 rx_queue->scatter_n = 0; 1775 rx_queue->scatter_len = 0; 1776 ++efx_rx_queue_channel(rx_queue)->n_rx_nodesc_trunc; 1777} 1778 1779static int efx_ef10_handle_rx_event(struct efx_channel *channel, 1780 const efx_qword_t *event) 1781{ 1782 unsigned int rx_bytes, next_ptr_lbits, rx_queue_label, rx_l4_class; 1783 unsigned int n_descs, n_packets, i; 1784 struct efx_nic *efx = channel->efx; 1785 struct efx_rx_queue *rx_queue; 1786 bool rx_cont; 1787 u16 flags = 0; 1788 1789 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 1790 return 0; 1791 1792 /* Basic packet information */ 1793 rx_bytes = EFX_QWORD_FIELD(*event, ESF_DZ_RX_BYTES); 1794 next_ptr_lbits = EFX_QWORD_FIELD(*event, ESF_DZ_RX_DSC_PTR_LBITS); 1795 rx_queue_label = EFX_QWORD_FIELD(*event, ESF_DZ_RX_QLABEL); 1796 rx_l4_class = EFX_QWORD_FIELD(*event, ESF_DZ_RX_L4_CLASS); 1797 rx_cont = EFX_QWORD_FIELD(*event, ESF_DZ_RX_CONT); 1798 1799 if (EFX_QWORD_FIELD(*event, ESF_DZ_RX_DROP_EVENT)) 1800 netdev_WARN(efx->net_dev, "saw RX_DROP_EVENT: event=" 1801 EFX_QWORD_FMT "\n", 1802 EFX_QWORD_VAL(*event)); 1803 1804 rx_queue = efx_channel_get_rx_queue(channel); 1805 1806 if (unlikely(rx_queue_label != efx_rx_queue_index(rx_queue))) 1807 efx_ef10_handle_rx_wrong_queue(rx_queue, rx_queue_label); 1808 1809 n_descs = ((next_ptr_lbits - rx_queue->removed_count) & 1810 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 1811 1812 if (n_descs != rx_queue->scatter_n + 1) { 1813 struct efx_ef10_nic_data *nic_data = efx->nic_data; 1814 1815 /* detect rx abort */ 1816 if (unlikely(n_descs == rx_queue->scatter_n)) { 1817 if (rx_queue->scatter_n == 0 || rx_bytes != 0) 1818 netdev_WARN(efx->net_dev, 1819 "invalid RX abort: scatter_n=%u event=" 1820 EFX_QWORD_FMT "\n", 1821 rx_queue->scatter_n, 1822 EFX_QWORD_VAL(*event)); 1823 efx_ef10_handle_rx_abort(rx_queue); 1824 return 0; 1825 } 1826 1827 /* Check that RX completion merging is valid, i.e. 1828 * the current firmware supports it and this is a 1829 * non-scattered packet. 1830 */ 1831 if (!(nic_data->datapath_caps & 1832 (1 << MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN)) || 1833 rx_queue->scatter_n != 0 || rx_cont) { 1834 efx_ef10_handle_rx_bad_lbits( 1835 rx_queue, next_ptr_lbits, 1836 (rx_queue->removed_count + 1837 rx_queue->scatter_n + 1) & 1838 ((1 << ESF_DZ_RX_DSC_PTR_LBITS_WIDTH) - 1)); 1839 return 0; 1840 } 1841 1842 /* Merged completion for multiple non-scattered packets */ 1843 rx_queue->scatter_n = 1; 1844 rx_queue->scatter_len = 0; 1845 n_packets = n_descs; 1846 ++channel->n_rx_merge_events; 1847 channel->n_rx_merge_packets += n_packets; 1848 flags |= EFX_RX_PKT_PREFIX_LEN; 1849 } else { 1850 ++rx_queue->scatter_n; 1851 rx_queue->scatter_len += rx_bytes; 1852 if (rx_cont) 1853 return 0; 1854 n_packets = 1; 1855 } 1856 1857 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_ECRC_ERR))) 1858 flags |= EFX_RX_PKT_DISCARD; 1859 1860 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_RX_IPCKSUM_ERR))) { 1861 channel->n_rx_ip_hdr_chksum_err += n_packets; 1862 } else if (unlikely(EFX_QWORD_FIELD(*event, 1863 ESF_DZ_RX_TCPUDP_CKSUM_ERR))) { 1864 channel->n_rx_tcp_udp_chksum_err += n_packets; 1865 } else if (rx_l4_class == ESE_DZ_L4_CLASS_TCP || 1866 rx_l4_class == ESE_DZ_L4_CLASS_UDP) { 1867 flags |= EFX_RX_PKT_CSUMMED; 1868 } 1869 1870 if (rx_l4_class == ESE_DZ_L4_CLASS_TCP) 1871 flags |= EFX_RX_PKT_TCP; 1872 1873 channel->irq_mod_score += 2 * n_packets; 1874 1875 /* Handle received packet(s) */ 1876 for (i = 0; i < n_packets; i++) { 1877 efx_rx_packet(rx_queue, 1878 rx_queue->removed_count & rx_queue->ptr_mask, 1879 rx_queue->scatter_n, rx_queue->scatter_len, 1880 flags); 1881 rx_queue->removed_count += rx_queue->scatter_n; 1882 } 1883 1884 rx_queue->scatter_n = 0; 1885 rx_queue->scatter_len = 0; 1886 1887 return n_packets; 1888} 1889 1890static int 1891efx_ef10_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) 1892{ 1893 struct efx_nic *efx = channel->efx; 1894 struct efx_tx_queue *tx_queue; 1895 unsigned int tx_ev_desc_ptr; 1896 unsigned int tx_ev_q_label; 1897 int tx_descs = 0; 1898 1899 if (unlikely(ACCESS_ONCE(efx->reset_pending))) 1900 return 0; 1901 1902 if (unlikely(EFX_QWORD_FIELD(*event, ESF_DZ_TX_DROP_EVENT))) 1903 return 0; 1904 1905 /* Transmit completion */ 1906 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, ESF_DZ_TX_DESCR_INDX); 1907 tx_ev_q_label = EFX_QWORD_FIELD(*event, ESF_DZ_TX_QLABEL); 1908 tx_queue = efx_channel_get_tx_queue(channel, 1909 tx_ev_q_label % EFX_TXQ_TYPES); 1910 tx_descs = ((tx_ev_desc_ptr + 1 - tx_queue->read_count) & 1911 tx_queue->ptr_mask); 1912 efx_xmit_done(tx_queue, tx_ev_desc_ptr & tx_queue->ptr_mask); 1913 1914 return tx_descs; 1915} 1916 1917static void 1918efx_ef10_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) 1919{ 1920 struct efx_nic *efx = channel->efx; 1921 int subcode; 1922 1923 subcode = EFX_QWORD_FIELD(*event, ESF_DZ_DRV_SUB_CODE); 1924 1925 switch (subcode) { 1926 case ESE_DZ_DRV_TIMER_EV: 1927 case ESE_DZ_DRV_WAKE_UP_EV: 1928 break; 1929 case ESE_DZ_DRV_START_UP_EV: 1930 /* event queue init complete. ok. */ 1931 break; 1932 default: 1933 netif_err(efx, hw, efx->net_dev, 1934 "channel %d unknown driver event type %d" 1935 " (data " EFX_QWORD_FMT ")\n", 1936 channel->channel, subcode, 1937 EFX_QWORD_VAL(*event)); 1938 1939 } 1940} 1941 1942static void efx_ef10_handle_driver_generated_event(struct efx_channel *channel, 1943 efx_qword_t *event) 1944{ 1945 struct efx_nic *efx = channel->efx; 1946 u32 subcode; 1947 1948 subcode = EFX_QWORD_FIELD(*event, EFX_DWORD_0); 1949 1950 switch (subcode) { 1951 case EFX_EF10_TEST: 1952 channel->event_test_cpu = raw_smp_processor_id(); 1953 break; 1954 case EFX_EF10_REFILL: 1955 /* The queue must be empty, so we won't receive any rx 1956 * events, so efx_process_channel() won't refill the 1957 * queue. Refill it here 1958 */ 1959 efx_fast_push_rx_descriptors(&channel->rx_queue, true); 1960 break; 1961 default: 1962 netif_err(efx, hw, efx->net_dev, 1963 "channel %d unknown driver event type %u" 1964 " (data " EFX_QWORD_FMT ")\n", 1965 channel->channel, (unsigned) subcode, 1966 EFX_QWORD_VAL(*event)); 1967 } 1968} 1969 1970static int efx_ef10_ev_process(struct efx_channel *channel, int quota) 1971{ 1972 struct efx_nic *efx = channel->efx; 1973 efx_qword_t event, *p_event; 1974 unsigned int read_ptr; 1975 int ev_code; 1976 int tx_descs = 0; 1977 int spent = 0; 1978 1979 if (quota <= 0) 1980 return spent; 1981 1982 read_ptr = channel->eventq_read_ptr; 1983 1984 for (;;) { 1985 p_event = efx_event(channel, read_ptr); 1986 event = *p_event; 1987 1988 if (!efx_event_present(&event)) 1989 break; 1990 1991 EFX_SET_QWORD(*p_event); 1992 1993 ++read_ptr; 1994 1995 ev_code = EFX_QWORD_FIELD(event, ESF_DZ_EV_CODE); 1996 1997 netif_vdbg(efx, drv, efx->net_dev, 1998 "processing event on %d " EFX_QWORD_FMT "\n", 1999 channel->channel, EFX_QWORD_VAL(event)); 2000 2001 switch (ev_code) { 2002 case ESE_DZ_EV_CODE_MCDI_EV: 2003 efx_mcdi_process_event(channel, &event); 2004 break; 2005 case ESE_DZ_EV_CODE_RX_EV: 2006 spent += efx_ef10_handle_rx_event(channel, &event); 2007 if (spent >= quota) { 2008 /* XXX can we split a merged event to 2009 * avoid going over-quota? 2010 */ 2011 spent = quota; 2012 goto out; 2013 } 2014 break; 2015 case ESE_DZ_EV_CODE_TX_EV: 2016 tx_descs += efx_ef10_handle_tx_event(channel, &event); 2017 if (tx_descs > efx->txq_entries) { 2018 spent = quota; 2019 goto out; 2020 } else if (++spent == quota) { 2021 goto out; 2022 } 2023 break; 2024 case ESE_DZ_EV_CODE_DRIVER_EV: 2025 efx_ef10_handle_driver_event(channel, &event); 2026 if (++spent == quota) 2027 goto out; 2028 break; 2029 case EFX_EF10_DRVGEN_EV: 2030 efx_ef10_handle_driver_generated_event(channel, &event); 2031 break; 2032 default: 2033 netif_err(efx, hw, efx->net_dev, 2034 "channel %d unknown event type %d" 2035 " (data " EFX_QWORD_FMT ")\n", 2036 channel->channel, ev_code, 2037 EFX_QWORD_VAL(event)); 2038 } 2039 } 2040 2041out: 2042 channel->eventq_read_ptr = read_ptr; 2043 return spent; 2044} 2045 2046static void efx_ef10_ev_read_ack(struct efx_channel *channel) 2047{ 2048 struct efx_nic *efx = channel->efx; 2049 efx_dword_t rptr; 2050 2051 if (EFX_EF10_WORKAROUND_35388(efx)) { 2052 BUILD_BUG_ON(EFX_MIN_EVQ_SIZE < 2053 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH)); 2054 BUILD_BUG_ON(EFX_MAX_EVQ_SIZE > 2055 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH)); 2056 2057 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2058 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH, 2059 ERF_DD_EVQ_IND_RPTR, 2060 (channel->eventq_read_ptr & 2061 channel->eventq_mask) >> 2062 ERF_DD_EVQ_IND_RPTR_WIDTH); 2063 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2064 channel->channel); 2065 EFX_POPULATE_DWORD_2(rptr, ERF_DD_EVQ_IND_RPTR_FLAGS, 2066 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW, 2067 ERF_DD_EVQ_IND_RPTR, 2068 channel->eventq_read_ptr & 2069 ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1)); 2070 efx_writed_page(efx, &rptr, ER_DD_EVQ_INDIRECT, 2071 channel->channel); 2072 } else { 2073 EFX_POPULATE_DWORD_1(rptr, ERF_DZ_EVQ_RPTR, 2074 channel->eventq_read_ptr & 2075 channel->eventq_mask); 2076 efx_writed_page(efx, &rptr, ER_DZ_EVQ_RPTR, channel->channel); 2077 } 2078} 2079 2080static void efx_ef10_ev_test_generate(struct efx_channel *channel) 2081{ 2082 MCDI_DECLARE_BUF(inbuf, MC_CMD_DRIVER_EVENT_IN_LEN); 2083 struct efx_nic *efx = channel->efx; 2084 efx_qword_t event; 2085 int rc; 2086 2087 EFX_POPULATE_QWORD_2(event, 2088 ESF_DZ_EV_CODE, EFX_EF10_DRVGEN_EV, 2089 ESF_DZ_EV_DATA, EFX_EF10_TEST); 2090 2091 MCDI_SET_DWORD(inbuf, DRIVER_EVENT_IN_EVQ, channel->channel); 2092 2093 /* MCDI_SET_QWORD is not appropriate here since EFX_POPULATE_* has 2094 * already swapped the data to little-endian order. 2095 */ 2096 memcpy(MCDI_PTR(inbuf, DRIVER_EVENT_IN_DATA), &event.u64[0], 2097 sizeof(efx_qword_t)); 2098 2099 rc = efx_mcdi_rpc(efx, MC_CMD_DRIVER_EVENT, inbuf, sizeof(inbuf), 2100 NULL, 0, NULL); 2101 if (rc != 0) 2102 goto fail; 2103 2104 return; 2105 2106fail: 2107 WARN_ON(true); 2108 netif_err(efx, hw, efx->net_dev, "%s: failed rc=%d\n", __func__, rc); 2109} 2110 2111void efx_ef10_handle_drain_event(struct efx_nic *efx) 2112{ 2113 if (atomic_dec_and_test(&efx->active_queues)) 2114 wake_up(&efx->flush_wq); 2115 2116 WARN_ON(atomic_read(&efx->active_queues) < 0); 2117} 2118 2119static int efx_ef10_fini_dmaq(struct efx_nic *efx) 2120{ 2121 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2122 struct efx_channel *channel; 2123 struct efx_tx_queue *tx_queue; 2124 struct efx_rx_queue *rx_queue; 2125 int pending; 2126 2127 /* If the MC has just rebooted, the TX/RX queues will have already been 2128 * torn down, but efx->active_queues needs to be set to zero. 2129 */ 2130 if (nic_data->must_realloc_vis) { 2131 atomic_set(&efx->active_queues, 0); 2132 return 0; 2133 } 2134 2135 /* Do not attempt to write to the NIC during EEH recovery */ 2136 if (efx->state != STATE_RECOVERY) { 2137 efx_for_each_channel(channel, efx) { 2138 efx_for_each_channel_rx_queue(rx_queue, channel) 2139 efx_ef10_rx_fini(rx_queue); 2140 efx_for_each_channel_tx_queue(tx_queue, channel) 2141 efx_ef10_tx_fini(tx_queue); 2142 } 2143 2144 wait_event_timeout(efx->flush_wq, 2145 atomic_read(&efx->active_queues) == 0, 2146 msecs_to_jiffies(EFX_MAX_FLUSH_TIME)); 2147 pending = atomic_read(&efx->active_queues); 2148 if (pending) { 2149 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues\n", 2150 pending); 2151 return -ETIMEDOUT; 2152 } 2153 } 2154 2155 return 0; 2156} 2157 2158static void efx_ef10_prepare_flr(struct efx_nic *efx) 2159{ 2160 atomic_set(&efx->active_queues, 0); 2161} 2162 2163static bool efx_ef10_filter_equal(const struct efx_filter_spec *left, 2164 const struct efx_filter_spec *right) 2165{ 2166 if ((left->match_flags ^ right->match_flags) | 2167 ((left->flags ^ right->flags) & 2168 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX))) 2169 return false; 2170 2171 return memcmp(&left->outer_vid, &right->outer_vid, 2172 sizeof(struct efx_filter_spec) - 2173 offsetof(struct efx_filter_spec, outer_vid)) == 0; 2174} 2175 2176static unsigned int efx_ef10_filter_hash(const struct efx_filter_spec *spec) 2177{ 2178 BUILD_BUG_ON(offsetof(struct efx_filter_spec, outer_vid) & 3); 2179 return jhash2((const u32 *)&spec->outer_vid, 2180 (sizeof(struct efx_filter_spec) - 2181 offsetof(struct efx_filter_spec, outer_vid)) / 4, 2182 0); 2183 /* XXX should we randomise the initval? */ 2184} 2185 2186/* Decide whether a filter should be exclusive or else should allow 2187 * delivery to additional recipients. Currently we decide that 2188 * filters for specific local unicast MAC and IP addresses are 2189 * exclusive. 2190 */ 2191static bool efx_ef10_filter_is_exclusive(const struct efx_filter_spec *spec) 2192{ 2193 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC && 2194 !is_multicast_ether_addr(spec->loc_mac)) 2195 return true; 2196 2197 if ((spec->match_flags & 2198 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) == 2199 (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_LOC_HOST)) { 2200 if (spec->ether_type == htons(ETH_P_IP) && 2201 !ipv4_is_multicast(spec->loc_host[0])) 2202 return true; 2203 if (spec->ether_type == htons(ETH_P_IPV6) && 2204 ((const u8 *)spec->loc_host)[0] != 0xff) 2205 return true; 2206 } 2207 2208 return false; 2209} 2210 2211static struct efx_filter_spec * 2212efx_ef10_filter_entry_spec(const struct efx_ef10_filter_table *table, 2213 unsigned int filter_idx) 2214{ 2215 return (struct efx_filter_spec *)(table->entry[filter_idx].spec & 2216 ~EFX_EF10_FILTER_FLAGS); 2217} 2218 2219static unsigned int 2220efx_ef10_filter_entry_flags(const struct efx_ef10_filter_table *table, 2221 unsigned int filter_idx) 2222{ 2223 return table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAGS; 2224} 2225 2226static void 2227efx_ef10_filter_set_entry(struct efx_ef10_filter_table *table, 2228 unsigned int filter_idx, 2229 const struct efx_filter_spec *spec, 2230 unsigned int flags) 2231{ 2232 table->entry[filter_idx].spec = (unsigned long)spec | flags; 2233} 2234 2235static void efx_ef10_filter_push_prep(struct efx_nic *efx, 2236 const struct efx_filter_spec *spec, 2237 efx_dword_t *inbuf, u64 handle, 2238 bool replacing) 2239{ 2240 struct efx_ef10_nic_data *nic_data = efx->nic_data; 2241 2242 memset(inbuf, 0, MC_CMD_FILTER_OP_IN_LEN); 2243 2244 if (replacing) { 2245 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2246 MC_CMD_FILTER_OP_IN_OP_REPLACE); 2247 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, handle); 2248 } else { 2249 u32 match_fields = 0; 2250 2251 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2252 efx_ef10_filter_is_exclusive(spec) ? 2253 MC_CMD_FILTER_OP_IN_OP_INSERT : 2254 MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE); 2255 2256 /* Convert match flags and values. Unlike almost 2257 * everything else in MCDI, these fields are in 2258 * network byte order. 2259 */ 2260 if (spec->match_flags & EFX_FILTER_MATCH_LOC_MAC_IG) 2261 match_fields |= 2262 is_multicast_ether_addr(spec->loc_mac) ? 2263 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN : 2264 1 << MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN; 2265#define COPY_FIELD(gen_flag, gen_field, mcdi_field) \ 2266 if (spec->match_flags & EFX_FILTER_MATCH_ ## gen_flag) { \ 2267 match_fields |= \ 2268 1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2269 mcdi_field ## _LBN; \ 2270 BUILD_BUG_ON( \ 2271 MC_CMD_FILTER_OP_IN_ ## mcdi_field ## _LEN < \ 2272 sizeof(spec->gen_field)); \ 2273 memcpy(MCDI_PTR(inbuf, FILTER_OP_IN_ ## mcdi_field), \ 2274 &spec->gen_field, sizeof(spec->gen_field)); \ 2275 } 2276 COPY_FIELD(REM_HOST, rem_host, SRC_IP); 2277 COPY_FIELD(LOC_HOST, loc_host, DST_IP); 2278 COPY_FIELD(REM_MAC, rem_mac, SRC_MAC); 2279 COPY_FIELD(REM_PORT, rem_port, SRC_PORT); 2280 COPY_FIELD(LOC_MAC, loc_mac, DST_MAC); 2281 COPY_FIELD(LOC_PORT, loc_port, DST_PORT); 2282 COPY_FIELD(ETHER_TYPE, ether_type, ETHER_TYPE); 2283 COPY_FIELD(INNER_VID, inner_vid, INNER_VLAN); 2284 COPY_FIELD(OUTER_VID, outer_vid, OUTER_VLAN); 2285 COPY_FIELD(IP_PROTO, ip_proto, IP_PROTO); 2286#undef COPY_FIELD 2287 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_MATCH_FIELDS, 2288 match_fields); 2289 } 2290 2291 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_PORT_ID, EVB_PORT_ID_ASSIGNED); 2292 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_DEST, 2293 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2294 MC_CMD_FILTER_OP_IN_RX_DEST_DROP : 2295 MC_CMD_FILTER_OP_IN_RX_DEST_HOST); 2296 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_TX_DEST, 2297 MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT); 2298 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_QUEUE, 2299 spec->dmaq_id == EFX_FILTER_RX_DMAQ_ID_DROP ? 2300 0 : spec->dmaq_id); 2301 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_MODE, 2302 (spec->flags & EFX_FILTER_FLAG_RX_RSS) ? 2303 MC_CMD_FILTER_OP_IN_RX_MODE_RSS : 2304 MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE); 2305 if (spec->flags & EFX_FILTER_FLAG_RX_RSS) 2306 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_RX_CONTEXT, 2307 spec->rss_context != 2308 EFX_FILTER_RSS_CONTEXT_DEFAULT ? 2309 spec->rss_context : nic_data->rx_rss_context); 2310} 2311 2312static int efx_ef10_filter_push(struct efx_nic *efx, 2313 const struct efx_filter_spec *spec, 2314 u64 *handle, bool replacing) 2315{ 2316 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2317 MCDI_DECLARE_BUF(outbuf, MC_CMD_FILTER_OP_OUT_LEN); 2318 int rc; 2319 2320 efx_ef10_filter_push_prep(efx, spec, inbuf, *handle, replacing); 2321 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 2322 outbuf, sizeof(outbuf), NULL); 2323 if (rc == 0) 2324 *handle = MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 2325 if (rc == -ENOSPC) 2326 rc = -EBUSY; /* to match efx_farch_filter_insert() */ 2327 return rc; 2328} 2329 2330static int efx_ef10_filter_rx_match_pri(struct efx_ef10_filter_table *table, 2331 enum efx_filter_match_flags match_flags) 2332{ 2333 unsigned int match_pri; 2334 2335 for (match_pri = 0; 2336 match_pri < table->rx_match_count; 2337 match_pri++) 2338 if (table->rx_match_flags[match_pri] == match_flags) 2339 return match_pri; 2340 2341 return -EPROTONOSUPPORT; 2342} 2343 2344static s32 efx_ef10_filter_insert(struct efx_nic *efx, 2345 struct efx_filter_spec *spec, 2346 bool replace_equal) 2347{ 2348 struct efx_ef10_filter_table *table = efx->filter_state; 2349 DECLARE_BITMAP(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2350 struct efx_filter_spec *saved_spec; 2351 unsigned int match_pri, hash; 2352 unsigned int priv_flags; 2353 bool replacing = false; 2354 int ins_index = -1; 2355 DEFINE_WAIT(wait); 2356 bool is_mc_recip; 2357 s32 rc; 2358 2359 /* For now, only support RX filters */ 2360 if ((spec->flags & (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_TX)) != 2361 EFX_FILTER_FLAG_RX) 2362 return -EINVAL; 2363 2364 rc = efx_ef10_filter_rx_match_pri(table, spec->match_flags); 2365 if (rc < 0) 2366 return rc; 2367 match_pri = rc; 2368 2369 hash = efx_ef10_filter_hash(spec); 2370 is_mc_recip = efx_filter_is_mc_recipient(spec); 2371 if (is_mc_recip) 2372 bitmap_zero(mc_rem_map, EFX_EF10_FILTER_SEARCH_LIMIT); 2373 2374 /* Find any existing filters with the same match tuple or 2375 * else a free slot to insert at. If any of them are busy, 2376 * we have to wait and retry. 2377 */ 2378 for (;;) { 2379 unsigned int depth = 1; 2380 unsigned int i; 2381 2382 spin_lock_bh(&efx->filter_lock); 2383 2384 for (;;) { 2385 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2386 saved_spec = efx_ef10_filter_entry_spec(table, i); 2387 2388 if (!saved_spec) { 2389 if (ins_index < 0) 2390 ins_index = i; 2391 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 2392 if (table->entry[i].spec & 2393 EFX_EF10_FILTER_FLAG_BUSY) 2394 break; 2395 if (spec->priority < saved_spec->priority && 2396 spec->priority != EFX_FILTER_PRI_AUTO) { 2397 rc = -EPERM; 2398 goto out_unlock; 2399 } 2400 if (!is_mc_recip) { 2401 /* This is the only one */ 2402 if (spec->priority == 2403 saved_spec->priority && 2404 !replace_equal) { 2405 rc = -EEXIST; 2406 goto out_unlock; 2407 } 2408 ins_index = i; 2409 goto found; 2410 } else if (spec->priority > 2411 saved_spec->priority || 2412 (spec->priority == 2413 saved_spec->priority && 2414 replace_equal)) { 2415 if (ins_index < 0) 2416 ins_index = i; 2417 else 2418 __set_bit(depth, mc_rem_map); 2419 } 2420 } 2421 2422 /* Once we reach the maximum search depth, use 2423 * the first suitable slot or return -EBUSY if 2424 * there was none 2425 */ 2426 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 2427 if (ins_index < 0) { 2428 rc = -EBUSY; 2429 goto out_unlock; 2430 } 2431 goto found; 2432 } 2433 2434 ++depth; 2435 } 2436 2437 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 2438 spin_unlock_bh(&efx->filter_lock); 2439 schedule(); 2440 } 2441 2442found: 2443 /* Create a software table entry if necessary, and mark it 2444 * busy. We might yet fail to insert, but any attempt to 2445 * insert a conflicting filter while we're waiting for the 2446 * firmware must find the busy entry. 2447 */ 2448 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 2449 if (saved_spec) { 2450 if (spec->priority == EFX_FILTER_PRI_AUTO && 2451 saved_spec->priority >= EFX_FILTER_PRI_AUTO) { 2452 /* Just make sure it won't be removed */ 2453 if (saved_spec->priority > EFX_FILTER_PRI_AUTO) 2454 saved_spec->flags |= EFX_FILTER_FLAG_RX_OVER_AUTO; 2455 table->entry[ins_index].spec &= 2456 ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 2457 rc = ins_index; 2458 goto out_unlock; 2459 } 2460 replacing = true; 2461 priv_flags = efx_ef10_filter_entry_flags(table, ins_index); 2462 } else { 2463 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 2464 if (!saved_spec) { 2465 rc = -ENOMEM; 2466 goto out_unlock; 2467 } 2468 *saved_spec = *spec; 2469 priv_flags = 0; 2470 } 2471 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 2472 priv_flags | EFX_EF10_FILTER_FLAG_BUSY); 2473 2474 /* Mark lower-priority multicast recipients busy prior to removal */ 2475 if (is_mc_recip) { 2476 unsigned int depth, i; 2477 2478 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 2479 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2480 if (test_bit(depth, mc_rem_map)) 2481 table->entry[i].spec |= 2482 EFX_EF10_FILTER_FLAG_BUSY; 2483 } 2484 } 2485 2486 spin_unlock_bh(&efx->filter_lock); 2487 2488 rc = efx_ef10_filter_push(efx, spec, &table->entry[ins_index].handle, 2489 replacing); 2490 2491 /* Finalise the software table entry */ 2492 spin_lock_bh(&efx->filter_lock); 2493 if (rc == 0) { 2494 if (replacing) { 2495 /* Update the fields that may differ */ 2496 if (saved_spec->priority == EFX_FILTER_PRI_AUTO) 2497 saved_spec->flags |= 2498 EFX_FILTER_FLAG_RX_OVER_AUTO; 2499 saved_spec->priority = spec->priority; 2500 saved_spec->flags &= EFX_FILTER_FLAG_RX_OVER_AUTO; 2501 saved_spec->flags |= spec->flags; 2502 saved_spec->rss_context = spec->rss_context; 2503 saved_spec->dmaq_id = spec->dmaq_id; 2504 } 2505 } else if (!replacing) { 2506 kfree(saved_spec); 2507 saved_spec = NULL; 2508 } 2509 efx_ef10_filter_set_entry(table, ins_index, saved_spec, priv_flags); 2510 2511 /* Remove and finalise entries for lower-priority multicast 2512 * recipients 2513 */ 2514 if (is_mc_recip) { 2515 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2516 unsigned int depth, i; 2517 2518 memset(inbuf, 0, sizeof(inbuf)); 2519 2520 for (depth = 0; depth < EFX_EF10_FILTER_SEARCH_LIMIT; depth++) { 2521 if (!test_bit(depth, mc_rem_map)) 2522 continue; 2523 2524 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2525 saved_spec = efx_ef10_filter_entry_spec(table, i); 2526 priv_flags = efx_ef10_filter_entry_flags(table, i); 2527 2528 if (rc == 0) { 2529 spin_unlock_bh(&efx->filter_lock); 2530 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2531 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 2532 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 2533 table->entry[i].handle); 2534 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 2535 inbuf, sizeof(inbuf), 2536 NULL, 0, NULL); 2537 spin_lock_bh(&efx->filter_lock); 2538 } 2539 2540 if (rc == 0) { 2541 kfree(saved_spec); 2542 saved_spec = NULL; 2543 priv_flags = 0; 2544 } else { 2545 priv_flags &= ~EFX_EF10_FILTER_FLAG_BUSY; 2546 } 2547 efx_ef10_filter_set_entry(table, i, saved_spec, 2548 priv_flags); 2549 } 2550 } 2551 2552 /* If successful, return the inserted filter ID */ 2553 if (rc == 0) 2554 rc = match_pri * HUNT_FILTER_TBL_ROWS + ins_index; 2555 2556 wake_up_all(&table->waitq); 2557out_unlock: 2558 spin_unlock_bh(&efx->filter_lock); 2559 finish_wait(&table->waitq, &wait); 2560 return rc; 2561} 2562 2563static void efx_ef10_filter_update_rx_scatter(struct efx_nic *efx) 2564{ 2565 /* no need to do anything here on EF10 */ 2566} 2567 2568/* Remove a filter. 2569 * If !by_index, remove by ID 2570 * If by_index, remove by index 2571 * Filter ID may come from userland and must be range-checked. 2572 */ 2573static int efx_ef10_filter_remove_internal(struct efx_nic *efx, 2574 unsigned int priority_mask, 2575 u32 filter_id, bool by_index) 2576{ 2577 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 2578 struct efx_ef10_filter_table *table = efx->filter_state; 2579 MCDI_DECLARE_BUF(inbuf, 2580 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 2581 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 2582 struct efx_filter_spec *spec; 2583 DEFINE_WAIT(wait); 2584 int rc; 2585 2586 /* Find the software table entry and mark it busy. Don't 2587 * remove it yet; any attempt to update while we're waiting 2588 * for the firmware must find the busy entry. 2589 */ 2590 for (;;) { 2591 spin_lock_bh(&efx->filter_lock); 2592 if (!(table->entry[filter_idx].spec & 2593 EFX_EF10_FILTER_FLAG_BUSY)) 2594 break; 2595 prepare_to_wait(&table->waitq, &wait, TASK_UNINTERRUPTIBLE); 2596 spin_unlock_bh(&efx->filter_lock); 2597 schedule(); 2598 } 2599 2600 spec = efx_ef10_filter_entry_spec(table, filter_idx); 2601 if (!spec || 2602 (!by_index && 2603 efx_ef10_filter_rx_match_pri(table, spec->match_flags) != 2604 filter_id / HUNT_FILTER_TBL_ROWS)) { 2605 rc = -ENOENT; 2606 goto out_unlock; 2607 } 2608 2609 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO && 2610 priority_mask == (1U << EFX_FILTER_PRI_AUTO)) { 2611 /* Just remove flags */ 2612 spec->flags &= ~EFX_FILTER_FLAG_RX_OVER_AUTO; 2613 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_AUTO_OLD; 2614 rc = 0; 2615 goto out_unlock; 2616 } 2617 2618 if (!(priority_mask & (1U << spec->priority))) { 2619 rc = -ENOENT; 2620 goto out_unlock; 2621 } 2622 2623 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 2624 spin_unlock_bh(&efx->filter_lock); 2625 2626 if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) { 2627 /* Reset to an automatic filter */ 2628 2629 struct efx_filter_spec new_spec = *spec; 2630 2631 new_spec.priority = EFX_FILTER_PRI_AUTO; 2632 new_spec.flags = (EFX_FILTER_FLAG_RX | 2633 EFX_FILTER_FLAG_RX_RSS); 2634 new_spec.dmaq_id = 0; 2635 new_spec.rss_context = EFX_FILTER_RSS_CONTEXT_DEFAULT; 2636 rc = efx_ef10_filter_push(efx, &new_spec, 2637 &table->entry[filter_idx].handle, 2638 true); 2639 2640 spin_lock_bh(&efx->filter_lock); 2641 if (rc == 0) 2642 *spec = new_spec; 2643 } else { 2644 /* Really remove the filter */ 2645 2646 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2647 efx_ef10_filter_is_exclusive(spec) ? 2648 MC_CMD_FILTER_OP_IN_OP_REMOVE : 2649 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 2650 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 2651 table->entry[filter_idx].handle); 2652 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, 2653 inbuf, sizeof(inbuf), NULL, 0, NULL); 2654 2655 spin_lock_bh(&efx->filter_lock); 2656 if (rc == 0) { 2657 kfree(spec); 2658 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 2659 } 2660 } 2661 2662 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 2663 wake_up_all(&table->waitq); 2664out_unlock: 2665 spin_unlock_bh(&efx->filter_lock); 2666 finish_wait(&table->waitq, &wait); 2667 return rc; 2668} 2669 2670static int efx_ef10_filter_remove_safe(struct efx_nic *efx, 2671 enum efx_filter_priority priority, 2672 u32 filter_id) 2673{ 2674 return efx_ef10_filter_remove_internal(efx, 1U << priority, 2675 filter_id, false); 2676} 2677 2678static int efx_ef10_filter_get_safe(struct efx_nic *efx, 2679 enum efx_filter_priority priority, 2680 u32 filter_id, struct efx_filter_spec *spec) 2681{ 2682 unsigned int filter_idx = filter_id % HUNT_FILTER_TBL_ROWS; 2683 struct efx_ef10_filter_table *table = efx->filter_state; 2684 const struct efx_filter_spec *saved_spec; 2685 int rc; 2686 2687 spin_lock_bh(&efx->filter_lock); 2688 saved_spec = efx_ef10_filter_entry_spec(table, filter_idx); 2689 if (saved_spec && saved_spec->priority == priority && 2690 efx_ef10_filter_rx_match_pri(table, saved_spec->match_flags) == 2691 filter_id / HUNT_FILTER_TBL_ROWS) { 2692 *spec = *saved_spec; 2693 rc = 0; 2694 } else { 2695 rc = -ENOENT; 2696 } 2697 spin_unlock_bh(&efx->filter_lock); 2698 return rc; 2699} 2700 2701static int efx_ef10_filter_clear_rx(struct efx_nic *efx, 2702 enum efx_filter_priority priority) 2703{ 2704 unsigned int priority_mask; 2705 unsigned int i; 2706 int rc; 2707 2708 priority_mask = (((1U << (priority + 1)) - 1) & 2709 ~(1U << EFX_FILTER_PRI_AUTO)); 2710 2711 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 2712 rc = efx_ef10_filter_remove_internal(efx, priority_mask, 2713 i, true); 2714 if (rc && rc != -ENOENT) 2715 return rc; 2716 } 2717 2718 return 0; 2719} 2720 2721static u32 efx_ef10_filter_count_rx_used(struct efx_nic *efx, 2722 enum efx_filter_priority priority) 2723{ 2724 struct efx_ef10_filter_table *table = efx->filter_state; 2725 unsigned int filter_idx; 2726 s32 count = 0; 2727 2728 spin_lock_bh(&efx->filter_lock); 2729 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 2730 if (table->entry[filter_idx].spec && 2731 efx_ef10_filter_entry_spec(table, filter_idx)->priority == 2732 priority) 2733 ++count; 2734 } 2735 spin_unlock_bh(&efx->filter_lock); 2736 return count; 2737} 2738 2739static u32 efx_ef10_filter_get_rx_id_limit(struct efx_nic *efx) 2740{ 2741 struct efx_ef10_filter_table *table = efx->filter_state; 2742 2743 return table->rx_match_count * HUNT_FILTER_TBL_ROWS; 2744} 2745 2746static s32 efx_ef10_filter_get_rx_ids(struct efx_nic *efx, 2747 enum efx_filter_priority priority, 2748 u32 *buf, u32 size) 2749{ 2750 struct efx_ef10_filter_table *table = efx->filter_state; 2751 struct efx_filter_spec *spec; 2752 unsigned int filter_idx; 2753 s32 count = 0; 2754 2755 spin_lock_bh(&efx->filter_lock); 2756 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 2757 spec = efx_ef10_filter_entry_spec(table, filter_idx); 2758 if (spec && spec->priority == priority) { 2759 if (count == size) { 2760 count = -EMSGSIZE; 2761 break; 2762 } 2763 buf[count++] = (efx_ef10_filter_rx_match_pri( 2764 table, spec->match_flags) * 2765 HUNT_FILTER_TBL_ROWS + 2766 filter_idx); 2767 } 2768 } 2769 spin_unlock_bh(&efx->filter_lock); 2770 return count; 2771} 2772 2773#ifdef CONFIG_RFS_ACCEL 2774 2775static efx_mcdi_async_completer efx_ef10_filter_rfs_insert_complete; 2776 2777static s32 efx_ef10_filter_rfs_insert(struct efx_nic *efx, 2778 struct efx_filter_spec *spec) 2779{ 2780 struct efx_ef10_filter_table *table = efx->filter_state; 2781 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 2782 struct efx_filter_spec *saved_spec; 2783 unsigned int hash, i, depth = 1; 2784 bool replacing = false; 2785 int ins_index = -1; 2786 u64 cookie; 2787 s32 rc; 2788 2789 /* Must be an RX filter without RSS and not for a multicast 2790 * destination address (RFS only works for connected sockets). 2791 * These restrictions allow us to pass only a tiny amount of 2792 * data through to the completion function. 2793 */ 2794 EFX_WARN_ON_PARANOID(spec->flags != 2795 (EFX_FILTER_FLAG_RX | EFX_FILTER_FLAG_RX_SCATTER)); 2796 EFX_WARN_ON_PARANOID(spec->priority != EFX_FILTER_PRI_HINT); 2797 EFX_WARN_ON_PARANOID(efx_filter_is_mc_recipient(spec)); 2798 2799 hash = efx_ef10_filter_hash(spec); 2800 2801 spin_lock_bh(&efx->filter_lock); 2802 2803 /* Find any existing filter with the same match tuple or else 2804 * a free slot to insert at. If an existing filter is busy, 2805 * we have to give up. 2806 */ 2807 for (;;) { 2808 i = (hash + depth) & (HUNT_FILTER_TBL_ROWS - 1); 2809 saved_spec = efx_ef10_filter_entry_spec(table, i); 2810 2811 if (!saved_spec) { 2812 if (ins_index < 0) 2813 ins_index = i; 2814 } else if (efx_ef10_filter_equal(spec, saved_spec)) { 2815 if (table->entry[i].spec & EFX_EF10_FILTER_FLAG_BUSY) { 2816 rc = -EBUSY; 2817 goto fail_unlock; 2818 } 2819 if (spec->priority < saved_spec->priority) { 2820 rc = -EPERM; 2821 goto fail_unlock; 2822 } 2823 ins_index = i; 2824 break; 2825 } 2826 2827 /* Once we reach the maximum search depth, use the 2828 * first suitable slot or return -EBUSY if there was 2829 * none 2830 */ 2831 if (depth == EFX_EF10_FILTER_SEARCH_LIMIT) { 2832 if (ins_index < 0) { 2833 rc = -EBUSY; 2834 goto fail_unlock; 2835 } 2836 break; 2837 } 2838 2839 ++depth; 2840 } 2841 2842 /* Create a software table entry if necessary, and mark it 2843 * busy. We might yet fail to insert, but any attempt to 2844 * insert a conflicting filter while we're waiting for the 2845 * firmware must find the busy entry. 2846 */ 2847 saved_spec = efx_ef10_filter_entry_spec(table, ins_index); 2848 if (saved_spec) { 2849 replacing = true; 2850 } else { 2851 saved_spec = kmalloc(sizeof(*spec), GFP_ATOMIC); 2852 if (!saved_spec) { 2853 rc = -ENOMEM; 2854 goto fail_unlock; 2855 } 2856 *saved_spec = *spec; 2857 } 2858 efx_ef10_filter_set_entry(table, ins_index, saved_spec, 2859 EFX_EF10_FILTER_FLAG_BUSY); 2860 2861 spin_unlock_bh(&efx->filter_lock); 2862 2863 /* Pack up the variables needed on completion */ 2864 cookie = replacing << 31 | ins_index << 16 | spec->dmaq_id; 2865 2866 efx_ef10_filter_push_prep(efx, spec, inbuf, 2867 table->entry[ins_index].handle, replacing); 2868 efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 2869 MC_CMD_FILTER_OP_OUT_LEN, 2870 efx_ef10_filter_rfs_insert_complete, cookie); 2871 2872 return ins_index; 2873 2874fail_unlock: 2875 spin_unlock_bh(&efx->filter_lock); 2876 return rc; 2877} 2878 2879static void 2880efx_ef10_filter_rfs_insert_complete(struct efx_nic *efx, unsigned long cookie, 2881 int rc, efx_dword_t *outbuf, 2882 size_t outlen_actual) 2883{ 2884 struct efx_ef10_filter_table *table = efx->filter_state; 2885 unsigned int ins_index, dmaq_id; 2886 struct efx_filter_spec *spec; 2887 bool replacing; 2888 2889 /* Unpack the cookie */ 2890 replacing = cookie >> 31; 2891 ins_index = (cookie >> 16) & (HUNT_FILTER_TBL_ROWS - 1); 2892 dmaq_id = cookie & 0xffff; 2893 2894 spin_lock_bh(&efx->filter_lock); 2895 spec = efx_ef10_filter_entry_spec(table, ins_index); 2896 if (rc == 0) { 2897 table->entry[ins_index].handle = 2898 MCDI_QWORD(outbuf, FILTER_OP_OUT_HANDLE); 2899 if (replacing) 2900 spec->dmaq_id = dmaq_id; 2901 } else if (!replacing) { 2902 kfree(spec); 2903 spec = NULL; 2904 } 2905 efx_ef10_filter_set_entry(table, ins_index, spec, 0); 2906 spin_unlock_bh(&efx->filter_lock); 2907 2908 wake_up_all(&table->waitq); 2909} 2910 2911static void 2912efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 2913 unsigned long filter_idx, 2914 int rc, efx_dword_t *outbuf, 2915 size_t outlen_actual); 2916 2917static bool efx_ef10_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id, 2918 unsigned int filter_idx) 2919{ 2920 struct efx_ef10_filter_table *table = efx->filter_state; 2921 struct efx_filter_spec *spec = 2922 efx_ef10_filter_entry_spec(table, filter_idx); 2923 MCDI_DECLARE_BUF(inbuf, 2924 MC_CMD_FILTER_OP_IN_HANDLE_OFST + 2925 MC_CMD_FILTER_OP_IN_HANDLE_LEN); 2926 2927 if (!spec || 2928 (table->entry[filter_idx].spec & EFX_EF10_FILTER_FLAG_BUSY) || 2929 spec->priority != EFX_FILTER_PRI_HINT || 2930 !rps_may_expire_flow(efx->net_dev, spec->dmaq_id, 2931 flow_id, filter_idx)) 2932 return false; 2933 2934 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 2935 MC_CMD_FILTER_OP_IN_OP_REMOVE); 2936 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 2937 table->entry[filter_idx].handle); 2938 if (efx_mcdi_rpc_async(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 0, 2939 efx_ef10_filter_rfs_expire_complete, filter_idx)) 2940 return false; 2941 2942 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 2943 return true; 2944} 2945 2946static void 2947efx_ef10_filter_rfs_expire_complete(struct efx_nic *efx, 2948 unsigned long filter_idx, 2949 int rc, efx_dword_t *outbuf, 2950 size_t outlen_actual) 2951{ 2952 struct efx_ef10_filter_table *table = efx->filter_state; 2953 struct efx_filter_spec *spec = 2954 efx_ef10_filter_entry_spec(table, filter_idx); 2955 2956 spin_lock_bh(&efx->filter_lock); 2957 if (rc == 0) { 2958 kfree(spec); 2959 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 2960 } 2961 table->entry[filter_idx].spec &= ~EFX_EF10_FILTER_FLAG_BUSY; 2962 wake_up_all(&table->waitq); 2963 spin_unlock_bh(&efx->filter_lock); 2964} 2965 2966#endif /* CONFIG_RFS_ACCEL */ 2967 2968static int efx_ef10_filter_match_flags_from_mcdi(u32 mcdi_flags) 2969{ 2970 int match_flags = 0; 2971 2972#define MAP_FLAG(gen_flag, mcdi_field) { \ 2973 u32 old_mcdi_flags = mcdi_flags; \ 2974 mcdi_flags &= ~(1 << MC_CMD_FILTER_OP_IN_MATCH_ ## \ 2975 mcdi_field ## _LBN); \ 2976 if (mcdi_flags != old_mcdi_flags) \ 2977 match_flags |= EFX_FILTER_MATCH_ ## gen_flag; \ 2978 } 2979 MAP_FLAG(LOC_MAC_IG, UNKNOWN_UCAST_DST); 2980 MAP_FLAG(LOC_MAC_IG, UNKNOWN_MCAST_DST); 2981 MAP_FLAG(REM_HOST, SRC_IP); 2982 MAP_FLAG(LOC_HOST, DST_IP); 2983 MAP_FLAG(REM_MAC, SRC_MAC); 2984 MAP_FLAG(REM_PORT, SRC_PORT); 2985 MAP_FLAG(LOC_MAC, DST_MAC); 2986 MAP_FLAG(LOC_PORT, DST_PORT); 2987 MAP_FLAG(ETHER_TYPE, ETHER_TYPE); 2988 MAP_FLAG(INNER_VID, INNER_VLAN); 2989 MAP_FLAG(OUTER_VID, OUTER_VLAN); 2990 MAP_FLAG(IP_PROTO, IP_PROTO); 2991#undef MAP_FLAG 2992 2993 /* Did we map them all? */ 2994 if (mcdi_flags) 2995 return -EINVAL; 2996 2997 return match_flags; 2998} 2999 3000static int efx_ef10_filter_table_probe(struct efx_nic *efx) 3001{ 3002 MCDI_DECLARE_BUF(inbuf, MC_CMD_GET_PARSER_DISP_INFO_IN_LEN); 3003 MCDI_DECLARE_BUF(outbuf, MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX); 3004 unsigned int pd_match_pri, pd_match_count; 3005 struct efx_ef10_filter_table *table; 3006 size_t outlen; 3007 int rc; 3008 3009 table = kzalloc(sizeof(*table), GFP_KERNEL); 3010 if (!table) 3011 return -ENOMEM; 3012 3013 /* Find out which RX filter types are supported, and their priorities */ 3014 MCDI_SET_DWORD(inbuf, GET_PARSER_DISP_INFO_IN_OP, 3015 MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES); 3016 rc = efx_mcdi_rpc(efx, MC_CMD_GET_PARSER_DISP_INFO, 3017 inbuf, sizeof(inbuf), outbuf, sizeof(outbuf), 3018 &outlen); 3019 if (rc) 3020 goto fail; 3021 pd_match_count = MCDI_VAR_ARRAY_LEN( 3022 outlen, GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES); 3023 table->rx_match_count = 0; 3024 3025 for (pd_match_pri = 0; pd_match_pri < pd_match_count; pd_match_pri++) { 3026 u32 mcdi_flags = 3027 MCDI_ARRAY_DWORD( 3028 outbuf, 3029 GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES, 3030 pd_match_pri); 3031 rc = efx_ef10_filter_match_flags_from_mcdi(mcdi_flags); 3032 if (rc < 0) { 3033 netif_dbg(efx, probe, efx->net_dev, 3034 "%s: fw flags %#x pri %u not supported in driver\n", 3035 __func__, mcdi_flags, pd_match_pri); 3036 } else { 3037 netif_dbg(efx, probe, efx->net_dev, 3038 "%s: fw flags %#x pri %u supported as driver flags %#x pri %u\n", 3039 __func__, mcdi_flags, pd_match_pri, 3040 rc, table->rx_match_count); 3041 table->rx_match_flags[table->rx_match_count++] = rc; 3042 } 3043 } 3044 3045 table->entry = vzalloc(HUNT_FILTER_TBL_ROWS * sizeof(*table->entry)); 3046 if (!table->entry) { 3047 rc = -ENOMEM; 3048 goto fail; 3049 } 3050 3051 efx->filter_state = table; 3052 init_waitqueue_head(&table->waitq); 3053 return 0; 3054 3055fail: 3056 kfree(table); 3057 return rc; 3058} 3059 3060static void efx_ef10_filter_table_restore(struct efx_nic *efx) 3061{ 3062 struct efx_ef10_filter_table *table = efx->filter_state; 3063 struct efx_ef10_nic_data *nic_data = efx->nic_data; 3064 struct efx_filter_spec *spec; 3065 unsigned int filter_idx; 3066 bool failed = false; 3067 int rc; 3068 3069 if (!nic_data->must_restore_filters) 3070 return; 3071 3072 spin_lock_bh(&efx->filter_lock); 3073 3074 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3075 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3076 if (!spec) 3077 continue; 3078 3079 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_BUSY; 3080 spin_unlock_bh(&efx->filter_lock); 3081 3082 rc = efx_ef10_filter_push(efx, spec, 3083 &table->entry[filter_idx].handle, 3084 false); 3085 if (rc) 3086 failed = true; 3087 3088 spin_lock_bh(&efx->filter_lock); 3089 if (rc) { 3090 kfree(spec); 3091 efx_ef10_filter_set_entry(table, filter_idx, NULL, 0); 3092 } else { 3093 table->entry[filter_idx].spec &= 3094 ~EFX_EF10_FILTER_FLAG_BUSY; 3095 } 3096 } 3097 3098 spin_unlock_bh(&efx->filter_lock); 3099 3100 if (failed) 3101 netif_err(efx, hw, efx->net_dev, 3102 "unable to restore all filters\n"); 3103 else 3104 nic_data->must_restore_filters = false; 3105} 3106 3107static void efx_ef10_filter_table_remove(struct efx_nic *efx) 3108{ 3109 struct efx_ef10_filter_table *table = efx->filter_state; 3110 MCDI_DECLARE_BUF(inbuf, MC_CMD_FILTER_OP_IN_LEN); 3111 struct efx_filter_spec *spec; 3112 unsigned int filter_idx; 3113 int rc; 3114 3115 for (filter_idx = 0; filter_idx < HUNT_FILTER_TBL_ROWS; filter_idx++) { 3116 spec = efx_ef10_filter_entry_spec(table, filter_idx); 3117 if (!spec) 3118 continue; 3119 3120 MCDI_SET_DWORD(inbuf, FILTER_OP_IN_OP, 3121 efx_ef10_filter_is_exclusive(spec) ? 3122 MC_CMD_FILTER_OP_IN_OP_REMOVE : 3123 MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE); 3124 MCDI_SET_QWORD(inbuf, FILTER_OP_IN_HANDLE, 3125 table->entry[filter_idx].handle); 3126 rc = efx_mcdi_rpc(efx, MC_CMD_FILTER_OP, inbuf, sizeof(inbuf), 3127 NULL, 0, NULL); 3128 if (rc) 3129 netdev_WARN(efx->net_dev, 3130 "filter_idx=%#x handle=%#llx\n", 3131 filter_idx, 3132 table->entry[filter_idx].handle); 3133 kfree(spec); 3134 } 3135 3136 vfree(table->entry); 3137 kfree(table); 3138} 3139 3140static void efx_ef10_filter_sync_rx_mode(struct efx_nic *efx) 3141{ 3142 struct efx_ef10_filter_table *table = efx->filter_state; 3143 struct net_device *net_dev = efx->net_dev; 3144 struct efx_filter_spec spec; 3145 bool remove_failed = false; 3146 struct netdev_hw_addr *uc; 3147 struct netdev_hw_addr *mc; 3148 unsigned int filter_idx; 3149 int i, n, rc; 3150 3151 if (!efx_dev_registered(efx)) 3152 return; 3153 3154 /* Mark old filters that may need to be removed */ 3155 spin_lock_bh(&efx->filter_lock); 3156 n = table->dev_uc_count < 0 ? 1 : table->dev_uc_count; 3157 for (i = 0; i < n; i++) { 3158 filter_idx = table->dev_uc_list[i].id % HUNT_FILTER_TBL_ROWS; 3159 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 3160 } 3161 n = table->dev_mc_count < 0 ? 1 : table->dev_mc_count; 3162 for (i = 0; i < n; i++) { 3163 filter_idx = table->dev_mc_list[i].id % HUNT_FILTER_TBL_ROWS; 3164 table->entry[filter_idx].spec |= EFX_EF10_FILTER_FLAG_AUTO_OLD; 3165 } 3166 spin_unlock_bh(&efx->filter_lock); 3167 3168 /* Copy/convert the address lists; add the primary station 3169 * address and broadcast address 3170 */ 3171 netif_addr_lock_bh(net_dev); 3172 if (net_dev->flags & IFF_PROMISC || 3173 netdev_uc_count(net_dev) >= EFX_EF10_FILTER_DEV_UC_MAX) { 3174 table->dev_uc_count = -1; 3175 } else { 3176 table->dev_uc_count = 1 + netdev_uc_count(net_dev); 3177 ether_addr_copy(table->dev_uc_list[0].addr, net_dev->dev_addr); 3178 i = 1; 3179 netdev_for_each_uc_addr(uc, net_dev) { 3180 ether_addr_copy(table->dev_uc_list[i].addr, uc->addr); 3181 i++; 3182 } 3183 } 3184 if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI) || 3185 netdev_mc_count(net_dev) >= EFX_EF10_FILTER_DEV_MC_MAX) { 3186 table->dev_mc_count = -1; 3187 } else { 3188 table->dev_mc_count = 1 + netdev_mc_count(net_dev); 3189 eth_broadcast_addr(table->dev_mc_list[0].addr); 3190 i = 1; 3191 netdev_for_each_mc_addr(mc, net_dev) { 3192 ether_addr_copy(table->dev_mc_list[i].addr, mc->addr); 3193 i++; 3194 } 3195 } 3196 netif_addr_unlock_bh(net_dev); 3197 3198 /* Insert/renew unicast filters */ 3199 if (table->dev_uc_count >= 0) { 3200 for (i = 0; i < table->dev_uc_count; i++) { 3201 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3202 EFX_FILTER_FLAG_RX_RSS, 3203 0); 3204 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3205 table->dev_uc_list[i].addr); 3206 rc = efx_ef10_filter_insert(efx, &spec, true); 3207 if (rc < 0) { 3208 /* Fall back to unicast-promisc */ 3209 while (i--) 3210 efx_ef10_filter_remove_safe( 3211 efx, EFX_FILTER_PRI_AUTO, 3212 table->dev_uc_list[i].id); 3213 table->dev_uc_count = -1; 3214 break; 3215 } 3216 table->dev_uc_list[i].id = rc; 3217 } 3218 } 3219 if (table->dev_uc_count < 0) { 3220 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3221 EFX_FILTER_FLAG_RX_RSS, 3222 0); 3223 efx_filter_set_uc_def(&spec); 3224 rc = efx_ef10_filter_insert(efx, &spec, true); 3225 if (rc < 0) { 3226 WARN_ON(1); 3227 table->dev_uc_count = 0; 3228 } else { 3229 table->dev_uc_list[0].id = rc; 3230 } 3231 } 3232 3233 /* Insert/renew multicast filters */ 3234 if (table->dev_mc_count >= 0) { 3235 for (i = 0; i < table->dev_mc_count; i++) { 3236 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3237 EFX_FILTER_FLAG_RX_RSS, 3238 0); 3239 efx_filter_set_eth_local(&spec, EFX_FILTER_VID_UNSPEC, 3240 table->dev_mc_list[i].addr); 3241 rc = efx_ef10_filter_insert(efx, &spec, true); 3242 if (rc < 0) { 3243 /* Fall back to multicast-promisc */ 3244 while (i--) 3245 efx_ef10_filter_remove_safe( 3246 efx, EFX_FILTER_PRI_AUTO, 3247 table->dev_mc_list[i].id); 3248 table->dev_mc_count = -1; 3249 break; 3250 } 3251 table->dev_mc_list[i].id = rc; 3252 } 3253 } 3254 if (table->dev_mc_count < 0) { 3255 efx_filter_init_rx(&spec, EFX_FILTER_PRI_AUTO, 3256 EFX_FILTER_FLAG_RX_RSS, 3257 0); 3258 efx_filter_set_mc_def(&spec); 3259 rc = efx_ef10_filter_insert(efx, &spec, true); 3260 if (rc < 0) { 3261 WARN_ON(1); 3262 table->dev_mc_count = 0; 3263 } else { 3264 table->dev_mc_list[0].id = rc; 3265 } 3266 } 3267 3268 /* Remove filters that weren't renewed. Since nothing else 3269 * changes the AUTO_OLD flag or removes these filters, we 3270 * don't need to hold the filter_lock while scanning for 3271 * these filters. 3272 */ 3273 for (i = 0; i < HUNT_FILTER_TBL_ROWS; i++) { 3274 if (ACCESS_ONCE(table->entry[i].spec) & 3275 EFX_EF10_FILTER_FLAG_AUTO_OLD) { 3276 if (efx_ef10_filter_remove_internal( 3277 efx, 1U << EFX_FILTER_PRI_AUTO, 3278 i, true) < 0) 3279 remove_failed = true; 3280 } 3281 } 3282 WARN_ON(remove_failed); 3283} 3284 3285static int efx_ef10_mac_reconfigure(struct efx_nic *efx) 3286{ 3287 efx_ef10_filter_sync_rx_mode(efx); 3288 3289 return efx_mcdi_set_mac(efx); 3290} 3291 3292static int efx_ef10_start_bist(struct efx_nic *efx, u32 bist_type) 3293{ 3294 MCDI_DECLARE_BUF(inbuf, MC_CMD_START_BIST_IN_LEN); 3295 3296 MCDI_SET_DWORD(inbuf, START_BIST_IN_TYPE, bist_type); 3297 return efx_mcdi_rpc(efx, MC_CMD_START_BIST, inbuf, sizeof(inbuf), 3298 NULL, 0, NULL); 3299} 3300 3301/* MC BISTs follow a different poll mechanism to phy BISTs. 3302 * The BIST is done in the poll handler on the MC, and the MCDI command 3303 * will block until the BIST is done. 3304 */ 3305static int efx_ef10_poll_bist(struct efx_nic *efx) 3306{ 3307 int rc; 3308 MCDI_DECLARE_BUF(outbuf, MC_CMD_POLL_BIST_OUT_LEN); 3309 size_t outlen; 3310 u32 result; 3311 3312 rc = efx_mcdi_rpc(efx, MC_CMD_POLL_BIST, NULL, 0, 3313 outbuf, sizeof(outbuf), &outlen); 3314 if (rc != 0) 3315 return rc; 3316 3317 if (outlen < MC_CMD_POLL_BIST_OUT_LEN) 3318 return -EIO; 3319 3320 result = MCDI_DWORD(outbuf, POLL_BIST_OUT_RESULT); 3321 switch (result) { 3322 case MC_CMD_POLL_BIST_PASSED: 3323 netif_dbg(efx, hw, efx->net_dev, "BIST passed.\n"); 3324 return 0; 3325 case MC_CMD_POLL_BIST_TIMEOUT: 3326 netif_err(efx, hw, efx->net_dev, "BIST timed out\n"); 3327 return -EIO; 3328 case MC_CMD_POLL_BIST_FAILED: 3329 netif_err(efx, hw, efx->net_dev, "BIST failed.\n"); 3330 return -EIO; 3331 default: 3332 netif_err(efx, hw, efx->net_dev, 3333 "BIST returned unknown result %u", result); 3334 return -EIO; 3335 } 3336} 3337 3338static int efx_ef10_run_bist(struct efx_nic *efx, u32 bist_type) 3339{ 3340 int rc; 3341 3342 netif_dbg(efx, drv, efx->net_dev, "starting BIST type %u\n", bist_type); 3343 3344 rc = efx_ef10_start_bist(efx, bist_type); 3345 if (rc != 0) 3346 return rc; 3347 3348 return efx_ef10_poll_bist(efx); 3349} 3350 3351static int 3352efx_ef10_test_chip(struct efx_nic *efx, struct efx_self_tests *tests) 3353{ 3354 int rc, rc2; 3355 3356 efx_reset_down(efx, RESET_TYPE_WORLD); 3357 3358 rc = efx_mcdi_rpc(efx, MC_CMD_ENABLE_OFFLINE_BIST, 3359 NULL, 0, NULL, 0, NULL); 3360 if (rc != 0) 3361 goto out; 3362 3363 tests->memory = efx_ef10_run_bist(efx, MC_CMD_MC_MEM_BIST) ? -1 : 1; 3364 tests->registers = efx_ef10_run_bist(efx, MC_CMD_REG_BIST) ? -1 : 1; 3365 3366 rc = efx_mcdi_reset(efx, RESET_TYPE_WORLD); 3367 3368out: 3369 rc2 = efx_reset_up(efx, RESET_TYPE_WORLD, rc == 0); 3370 return rc ? rc : rc2; 3371} 3372 3373#ifdef CONFIG_SFC_MTD 3374 3375struct efx_ef10_nvram_type_info { 3376 u16 type, type_mask; 3377 u8 port; 3378 const char *name; 3379}; 3380 3381static const struct efx_ef10_nvram_type_info efx_ef10_nvram_types[] = { 3382 { NVRAM_PARTITION_TYPE_MC_FIRMWARE, 0, 0, "sfc_mcfw" }, 3383 { NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 0, 0, "sfc_mcfw_backup" }, 3384 { NVRAM_PARTITION_TYPE_EXPANSION_ROM, 0, 0, "sfc_exp_rom" }, 3385 { NVRAM_PARTITION_TYPE_STATIC_CONFIG, 0, 0, "sfc_static_cfg" }, 3386 { NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 0, 0, "sfc_dynamic_cfg" }, 3387 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 0, 0, "sfc_exp_rom_cfg" }, 3388 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 0, 1, "sfc_exp_rom_cfg" }, 3389 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 0, 2, "sfc_exp_rom_cfg" }, 3390 { NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 0, 3, "sfc_exp_rom_cfg" }, 3391 { NVRAM_PARTITION_TYPE_LICENSE, 0, 0, "sfc_license" }, 3392 { NVRAM_PARTITION_TYPE_PHY_MIN, 0xff, 0, "sfc_phy_fw" }, 3393}; 3394 3395static int efx_ef10_mtd_probe_partition(struct efx_nic *efx, 3396 struct efx_mcdi_mtd_partition *part, 3397 unsigned int type) 3398{ 3399 MCDI_DECLARE_BUF(inbuf, MC_CMD_NVRAM_METADATA_IN_LEN); 3400 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_METADATA_OUT_LENMAX); 3401 const struct efx_ef10_nvram_type_info *info; 3402 size_t size, erase_size, outlen; 3403 bool protected; 3404 int rc; 3405 3406 for (info = efx_ef10_nvram_types; ; info++) { 3407 if (info == 3408 efx_ef10_nvram_types + ARRAY_SIZE(efx_ef10_nvram_types)) 3409 return -ENODEV; 3410 if ((type & ~info->type_mask) == info->type) 3411 break; 3412 } 3413 if (info->port != efx_port_num(efx)) 3414 return -ENODEV; 3415 3416 rc = efx_mcdi_nvram_info(efx, type, &size, &erase_size, &protected); 3417 if (rc) 3418 return rc; 3419 if (protected) 3420 return -ENODEV; /* hide it */ 3421 3422 part->nvram_type = type; 3423 3424 MCDI_SET_DWORD(inbuf, NVRAM_METADATA_IN_TYPE, type); 3425 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_METADATA, inbuf, sizeof(inbuf), 3426 outbuf, sizeof(outbuf), &outlen); 3427 if (rc) 3428 return rc; 3429 if (outlen < MC_CMD_NVRAM_METADATA_OUT_LENMIN) 3430 return -EIO; 3431 if (MCDI_DWORD(outbuf, NVRAM_METADATA_OUT_FLAGS) & 3432 (1 << MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN)) 3433 part->fw_subtype = MCDI_DWORD(outbuf, 3434 NVRAM_METADATA_OUT_SUBTYPE); 3435 3436 part->common.dev_type_name = "EF10 NVRAM manager"; 3437 part->common.type_name = info->name; 3438 3439 part->common.mtd.type = MTD_NORFLASH; 3440 part->common.mtd.flags = MTD_CAP_NORFLASH; 3441 part->common.mtd.size = size; 3442 part->common.mtd.erasesize = erase_size; 3443 3444 return 0; 3445} 3446 3447static int efx_ef10_mtd_probe(struct efx_nic *efx) 3448{ 3449 MCDI_DECLARE_BUF(outbuf, MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX); 3450 struct efx_mcdi_mtd_partition *parts; 3451 size_t outlen, n_parts_total, i, n_parts; 3452 unsigned int type; 3453 int rc; 3454 3455 ASSERT_RTNL(); 3456 3457 BUILD_BUG_ON(MC_CMD_NVRAM_PARTITIONS_IN_LEN != 0); 3458 rc = efx_mcdi_rpc(efx, MC_CMD_NVRAM_PARTITIONS, NULL, 0, 3459 outbuf, sizeof(outbuf), &outlen); 3460 if (rc) 3461 return rc; 3462 if (outlen < MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN) 3463 return -EIO; 3464 3465 n_parts_total = MCDI_DWORD(outbuf, NVRAM_PARTITIONS_OUT_NUM_PARTITIONS); 3466 if (n_parts_total > 3467 MCDI_VAR_ARRAY_LEN(outlen, NVRAM_PARTITIONS_OUT_TYPE_ID)) 3468 return -EIO; 3469 3470 parts = kcalloc(n_parts_total, sizeof(*parts), GFP_KERNEL); 3471 if (!parts) 3472 return -ENOMEM; 3473 3474 n_parts = 0; 3475 for (i = 0; i < n_parts_total; i++) { 3476 type = MCDI_ARRAY_DWORD(outbuf, NVRAM_PARTITIONS_OUT_TYPE_ID, 3477 i); 3478 rc = efx_ef10_mtd_probe_partition(efx, &parts[n_parts], type); 3479 if (rc == 0) 3480 n_parts++; 3481 else if (rc != -ENODEV) 3482 goto fail; 3483 } 3484 3485 rc = efx_mtd_add(efx, &parts[0].common, n_parts, sizeof(*parts)); 3486fail: 3487 if (rc) 3488 kfree(parts); 3489 return rc; 3490} 3491 3492#endif /* CONFIG_SFC_MTD */ 3493 3494static void efx_ef10_ptp_write_host_time(struct efx_nic *efx, u32 host_time) 3495{ 3496 _efx_writed(efx, cpu_to_le32(host_time), ER_DZ_MC_DB_LWRD); 3497} 3498 3499static int efx_ef10_rx_enable_timestamping(struct efx_channel *channel, 3500 bool temp) 3501{ 3502 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN); 3503 int rc; 3504 3505 if (channel->sync_events_state == SYNC_EVENTS_REQUESTED || 3506 channel->sync_events_state == SYNC_EVENTS_VALID || 3507 (temp && channel->sync_events_state == SYNC_EVENTS_DISABLED)) 3508 return 0; 3509 channel->sync_events_state = SYNC_EVENTS_REQUESTED; 3510 3511 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE); 3512 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3513 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE, 3514 channel->channel); 3515 3516 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3517 inbuf, sizeof(inbuf), NULL, 0, NULL); 3518 3519 if (rc != 0) 3520 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3521 SYNC_EVENTS_DISABLED; 3522 3523 return rc; 3524} 3525 3526static int efx_ef10_rx_disable_timestamping(struct efx_channel *channel, 3527 bool temp) 3528{ 3529 MCDI_DECLARE_BUF(inbuf, MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN); 3530 int rc; 3531 3532 if (channel->sync_events_state == SYNC_EVENTS_DISABLED || 3533 (temp && channel->sync_events_state == SYNC_EVENTS_QUIESCENT)) 3534 return 0; 3535 if (channel->sync_events_state == SYNC_EVENTS_QUIESCENT) { 3536 channel->sync_events_state = SYNC_EVENTS_DISABLED; 3537 return 0; 3538 } 3539 channel->sync_events_state = temp ? SYNC_EVENTS_QUIESCENT : 3540 SYNC_EVENTS_DISABLED; 3541 3542 MCDI_SET_DWORD(inbuf, PTP_IN_OP, MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE); 3543 MCDI_SET_DWORD(inbuf, PTP_IN_PERIPH_ID, 0); 3544 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL, 3545 MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE); 3546 MCDI_SET_DWORD(inbuf, PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE, 3547 channel->channel); 3548 3549 rc = efx_mcdi_rpc(channel->efx, MC_CMD_PTP, 3550 inbuf, sizeof(inbuf), NULL, 0, NULL); 3551 3552 return rc; 3553} 3554 3555static int efx_ef10_ptp_set_ts_sync_events(struct efx_nic *efx, bool en, 3556 bool temp) 3557{ 3558 int (*set)(struct efx_channel *channel, bool temp); 3559 struct efx_channel *channel; 3560 3561 set = en ? 3562 efx_ef10_rx_enable_timestamping : 3563 efx_ef10_rx_disable_timestamping; 3564 3565 efx_for_each_channel(channel, efx) { 3566 int rc = set(channel, temp); 3567 if (en && rc != 0) { 3568 efx_ef10_ptp_set_ts_sync_events(efx, false, temp); 3569 return rc; 3570 } 3571 } 3572 3573 return 0; 3574} 3575 3576static int efx_ef10_ptp_set_ts_config(struct efx_nic *efx, 3577 struct hwtstamp_config *init) 3578{ 3579 int rc; 3580 3581 switch (init->rx_filter) { 3582 case HWTSTAMP_FILTER_NONE: 3583 efx_ef10_ptp_set_ts_sync_events(efx, false, false); 3584 /* if TX timestamping is still requested then leave PTP on */ 3585 return efx_ptp_change_mode(efx, 3586 init->tx_type != HWTSTAMP_TX_OFF, 0); 3587 case HWTSTAMP_FILTER_ALL: 3588 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 3589 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 3590 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 3591 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 3592 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 3593 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 3594 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 3595 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 3596 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 3597 case HWTSTAMP_FILTER_PTP_V2_EVENT: 3598 case HWTSTAMP_FILTER_PTP_V2_SYNC: 3599 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 3600 init->rx_filter = HWTSTAMP_FILTER_ALL; 3601 rc = efx_ptp_change_mode(efx, true, 0); 3602 if (!rc) 3603 rc = efx_ef10_ptp_set_ts_sync_events(efx, true, false); 3604 if (rc) 3605 efx_ptp_change_mode(efx, false, 0); 3606 return rc; 3607 default: 3608 return -ERANGE; 3609 } 3610} 3611 3612const struct efx_nic_type efx_hunt_a0_nic_type = { 3613 .mem_map_size = efx_ef10_mem_map_size, 3614 .probe = efx_ef10_probe, 3615 .remove = efx_ef10_remove, 3616 .dimension_resources = efx_ef10_dimension_resources, 3617 .init = efx_ef10_init_nic, 3618 .fini = efx_port_dummy_op_void, 3619 .map_reset_reason = efx_mcdi_map_reset_reason, 3620 .map_reset_flags = efx_ef10_map_reset_flags, 3621 .reset = efx_ef10_reset, 3622 .probe_port = efx_mcdi_port_probe, 3623 .remove_port = efx_mcdi_port_remove, 3624 .fini_dmaq = efx_ef10_fini_dmaq, 3625 .prepare_flr = efx_ef10_prepare_flr, 3626 .finish_flr = efx_port_dummy_op_void, 3627 .describe_stats = efx_ef10_describe_stats, 3628 .update_stats = efx_ef10_update_stats, 3629 .start_stats = efx_mcdi_mac_start_stats, 3630 .pull_stats = efx_mcdi_mac_pull_stats, 3631 .stop_stats = efx_mcdi_mac_stop_stats, 3632 .set_id_led = efx_mcdi_set_id_led, 3633 .push_irq_moderation = efx_ef10_push_irq_moderation, 3634 .reconfigure_mac = efx_ef10_mac_reconfigure, 3635 .check_mac_fault = efx_mcdi_mac_check_fault, 3636 .reconfigure_port = efx_mcdi_port_reconfigure, 3637 .get_wol = efx_ef10_get_wol, 3638 .set_wol = efx_ef10_set_wol, 3639 .resume_wol = efx_port_dummy_op_void, 3640 .test_chip = efx_ef10_test_chip, 3641 .test_nvram = efx_mcdi_nvram_test_all, 3642 .mcdi_request = efx_ef10_mcdi_request, 3643 .mcdi_poll_response = efx_ef10_mcdi_poll_response, 3644 .mcdi_read_response = efx_ef10_mcdi_read_response, 3645 .mcdi_poll_reboot = efx_ef10_mcdi_poll_reboot, 3646 .irq_enable_master = efx_port_dummy_op_void, 3647 .irq_test_generate = efx_ef10_irq_test_generate, 3648 .irq_disable_non_ev = efx_port_dummy_op_void, 3649 .irq_handle_msi = efx_ef10_msi_interrupt, 3650 .irq_handle_legacy = efx_ef10_legacy_interrupt, 3651 .tx_probe = efx_ef10_tx_probe, 3652 .tx_init = efx_ef10_tx_init, 3653 .tx_remove = efx_ef10_tx_remove, 3654 .tx_write = efx_ef10_tx_write, 3655 .rx_push_rss_config = efx_ef10_rx_push_rss_config, 3656 .rx_probe = efx_ef10_rx_probe, 3657 .rx_init = efx_ef10_rx_init, 3658 .rx_remove = efx_ef10_rx_remove, 3659 .rx_write = efx_ef10_rx_write, 3660 .rx_defer_refill = efx_ef10_rx_defer_refill, 3661 .ev_probe = efx_ef10_ev_probe, 3662 .ev_init = efx_ef10_ev_init, 3663 .ev_fini = efx_ef10_ev_fini, 3664 .ev_remove = efx_ef10_ev_remove, 3665 .ev_process = efx_ef10_ev_process, 3666 .ev_read_ack = efx_ef10_ev_read_ack, 3667 .ev_test_generate = efx_ef10_ev_test_generate, 3668 .filter_table_probe = efx_ef10_filter_table_probe, 3669 .filter_table_restore = efx_ef10_filter_table_restore, 3670 .filter_table_remove = efx_ef10_filter_table_remove, 3671 .filter_update_rx_scatter = efx_ef10_filter_update_rx_scatter, 3672 .filter_insert = efx_ef10_filter_insert, 3673 .filter_remove_safe = efx_ef10_filter_remove_safe, 3674 .filter_get_safe = efx_ef10_filter_get_safe, 3675 .filter_clear_rx = efx_ef10_filter_clear_rx, 3676 .filter_count_rx_used = efx_ef10_filter_count_rx_used, 3677 .filter_get_rx_id_limit = efx_ef10_filter_get_rx_id_limit, 3678 .filter_get_rx_ids = efx_ef10_filter_get_rx_ids, 3679#ifdef CONFIG_RFS_ACCEL 3680 .filter_rfs_insert = efx_ef10_filter_rfs_insert, 3681 .filter_rfs_expire_one = efx_ef10_filter_rfs_expire_one, 3682#endif 3683#ifdef CONFIG_SFC_MTD 3684 .mtd_probe = efx_ef10_mtd_probe, 3685 .mtd_rename = efx_mcdi_mtd_rename, 3686 .mtd_read = efx_mcdi_mtd_read, 3687 .mtd_erase = efx_mcdi_mtd_erase, 3688 .mtd_write = efx_mcdi_mtd_write, 3689 .mtd_sync = efx_mcdi_mtd_sync, 3690#endif 3691 .ptp_write_host_time = efx_ef10_ptp_write_host_time, 3692 .ptp_set_ts_sync_events = efx_ef10_ptp_set_ts_sync_events, 3693 .ptp_set_ts_config = efx_ef10_ptp_set_ts_config, 3694 .sriov_init = efx_ef10_sriov_init, 3695 .sriov_fini = efx_ef10_sriov_fini, 3696 .sriov_mac_address_changed = efx_ef10_sriov_mac_address_changed, 3697 .sriov_wanted = efx_ef10_sriov_wanted, 3698 .sriov_reset = efx_ef10_sriov_reset, 3699 3700 .revision = EFX_REV_HUNT_A0, 3701 .max_dma_mask = DMA_BIT_MASK(ESF_DZ_TX_KER_BUF_ADDR_WIDTH), 3702 .rx_prefix_size = ES_DZ_RX_PREFIX_SIZE, 3703 .rx_hash_offset = ES_DZ_RX_PREFIX_HASH_OFST, 3704 .rx_ts_offset = ES_DZ_RX_PREFIX_TSTAMP_OFST, 3705 .can_rx_scatter = true, 3706 .always_rx_scatter = true, 3707 .max_interrupt_mode = EFX_INT_MODE_MSIX, 3708 .timer_period_max = 1 << ERF_DD_EVQ_IND_TIMER_VAL_WIDTH, 3709 .offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 3710 NETIF_F_RXHASH | NETIF_F_NTUPLE), 3711 .mcdi_max_ver = 2, 3712 .max_rx_ip_filters = HUNT_FILTER_TBL_ROWS, 3713 .hwtstamp_filters = 1 << HWTSTAMP_FILTER_NONE | 3714 1 << HWTSTAMP_FILTER_ALL, 3715}; 3716