1/******************************************************************************* 2 3 Intel 82599 Virtual Function driver 4 Copyright(c) 1999 - 2015 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#ifndef _IXGBEVF_H_ 28#define _IXGBEVF_H_ 29 30#include <linux/types.h> 31#include <linux/bitops.h> 32#include <linux/timer.h> 33#include <linux/io.h> 34#include <linux/netdevice.h> 35#include <linux/if_vlan.h> 36#include <linux/u64_stats_sync.h> 37 38#include "vf.h" 39 40#ifdef CONFIG_NET_RX_BUSY_POLL 41#include <net/busy_poll.h> 42#define BP_EXTENDED_STATS 43#endif 44 45#define IXGBE_MAX_TXD_PWR 14 46#define IXGBE_MAX_DATA_PER_TXD BIT(IXGBE_MAX_TXD_PWR) 47 48/* Tx Descriptors needed, worst case */ 49#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IXGBE_MAX_DATA_PER_TXD) 50#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 51 52/* wrapper around a pointer to a socket buffer, 53 * so a DMA handle can be stored along with the buffer 54 */ 55struct ixgbevf_tx_buffer { 56 union ixgbe_adv_tx_desc *next_to_watch; 57 unsigned long time_stamp; 58 struct sk_buff *skb; 59 unsigned int bytecount; 60 unsigned short gso_segs; 61 __be16 protocol; 62 DEFINE_DMA_UNMAP_ADDR(dma); 63 DEFINE_DMA_UNMAP_LEN(len); 64 u32 tx_flags; 65}; 66 67struct ixgbevf_rx_buffer { 68 dma_addr_t dma; 69 struct page *page; 70 unsigned int page_offset; 71}; 72 73struct ixgbevf_stats { 74 u64 packets; 75 u64 bytes; 76#ifdef BP_EXTENDED_STATS 77 u64 yields; 78 u64 misses; 79 u64 cleaned; 80#endif 81}; 82 83struct ixgbevf_tx_queue_stats { 84 u64 restart_queue; 85 u64 tx_busy; 86 u64 tx_done_old; 87}; 88 89struct ixgbevf_rx_queue_stats { 90 u64 alloc_rx_page_failed; 91 u64 alloc_rx_buff_failed; 92 u64 csum_err; 93}; 94 95enum ixgbevf_ring_state_t { 96 __IXGBEVF_TX_DETECT_HANG, 97 __IXGBEVF_HANG_CHECK_ARMED, 98}; 99 100#define check_for_tx_hang(ring) \ 101 test_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 102#define set_check_for_tx_hang(ring) \ 103 set_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 104#define clear_check_for_tx_hang(ring) \ 105 clear_bit(__IXGBEVF_TX_DETECT_HANG, &(ring)->state) 106 107struct ixgbevf_ring { 108 struct ixgbevf_ring *next; 109 struct net_device *netdev; 110 struct device *dev; 111 void *desc; /* descriptor ring memory */ 112 dma_addr_t dma; /* phys. address of descriptor ring */ 113 unsigned int size; /* length in bytes */ 114 u16 count; /* amount of descriptors */ 115 u16 next_to_use; 116 u16 next_to_clean; 117 u16 next_to_alloc; 118 119 union { 120 struct ixgbevf_tx_buffer *tx_buffer_info; 121 struct ixgbevf_rx_buffer *rx_buffer_info; 122 }; 123 unsigned long state; 124 struct ixgbevf_stats stats; 125 struct u64_stats_sync syncp; 126 union { 127 struct ixgbevf_tx_queue_stats tx_stats; 128 struct ixgbevf_rx_queue_stats rx_stats; 129 }; 130 131 u64 hw_csum_rx_error; 132 u8 __iomem *tail; 133 struct sk_buff *skb; 134 135 /* holds the special value that gets the hardware register offset 136 * associated with this ring, which is different for DCB and RSS modes 137 */ 138 u16 reg_idx; 139 int queue_index; /* needed for multiqueue queue management */ 140}; 141 142/* How many Rx Buffers do we bundle into one write to the hardware ? */ 143#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 144 145#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES 146#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES 147#define IXGBEVF_MAX_RSS_QUEUES 2 148#define IXGBEVF_82599_RETA_SIZE 128 149#define IXGBEVF_RSS_HASH_KEY_SIZE 40 150 151#define IXGBEVF_DEFAULT_TXD 1024 152#define IXGBEVF_DEFAULT_RXD 512 153#define IXGBEVF_MAX_TXD 4096 154#define IXGBEVF_MIN_TXD 64 155#define IXGBEVF_MAX_RXD 4096 156#define IXGBEVF_MIN_RXD 64 157 158/* Supported Rx Buffer Sizes */ 159#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */ 160#define IXGBEVF_RXBUFFER_2048 2048 161 162#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256 163#define IXGBEVF_RX_BUFSZ IXGBEVF_RXBUFFER_2048 164 165#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 166 167#define IXGBE_TX_FLAGS_CSUM (u32)(1) 168#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1) 169#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2) 170#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3) 171#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000 172#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000 173#define IXGBE_TX_FLAGS_VLAN_SHIFT 16 174 175struct ixgbevf_ring_container { 176 struct ixgbevf_ring *ring; /* pointer to linked list of rings */ 177 unsigned int total_bytes; /* total bytes processed this int */ 178 unsigned int total_packets; /* total packets processed this int */ 179 u8 count; /* total number of rings in vector */ 180 u8 itr; /* current ITR setting for ring */ 181}; 182 183/* iterator for handling rings in ring container */ 184#define ixgbevf_for_each_ring(pos, head) \ 185 for (pos = (head).ring; pos != NULL; pos = pos->next) 186 187/* MAX_MSIX_Q_VECTORS of these are allocated, 188 * but we only use one per queue-specific vector. 189 */ 190struct ixgbevf_q_vector { 191 struct ixgbevf_adapter *adapter; 192 /* index of q_vector within array, also used for finding the bit in 193 * EICR and friends that represents the vector for this ring 194 */ 195 u16 v_idx; 196 u16 itr; /* Interrupt throttle rate written to EITR */ 197 struct napi_struct napi; 198 struct ixgbevf_ring_container rx, tx; 199 char name[IFNAMSIZ + 9]; 200#ifdef CONFIG_NET_RX_BUSY_POLL 201 unsigned int state; 202#define IXGBEVF_QV_STATE_IDLE 0 203#define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */ 204#define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */ 205#define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */ 206#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL) 207#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED) 208#define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */ 209#define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */ 210#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | \ 211 IXGBEVF_QV_STATE_POLL_YIELD) 212#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | \ 213 IXGBEVF_QV_STATE_POLL_YIELD) 214 spinlock_t lock; 215#endif /* CONFIG_NET_RX_BUSY_POLL */ 216}; 217 218#ifdef CONFIG_NET_RX_BUSY_POLL 219static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector) 220{ 221 spin_lock_init(&q_vector->lock); 222 q_vector->state = IXGBEVF_QV_STATE_IDLE; 223} 224 225/* called from the device poll routine to get ownership of a q_vector */ 226static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector) 227{ 228 int rc = true; 229 230 spin_lock_bh(&q_vector->lock); 231 if (q_vector->state & IXGBEVF_QV_LOCKED) { 232 WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI); 233 q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD; 234 rc = false; 235#ifdef BP_EXTENDED_STATS 236 q_vector->tx.ring->stats.yields++; 237#endif 238 } else { 239 /* we don't care if someone yielded */ 240 q_vector->state = IXGBEVF_QV_STATE_NAPI; 241 } 242 spin_unlock_bh(&q_vector->lock); 243 return rc; 244} 245 246/* returns true is someone tried to get the qv while napi had it */ 247static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector) 248{ 249 int rc = false; 250 251 spin_lock_bh(&q_vector->lock); 252 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL | 253 IXGBEVF_QV_STATE_NAPI_YIELD)); 254 255 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD) 256 rc = true; 257 /* reset state to idle, unless QV is disabled */ 258 q_vector->state &= IXGBEVF_QV_STATE_DISABLED; 259 spin_unlock_bh(&q_vector->lock); 260 return rc; 261} 262 263/* called from ixgbevf_low_latency_poll() */ 264static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector) 265{ 266 int rc = true; 267 268 spin_lock_bh(&q_vector->lock); 269 if ((q_vector->state & IXGBEVF_QV_LOCKED)) { 270 q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD; 271 rc = false; 272#ifdef BP_EXTENDED_STATS 273 q_vector->rx.ring->stats.yields++; 274#endif 275 } else { 276 /* preserve yield marks */ 277 q_vector->state |= IXGBEVF_QV_STATE_POLL; 278 } 279 spin_unlock_bh(&q_vector->lock); 280 return rc; 281} 282 283/* returns true if someone tried to get the qv while it was locked */ 284static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector) 285{ 286 int rc = false; 287 288 spin_lock_bh(&q_vector->lock); 289 WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI)); 290 291 if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD) 292 rc = true; 293 /* reset state to idle, unless QV is disabled */ 294 q_vector->state &= IXGBEVF_QV_STATE_DISABLED; 295 spin_unlock_bh(&q_vector->lock); 296 return rc; 297} 298 299/* true if a socket is polling, even if it did not get the lock */ 300static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector) 301{ 302 WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED)); 303 return q_vector->state & IXGBEVF_QV_USER_PEND; 304} 305 306/* false if QV is currently owned */ 307static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector) 308{ 309 int rc = true; 310 311 spin_lock_bh(&q_vector->lock); 312 if (q_vector->state & IXGBEVF_QV_OWNED) 313 rc = false; 314 q_vector->state |= IXGBEVF_QV_STATE_DISABLED; 315 spin_unlock_bh(&q_vector->lock); 316 return rc; 317} 318 319#endif /* CONFIG_NET_RX_BUSY_POLL */ 320 321/* microsecond values for various ITR rates shifted by 2 to fit itr register 322 * with the first 3 bits reserved 0 323 */ 324#define IXGBE_MIN_RSC_ITR 24 325#define IXGBE_100K_ITR 40 326#define IXGBE_20K_ITR 200 327#define IXGBE_10K_ITR 400 328#define IXGBE_8K_ITR 500 329 330/* Helper macros to switch between ints/sec and what the register uses. 331 * And yes, it's the same math going both ways. The lowest value 332 * supported by all of the ixgbe hardware is 8. 333 */ 334#define EITR_INTS_PER_SEC_TO_REG(_eitr) \ 335 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8) 336#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG 337 338/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */ 339static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc, 340 const u32 stat_err_bits) 341{ 342 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 343} 344 345static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring) 346{ 347 u16 ntc = ring->next_to_clean; 348 u16 ntu = ring->next_to_use; 349 350 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 351} 352 353static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value) 354{ 355 writel(value, ring->tail); 356} 357 358#define IXGBEVF_RX_DESC(R, i) \ 359 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i])) 360#define IXGBEVF_TX_DESC(R, i) \ 361 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i])) 362#define IXGBEVF_TX_CTXTDESC(R, i) \ 363 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i])) 364 365#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */ 366 367#define OTHER_VECTOR 1 368#define NON_Q_VECTORS (OTHER_VECTOR) 369 370#define MAX_MSIX_Q_VECTORS 2 371 372#define MIN_MSIX_Q_VECTORS 1 373#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS) 374 375/* board specific private data structure */ 376struct ixgbevf_adapter { 377 /* this field must be first, see ixgbevf_process_skb_fields */ 378 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 379 380 struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS]; 381 382 /* Interrupt Throttle Rate */ 383 u16 rx_itr_setting; 384 u16 tx_itr_setting; 385 386 /* interrupt masks */ 387 u32 eims_enable_mask; 388 u32 eims_other; 389 390 /* TX */ 391 int num_tx_queues; 392 struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */ 393 u64 restart_queue; 394 u32 tx_timeout_count; 395 396 /* RX */ 397 int num_rx_queues; 398 struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */ 399 u64 hw_csum_rx_error; 400 u64 hw_rx_no_dma_resources; 401 int num_msix_vectors; 402 u32 alloc_rx_page_failed; 403 u32 alloc_rx_buff_failed; 404 405 /* Some features need tri-state capability, 406 * thus the additional *_CAPABLE flags. 407 */ 408 u32 flags; 409#define IXGBEVF_FLAG_RESET_REQUESTED (u32)(1) 410#define IXGBEVF_FLAG_QUEUE_RESET_REQUESTED (u32)(1 << 2) 411 412 struct msix_entry *msix_entries; 413 414 /* OS defined structs */ 415 struct net_device *netdev; 416 struct pci_dev *pdev; 417 418 /* structs defined in ixgbe_vf.h */ 419 struct ixgbe_hw hw; 420 u16 msg_enable; 421 /* Interrupt Throttle Rate */ 422 u32 eitr_param; 423 424 struct ixgbevf_hw_stats stats; 425 426 unsigned long state; 427 u64 tx_busy; 428 unsigned int tx_ring_count; 429 unsigned int rx_ring_count; 430 431#ifdef BP_EXTENDED_STATS 432 u64 bp_rx_yields; 433 u64 bp_rx_cleaned; 434 u64 bp_rx_missed; 435 436 u64 bp_tx_yields; 437 u64 bp_tx_cleaned; 438 u64 bp_tx_missed; 439#endif 440 441 u8 __iomem *io_addr; /* Mainly for iounmap use */ 442 u32 link_speed; 443 bool link_up; 444 445 struct timer_list service_timer; 446 struct work_struct service_task; 447 448 spinlock_t mbx_lock; 449 unsigned long last_reset; 450}; 451 452enum ixbgevf_state_t { 453 __IXGBEVF_TESTING, 454 __IXGBEVF_RESETTING, 455 __IXGBEVF_DOWN, 456 __IXGBEVF_DISABLED, 457 __IXGBEVF_REMOVING, 458 __IXGBEVF_SERVICE_SCHED, 459 __IXGBEVF_SERVICE_INITED, 460}; 461 462enum ixgbevf_boards { 463 board_82599_vf, 464 board_X540_vf, 465 board_X550_vf, 466 board_X550EM_x_vf, 467}; 468 469extern const struct ixgbevf_info ixgbevf_82599_vf_info; 470extern const struct ixgbevf_info ixgbevf_X540_vf_info; 471extern const struct ixgbevf_info ixgbevf_X550_vf_info; 472extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info; 473extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops; 474 475/* needed by ethtool.c */ 476extern const char ixgbevf_driver_name[]; 477extern const char ixgbevf_driver_version[]; 478 479void ixgbevf_up(struct ixgbevf_adapter *adapter); 480void ixgbevf_down(struct ixgbevf_adapter *adapter); 481void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter); 482void ixgbevf_reset(struct ixgbevf_adapter *adapter); 483void ixgbevf_set_ethtool_ops(struct net_device *netdev); 484int ixgbevf_setup_rx_resources(struct ixgbevf_ring *); 485int ixgbevf_setup_tx_resources(struct ixgbevf_ring *); 486void ixgbevf_free_rx_resources(struct ixgbevf_ring *); 487void ixgbevf_free_tx_resources(struct ixgbevf_ring *); 488void ixgbevf_update_stats(struct ixgbevf_adapter *adapter); 489int ethtool_ioctl(struct ifreq *ifr); 490 491extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector); 492 493void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter); 494void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter); 495 496#ifdef DEBUG 497char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw); 498#define hw_dbg(hw, format, arg...) \ 499 printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg) 500#else 501#define hw_dbg(hw, format, arg...) do {} while (0) 502#endif 503 504#endif /* _IXGBEVF_H_ */ 505