1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_TXRX_H_ 28#define _I40E_TXRX_H_ 29 30/* Interrupt Throttling and Rate Limiting Goodies */ 31 32#define I40E_MAX_ITR 0x0FF0 /* reg uses 2 usec resolution */ 33#define I40E_MIN_ITR 0x0001 /* reg uses 2 usec resolution */ 34#define I40E_ITR_100K 0x0005 35#define I40E_ITR_20K 0x0019 36#define I40E_ITR_8K 0x003E 37#define I40E_ITR_4K 0x007A 38#define I40E_ITR_RX_DEF I40E_ITR_8K 39#define I40E_ITR_TX_DEF I40E_ITR_4K 40#define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 41#define I40E_MIN_INT_RATE 250 /* ~= 1000000 / (I40E_MAX_ITR * 2) */ 42#define I40E_MAX_INT_RATE 500000 /* == 1000000 / (I40E_MIN_ITR * 2) */ 43#define I40E_DEFAULT_IRQ_WORK 256 44#define ITR_TO_REG(setting) ((setting & ~I40E_ITR_DYNAMIC) >> 1) 45#define ITR_IS_DYNAMIC(setting) (!!(setting & I40E_ITR_DYNAMIC)) 46#define ITR_REG_TO_USEC(itr_reg) (itr_reg << 1) 47 48#define I40E_QUEUE_END_OF_LIST 0x7FF 49 50/* this enum matches hardware bits and is meant to be used by DYN_CTLN 51 * registers and QINT registers or more generally anywhere in the manual 52 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 53 * register but instead is a special value meaning "don't update" ITR0/1/2. 54 */ 55enum i40e_dyn_idx_t { 56 I40E_IDX_ITR0 = 0, 57 I40E_IDX_ITR1 = 1, 58 I40E_IDX_ITR2 = 2, 59 I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 60}; 61 62/* these are indexes into ITRN registers */ 63#define I40E_RX_ITR I40E_IDX_ITR0 64#define I40E_TX_ITR I40E_IDX_ITR1 65#define I40E_PE_ITR I40E_IDX_ITR2 66 67/* Supported RSS offloads */ 68#define I40E_DEFAULT_RSS_HENA ( \ 69 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ 70 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ 71 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ 72 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ 73 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV4) | \ 74 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ 75 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ 76 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ 77 ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ 78 ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6) | \ 79 ((u64)1 << I40E_FILTER_PCTYPE_L2_PAYLOAD)) 80 81/* Supported Rx Buffer Sizes */ 82#define I40E_RXBUFFER_512 512 /* Used for packet split */ 83#define I40E_RXBUFFER_2048 2048 84#define I40E_RXBUFFER_3072 3072 /* For FCoE MTU of 2158 */ 85#define I40E_RXBUFFER_4096 4096 86#define I40E_RXBUFFER_8192 8192 87#define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ 88 89/* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we 90 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, 91 * this adds up to 512 bytes of extra data meaning the smallest allocation 92 * we could have is 1K. 93 * i.e. RXBUFFER_512 --> size-1024 slab 94 */ 95#define I40E_RX_HDR_SIZE I40E_RXBUFFER_512 96 97/* How many Rx Buffers do we bundle into one write to the hardware ? */ 98#define I40E_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 99#define I40E_RX_INCREMENT(r, i) \ 100 do { \ 101 (i)++; \ 102 if ((i) == (r)->count) \ 103 i = 0; \ 104 r->next_to_clean = i; \ 105 } while (0) 106 107#define I40E_RX_NEXT_DESC(r, i, n) \ 108 do { \ 109 (i)++; \ 110 if ((i) == (r)->count) \ 111 i = 0; \ 112 (n) = I40E_RX_DESC((r), (i)); \ 113 } while (0) 114 115#define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \ 116 do { \ 117 I40E_RX_NEXT_DESC((r), (i), (n)); \ 118 prefetch((n)); \ 119 } while (0) 120 121#define i40e_rx_desc i40e_32byte_rx_desc 122 123#define I40E_MAX_BUFFER_TXD 8 124#define I40E_MIN_TX_LEN 17 125#define I40E_MAX_DATA_PER_TXD 8192 126 127/* Tx Descriptors needed, worst case */ 128#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD) 129#define DESC_NEEDED (MAX_SKB_FRAGS + 4) 130#define I40E_MIN_DESC_PENDING 4 131 132#define I40E_TX_FLAGS_CSUM (u32)(1) 133#define I40E_TX_FLAGS_HW_VLAN (u32)(1 << 1) 134#define I40E_TX_FLAGS_SW_VLAN (u32)(1 << 2) 135#define I40E_TX_FLAGS_TSO (u32)(1 << 3) 136#define I40E_TX_FLAGS_IPV4 (u32)(1 << 4) 137#define I40E_TX_FLAGS_IPV6 (u32)(1 << 5) 138#define I40E_TX_FLAGS_FCCRC (u32)(1 << 6) 139#define I40E_TX_FLAGS_FSO (u32)(1 << 7) 140#define I40E_TX_FLAGS_FD_SB (u32)(1 << 9) 141#define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 142#define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 143#define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 144#define I40E_TX_FLAGS_VLAN_SHIFT 16 145 146struct i40e_tx_buffer { 147 struct i40e_tx_desc *next_to_watch; 148 unsigned long time_stamp; 149 union { 150 struct sk_buff *skb; 151 void *raw_buf; 152 }; 153 unsigned int bytecount; 154 unsigned short gso_segs; 155 DEFINE_DMA_UNMAP_ADDR(dma); 156 DEFINE_DMA_UNMAP_LEN(len); 157 u32 tx_flags; 158}; 159 160struct i40e_rx_buffer { 161 struct sk_buff *skb; 162 void *hdr_buf; 163 dma_addr_t dma; 164 struct page *page; 165 dma_addr_t page_dma; 166 unsigned int page_offset; 167}; 168 169struct i40e_queue_stats { 170 u64 packets; 171 u64 bytes; 172}; 173 174struct i40e_tx_queue_stats { 175 u64 restart_queue; 176 u64 tx_busy; 177 u64 tx_done_old; 178}; 179 180struct i40e_rx_queue_stats { 181 u64 non_eop_descs; 182 u64 alloc_page_failed; 183 u64 alloc_buff_failed; 184}; 185 186enum i40e_ring_state_t { 187 __I40E_TX_FDIR_INIT_DONE, 188 __I40E_TX_XPS_INIT_DONE, 189 __I40E_TX_DETECT_HANG, 190 __I40E_HANG_CHECK_ARMED, 191 __I40E_RX_PS_ENABLED, 192 __I40E_RX_16BYTE_DESC_ENABLED, 193}; 194 195#define ring_is_ps_enabled(ring) \ 196 test_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 197#define set_ring_ps_enabled(ring) \ 198 set_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 199#define clear_ring_ps_enabled(ring) \ 200 clear_bit(__I40E_RX_PS_ENABLED, &(ring)->state) 201#define check_for_tx_hang(ring) \ 202 test_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 203#define set_check_for_tx_hang(ring) \ 204 set_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 205#define clear_check_for_tx_hang(ring) \ 206 clear_bit(__I40E_TX_DETECT_HANG, &(ring)->state) 207#define ring_is_16byte_desc_enabled(ring) \ 208 test_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 209#define set_ring_16byte_desc_enabled(ring) \ 210 set_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 211#define clear_ring_16byte_desc_enabled(ring) \ 212 clear_bit(__I40E_RX_16BYTE_DESC_ENABLED, &(ring)->state) 213 214/* struct that defines a descriptor ring, associated with a VSI */ 215struct i40e_ring { 216 struct i40e_ring *next; /* pointer to next ring in q_vector */ 217 void *desc; /* Descriptor ring memory */ 218 struct device *dev; /* Used for DMA mapping */ 219 struct net_device *netdev; /* netdev ring maps to */ 220 union { 221 struct i40e_tx_buffer *tx_bi; 222 struct i40e_rx_buffer *rx_bi; 223 }; 224 unsigned long state; 225 u16 queue_index; /* Queue number of ring */ 226 u8 dcb_tc; /* Traffic class of ring */ 227 u8 __iomem *tail; 228 229 u16 count; /* Number of descriptors */ 230 u16 reg_idx; /* HW register index of the ring */ 231 u16 rx_hdr_len; 232 u16 rx_buf_len; 233 u8 dtype; 234#define I40E_RX_DTYPE_NO_SPLIT 0 235#define I40E_RX_DTYPE_HEADER_SPLIT 1 236#define I40E_RX_DTYPE_SPLIT_ALWAYS 2 237 u8 hsplit; 238#define I40E_RX_SPLIT_L2 0x1 239#define I40E_RX_SPLIT_IP 0x2 240#define I40E_RX_SPLIT_TCP_UDP 0x4 241#define I40E_RX_SPLIT_SCTP 0x8 242 243 /* used in interrupt processing */ 244 u16 next_to_use; 245 u16 next_to_clean; 246 247 u8 atr_sample_rate; 248 u8 atr_count; 249 250 bool ring_active; /* is ring online or not */ 251 bool arm_wb; /* do something to arm write back */ 252 253 /* stats structs */ 254 struct i40e_queue_stats stats; 255 struct u64_stats_sync syncp; 256 union { 257 struct i40e_tx_queue_stats tx_stats; 258 struct i40e_rx_queue_stats rx_stats; 259 }; 260 261 unsigned int size; /* length of descriptor ring in bytes */ 262 dma_addr_t dma; /* physical address of ring */ 263 264 struct i40e_vsi *vsi; /* Backreference to associated VSI */ 265 struct i40e_q_vector *q_vector; /* Backreference to associated vector */ 266 267 struct rcu_head rcu; /* to avoid race on free */ 268} ____cacheline_internodealigned_in_smp; 269 270enum i40e_latency_range { 271 I40E_LOWEST_LATENCY = 0, 272 I40E_LOW_LATENCY = 1, 273 I40E_BULK_LATENCY = 2, 274}; 275 276struct i40e_ring_container { 277 /* array of pointers to rings */ 278 struct i40e_ring *ring; 279 unsigned int total_bytes; /* total bytes processed this int */ 280 unsigned int total_packets; /* total packets processed this int */ 281 u16 count; 282 enum i40e_latency_range latency_range; 283 u16 itr; 284}; 285 286/* iterator for handling rings in ring container */ 287#define i40e_for_each_ring(pos, head) \ 288 for (pos = (head).ring; pos != NULL; pos = pos->next) 289 290void i40evf_alloc_rx_buffers_ps(struct i40e_ring *rxr, u16 cleaned_count); 291void i40evf_alloc_rx_buffers_1buf(struct i40e_ring *rxr, u16 cleaned_count); 292void i40evf_alloc_rx_headers(struct i40e_ring *rxr); 293netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev); 294void i40evf_clean_tx_ring(struct i40e_ring *tx_ring); 295void i40evf_clean_rx_ring(struct i40e_ring *rx_ring); 296int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring); 297int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring); 298void i40evf_free_tx_resources(struct i40e_ring *tx_ring); 299void i40evf_free_rx_resources(struct i40e_ring *rx_ring); 300int i40evf_napi_poll(struct napi_struct *napi, int budget); 301#endif /* _I40E_TXRX_H_ */ 302