1/******************************************************************************* 2 * 3 * Intel Ethernet Controller XL710 Family Linux Driver 4 * Copyright(c) 2013 - 2014 Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program. If not, see <http://www.gnu.org/licenses/>. 17 * 18 * The full GNU General Public License is included in this distribution in 19 * the file called "COPYING". 20 * 21 * Contact Information: 22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 ******************************************************************************/ 26 27#ifndef _I40E_REGISTER_H_ 28#define _I40E_REGISTER_H_ 29 30#define I40E_GL_ARQBAH 0x000801C0 /* Reset: EMPR */ 31#define I40E_GL_ARQBAH_ARQBAH_SHIFT 0 32#define I40E_GL_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAH_ARQBAH_SHIFT) 33#define I40E_GL_ARQBAL 0x000800C0 /* Reset: EMPR */ 34#define I40E_GL_ARQBAL_ARQBAL_SHIFT 0 35#define I40E_GL_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ARQBAL_ARQBAL_SHIFT) 36#define I40E_GL_ARQH 0x000803C0 /* Reset: EMPR */ 37#define I40E_GL_ARQH_ARQH_SHIFT 0 38#define I40E_GL_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_GL_ARQH_ARQH_SHIFT) 39#define I40E_GL_ARQT 0x000804C0 /* Reset: EMPR */ 40#define I40E_GL_ARQT_ARQT_SHIFT 0 41#define I40E_GL_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_GL_ARQT_ARQT_SHIFT) 42#define I40E_GL_ATQBAH 0x00080140 /* Reset: EMPR */ 43#define I40E_GL_ATQBAH_ATQBAH_SHIFT 0 44#define I40E_GL_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAH_ATQBAH_SHIFT) 45#define I40E_GL_ATQBAL 0x00080040 /* Reset: EMPR */ 46#define I40E_GL_ATQBAL_ATQBAL_SHIFT 0 47#define I40E_GL_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_ATQBAL_ATQBAL_SHIFT) 48#define I40E_GL_ATQH 0x00080340 /* Reset: EMPR */ 49#define I40E_GL_ATQH_ATQH_SHIFT 0 50#define I40E_GL_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_GL_ATQH_ATQH_SHIFT) 51#define I40E_GL_ATQLEN 0x00080240 /* Reset: EMPR */ 52#define I40E_GL_ATQLEN_ATQLEN_SHIFT 0 53#define I40E_GL_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_GL_ATQLEN_ATQLEN_SHIFT) 54#define I40E_GL_ATQLEN_ATQVFE_SHIFT 28 55#define I40E_GL_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQVFE_SHIFT) 56#define I40E_GL_ATQLEN_ATQOVFL_SHIFT 29 57#define I40E_GL_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQOVFL_SHIFT) 58#define I40E_GL_ATQLEN_ATQCRIT_SHIFT 30 59#define I40E_GL_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQCRIT_SHIFT) 60#define I40E_GL_ATQLEN_ATQENABLE_SHIFT 31 61#define I40E_GL_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_GL_ATQLEN_ATQENABLE_SHIFT) 62#define I40E_GL_ATQT 0x00080440 /* Reset: EMPR */ 63#define I40E_GL_ATQT_ATQT_SHIFT 0 64#define I40E_GL_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_GL_ATQT_ATQT_SHIFT) 65#define I40E_PF_ARQBAH 0x00080180 /* Reset: EMPR */ 66#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0 67#define I40E_PF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAH_ARQBAH_SHIFT) 68#define I40E_PF_ARQBAL 0x00080080 /* Reset: EMPR */ 69#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0 70#define I40E_PF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ARQBAL_ARQBAL_SHIFT) 71#define I40E_PF_ARQH 0x00080380 /* Reset: EMPR */ 72#define I40E_PF_ARQH_ARQH_SHIFT 0 73#define I40E_PF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_PF_ARQH_ARQH_SHIFT) 74#define I40E_PF_ARQLEN 0x00080280 /* Reset: EMPR */ 75#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0 76#define I40E_PF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ARQLEN_ARQLEN_SHIFT) 77#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28 78#define I40E_PF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQVFE_SHIFT) 79#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29 80#define I40E_PF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQOVFL_SHIFT) 81#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30 82#define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT) 83#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31 84#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT) 85#define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */ 86#define I40E_PF_ARQT_ARQT_SHIFT 0 87#define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT) 88#define I40E_PF_ATQBAH 0x00080100 /* Reset: EMPR */ 89#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0 90#define I40E_PF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAH_ATQBAH_SHIFT) 91#define I40E_PF_ATQBAL 0x00080000 /* Reset: EMPR */ 92#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0 93#define I40E_PF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_ATQBAL_ATQBAL_SHIFT) 94#define I40E_PF_ATQH 0x00080300 /* Reset: EMPR */ 95#define I40E_PF_ATQH_ATQH_SHIFT 0 96#define I40E_PF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_PF_ATQH_ATQH_SHIFT) 97#define I40E_PF_ATQLEN 0x00080200 /* Reset: EMPR */ 98#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0 99#define I40E_PF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_PF_ATQLEN_ATQLEN_SHIFT) 100#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28 101#define I40E_PF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQVFE_SHIFT) 102#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29 103#define I40E_PF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQOVFL_SHIFT) 104#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30 105#define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT) 106#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31 107#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT) 108#define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */ 109#define I40E_PF_ATQT_ATQT_SHIFT 0 110#define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT) 111#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 112#define I40E_VF_ARQBAH_MAX_INDEX 127 113#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0 114#define I40E_VF_ARQBAH_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH_ARQBAH_SHIFT) 115#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 116#define I40E_VF_ARQBAL_MAX_INDEX 127 117#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0 118#define I40E_VF_ARQBAL_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL_ARQBAL_SHIFT) 119#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 120#define I40E_VF_ARQH_MAX_INDEX 127 121#define I40E_VF_ARQH_ARQH_SHIFT 0 122#define I40E_VF_ARQH_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH_ARQH_SHIFT) 123#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 124#define I40E_VF_ARQLEN_MAX_INDEX 127 125#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0 126#define I40E_VF_ARQLEN_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN_ARQLEN_SHIFT) 127#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28 128#define I40E_VF_ARQLEN_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQVFE_SHIFT) 129#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29 130#define I40E_VF_ARQLEN_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQOVFL_SHIFT) 131#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30 132#define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT) 133#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31 134#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT) 135#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 136#define I40E_VF_ARQT_MAX_INDEX 127 137#define I40E_VF_ARQT_ARQT_SHIFT 0 138#define I40E_VF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT_ARQT_SHIFT) 139#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 140#define I40E_VF_ATQBAH_MAX_INDEX 127 141#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0 142#define I40E_VF_ATQBAH_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH_ATQBAH_SHIFT) 143#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 144#define I40E_VF_ATQBAL_MAX_INDEX 127 145#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0 146#define I40E_VF_ATQBAL_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL_ATQBAL_SHIFT) 147#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 148#define I40E_VF_ATQH_MAX_INDEX 127 149#define I40E_VF_ATQH_ATQH_SHIFT 0 150#define I40E_VF_ATQH_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH_ATQH_SHIFT) 151#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 152#define I40E_VF_ATQLEN_MAX_INDEX 127 153#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0 154#define I40E_VF_ATQLEN_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN_ATQLEN_SHIFT) 155#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28 156#define I40E_VF_ATQLEN_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQVFE_SHIFT) 157#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29 158#define I40E_VF_ATQLEN_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQOVFL_SHIFT) 159#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30 160#define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT) 161#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31 162#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT) 163#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */ 164#define I40E_VF_ATQT_MAX_INDEX 127 165#define I40E_VF_ATQT_ATQT_SHIFT 0 166#define I40E_VF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT_ATQT_SHIFT) 167#define I40E_PRT_L2TAGSEN 0x001C0B20 /* Reset: CORER */ 168#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0 169#define I40E_PRT_L2TAGSEN_ENABLE_MASK I40E_MASK(0xFF, I40E_PRT_L2TAGSEN_ENABLE_SHIFT) 170#define I40E_PFCM_LAN_ERRDATA 0x0010C080 /* Reset: PFR */ 171#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0 172#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT) 173#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4 174#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT) 175#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8 176#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT) 177#define I40E_PFCM_LAN_ERRINFO 0x0010C000 /* Reset: PFR */ 178#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0 179#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT) 180#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4 181#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT) 182#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8 183#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT) 184#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16 185#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT) 186#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24 187#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT) 188#define I40E_PFCM_LANCTXCTL 0x0010C300 /* Reset: CORER */ 189#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0 190#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK I40E_MASK(0xFFF, I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT) 191#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12 192#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK I40E_MASK(0x7, I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT) 193#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15 194#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT) 195#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17 196#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK I40E_MASK(0x3, I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT) 197#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */ /* Reset: CORER */ 198#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3 199#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0 200#define I40E_PFCM_LANCTXDATA_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFCM_LANCTXDATA_DATA_SHIFT) 201#define I40E_PFCM_LANCTXSTAT 0x0010C380 /* Reset: CORER */ 202#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0 203#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT) 204#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1 205#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK I40E_MASK(0x1, I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT) 206#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 207#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127 208#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0 209#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT) 210#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4 211#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT) 212#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8 213#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT) 214#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 215#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127 216#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0 217#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT) 218#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4 219#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT) 220#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8 221#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT) 222#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16 223#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) 224#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 225#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) 226#define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */ 227#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 228#define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT) 229#define I40E_GLDCB_RUPTI 0x00122618 /* Reset: CORER */ 230#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0 231#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT) 232#define I40E_PRTDCB_FCCFG 0x001E4640 /* Reset: GLOBR */ 233#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3 234#define I40E_PRTDCB_FCCFG_TFCE_MASK I40E_MASK(0x3, I40E_PRTDCB_FCCFG_TFCE_SHIFT) 235#define I40E_PRTDCB_FCRTV 0x001E4600 /* Reset: GLOBR */ 236#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0 237#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT) 238#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: GLOBR */ 239#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3 240#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0 241#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT) 242#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16 243#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT) 244#define I40E_PRTDCB_GENC 0x00083000 /* Reset: CORER */ 245#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0 246#define I40E_PRTDCB_GENC_RESERVED_1_MASK I40E_MASK(0x3, I40E_PRTDCB_GENC_RESERVED_1_SHIFT) 247#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2 248#define I40E_PRTDCB_GENC_NUMTC_MASK I40E_MASK(0xF, I40E_PRTDCB_GENC_NUMTC_SHIFT) 249#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6 250#define I40E_PRTDCB_GENC_FCOEUP_MASK I40E_MASK(0x7, I40E_PRTDCB_GENC_FCOEUP_SHIFT) 251#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9 252#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK I40E_MASK(0x1, I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT) 253#define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16 254#define I40E_PRTDCB_GENC_PFCLDA_MASK I40E_MASK(0xFFFF, I40E_PRTDCB_GENC_PFCLDA_SHIFT) 255#define I40E_PRTDCB_GENS 0x00083020 /* Reset: CORER */ 256#define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0 257#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK I40E_MASK(0x7, I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT) 258#define I40E_PRTDCB_MFLCN 0x001E2400 /* Reset: GLOBR */ 259#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0 260#define I40E_PRTDCB_MFLCN_PMCF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_PMCF_SHIFT) 261#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1 262#define I40E_PRTDCB_MFLCN_DPF_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_DPF_SHIFT) 263#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2 264#define I40E_PRTDCB_MFLCN_RPFCM_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RPFCM_SHIFT) 265#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3 266#define I40E_PRTDCB_MFLCN_RFCE_MASK I40E_MASK(0x1, I40E_PRTDCB_MFLCN_RFCE_SHIFT) 267#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4 268#define I40E_PRTDCB_MFLCN_RPFCE_MASK I40E_MASK(0xFF, I40E_PRTDCB_MFLCN_RPFCE_SHIFT) 269#define I40E_PRTDCB_RETSC 0x001223E0 /* Reset: CORER */ 270#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0 271#define I40E_PRTDCB_RETSC_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_ETS_MODE_SHIFT) 272#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1 273#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT) 274#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2 275#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK I40E_MASK(0xF, I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT) 276#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8 277#define I40E_PRTDCB_RETSC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_RETSC_LLTC_SHIFT) 278#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 279#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7 280#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0 281#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK I40E_MASK(0x7F, I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) 282#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30 283#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) 284#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31 285#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) 286#define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */ 287#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0 288#define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT) 289#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8 290#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT) 291#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16 292#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT) 293#define I40E_PRTDCB_RUP 0x001C0B00 /* Reset: CORER */ 294#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0 295#define I40E_PRTDCB_RUP_NOVLANUP_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP_NOVLANUP_SHIFT) 296#define I40E_PRTDCB_RUP2TC 0x001C09A0 /* Reset: CORER */ 297#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0 298#define I40E_PRTDCB_RUP2TC_UP0TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP0TC_SHIFT) 299#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3 300#define I40E_PRTDCB_RUP2TC_UP1TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP1TC_SHIFT) 301#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6 302#define I40E_PRTDCB_RUP2TC_UP2TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP2TC_SHIFT) 303#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9 304#define I40E_PRTDCB_RUP2TC_UP3TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP3TC_SHIFT) 305#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12 306#define I40E_PRTDCB_RUP2TC_UP4TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP4TC_SHIFT) 307#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15 308#define I40E_PRTDCB_RUP2TC_UP5TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP5TC_SHIFT) 309#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18 310#define I40E_PRTDCB_RUP2TC_UP6TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP6TC_SHIFT) 311#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21 312#define I40E_PRTDCB_RUP2TC_UP7TC_MASK I40E_MASK(0x7, I40E_PRTDCB_RUP2TC_UP7TC_SHIFT) 313#define I40E_PRTDCB_RUPTQ(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 314#define I40E_PRTDCB_RUPTQ_MAX_INDEX 7 315#define I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT 0 316#define I40E_PRTDCB_RUPTQ_RXQNUM_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_RUPTQ_RXQNUM_SHIFT) 317#define I40E_PRTDCB_TC2PFC 0x001C0980 /* Reset: CORER */ 318#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0 319#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT) 320#define I40E_PRTDCB_TCMSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 321#define I40E_PRTDCB_TCMSTC_MAX_INDEX 7 322#define I40E_PRTDCB_TCMSTC_MSTC_SHIFT 0 323#define I40E_PRTDCB_TCMSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCMSTC_MSTC_SHIFT) 324#define I40E_PRTDCB_TCPMC 0x000A21A0 /* Reset: CORER */ 325#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0 326#define I40E_PRTDCB_TCPMC_CPM_MASK I40E_MASK(0x1FFF, I40E_PRTDCB_TCPMC_CPM_SHIFT) 327#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13 328#define I40E_PRTDCB_TCPMC_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TCPMC_LLTC_SHIFT) 329#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30 330#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT) 331#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 332#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7 333#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0 334#define I40E_PRTDCB_TCWSTC_MSTC_MASK I40E_MASK(0xFFFFF, I40E_PRTDCB_TCWSTC_MSTC_SHIFT) 335#define I40E_PRTDCB_TDPMC 0x000A0180 /* Reset: CORER */ 336#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0 337#define I40E_PRTDCB_TDPMC_DPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_TDPMC_DPM_SHIFT) 338#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30 339#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT) 340#define I40E_PRTDCB_TETSC_TCB 0x000AE060 /* Reset: CORER */ 341#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0 342#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT) 343#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8 344#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT) 345#define I40E_PRTDCB_TETSC_TPB 0x00098060 /* Reset: CORER */ 346#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0 347#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK I40E_MASK(0x1, I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT) 348#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8 349#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK I40E_MASK(0xFF, I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT) 350#define I40E_PRTDCB_TFCS 0x001E4560 /* Reset: GLOBR */ 351#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0 352#define I40E_PRTDCB_TFCS_TXOFF_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF_SHIFT) 353#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8 354#define I40E_PRTDCB_TFCS_TXOFF0_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF0_SHIFT) 355#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9 356#define I40E_PRTDCB_TFCS_TXOFF1_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF1_SHIFT) 357#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10 358#define I40E_PRTDCB_TFCS_TXOFF2_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF2_SHIFT) 359#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11 360#define I40E_PRTDCB_TFCS_TXOFF3_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF3_SHIFT) 361#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12 362#define I40E_PRTDCB_TFCS_TXOFF4_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF4_SHIFT) 363#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13 364#define I40E_PRTDCB_TFCS_TXOFF5_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF5_SHIFT) 365#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14 366#define I40E_PRTDCB_TFCS_TXOFF6_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF6_SHIFT) 367#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15 368#define I40E_PRTDCB_TFCS_TXOFF7_MASK I40E_MASK(0x1, I40E_PRTDCB_TFCS_TXOFF7_SHIFT) 369#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */ /* Reset: GLOBR */ 370#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7 371#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0 372#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK I40E_MASK(0x3FFF, I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT) 373#define I40E_GLFCOE_RCTL 0x00269B94 /* Reset: CORER */ 374#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0 375#define I40E_GLFCOE_RCTL_FCOEVER_MASK I40E_MASK(0xF, I40E_GLFCOE_RCTL_FCOEVER_SHIFT) 376#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4 377#define I40E_GLFCOE_RCTL_SAVBAD_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_SAVBAD_SHIFT) 378#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5 379#define I40E_GLFCOE_RCTL_ICRC_MASK I40E_MASK(0x1, I40E_GLFCOE_RCTL_ICRC_SHIFT) 380#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16 381#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK I40E_MASK(0x3FFF, I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT) 382#define I40E_GL_FWSTS 0x00083048 /* Reset: POR */ 383#define I40E_GL_FWSTS_FWS0B_SHIFT 0 384#define I40E_GL_FWSTS_FWS0B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS0B_SHIFT) 385#define I40E_GL_FWSTS_FWRI_SHIFT 9 386#define I40E_GL_FWSTS_FWRI_MASK I40E_MASK(0x1, I40E_GL_FWSTS_FWRI_SHIFT) 387#define I40E_GL_FWSTS_FWS1B_SHIFT 16 388#define I40E_GL_FWSTS_FWS1B_MASK I40E_MASK(0xFF, I40E_GL_FWSTS_FWS1B_SHIFT) 389#define I40E_GLGEN_CLKSTAT 0x000B8184 /* Reset: POR */ 390#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0 391#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK I40E_MASK(0x1, I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT) 392#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4 393#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK I40E_MASK(0x3, I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT) 394#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8 395#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT) 396#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12 397#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT) 398#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16 399#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT) 400#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20 401#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK I40E_MASK(0x7, I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT) 402#define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */ /* Reset: POR */ 403#define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29 404#define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0 405#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT) 406#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3 407#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT) 408#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4 409#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT) 410#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5 411#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT) 412#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6 413#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT) 414#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7 415#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK I40E_MASK(0x7, I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) 416#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10 417#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT) 418#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11 419#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT) 420#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12 421#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) 422#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17 423#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK I40E_MASK(0x3, I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT) 424#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19 425#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT) 426#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20 427#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK I40E_MASK(0x3F, I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT) 428#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT 26 429#define I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_MASK I40E_MASK(0xF, I40E_GLGEN_GPIO_CTL_PRT_BIT_MAP_SHIFT) 430#define I40E_GLGEN_GPIO_SET 0x00088184 /* Reset: POR */ 431#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0 432#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK I40E_MASK(0x1F, I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT) 433#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5 434#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT) 435#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6 436#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK I40E_MASK(0x1, I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT) 437#define I40E_GLGEN_GPIO_STAT 0x0008817C /* Reset: POR */ 438#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0 439#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT) 440#define I40E_GLGEN_GPIO_TRANSIT 0x00088180 /* Reset: POR */ 441#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0 442#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT) 443#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 444#define I40E_GLGEN_I2CCMD_MAX_INDEX 3 445#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0 446#define I40E_GLGEN_I2CCMD_DATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_I2CCMD_DATA_SHIFT) 447#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16 448#define I40E_GLGEN_I2CCMD_REGADD_MASK I40E_MASK(0xFF, I40E_GLGEN_I2CCMD_REGADD_SHIFT) 449#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24 450#define I40E_GLGEN_I2CCMD_PHYADD_MASK I40E_MASK(0x7, I40E_GLGEN_I2CCMD_PHYADD_SHIFT) 451#define I40E_GLGEN_I2CCMD_OP_SHIFT 27 452#define I40E_GLGEN_I2CCMD_OP_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_OP_SHIFT) 453#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28 454#define I40E_GLGEN_I2CCMD_RESET_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_RESET_SHIFT) 455#define I40E_GLGEN_I2CCMD_R_SHIFT 29 456#define I40E_GLGEN_I2CCMD_R_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_R_SHIFT) 457#define I40E_GLGEN_I2CCMD_E_SHIFT 31 458#define I40E_GLGEN_I2CCMD_E_MASK I40E_MASK(0x1, I40E_GLGEN_I2CCMD_E_SHIFT) 459#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 460#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3 461#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0 462#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK I40E_MASK(0x1F, I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT) 463#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5 464#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK I40E_MASK(0x7, I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT) 465#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8 466#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT) 467#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9 468#define I40E_GLGEN_I2CPARAMS_CLK_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_SHIFT) 469#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10 470#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT) 471#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11 472#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT) 473#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12 474#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT) 475#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13 476#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT) 477#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14 478#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT) 479#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15 480#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT) 481#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31 482#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK I40E_MASK(0x1, I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT) 483#define I40E_GLGEN_LED_CTL 0x00088178 /* Reset: POR */ 484#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0 485#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT) 486#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 487#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3 488#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0 489#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK I40E_MASK(0x1FFFF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT) 490#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17 491#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT) 492#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18 493#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK I40E_MASK(0x7FF, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT) 494#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT 29 495#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_MASK I40E_MASK(0x7, I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD0_SHIFT) 496#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 497#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3 498#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0 499#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT) 500#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1 501#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT) 502#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5 503#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT) 504#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10 505#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT) 506#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15 507#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT) 508#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20 509#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK I40E_MASK(0x1F, I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT) 510#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25 511#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK I40E_MASK(0xF, I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT) 512#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31 513#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK I40E_MASK(0x1, I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT) 514#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 515#define I40E_GLGEN_MSCA_MAX_INDEX 3 516#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0 517#define I40E_GLGEN_MSCA_MDIADD_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSCA_MDIADD_SHIFT) 518#define I40E_GLGEN_MSCA_DEVADD_SHIFT 16 519#define I40E_GLGEN_MSCA_DEVADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_DEVADD_SHIFT) 520#define I40E_GLGEN_MSCA_PHYADD_SHIFT 21 521#define I40E_GLGEN_MSCA_PHYADD_MASK I40E_MASK(0x1F, I40E_GLGEN_MSCA_PHYADD_SHIFT) 522#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26 523#define I40E_GLGEN_MSCA_OPCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_OPCODE_SHIFT) 524#define I40E_GLGEN_MSCA_STCODE_SHIFT 28 525#define I40E_GLGEN_MSCA_STCODE_MASK I40E_MASK(0x3, I40E_GLGEN_MSCA_STCODE_SHIFT) 526#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30 527#define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT) 528#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31 529#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT) 530#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */ 531#define I40E_GLGEN_MSRWD_MAX_INDEX 3 532#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0 533#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT) 534#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16 535#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK I40E_MASK(0xFFFF, I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT) 536#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4 /* Reset: PCIR */ 537#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0 538#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK I40E_MASK(0x1F, I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT) 539#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16 540#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK I40E_MASK(0xFF, I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT) 541#define I40E_GLGEN_RSTAT 0x000B8188 /* Reset: POR */ 542#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0 543#define I40E_GLGEN_RSTAT_DEVSTATE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_DEVSTATE_SHIFT) 544#define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2 545#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT) 546#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4 547#define I40E_GLGEN_RSTAT_CORERCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_CORERCNT_SHIFT) 548#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6 549#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT) 550#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8 551#define I40E_GLGEN_RSTAT_EMPRCNT_MASK I40E_MASK(0x3, I40E_GLGEN_RSTAT_EMPRCNT_SHIFT) 552#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10 553#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT) 554#define I40E_GLGEN_RSTCTL 0x000B8180 /* Reset: POR */ 555#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0 556#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK I40E_MASK(0x3F, I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT) 557#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8 558#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK I40E_MASK(0x1, I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT) 559#define I40E_GLGEN_RTRIG 0x000B8190 /* Reset: CORER */ 560#define I40E_GLGEN_RTRIG_CORER_SHIFT 0 561#define I40E_GLGEN_RTRIG_CORER_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_CORER_SHIFT) 562#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1 563#define I40E_GLGEN_RTRIG_GLOBR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_GLOBR_SHIFT) 564#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2 565#define I40E_GLGEN_RTRIG_EMPFWR_MASK I40E_MASK(0x1, I40E_GLGEN_RTRIG_EMPFWR_SHIFT) 566#define I40E_GLGEN_STAT 0x000B612C /* Reset: POR */ 567#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0 568#define I40E_GLGEN_STAT_HWRSVD0_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD0_SHIFT) 569#define I40E_GLGEN_STAT_DCBEN_SHIFT 2 570#define I40E_GLGEN_STAT_DCBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_DCBEN_SHIFT) 571#define I40E_GLGEN_STAT_VTEN_SHIFT 3 572#define I40E_GLGEN_STAT_VTEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_VTEN_SHIFT) 573#define I40E_GLGEN_STAT_FCOEN_SHIFT 4 574#define I40E_GLGEN_STAT_FCOEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_FCOEN_SHIFT) 575#define I40E_GLGEN_STAT_EVBEN_SHIFT 5 576#define I40E_GLGEN_STAT_EVBEN_MASK I40E_MASK(0x1, I40E_GLGEN_STAT_EVBEN_SHIFT) 577#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6 578#define I40E_GLGEN_STAT_HWRSVD1_MASK I40E_MASK(0x3, I40E_GLGEN_STAT_HWRSVD1_SHIFT) 579#define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */ /* Reset: CORER */ 580#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3 581#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0 582#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK I40E_MASK(0xFFFFFFFF, I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT) 583#define I40E_GLVFGEN_TIMER 0x000881BC /* Reset: CORER */ 584#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0 585#define I40E_GLVFGEN_TIMER_GTIME_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVFGEN_TIMER_GTIME_SHIFT) 586#define I40E_PFGEN_CTRL 0x00092400 /* Reset: PFR */ 587#define I40E_PFGEN_CTRL_PFSWR_SHIFT 0 588#define I40E_PFGEN_CTRL_PFSWR_MASK I40E_MASK(0x1, I40E_PFGEN_CTRL_PFSWR_SHIFT) 589#define I40E_PFGEN_DRUN 0x00092500 /* Reset: CORER */ 590#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0 591#define I40E_PFGEN_DRUN_DRVUNLD_MASK I40E_MASK(0x1, I40E_PFGEN_DRUN_DRVUNLD_SHIFT) 592#define I40E_PFGEN_PORTNUM 0x001C0480 /* Reset: CORER */ 593#define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0 594#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT) 595#define I40E_PFGEN_STATE 0x00088000 /* Reset: CORER */ 596#define I40E_PFGEN_STATE_RESERVED_0_SHIFT 0 597#define I40E_PFGEN_STATE_RESERVED_0_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_RESERVED_0_SHIFT) 598#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1 599#define I40E_PFGEN_STATE_PFFCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFFCEN_SHIFT) 600#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2 601#define I40E_PFGEN_STATE_PFLINKEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFLINKEN_SHIFT) 602#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3 603#define I40E_PFGEN_STATE_PFSCEN_MASK I40E_MASK(0x1, I40E_PFGEN_STATE_PFSCEN_SHIFT) 604#define I40E_PRTGEN_CNF 0x000B8120 /* Reset: POR */ 605#define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0 606#define I40E_PRTGEN_CNF_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_PORT_DIS_SHIFT) 607#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1 608#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT) 609#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2 610#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT) 611#define I40E_PRTGEN_CNF2 0x000B8160 /* Reset: POR */ 612#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0 613#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK I40E_MASK(0x1, I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT) 614#define I40E_PRTGEN_STATUS 0x000B8100 /* Reset: POR */ 615#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0 616#define I40E_PRTGEN_STATUS_PORT_VALID_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_VALID_SHIFT) 617#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1 618#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK I40E_MASK(0x1, I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT) 619#define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 620#define I40E_VFGEN_RSTAT1_MAX_INDEX 127 621#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0 622#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT) 623#define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 624#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127 625#define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0 626#define I40E_VPGEN_VFRSTAT_VFRD_MASK I40E_MASK(0x1, I40E_VPGEN_VFRSTAT_VFRD_SHIFT) 627#define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 628#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127 629#define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0 630#define I40E_VPGEN_VFRTRIG_VFSWR_MASK I40E_MASK(0x1, I40E_VPGEN_VFRTRIG_VFSWR_SHIFT) 631#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 632#define I40E_VSIGEN_RSTAT_MAX_INDEX 383 633#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0 634#define I40E_VSIGEN_RSTAT_VMRD_MASK I40E_MASK(0x1, I40E_VSIGEN_RSTAT_VMRD_SHIFT) 635#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 636#define I40E_VSIGEN_RTRIG_MAX_INDEX 383 637#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0 638#define I40E_VSIGEN_RTRIG_VMSWR_MASK I40E_MASK(0x1, I40E_VSIGEN_RTRIG_VMSWR_SHIFT) 639#define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 640#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15 641#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0 642#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT) 643#define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 644#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15 645#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0 646#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK I40E_MASK(0xFFFFF, I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT) 647#define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010 /* Reset: CORER */ 648#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0 649#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT) 650#define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 651#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15 652#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0 653#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT) 654#define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 655#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15 656#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0 657#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK I40E_MASK(0x7FFFFF, I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT) 658#define I40E_GLHMC_FCOEFMAX 0x000C20D0 /* Reset: CORER */ 659#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0 660#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK I40E_MASK(0xFFFF, I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT) 661#define I40E_GLHMC_FCOEFOBJSZ 0x000C2018 /* Reset: CORER */ 662#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0 663#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT) 664#define I40E_GLHMC_FCOEMAX 0x000C2014 /* Reset: CORER */ 665#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0 666#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK I40E_MASK(0x1FFF, I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT) 667#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 668#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15 669#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0 670#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT) 671#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 672#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15 673#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0 674#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT) 675#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29 676#define I40E_GLHMC_FSIAVCNT_RSVD_MASK I40E_MASK(0x7, I40E_GLHMC_FSIAVCNT_RSVD_SHIFT) 677#define I40E_GLHMC_FSIAVMAX 0x000C2068 /* Reset: CORER */ 678#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0 679#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK I40E_MASK(0x1FFFF, I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT) 680#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064 /* Reset: CORER */ 681#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0 682#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT) 683#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 684#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15 685#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0 686#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT) 687#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 688#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15 689#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0 690#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK I40E_MASK(0x1FFFFFFF, I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT) 691#define I40E_GLHMC_FSIMCMAX 0x000C2060 /* Reset: CORER */ 692#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0 693#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK I40E_MASK(0x3FFF, I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT) 694#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c /* Reset: CORER */ 695#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0 696#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT) 697#define I40E_GLHMC_LANQMAX 0x000C2008 /* Reset: CORER */ 698#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0 699#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT) 700#define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 701#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15 702#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0 703#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT) 704#define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 705#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15 706#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0 707#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT) 708#define I40E_GLHMC_LANRXOBJSZ 0x000C200c /* Reset: CORER */ 709#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0 710#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT) 711#define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 712#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15 713#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0 714#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK I40E_MASK(0xFFFFFF, I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT) 715#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24 716#define I40E_GLHMC_LANTXBASE_RSVD_MASK I40E_MASK(0xFF, I40E_GLHMC_LANTXBASE_RSVD_SHIFT) 717#define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 718#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15 719#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0 720#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK I40E_MASK(0x7FF, I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT) 721#define I40E_GLHMC_LANTXOBJSZ 0x000C2004 /* Reset: CORER */ 722#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0 723#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK I40E_MASK(0xF, I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT) 724#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 725#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15 726#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0 727#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK I40E_MASK(0xF, I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT) 728#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 729#define I40E_GLHMC_SDPART_MAX_INDEX 15 730#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0 731#define I40E_GLHMC_SDPART_PMSDBASE_MASK I40E_MASK(0xFFF, I40E_GLHMC_SDPART_PMSDBASE_SHIFT) 732#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16 733#define I40E_GLHMC_SDPART_PMSDSIZE_MASK I40E_MASK(0x1FFF, I40E_GLHMC_SDPART_PMSDSIZE_SHIFT) 734#define I40E_PFHMC_ERRORDATA 0x000C0500 /* Reset: PFR */ 735#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0 736#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK I40E_MASK(0x3FFFFFFF, I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT) 737#define I40E_PFHMC_ERRORINFO 0x000C0400 /* Reset: PFR */ 738#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0 739#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT) 740#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7 741#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT) 742#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8 743#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK I40E_MASK(0xF, I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT) 744#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16 745#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK I40E_MASK(0x1F, I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT) 746#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31 747#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK I40E_MASK(0x1, I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT) 748#define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ 749#define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0 750#define I40E_PFHMC_PDINV_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_PDINV_PMSDIDX_SHIFT) 751#define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16 752#define I40E_PFHMC_PDINV_PMPDIDX_MASK I40E_MASK(0x1FF, I40E_PFHMC_PDINV_PMPDIDX_SHIFT) 753#define I40E_PFHMC_SDCMD 0x000C0000 /* Reset: PFR */ 754#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0 755#define I40E_PFHMC_SDCMD_PMSDIDX_MASK I40E_MASK(0xFFF, I40E_PFHMC_SDCMD_PMSDIDX_SHIFT) 756#define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31 757#define I40E_PFHMC_SDCMD_PMSDWR_MASK I40E_MASK(0x1, I40E_PFHMC_SDCMD_PMSDWR_SHIFT) 758#define I40E_PFHMC_SDDATAHIGH 0x000C0200 /* Reset: PFR */ 759#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0 760#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT) 761#define I40E_PFHMC_SDDATALOW 0x000C0100 /* Reset: PFR */ 762#define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0 763#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT) 764#define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1 765#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK I40E_MASK(0x1, I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) 766#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2 767#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK I40E_MASK(0x3FF, I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) 768#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12 769#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK I40E_MASK(0xFFFFF, I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT) 770#define I40E_GL_GP_FUSE(_i) (0x0009400C + ((_i) * 4)) /* _i=0...28 */ /* Reset: POR */ 771#define I40E_GL_GP_FUSE_MAX_INDEX 28 772#define I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT 0 773#define I40E_GL_GP_FUSE_GL_GP_FUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_GP_FUSE_GL_GP_FUSE_SHIFT) 774#define I40E_GL_UFUSE 0x00094008 /* Reset: POR */ 775#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1 776#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK I40E_MASK(0x1, I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT) 777#define I40E_GL_UFUSE_NIC_ID_SHIFT 2 778#define I40E_GL_UFUSE_NIC_ID_MASK I40E_MASK(0x1, I40E_GL_UFUSE_NIC_ID_SHIFT) 779#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10 780#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT) 781#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11 782#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK I40E_MASK(0x1, I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT) 783#define I40E_EMPINT_GPIO_ENA 0x00088188 /* Reset: POR */ 784#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 785#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT) 786#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 787#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT) 788#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 789#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT) 790#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 791#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT) 792#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 793#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT) 794#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 795#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT) 796#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 797#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT) 798#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 799#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT) 800#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 801#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT) 802#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 803#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT) 804#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 805#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT) 806#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 807#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT) 808#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 809#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT) 810#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 811#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT) 812#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 813#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT) 814#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 815#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT) 816#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 817#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT) 818#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 819#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT) 820#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 821#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT) 822#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 823#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT) 824#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 825#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT) 826#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 827#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT) 828#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 829#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT) 830#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 831#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT) 832#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 833#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT) 834#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 835#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT) 836#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 837#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT) 838#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 839#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT) 840#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 841#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT) 842#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 843#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT) 844#define I40E_PFGEN_PORTMDIO_NUM 0x0003F100 /* Reset: CORER */ 845#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0 846#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK I40E_MASK(0x3, I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT) 847#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4 848#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK I40E_MASK(0x1, I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT) 849#define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ 850#define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0 851#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT) 852#define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11 853#define I40E_PFINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_AEQCTL_ITR_INDX_SHIFT) 854#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13 855#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT) 856#define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30 857#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT) 858#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31 859#define I40E_PFINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_AEQCTL_INTEVENT_SHIFT) 860#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 861#define I40E_PFINT_CEQCTL_MAX_INDEX 511 862#define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0 863#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT) 864#define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11 865#define I40E_PFINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_ITR_INDX_SHIFT) 866#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13 867#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT) 868#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16 869#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT) 870#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 871#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT) 872#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30 873#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT) 874#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31 875#define I40E_PFINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_CEQCTL_INTEVENT_SHIFT) 876#define I40E_PFINT_DYN_CTL0 0x00038480 /* Reset: PFR */ 877#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0 878#define I40E_PFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_SHIFT) 879#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1 880#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT) 881#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 882#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 883#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3 884#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) 885#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5 886#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT) 887#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 888#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 889#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 890#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 891#define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 892#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT) 893#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 894#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511 895#define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0 896#define I40E_PFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_SHIFT) 897#define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1 898#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT) 899#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 900#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 901#define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3 902#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) 903#define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5 904#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT) 905#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 906#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 907#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 908#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 909#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 910#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT) 911#define I40E_PFINT_GPIO_ENA 0x00088080 /* Reset: CORER */ 912#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0 913#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT) 914#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1 915#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT) 916#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2 917#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT) 918#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3 919#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT) 920#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4 921#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT) 922#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5 923#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT) 924#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6 925#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT) 926#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7 927#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT) 928#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8 929#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT) 930#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9 931#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT) 932#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10 933#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT) 934#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11 935#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT) 936#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12 937#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT) 938#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13 939#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT) 940#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14 941#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT) 942#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15 943#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT) 944#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16 945#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT) 946#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17 947#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT) 948#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18 949#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT) 950#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19 951#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT) 952#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20 953#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT) 954#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21 955#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT) 956#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22 957#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT) 958#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23 959#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT) 960#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24 961#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT) 962#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25 963#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT) 964#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26 965#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT) 966#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27 967#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT) 968#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28 969#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT) 970#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29 971#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK I40E_MASK(0x1, I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT) 972#define I40E_PFINT_ICR0 0x00038780 /* Reset: CORER */ 973#define I40E_PFINT_ICR0_INTEVENT_SHIFT 0 974#define I40E_PFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_INTEVENT_SHIFT) 975#define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1 976#define I40E_PFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_0_SHIFT) 977#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2 978#define I40E_PFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_1_SHIFT) 979#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3 980#define I40E_PFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_2_SHIFT) 981#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4 982#define I40E_PFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_3_SHIFT) 983#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5 984#define I40E_PFINT_ICR0_QUEUE_4_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_4_SHIFT) 985#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6 986#define I40E_PFINT_ICR0_QUEUE_5_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_5_SHIFT) 987#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7 988#define I40E_PFINT_ICR0_QUEUE_6_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_6_SHIFT) 989#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8 990#define I40E_PFINT_ICR0_QUEUE_7_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_QUEUE_7_SHIFT) 991#define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16 992#define I40E_PFINT_ICR0_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ECC_ERR_SHIFT) 993#define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19 994#define I40E_PFINT_ICR0_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_MAL_DETECT_SHIFT) 995#define I40E_PFINT_ICR0_GRST_SHIFT 20 996#define I40E_PFINT_ICR0_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GRST_SHIFT) 997#define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21 998#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT) 999#define I40E_PFINT_ICR0_GPIO_SHIFT 22 1000#define I40E_PFINT_ICR0_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_GPIO_SHIFT) 1001#define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23 1002#define I40E_PFINT_ICR0_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_TIMESYNC_SHIFT) 1003#define I40E_PFINT_ICR0_STORM_DETECT_SHIFT 24 1004#define I40E_PFINT_ICR0_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_STORM_DETECT_SHIFT) 1005#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 1006#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 1007#define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26 1008#define I40E_PFINT_ICR0_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_HMC_ERR_SHIFT) 1009#define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28 1010#define I40E_PFINT_ICR0_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_PE_CRITERR_SHIFT) 1011#define I40E_PFINT_ICR0_VFLR_SHIFT 29 1012#define I40E_PFINT_ICR0_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_VFLR_SHIFT) 1013#define I40E_PFINT_ICR0_ADMINQ_SHIFT 30 1014#define I40E_PFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ADMINQ_SHIFT) 1015#define I40E_PFINT_ICR0_SWINT_SHIFT 31 1016#define I40E_PFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_SWINT_SHIFT) 1017#define I40E_PFINT_ICR0_ENA 0x00038800 /* Reset: CORER */ 1018#define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16 1019#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT) 1020#define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19 1021#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT) 1022#define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20 1023#define I40E_PFINT_ICR0_ENA_GRST_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GRST_SHIFT) 1024#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21 1025#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT) 1026#define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22 1027#define I40E_PFINT_ICR0_ENA_GPIO_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_GPIO_SHIFT) 1028#define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23 1029#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT) 1030#define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT 24 1031#define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT) 1032#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 1033#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 1034#define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26 1035#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT) 1036#define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28 1037#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT) 1038#define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29 1039#define I40E_PFINT_ICR0_ENA_VFLR_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_VFLR_SHIFT) 1040#define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30 1041#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT) 1042#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31 1043#define I40E_PFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_PFINT_ICR0_ENA_RSVD_SHIFT) 1044#define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */ /* Reset: PFR */ 1045#define I40E_PFINT_ITR0_MAX_INDEX 2 1046#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0 1047#define I40E_PFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITR0_INTERVAL_SHIFT) 1048#define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4)) /* _i=0...2, _INTPF=0...511 */ /* Reset: PFR */ 1049#define I40E_PFINT_ITRN_MAX_INDEX 2 1050#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0 1051#define I40E_PFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_PFINT_ITRN_INTERVAL_SHIFT) 1052#define I40E_PFINT_LNKLST0 0x00038500 /* Reset: PFR */ 1053#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 1054#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) 1055#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 1056#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 1057#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 1058#define I40E_PFINT_LNKLSTN_MAX_INDEX 511 1059#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 1060#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 1061#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 1062#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 1063#define I40E_PFINT_RATE0 0x00038580 /* Reset: PFR */ 1064#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0 1065#define I40E_PFINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATE0_INTERVAL_SHIFT) 1066#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6 1067#define I40E_PFINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATE0_INTRL_ENA_SHIFT) 1068#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ 1069#define I40E_PFINT_RATEN_MAX_INDEX 511 1070#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0 1071#define I40E_PFINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_PFINT_RATEN_INTERVAL_SHIFT) 1072#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6 1073#define I40E_PFINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_PFINT_RATEN_INTRL_ENA_SHIFT) 1074#define I40E_PFINT_STAT_CTL0 0x00038400 /* Reset: CORER */ 1075#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1076#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1077#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1078#define I40E_QINT_RQCTL_MAX_INDEX 1535 1079#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0 1080#define I40E_QINT_RQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_RQCTL_MSIX_INDX_SHIFT) 1081#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11 1082#define I40E_QINT_RQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_ITR_INDX_SHIFT) 1083#define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13 1084#define I40E_QINT_RQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_RQCTL_MSIX0_INDX_SHIFT) 1085#define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16 1086#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) 1087#define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27 1088#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) 1089#define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30 1090#define I40E_QINT_RQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) 1091#define I40E_QINT_RQCTL_INTEVENT_SHIFT 31 1092#define I40E_QINT_RQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_RQCTL_INTEVENT_SHIFT) 1093#define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1094#define I40E_QINT_TQCTL_MAX_INDEX 1535 1095#define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0 1096#define I40E_QINT_TQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_QINT_TQCTL_MSIX_INDX_SHIFT) 1097#define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11 1098#define I40E_QINT_TQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_ITR_INDX_SHIFT) 1099#define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13 1100#define I40E_QINT_TQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_QINT_TQCTL_MSIX0_INDX_SHIFT) 1101#define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16 1102#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) 1103#define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27 1104#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT) 1105#define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30 1106#define I40E_QINT_TQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_CAUSE_ENA_SHIFT) 1107#define I40E_QINT_TQCTL_INTEVENT_SHIFT 31 1108#define I40E_QINT_TQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_QINT_TQCTL_INTEVENT_SHIFT) 1109#define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1110#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127 1111#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0 1112#define I40E_VFINT_DYN_CTL0_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_SHIFT) 1113#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1 1114#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT) 1115#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2 1116#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT) 1117#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3 1118#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) 1119#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5 1120#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT) 1121#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24 1122#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT) 1123#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25 1124#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT) 1125#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31 1126#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT) 1127#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 1128#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511 1129#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0 1130#define I40E_VFINT_DYN_CTLN_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_SHIFT) 1131#define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1 1132#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT) 1133#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2 1134#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT) 1135#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3 1136#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT) 1137#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5 1138#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT) 1139#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24 1140#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT) 1141#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25 1142#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT) 1143#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31 1144#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT) 1145#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1146#define I40E_VFINT_ICR0_MAX_INDEX 127 1147#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0 1148#define I40E_VFINT_ICR0_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_INTEVENT_SHIFT) 1149#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1 1150#define I40E_VFINT_ICR0_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_0_SHIFT) 1151#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2 1152#define I40E_VFINT_ICR0_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_1_SHIFT) 1153#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3 1154#define I40E_VFINT_ICR0_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_2_SHIFT) 1155#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4 1156#define I40E_VFINT_ICR0_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_QUEUE_3_SHIFT) 1157#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25 1158#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT) 1159#define I40E_VFINT_ICR0_ADMINQ_SHIFT 30 1160#define I40E_VFINT_ICR0_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ADMINQ_SHIFT) 1161#define I40E_VFINT_ICR0_SWINT_SHIFT 31 1162#define I40E_VFINT_ICR0_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_SWINT_SHIFT) 1163#define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1164#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127 1165#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25 1166#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT) 1167#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30 1168#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT) 1169#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31 1170#define I40E_VFINT_ICR0_ENA_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA_RSVD_SHIFT) 1171#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */ /* Reset: VFR */ 1172#define I40E_VFINT_ITR0_MAX_INDEX 2 1173#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0 1174#define I40E_VFINT_ITR0_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR0_INTERVAL_SHIFT) 1175#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...511 */ /* Reset: VFR */ 1176#define I40E_VFINT_ITRN_MAX_INDEX 2 1177#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0 1178#define I40E_VFINT_ITRN_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN_INTERVAL_SHIFT) 1179#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1180#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127 1181#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2 1182#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT) 1183#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 1184#define I40E_VPINT_AEQCTL_MAX_INDEX 127 1185#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0 1186#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT) 1187#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11 1188#define I40E_VPINT_AEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_AEQCTL_ITR_INDX_SHIFT) 1189#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13 1190#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT) 1191#define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30 1192#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT) 1193#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31 1194#define I40E_VPINT_AEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_AEQCTL_INTEVENT_SHIFT) 1195#define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: CORER */ 1196#define I40E_VPINT_CEQCTL_MAX_INDEX 511 1197#define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0 1198#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK I40E_MASK(0xFF, I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT) 1199#define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11 1200#define I40E_VPINT_CEQCTL_ITR_INDX_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_ITR_INDX_SHIFT) 1201#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13 1202#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK I40E_MASK(0x7, I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT) 1203#define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16 1204#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT) 1205#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27 1206#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT) 1207#define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30 1208#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT) 1209#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31 1210#define I40E_VPINT_CEQCTL_INTEVENT_MASK I40E_MASK(0x1, I40E_VPINT_CEQCTL_INTEVENT_SHIFT) 1211#define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1212#define I40E_VPINT_LNKLST0_MAX_INDEX 127 1213#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0 1214#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) 1215#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11 1216#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT) 1217#define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 1218#define I40E_VPINT_LNKLSTN_MAX_INDEX 511 1219#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0 1220#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK I40E_MASK(0x7FF, I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) 1221#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11 1222#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK I40E_MASK(0x3, I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT) 1223#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1224#define I40E_VPINT_RATE0_MAX_INDEX 127 1225#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0 1226#define I40E_VPINT_RATE0_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATE0_INTERVAL_SHIFT) 1227#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6 1228#define I40E_VPINT_RATE0_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATE0_INTRL_ENA_SHIFT) 1229#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ 1230#define I40E_VPINT_RATEN_MAX_INDEX 511 1231#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0 1232#define I40E_VPINT_RATEN_INTERVAL_MASK I40E_MASK(0x3F, I40E_VPINT_RATEN_INTERVAL_SHIFT) 1233#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6 1234#define I40E_VPINT_RATEN_INTRL_ENA_MASK I40E_MASK(0x1, I40E_VPINT_RATEN_INTRL_ENA_SHIFT) 1235#define I40E_GL_RDPU_CNTRL 0x00051060 /* Reset: CORER */ 1236#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0 1237#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK I40E_MASK(0x1, I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT) 1238#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1 1239#define I40E_GL_RDPU_CNTRL_ECO_MASK I40E_MASK(0x7FFFFFFF, I40E_GL_RDPU_CNTRL_ECO_SHIFT) 1240#define I40E_GLLAN_RCTL_0 0x0012A500 /* Reset: CORER */ 1241#define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0 1242#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK I40E_MASK(0x1, I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT) 1243#define I40E_GLLAN_TSOMSK_F 0x000442D8 /* Reset: CORER */ 1244#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0 1245#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT) 1246#define I40E_GLLAN_TSOMSK_L 0x000442E0 /* Reset: CORER */ 1247#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0 1248#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT) 1249#define I40E_GLLAN_TSOMSK_M 0x000442DC /* Reset: CORER */ 1250#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0 1251#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK I40E_MASK(0xFFF, I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT) 1252#define I40E_GLLAN_TXPRE_QDIS(_i) (0x000e6500 + ((_i) * 4)) /* _i=0...11 */ /* Reset: CORER */ 1253#define I40E_GLLAN_TXPRE_QDIS_MAX_INDEX 11 1254#define I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT 0 1255#define I40E_GLLAN_TXPRE_QDIS_QINDX_MASK I40E_MASK(0x7FF, I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT) 1256#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT 16 1257#define I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_QDIS_STAT_SHIFT) 1258#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30 1259#define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT) 1260#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31 1261#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT) 1262#define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */ 1263#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0 1264#define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT) 1265#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16 1266#define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT) 1267#define I40E_PFLAN_QALLOC_VALID_SHIFT 31 1268#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT) 1269#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1270#define I40E_QRX_ENA_MAX_INDEX 1535 1271#define I40E_QRX_ENA_QENA_REQ_SHIFT 0 1272#define I40E_QRX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_REQ_SHIFT) 1273#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1 1274#define I40E_QRX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QRX_ENA_FAST_QDIS_SHIFT) 1275#define I40E_QRX_ENA_QENA_STAT_SHIFT 2 1276#define I40E_QRX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QRX_ENA_QENA_STAT_SHIFT) 1277#define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1278#define I40E_QRX_TAIL_MAX_INDEX 1535 1279#define I40E_QRX_TAIL_TAIL_SHIFT 0 1280#define I40E_QRX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL_TAIL_SHIFT) 1281#define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1282#define I40E_QTX_CTL_MAX_INDEX 1535 1283#define I40E_QTX_CTL_PFVF_Q_SHIFT 0 1284#define I40E_QTX_CTL_PFVF_Q_MASK I40E_MASK(0x3, I40E_QTX_CTL_PFVF_Q_SHIFT) 1285#define I40E_QTX_CTL_PF_INDX_SHIFT 2 1286#define I40E_QTX_CTL_PF_INDX_MASK I40E_MASK(0xF, I40E_QTX_CTL_PF_INDX_SHIFT) 1287#define I40E_QTX_CTL_VFVM_INDX_SHIFT 7 1288#define I40E_QTX_CTL_VFVM_INDX_MASK I40E_MASK(0x1FF, I40E_QTX_CTL_VFVM_INDX_SHIFT) 1289#define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1290#define I40E_QTX_ENA_MAX_INDEX 1535 1291#define I40E_QTX_ENA_QENA_REQ_SHIFT 0 1292#define I40E_QTX_ENA_QENA_REQ_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_REQ_SHIFT) 1293#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1 1294#define I40E_QTX_ENA_FAST_QDIS_MASK I40E_MASK(0x1, I40E_QTX_ENA_FAST_QDIS_SHIFT) 1295#define I40E_QTX_ENA_QENA_STAT_SHIFT 2 1296#define I40E_QTX_ENA_QENA_STAT_MASK I40E_MASK(0x1, I40E_QTX_ENA_QENA_STAT_SHIFT) 1297#define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: CORER */ 1298#define I40E_QTX_HEAD_MAX_INDEX 1535 1299#define I40E_QTX_HEAD_HEAD_SHIFT 0 1300#define I40E_QTX_HEAD_HEAD_MASK I40E_MASK(0x1FFF, I40E_QTX_HEAD_HEAD_SHIFT) 1301#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16 1302#define I40E_QTX_HEAD_RS_PENDING_MASK I40E_MASK(0x1, I40E_QTX_HEAD_RS_PENDING_SHIFT) 1303#define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */ 1304#define I40E_QTX_TAIL_MAX_INDEX 1535 1305#define I40E_QTX_TAIL_TAIL_SHIFT 0 1306#define I40E_QTX_TAIL_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL_TAIL_SHIFT) 1307#define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 1308#define I40E_VPLAN_MAPENA_MAX_INDEX 127 1309#define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0 1310#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK I40E_MASK(0x1, I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT) 1311#define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: VFR */ 1312#define I40E_VPLAN_QTABLE_MAX_INDEX 15 1313#define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0 1314#define I40E_VPLAN_QTABLE_QINDEX_MASK I40E_MASK(0x7FF, I40E_VPLAN_QTABLE_QINDEX_SHIFT) 1315#define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 1316#define I40E_VSILAN_QBASE_MAX_INDEX 383 1317#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0 1318#define I40E_VSILAN_QBASE_VSIBASE_MASK I40E_MASK(0x7FF, I40E_VSILAN_QBASE_VSIBASE_SHIFT) 1319#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11 1320#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK I40E_MASK(0x1, I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT) 1321#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...7, _VSI=0...383 */ /* Reset: PFR */ 1322#define I40E_VSILAN_QTABLE_MAX_INDEX 7 1323#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0 1324#define I40E_VSILAN_QTABLE_QINDEX_0_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_0_SHIFT) 1325#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16 1326#define I40E_VSILAN_QTABLE_QINDEX_1_MASK I40E_MASK(0x7FF, I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) 1327#define I40E_PRTGL_SAH 0x001E2140 /* Reset: GLOBR */ 1328#define I40E_PRTGL_SAH_FC_SAH_SHIFT 0 1329#define I40E_PRTGL_SAH_FC_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_FC_SAH_SHIFT) 1330#define I40E_PRTGL_SAH_MFS_SHIFT 16 1331#define I40E_PRTGL_SAH_MFS_MASK I40E_MASK(0xFFFF, I40E_PRTGL_SAH_MFS_SHIFT) 1332#define I40E_PRTGL_SAL 0x001E2120 /* Reset: GLOBR */ 1333#define I40E_PRTGL_SAL_FC_SAL_SHIFT 0 1334#define I40E_PRTGL_SAL_FC_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTGL_SAL_FC_SAL_SHIFT) 1335#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0 /* Reset: GLOBR */ 1336#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0 1337#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT) 1338#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260 /* Reset: GLOBR */ 1339#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0 1340#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT) 1341#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0 /* Reset: GLOBR */ 1342#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0 1343#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT) 1344#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360 /* Reset: GLOBR */ 1345#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0 1346#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK I40E_MASK(0x1, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT) 1347#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110 /* Reset: GLOBR */ 1348#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0 1349#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT) 1350#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120 /* Reset: GLOBR */ 1351#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0 1352#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT) 1353#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0 /* Reset: GLOBR */ 1354#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0 1355#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT) 1356#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140 /* Reset: GLOBR */ 1357#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0 1358#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT) 1359#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150 /* Reset: GLOBR */ 1360#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0 1361#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT) 1362#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0 /* Reset: GLOBR */ 1363#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0 1364#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK I40E_MASK(0x1FF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT) 1365#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */ 1366#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8 1367#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0 1368#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT) 1369#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16)) /* _i=0...8 */ /* Reset: GLOBR */ 1370#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8 1371#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0 1372#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT) 1373#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0 /* Reset: GLOBR */ 1374#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0 1375#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT) 1376#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0 /* Reset: GLOBR */ 1377#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0 1378#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK I40E_MASK(0xFFFF, I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT) 1379#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480 /* Reset: GLOBR */ 1380#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0 1381#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT) 1382#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2 1383#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT) 1384#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4 1385#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT) 1386#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6 1387#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT) 1388#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8 1389#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT) 1390#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10 1391#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT) 1392#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12 1393#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT) 1394#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14 1395#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT) 1396#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484 /* Reset: GLOBR */ 1397#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0 1398#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT) 1399#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2 1400#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT) 1401#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4 1402#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT) 1403#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6 1404#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT) 1405#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8 1406#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT) 1407#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10 1408#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT) 1409#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12 1410#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT) 1411#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14 1412#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK I40E_MASK(0x3, I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT) 1413#define I40E_GL_FWRESETCNT 0x00083100 /* Reset: POR */ 1414#define I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT 0 1415#define I40E_GL_FWRESETCNT_FWRESETCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FWRESETCNT_FWRESETCNT_SHIFT) 1416#define I40E_GL_MNG_FWSM 0x000B6134 /* Reset: POR */ 1417#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0 1418#define I40E_GL_MNG_FWSM_FW_MODES_MASK I40E_MASK(0x3, I40E_GL_MNG_FWSM_FW_MODES_SHIFT) 1419#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10 1420#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT) 1421#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11 1422#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK I40E_MASK(0xF, I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT) 1423#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15 1424#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT) 1425#define I40E_GL_MNG_FWSM_RESET_CNT_SHIFT 16 1426#define I40E_GL_MNG_FWSM_RESET_CNT_MASK I40E_MASK(0x7, I40E_GL_MNG_FWSM_RESET_CNT_SHIFT) 1427#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19 1428#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK I40E_MASK(0x3F, I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT) 1429#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26 1430#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT) 1431#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27 1432#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT) 1433#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28 1434#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT) 1435#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29 1436#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK I40E_MASK(0x1, I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT) 1437#define I40E_GL_MNG_HWARB_CTRL 0x000B6130 /* Reset: POR */ 1438#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0 1439#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK I40E_MASK(0x1, I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT) 1440#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */ /* Reset: POR */ 1441#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31 1442#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0 1443#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT) 1444#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260 /* Reset: POR */ 1445#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0 1446#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT) 1447#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1448#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7 1449#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0 1450#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT) 1451#define I40E_PRT_MNG_MANC 0x00256A20 /* Reset: POR */ 1452#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0 1453#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT) 1454#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1 1455#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT) 1456#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17 1457#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT) 1458#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19 1459#define I40E_PRT_MNG_MANC_RCV_ALL_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_RCV_ALL_SHIFT) 1460#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25 1461#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT) 1462#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26 1463#define I40E_PRT_MNG_MANC_NET_TYPE_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_NET_TYPE_SHIFT) 1464#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28 1465#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT) 1466#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29 1467#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK I40E_MASK(0x1, I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT) 1468#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1469#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7 1470#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0 1471#define I40E_PRT_MNG_MAVTV_VID_MASK I40E_MASK(0xFFF, I40E_PRT_MNG_MAVTV_VID_SHIFT) 1472#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1473#define I40E_PRT_MNG_MDEF_MAX_INDEX 7 1474#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0 1475#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT) 1476#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4 1477#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT) 1478#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5 1479#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT) 1480#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13 1481#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT) 1482#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17 1483#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT) 1484#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21 1485#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT) 1486#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25 1487#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT) 1488#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26 1489#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT) 1490#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27 1491#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT) 1492#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28 1493#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT) 1494#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29 1495#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT) 1496#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30 1497#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT) 1498#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31 1499#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT) 1500#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32)) /* _i=0...7 */ /* Reset: POR */ 1501#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7 1502#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0 1503#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT) 1504#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4 1505#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK I40E_MASK(0xF, I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT) 1506#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8 1507#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT) 1508#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24 1509#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT) 1510#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25 1511#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT) 1512#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26 1513#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT) 1514#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27 1515#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT) 1516#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28 1517#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT) 1518#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29 1519#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT) 1520#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30 1521#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT) 1522#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31 1523#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK I40E_MASK(0x1, I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT) 1524#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1525#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3 1526#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0 1527#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT) 1528#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16 1529#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT) 1530#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1531#define I40E_PRT_MNG_METF_MAX_INDEX 3 1532#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0 1533#define I40E_PRT_MNG_METF_ETYPE_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_METF_ETYPE_SHIFT) 1534#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30 1535#define I40E_PRT_MNG_METF_POLARITY_MASK I40E_MASK(0x1, I40E_PRT_MNG_METF_POLARITY_SHIFT) 1536#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */ 1537#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15 1538#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0 1539#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT) 1540#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16 1541#define I40E_PRT_MNG_MFUTP_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_UDP_SHIFT) 1542#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17 1543#define I40E_PRT_MNG_MFUTP_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_TCP_SHIFT) 1544#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18 1545#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK I40E_MASK(0x1, I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT) 1546#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1547#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3 1548#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0 1549#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT) 1550#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */ /* Reset: POR */ 1551#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15 1552#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0 1553#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT) 1554#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1555#define I40E_PRT_MNG_MMAH_MAX_INDEX 3 1556#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0 1557#define I40E_PRT_MNG_MMAH_MMAH_MASK I40E_MASK(0xFFFF, I40E_PRT_MNG_MMAH_MMAH_SHIFT) 1558#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */ /* Reset: POR */ 1559#define I40E_PRT_MNG_MMAL_MAX_INDEX 3 1560#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0 1561#define I40E_PRT_MNG_MMAL_MMAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRT_MNG_MMAL_MMAL_SHIFT) 1562#define I40E_PRT_MNG_MNGONLY 0x00256A60 /* Reset: POR */ 1563#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0 1564#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK I40E_MASK(0xFF, I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT) 1565#define I40E_PRT_MNG_MSFM 0x00256AA0 /* Reset: POR */ 1566#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0 1567#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT) 1568#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1 1569#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT) 1570#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2 1571#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT) 1572#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3 1573#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT) 1574#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4 1575#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT) 1576#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5 1577#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT) 1578#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6 1579#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT) 1580#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7 1581#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK I40E_MASK(0x1, I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT) 1582#define I40E_MSIX_PBA(_i) (0x00001000 + ((_i) * 4)) /* _i=0...5 */ /* Reset: FLR */ 1583#define I40E_MSIX_PBA_MAX_INDEX 5 1584#define I40E_MSIX_PBA_PENBIT_SHIFT 0 1585#define I40E_MSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_PBA_PENBIT_SHIFT) 1586#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1587#define I40E_MSIX_TADD_MAX_INDEX 128 1588#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0 1589#define I40E_MSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_MSIX_TADD_MSIXTADD10_SHIFT) 1590#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2 1591#define I40E_MSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_MSIX_TADD_MSIXTADD_SHIFT) 1592#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1593#define I40E_MSIX_TMSG_MAX_INDEX 128 1594#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0 1595#define I40E_MSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TMSG_MSIXTMSG_SHIFT) 1596#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1597#define I40E_MSIX_TUADD_MAX_INDEX 128 1598#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0 1599#define I40E_MSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_MSIX_TUADD_MSIXTUADD_SHIFT) 1600#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */ /* Reset: FLR */ 1601#define I40E_MSIX_TVCTRL_MAX_INDEX 128 1602#define I40E_MSIX_TVCTRL_MASK_SHIFT 0 1603#define I40E_MSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_MSIX_TVCTRL_MASK_SHIFT) 1604#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ 1605#define I40E_VFMSIX_PBA1_MAX_INDEX 19 1606#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 1607#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT) 1608#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1609#define I40E_VFMSIX_TADD1_MAX_INDEX 639 1610#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 1611#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) 1612#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 1613#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) 1614#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1615#define I40E_VFMSIX_TMSG1_MAX_INDEX 639 1616#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 1617#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) 1618#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1619#define I40E_VFMSIX_TUADD1_MAX_INDEX 639 1620#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 1621#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) 1622#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ 1623#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 1624#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 1625#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT) 1626#define I40E_GLNVM_FLA 0x000B6108 /* Reset: POR */ 1627#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0 1628#define I40E_GLNVM_FLA_FL_SCK_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SCK_SHIFT) 1629#define I40E_GLNVM_FLA_FL_CE_SHIFT 1 1630#define I40E_GLNVM_FLA_FL_CE_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_CE_SHIFT) 1631#define I40E_GLNVM_FLA_FL_SI_SHIFT 2 1632#define I40E_GLNVM_FLA_FL_SI_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SI_SHIFT) 1633#define I40E_GLNVM_FLA_FL_SO_SHIFT 3 1634#define I40E_GLNVM_FLA_FL_SO_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_SO_SHIFT) 1635#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4 1636#define I40E_GLNVM_FLA_FL_REQ_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_REQ_SHIFT) 1637#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5 1638#define I40E_GLNVM_FLA_FL_GNT_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_GNT_SHIFT) 1639#define I40E_GLNVM_FLA_LOCKED_SHIFT 6 1640#define I40E_GLNVM_FLA_LOCKED_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_LOCKED_SHIFT) 1641#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18 1642#define I40E_GLNVM_FLA_FL_SADDR_MASK I40E_MASK(0x7FF, I40E_GLNVM_FLA_FL_SADDR_SHIFT) 1643#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30 1644#define I40E_GLNVM_FLA_FL_BUSY_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_BUSY_SHIFT) 1645#define I40E_GLNVM_FLA_FL_DER_SHIFT 31 1646#define I40E_GLNVM_FLA_FL_DER_MASK I40E_MASK(0x1, I40E_GLNVM_FLA_FL_DER_SHIFT) 1647#define I40E_GLNVM_FLASHID 0x000B6104 /* Reset: POR */ 1648#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0 1649#define I40E_GLNVM_FLASHID_FLASHID_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_FLASHID_FLASHID_SHIFT) 1650#define I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT 31 1651#define I40E_GLNVM_FLASHID_FLEEP_PERF_MASK I40E_MASK(0x1, I40E_GLNVM_FLASHID_FLEEP_PERF_SHIFT) 1652#define I40E_GLNVM_GENS 0x000B6100 /* Reset: POR */ 1653#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0 1654#define I40E_GLNVM_GENS_NVM_PRES_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_NVM_PRES_SHIFT) 1655#define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5 1656#define I40E_GLNVM_GENS_SR_SIZE_MASK I40E_MASK(0x7, I40E_GLNVM_GENS_SR_SIZE_SHIFT) 1657#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8 1658#define I40E_GLNVM_GENS_BANK1VAL_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_BANK1VAL_SHIFT) 1659#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23 1660#define I40E_GLNVM_GENS_ALT_PRST_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_ALT_PRST_SHIFT) 1661#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25 1662#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK I40E_MASK(0x1, I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT) 1663#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */ /* Reset: POR */ 1664#define I40E_GLNVM_PROTCSR_MAX_INDEX 59 1665#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0 1666#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK I40E_MASK(0xFFFFFF, I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT) 1667#define I40E_GLNVM_SRCTL 0x000B6110 /* Reset: POR */ 1668#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0 1669#define I40E_GLNVM_SRCTL_SRBUSY_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_SRBUSY_SHIFT) 1670#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14 1671#define I40E_GLNVM_SRCTL_ADDR_MASK I40E_MASK(0x7FFF, I40E_GLNVM_SRCTL_ADDR_SHIFT) 1672#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29 1673#define I40E_GLNVM_SRCTL_WRITE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_WRITE_SHIFT) 1674#define I40E_GLNVM_SRCTL_START_SHIFT 30 1675#define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT) 1676#define I40E_GLNVM_SRCTL_DONE_SHIFT 31 1677#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT) 1678#define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */ 1679#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0 1680#define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT) 1681#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16 1682#define I40E_GLNVM_SRDATA_RDDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_RDDATA_SHIFT) 1683#define I40E_GLNVM_ULD 0x000B6008 /* Reset: POR */ 1684#define I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT 0 1685#define I40E_GLNVM_ULD_CONF_PCIR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIR_DONE_SHIFT) 1686#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT 1 1687#define I40E_GLNVM_ULD_CONF_PCIRTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIRTL_DONE_SHIFT) 1688#define I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT 2 1689#define I40E_GLNVM_ULD_CONF_LCB_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_LCB_DONE_SHIFT) 1690#define I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT 3 1691#define I40E_GLNVM_ULD_CONF_CORE_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_CORE_DONE_SHIFT) 1692#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT 4 1693#define I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_GLOBAL_DONE_SHIFT) 1694#define I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT 5 1695#define I40E_GLNVM_ULD_CONF_POR_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_POR_DONE_SHIFT) 1696#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT 6 1697#define I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIE_ANA_DONE_SHIFT) 1698#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT 7 1699#define I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PHY_ANA_DONE_SHIFT) 1700#define I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT 8 1701#define I40E_GLNVM_ULD_CONF_EMP_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_EMP_DONE_SHIFT) 1702#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT 9 1703#define I40E_GLNVM_ULD_CONF_PCIALT_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_ULD_CONF_PCIALT_DONE_SHIFT) 1704#define I40E_GLPCI_BYTCTH 0x0009C484 /* Reset: PCIR */ 1705#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0 1706#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT) 1707#define I40E_GLPCI_BYTCTL 0x0009C488 /* Reset: PCIR */ 1708#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0 1709#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT) 1710#define I40E_GLPCI_CAPCTRL 0x000BE4A4 /* Reset: PCIR */ 1711#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0 1712#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT) 1713#define I40E_GLPCI_CAPSUP 0x000BE4A8 /* Reset: PCIR */ 1714#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0 1715#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT) 1716#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2 1717#define I40E_GLPCI_CAPSUP_LTR_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LTR_EN_SHIFT) 1718#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3 1719#define I40E_GLPCI_CAPSUP_TPH_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_TPH_EN_SHIFT) 1720#define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4 1721#define I40E_GLPCI_CAPSUP_ARI_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ARI_EN_SHIFT) 1722#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5 1723#define I40E_GLPCI_CAPSUP_IOV_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IOV_EN_SHIFT) 1724#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6 1725#define I40E_GLPCI_CAPSUP_ACS_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ACS_EN_SHIFT) 1726#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7 1727#define I40E_GLPCI_CAPSUP_SEC_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_SEC_EN_SHIFT) 1728#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16 1729#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT) 1730#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17 1731#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT) 1732#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18 1733#define I40E_GLPCI_CAPSUP_IDO_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_IDO_EN_SHIFT) 1734#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19 1735#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT) 1736#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20 1737#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT) 1738#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30 1739#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT) 1740#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31 1741#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK I40E_MASK(0x1, I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT) 1742#define I40E_GLPCI_CNF 0x000BE4C0 /* Reset: POR */ 1743#define I40E_GLPCI_CNF_FLEX10_SHIFT 1 1744#define I40E_GLPCI_CNF_FLEX10_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_FLEX10_SHIFT) 1745#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2 1746#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK I40E_MASK(0x1, I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT) 1747#define I40E_GLPCI_CNF2 0x000BE494 /* Reset: PCIR */ 1748#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0 1749#define I40E_GLPCI_CNF2_RO_DIS_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_RO_DIS_SHIFT) 1750#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1 1751#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK I40E_MASK(0x1, I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT) 1752#define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2 1753#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT) 1754#define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13 1755#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK I40E_MASK(0x7FF, I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT) 1756#define I40E_GLPCI_DREVID 0x0009C480 /* Reset: PCIR */ 1757#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0 1758#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT) 1759#define I40E_GLPCI_GSCL_1 0x0009C48C /* Reset: PCIR */ 1760#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0 1761#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT) 1762#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1 1763#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT) 1764#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2 1765#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT) 1766#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3 1767#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT) 1768#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4 1769#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT) 1770#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5 1771#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT) 1772#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6 1773#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT) 1774#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7 1775#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT) 1776#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8 1777#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT) 1778#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9 1779#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT) 1780#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14 1781#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT) 1782#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15 1783#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK I40E_MASK(0x1F, I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT) 1784#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28 1785#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT) 1786#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29 1787#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT) 1788#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30 1789#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT) 1790#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31 1791#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK I40E_MASK(0x1, I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT) 1792#define I40E_GLPCI_GSCL_2 0x0009C490 /* Reset: PCIR */ 1793#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0 1794#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT) 1795#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8 1796#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT) 1797#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16 1798#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT) 1799#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24 1800#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK I40E_MASK(0xFF, I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT) 1801#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 1802#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3 1803#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0 1804#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT) 1805#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16 1806#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK I40E_MASK(0xFFFF, I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT) 1807#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */ /* Reset: PCIR */ 1808#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3 1809#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0 1810#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT) 1811#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ 1812#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0 1813#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT) 1814#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1 1815#define I40E_GLPCI_LBARCTRL_BAR32_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_BAR32_SHIFT) 1816#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3 1817#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT) 1818#define I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT 4 1819#define I40E_GLPCI_LBARCTRL_RSVD_4_MASK I40E_MASK(0x3, I40E_GLPCI_LBARCTRL_RSVD_4_SHIFT) 1820#define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6 1821#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT) 1822#define I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT 10 1823#define I40E_GLPCI_LBARCTRL_RSVD_10_MASK I40E_MASK(0x1, I40E_GLPCI_LBARCTRL_RSVD_10_SHIFT) 1824#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11 1825#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK I40E_MASK(0x7, I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT) 1826#define I40E_GLPCI_LINKCAP 0x000BE4AC /* Reset: PCIR */ 1827#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0 1828#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK I40E_MASK(0x3F, I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT) 1829#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6 1830#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK I40E_MASK(0x7, I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT) 1831#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9 1832#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK I40E_MASK(0xF, I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT) 1833#define I40E_GLPCI_PCIERR 0x000BE4FC /* Reset: PCIR */ 1834#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0 1835#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT) 1836#define I40E_GLPCI_PKTCT 0x0009C4BC /* Reset: PCIR */ 1837#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0 1838#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT) 1839#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4 /* Reset: PCIR */ 1840#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0 1841#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT) 1842#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16 1843#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT) 1844#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0 /* Reset: PCIR */ 1845#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0 1846#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK I40E_MASK(0x1F, I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT) 1847#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16 1848#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK I40E_MASK(0x7, I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT) 1849#define I40E_GLPCI_PMSUP 0x000BE4B0 /* Reset: PCIR */ 1850#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0 1851#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT) 1852#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2 1853#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT) 1854#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5 1855#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT) 1856#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8 1857#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT) 1858#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11 1859#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK I40E_MASK(0x7, I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT) 1860#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14 1861#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK I40E_MASK(0x1, I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT) 1862#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15 1863#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK I40E_MASK(0x3, I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT) 1864#define I40E_GLPCI_PQ_MAX_USED_SPC 0x0009C4EC /* Reset: PCIR */ 1865#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT 0 1866#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_12_SHIFT) 1867#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT 8 1868#define I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_MASK I40E_MASK(0xFF, I40E_GLPCI_PQ_MAX_USED_SPC_GLPCI_PQ_MAX_USED_SPC_13_SHIFT) 1869#define I40E_GLPCI_PWRDATA 0x000BE490 /* Reset: PCIR */ 1870#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0 1871#define I40E_GLPCI_PWRDATA_D0_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D0_POWER_SHIFT) 1872#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8 1873#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT) 1874#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16 1875#define I40E_GLPCI_PWRDATA_D3_POWER_MASK I40E_MASK(0xFF, I40E_GLPCI_PWRDATA_D3_POWER_SHIFT) 1876#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24 1877#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK I40E_MASK(0x3, I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT) 1878#define I40E_GLPCI_REVID 0x000BE4B4 /* Reset: PCIR */ 1879#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0 1880#define I40E_GLPCI_REVID_NVM_REVID_MASK I40E_MASK(0xFF, I40E_GLPCI_REVID_NVM_REVID_SHIFT) 1881#define I40E_GLPCI_SERH 0x000BE49C /* Reset: PCIR */ 1882#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0 1883#define I40E_GLPCI_SERH_SER_NUM_H_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SERH_SER_NUM_H_SHIFT) 1884#define I40E_GLPCI_SERL 0x000BE498 /* Reset: PCIR */ 1885#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0 1886#define I40E_GLPCI_SERL_SER_NUM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SERL_SER_NUM_L_SHIFT) 1887#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8 /* Reset: PCIR */ 1888#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0 1889#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT) 1890#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC /* Reset: PCIR */ 1891#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0 1892#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT) 1893#define I40E_GLPCI_SUBVENID 0x000BE48C /* Reset: PCIR */ 1894#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT 0 1895#define I40E_GLPCI_SUBVENID_SUB_VEN_ID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_SUBVENID_SUB_VEN_ID_SHIFT) 1896#define I40E_GLPCI_UPADD 0x000BE4F8 /* Reset: PCIR */ 1897#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1 1898#define I40E_GLPCI_UPADD_ADDRESS_MASK I40E_MASK(0x7FFFFFFF, I40E_GLPCI_UPADD_ADDRESS_SHIFT) 1899#define I40E_GLPCI_VENDORID 0x000BE518 /* Reset: PCIR */ 1900#define I40E_GLPCI_VENDORID_VENDORID_SHIFT 0 1901#define I40E_GLPCI_VENDORID_VENDORID_MASK I40E_MASK(0xFFFF, I40E_GLPCI_VENDORID_VENDORID_SHIFT) 1902#define I40E_GLPCI_VFSUP 0x000BE4B8 /* Reset: PCIR */ 1903#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0 1904#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT) 1905#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1 1906#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK I40E_MASK(0x1, I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT) 1907#define I40E_GLTPH_CTRL 0x000BE480 /* Reset: PCIR */ 1908#define I40E_GLTPH_CTRL_DESC_PH_SHIFT 9 1909#define I40E_GLTPH_CTRL_DESC_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DESC_PH_SHIFT) 1910#define I40E_GLTPH_CTRL_DATA_PH_SHIFT 11 1911#define I40E_GLTPH_CTRL_DATA_PH_MASK I40E_MASK(0x3, I40E_GLTPH_CTRL_DATA_PH_SHIFT) 1912#define I40E_PF_FUNC_RID 0x0009C000 /* Reset: PCIR */ 1913#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0 1914#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK I40E_MASK(0x7, I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT) 1915#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3 1916#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK I40E_MASK(0x1F, I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT) 1917#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8 1918#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK I40E_MASK(0xFF, I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT) 1919#define I40E_PF_PCI_CIAA 0x0009C080 /* Reset: FLR */ 1920#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0 1921#define I40E_PF_PCI_CIAA_ADDRESS_MASK I40E_MASK(0xFFF, I40E_PF_PCI_CIAA_ADDRESS_SHIFT) 1922#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12 1923#define I40E_PF_PCI_CIAA_VF_NUM_MASK I40E_MASK(0x7F, I40E_PF_PCI_CIAA_VF_NUM_SHIFT) 1924#define I40E_PF_PCI_CIAD 0x0009C100 /* Reset: FLR */ 1925#define I40E_PF_PCI_CIAD_DATA_SHIFT 0 1926#define I40E_PF_PCI_CIAD_DATA_MASK I40E_MASK(0xFFFFFFFF, I40E_PF_PCI_CIAD_DATA_SHIFT) 1927#define I40E_PFPCI_CLASS 0x000BE400 /* Reset: PCIR */ 1928#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0 1929#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT) 1930#define I40E_PFPCI_CLASS_RESERVED_1_SHIFT 1 1931#define I40E_PFPCI_CLASS_RESERVED_1_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_RESERVED_1_SHIFT) 1932#define I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT 2 1933#define I40E_PFPCI_CLASS_PF_IS_LAN_MASK I40E_MASK(0x1, I40E_PFPCI_CLASS_PF_IS_LAN_SHIFT) 1934#define I40E_PFPCI_CNF 0x000BE000 /* Reset: PCIR */ 1935#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2 1936#define I40E_PFPCI_CNF_MSI_EN_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_MSI_EN_SHIFT) 1937#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3 1938#define I40E_PFPCI_CNF_EXROM_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_EXROM_DIS_SHIFT) 1939#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4 1940#define I40E_PFPCI_CNF_IO_BAR_MASK I40E_MASK(0x1, I40E_PFPCI_CNF_IO_BAR_SHIFT) 1941#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5 1942#define I40E_PFPCI_CNF_INT_PIN_MASK I40E_MASK(0x3, I40E_PFPCI_CNF_INT_PIN_SHIFT) 1943#define I40E_PFPCI_DEVID 0x000BE080 /* Reset: PCIR */ 1944#define I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT 0 1945#define I40E_PFPCI_DEVID_PF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_PF_DEV_ID_SHIFT) 1946#define I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT 16 1947#define I40E_PFPCI_DEVID_VF_DEV_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_DEVID_VF_DEV_ID_SHIFT) 1948#define I40E_PFPCI_FACTPS 0x0009C180 /* Reset: FLR */ 1949#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0 1950#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK I40E_MASK(0x3, I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT) 1951#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3 1952#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK I40E_MASK(0x1, I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT) 1953#define I40E_PFPCI_FUNC 0x000BE200 /* Reset: POR */ 1954#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0 1955#define I40E_PFPCI_FUNC_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_FUNC_DIS_SHIFT) 1956#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1 1957#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT) 1958#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2 1959#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT) 1960#define I40E_PFPCI_FUNC2 0x000BE180 /* Reset: PCIR */ 1961#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0 1962#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK I40E_MASK(0x1, I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT) 1963#define I40E_PFPCI_ICAUSE 0x0009C200 /* Reset: PFR */ 1964#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0 1965#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT) 1966#define I40E_PFPCI_IENA 0x0009C280 /* Reset: PFR */ 1967#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0 1968#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK I40E_MASK(0xFFFFFFFF, I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT) 1969#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800 /* Reset: PCIR */ 1970#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 1971#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT) 1972#define I40E_PFPCI_PM 0x000BE300 /* Reset: POR */ 1973#define I40E_PFPCI_PM_PME_EN_SHIFT 0 1974#define I40E_PFPCI_PM_PME_EN_MASK I40E_MASK(0x1, I40E_PFPCI_PM_PME_EN_SHIFT) 1975#define I40E_PFPCI_STATUS1 0x000BE280 /* Reset: POR */ 1976#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0 1977#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK I40E_MASK(0x1, I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT) 1978#define I40E_PFPCI_SUBSYSID 0x000BE100 /* Reset: PCIR */ 1979#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT 0 1980#define I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_PF_SUBSYS_ID_SHIFT) 1981#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT 16 1982#define I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_MASK I40E_MASK(0xFFFF, I40E_PFPCI_SUBSYSID_VF_SUBSYS_ID_SHIFT) 1983#define I40E_PFPCI_VF_FLUSH_DONE 0x0000E400 /* Reset: PCIR */ 1984#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0 1985#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT) 1986#define I40E_PFPCI_VF_FLUSH_DONE1(_VF) (0x0009C600 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: PCIR */ 1987#define I40E_PFPCI_VF_FLUSH_DONE1_MAX_INDEX 127 1988#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT 0 1989#define I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VF_FLUSH_DONE1_FLUSH_DONE_SHIFT) 1990#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880 /* Reset: PCIR */ 1991#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0 1992#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK I40E_MASK(0x1, I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT) 1993#define I40E_PFPCI_VMINDEX 0x0009C300 /* Reset: PCIR */ 1994#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0 1995#define I40E_PFPCI_VMINDEX_VMINDEX_MASK I40E_MASK(0x1FF, I40E_PFPCI_VMINDEX_VMINDEX_SHIFT) 1996#define I40E_PFPCI_VMPEND 0x0009C380 /* Reset: PCIR */ 1997#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0 1998#define I40E_PFPCI_VMPEND_PENDING_MASK I40E_MASK(0x1, I40E_PFPCI_VMPEND_PENDING_SHIFT) 1999#define I40E_PRTPM_EEE_STAT 0x001E4320 /* Reset: GLOBR */ 2000#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29 2001#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT) 2002#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30 2003#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT) 2004#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31 2005#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK I40E_MASK(0x1, I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT) 2006#define I40E_PRTPM_EEEC 0x001E4380 /* Reset: GLOBR */ 2007#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16 2008#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT) 2009#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24 2010#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK I40E_MASK(0x3, I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT) 2011#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26 2012#define I40E_PRTPM_EEEC_TEEE_DLY_MASK I40E_MASK(0x3F, I40E_PRTPM_EEEC_TEEE_DLY_SHIFT) 2013#define I40E_PRTPM_EEEFWD 0x001E4400 /* Reset: GLOBR */ 2014#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31 2015#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK I40E_MASK(0x1, I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT) 2016#define I40E_PRTPM_EEER 0x001E4360 /* Reset: GLOBR */ 2017#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0 2018#define I40E_PRTPM_EEER_TW_SYSTEM_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEER_TW_SYSTEM_SHIFT) 2019#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16 2020#define I40E_PRTPM_EEER_TX_LPI_EN_MASK I40E_MASK(0x1, I40E_PRTPM_EEER_TX_LPI_EN_SHIFT) 2021#define I40E_PRTPM_EEETXC 0x001E43E0 /* Reset: GLOBR */ 2022#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0 2023#define I40E_PRTPM_EEETXC_TW_PHY_MASK I40E_MASK(0xFFFF, I40E_PRTPM_EEETXC_TW_PHY_SHIFT) 2024#define I40E_PRTPM_GC 0x000B8140 /* Reset: POR */ 2025#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0 2026#define I40E_PRTPM_GC_EMP_LINK_ON_MASK I40E_MASK(0x1, I40E_PRTPM_GC_EMP_LINK_ON_SHIFT) 2027#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1 2028#define I40E_PRTPM_GC_MNG_VETO_MASK I40E_MASK(0x1, I40E_PRTPM_GC_MNG_VETO_SHIFT) 2029#define I40E_PRTPM_GC_RATD_SHIFT 2 2030#define I40E_PRTPM_GC_RATD_MASK I40E_MASK(0x1, I40E_PRTPM_GC_RATD_SHIFT) 2031#define I40E_PRTPM_GC_LCDMP_SHIFT 3 2032#define I40E_PRTPM_GC_LCDMP_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LCDMP_SHIFT) 2033#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31 2034#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK I40E_MASK(0x1, I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT) 2035#define I40E_PRTPM_RLPIC 0x001E43A0 /* Reset: GLOBR */ 2036#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0 2037#define I40E_PRTPM_RLPIC_ERLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_RLPIC_ERLPIC_SHIFT) 2038#define I40E_PRTPM_TLPIC 0x001E43C0 /* Reset: GLOBR */ 2039#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0 2040#define I40E_PRTPM_TLPIC_ETLPIC_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_TLPIC_ETLPIC_SHIFT) 2041#define I40E_GLRPB_DPSS 0x000AC828 /* Reset: CORER */ 2042#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0 2043#define I40E_GLRPB_DPSS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_DPSS_DPS_TCN_SHIFT) 2044#define I40E_GLRPB_GHW 0x000AC830 /* Reset: CORER */ 2045#define I40E_GLRPB_GHW_GHW_SHIFT 0 2046#define I40E_GLRPB_GHW_GHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GHW_GHW_SHIFT) 2047#define I40E_GLRPB_GLW 0x000AC834 /* Reset: CORER */ 2048#define I40E_GLRPB_GLW_GLW_SHIFT 0 2049#define I40E_GLRPB_GLW_GLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_GLW_GLW_SHIFT) 2050#define I40E_GLRPB_PHW 0x000AC844 /* Reset: CORER */ 2051#define I40E_GLRPB_PHW_PHW_SHIFT 0 2052#define I40E_GLRPB_PHW_PHW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PHW_PHW_SHIFT) 2053#define I40E_GLRPB_PLW 0x000AC848 /* Reset: CORER */ 2054#define I40E_GLRPB_PLW_PLW_SHIFT 0 2055#define I40E_GLRPB_PLW_PLW_MASK I40E_MASK(0xFFFFF, I40E_GLRPB_PLW_PLW_SHIFT) 2056#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2057#define I40E_PRTRPB_DHW_MAX_INDEX 7 2058#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0 2059#define I40E_PRTRPB_DHW_DHW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DHW_DHW_TCN_SHIFT) 2060#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2061#define I40E_PRTRPB_DLW_MAX_INDEX 7 2062#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0 2063#define I40E_PRTRPB_DLW_DLW_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DLW_DLW_TCN_SHIFT) 2064#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2065#define I40E_PRTRPB_DPS_MAX_INDEX 7 2066#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0 2067#define I40E_PRTRPB_DPS_DPS_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_DPS_DPS_TCN_SHIFT) 2068#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2069#define I40E_PRTRPB_SHT_MAX_INDEX 7 2070#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0 2071#define I40E_PRTRPB_SHT_SHT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHT_SHT_TCN_SHIFT) 2072#define I40E_PRTRPB_SHW 0x000AC580 /* Reset: CORER */ 2073#define I40E_PRTRPB_SHW_SHW_SHIFT 0 2074#define I40E_PRTRPB_SHW_SHW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SHW_SHW_SHIFT) 2075#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */ /* Reset: CORER */ 2076#define I40E_PRTRPB_SLT_MAX_INDEX 7 2077#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0 2078#define I40E_PRTRPB_SLT_SLT_TCN_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLT_SLT_TCN_SHIFT) 2079#define I40E_PRTRPB_SLW 0x000AC6A0 /* Reset: CORER */ 2080#define I40E_PRTRPB_SLW_SLW_SHIFT 0 2081#define I40E_PRTRPB_SLW_SLW_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SLW_SLW_SHIFT) 2082#define I40E_PRTRPB_SPS 0x000AC7C0 /* Reset: CORER */ 2083#define I40E_PRTRPB_SPS_SPS_SHIFT 0 2084#define I40E_PRTRPB_SPS_SPS_MASK I40E_MASK(0xFFFFF, I40E_PRTRPB_SPS_SPS_SHIFT) 2085#define I40E_GLQF_CTL 0x00269BA4 /* Reset: CORER */ 2086#define I40E_GLQF_CTL_HTOEP_SHIFT 1 2087#define I40E_GLQF_CTL_HTOEP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_SHIFT) 2088#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2 2089#define I40E_GLQF_CTL_HTOEP_FCOE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_HTOEP_FCOE_SHIFT) 2090#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3 2091#define I40E_GLQF_CTL_PCNT_ALLOC_MASK I40E_MASK(0x7, I40E_GLQF_CTL_PCNT_ALLOC_SHIFT) 2092#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT 6 2093#define I40E_GLQF_CTL_FD_AUTO_PCTYPE_MASK I40E_MASK(0x1, I40E_GLQF_CTL_FD_AUTO_PCTYPE_SHIFT) 2094#define I40E_GLQF_CTL_RSVD_SHIFT 7 2095#define I40E_GLQF_CTL_RSVD_MASK I40E_MASK(0x1, I40E_GLQF_CTL_RSVD_SHIFT) 2096#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8 2097#define I40E_GLQF_CTL_MAXPEBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXPEBLEN_SHIFT) 2098#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11 2099#define I40E_GLQF_CTL_MAXFCBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFCBLEN_SHIFT) 2100#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14 2101#define I40E_GLQF_CTL_MAXFDBLEN_MASK I40E_MASK(0x7, I40E_GLQF_CTL_MAXFDBLEN_SHIFT) 2102#define I40E_GLQF_CTL_FDBEST_SHIFT 17 2103#define I40E_GLQF_CTL_FDBEST_MASK I40E_MASK(0xFF, I40E_GLQF_CTL_FDBEST_SHIFT) 2104#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25 2105#define I40E_GLQF_CTL_PROGPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_PROGPRIO_SHIFT) 2106#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26 2107#define I40E_GLQF_CTL_INVALPRIO_MASK I40E_MASK(0x1, I40E_GLQF_CTL_INVALPRIO_SHIFT) 2108#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27 2109#define I40E_GLQF_CTL_IGNORE_IP_MASK I40E_MASK(0x1, I40E_GLQF_CTL_IGNORE_IP_SHIFT) 2110#define I40E_GLQF_FDCNT_0 0x00269BAC /* Reset: CORER */ 2111#define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0 2112#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT) 2113#define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13 2114#define I40E_GLQF_FDCNT_0_BESTCNT_MASK I40E_MASK(0x1FFF, I40E_GLQF_FDCNT_0_BESTCNT_SHIFT) 2115#define I40E_GLQF_HKEY(_i) (0x00270140 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 2116#define I40E_GLQF_HKEY_MAX_INDEX 12 2117#define I40E_GLQF_HKEY_KEY_0_SHIFT 0 2118#define I40E_GLQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_0_SHIFT) 2119#define I40E_GLQF_HKEY_KEY_1_SHIFT 8 2120#define I40E_GLQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_1_SHIFT) 2121#define I40E_GLQF_HKEY_KEY_2_SHIFT 16 2122#define I40E_GLQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_2_SHIFT) 2123#define I40E_GLQF_HKEY_KEY_3_SHIFT 24 2124#define I40E_GLQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_GLQF_HKEY_KEY_3_SHIFT) 2125#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */ /* Reset: CORER */ 2126#define I40E_GLQF_HSYM_MAX_INDEX 63 2127#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0 2128#define I40E_GLQF_HSYM_SYMH_ENA_MASK I40E_MASK(0x1, I40E_GLQF_HSYM_SYMH_ENA_SHIFT) 2129#define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */ /* Reset: CORER */ 2130#define I40E_GLQF_PCNT_MAX_INDEX 511 2131#define I40E_GLQF_PCNT_PCNT_SHIFT 0 2132#define I40E_GLQF_PCNT_PCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLQF_PCNT_PCNT_SHIFT) 2133#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */ /* Reset: CORER */ 2134#define I40E_GLQF_SWAP_MAX_INDEX 1 2135#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0 2136#define I40E_GLQF_SWAP_OFF0_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC0_SHIFT) 2137#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6 2138#define I40E_GLQF_SWAP_OFF0_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF0_SRC1_SHIFT) 2139#define I40E_GLQF_SWAP_FLEN0_SHIFT 12 2140#define I40E_GLQF_SWAP_FLEN0_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN0_SHIFT) 2141#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16 2142#define I40E_GLQF_SWAP_OFF1_SRC0_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC0_SHIFT) 2143#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22 2144#define I40E_GLQF_SWAP_OFF1_SRC1_MASK I40E_MASK(0x3F, I40E_GLQF_SWAP_OFF1_SRC1_SHIFT) 2145#define I40E_GLQF_SWAP_FLEN1_SHIFT 28 2146#define I40E_GLQF_SWAP_FLEN1_MASK I40E_MASK(0xF, I40E_GLQF_SWAP_FLEN1_SHIFT) 2147#define I40E_PFQF_CTL_0 0x001C0AC0 /* Reset: CORER */ 2148#define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0 2149#define I40E_PFQF_CTL_0_PEHSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEHSIZE_SHIFT) 2150#define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5 2151#define I40E_PFQF_CTL_0_PEDSIZE_MASK I40E_MASK(0x1F, I40E_PFQF_CTL_0_PEDSIZE_SHIFT) 2152#define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10 2153#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) 2154#define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14 2155#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) 2156#define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16 2157#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) 2158#define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17 2159#define I40E_PFQF_CTL_0_FD_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_FD_ENA_SHIFT) 2160#define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18 2161#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT) 2162#define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19 2163#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK I40E_MASK(0x1, I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT) 2164#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20 2165#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK I40E_MASK(0xF, I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT) 2166#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24 2167#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK I40E_MASK(0x3, I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT) 2168#define I40E_PFQF_CTL_1 0x00245D80 /* Reset: CORER */ 2169#define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0 2170#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK I40E_MASK(0x1, I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT) 2171#define I40E_PFQF_FDALLOC 0x00246280 /* Reset: CORER */ 2172#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0 2173#define I40E_PFQF_FDALLOC_FDALLOC_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDALLOC_SHIFT) 2174#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8 2175#define I40E_PFQF_FDALLOC_FDBEST_MASK I40E_MASK(0xFF, I40E_PFQF_FDALLOC_FDBEST_SHIFT) 2176#define I40E_PFQF_FDSTAT 0x00246380 /* Reset: CORER */ 2177#define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0 2178#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT) 2179#define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16 2180#define I40E_PFQF_FDSTAT_BEST_CNT_MASK I40E_MASK(0x1FFF, I40E_PFQF_FDSTAT_BEST_CNT_SHIFT) 2181#define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */ /* Reset: CORER */ 2182#define I40E_PFQF_HENA_MAX_INDEX 1 2183#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0 2184#define I40E_PFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_PFQF_HENA_PTYPE_ENA_SHIFT) 2185#define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */ /* Reset: CORER */ 2186#define I40E_PFQF_HKEY_MAX_INDEX 12 2187#define I40E_PFQF_HKEY_KEY_0_SHIFT 0 2188#define I40E_PFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_0_SHIFT) 2189#define I40E_PFQF_HKEY_KEY_1_SHIFT 8 2190#define I40E_PFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_1_SHIFT) 2191#define I40E_PFQF_HKEY_KEY_2_SHIFT 16 2192#define I40E_PFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_2_SHIFT) 2193#define I40E_PFQF_HKEY_KEY_3_SHIFT 24 2194#define I40E_PFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_PFQF_HKEY_KEY_3_SHIFT) 2195#define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */ /* Reset: CORER */ 2196#define I40E_PFQF_HLUT_MAX_INDEX 127 2197#define I40E_PFQF_HLUT_LUT0_SHIFT 0 2198#define I40E_PFQF_HLUT_LUT0_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT0_SHIFT) 2199#define I40E_PFQF_HLUT_LUT1_SHIFT 8 2200#define I40E_PFQF_HLUT_LUT1_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT1_SHIFT) 2201#define I40E_PFQF_HLUT_LUT2_SHIFT 16 2202#define I40E_PFQF_HLUT_LUT2_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT2_SHIFT) 2203#define I40E_PFQF_HLUT_LUT3_SHIFT 24 2204#define I40E_PFQF_HLUT_LUT3_MASK I40E_MASK(0x3F, I40E_PFQF_HLUT_LUT3_SHIFT) 2205#define I40E_PRTQF_CTL_0 0x00256E60 /* Reset: CORER */ 2206#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0 2207#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK I40E_MASK(0x1, I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT) 2208#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */ /* Reset: CORER */ 2209#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63 2210#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0 2211#define I40E_PRTQF_FD_FLXINSET_INSET_MASK I40E_MASK(0xFF, I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) 2212#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */ /* Reset: CORER */ 2213#define I40E_PRTQF_FD_MSK_MAX_INDEX 63 2214#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0 2215#define I40E_PRTQF_FD_MSK_MASK_MASK I40E_MASK(0xFFFF, I40E_PRTQF_FD_MSK_MASK_SHIFT) 2216#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16 2217#define I40E_PRTQF_FD_MSK_OFFSET_MASK I40E_MASK(0x3F, I40E_PRTQF_FD_MSK_OFFSET_SHIFT) 2218#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */ /* Reset: CORER */ 2219#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8 2220#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0 2221#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) 2222#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 5 2223#define I40E_PRTQF_FLX_PIT_FSIZE_MASK I40E_MASK(0x1F, I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) 2224#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10 2225#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK I40E_MASK(0x3F, I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) 2226#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...1, _VF=0...127 */ /* Reset: CORER */ 2227#define I40E_VFQF_HENA1_MAX_INDEX 1 2228#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0 2229#define I40E_VFQF_HENA1_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA1_PTYPE_ENA_SHIFT) 2230#define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */ /* Reset: CORER */ 2231#define I40E_VFQF_HKEY1_MAX_INDEX 12 2232#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0 2233#define I40E_VFQF_HKEY1_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_0_SHIFT) 2234#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8 2235#define I40E_VFQF_HKEY1_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_1_SHIFT) 2236#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16 2237#define I40E_VFQF_HKEY1_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_2_SHIFT) 2238#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24 2239#define I40E_VFQF_HKEY1_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY1_KEY_3_SHIFT) 2240#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */ /* Reset: CORER */ 2241#define I40E_VFQF_HLUT1_MAX_INDEX 15 2242#define I40E_VFQF_HLUT1_LUT0_SHIFT 0 2243#define I40E_VFQF_HLUT1_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT0_SHIFT) 2244#define I40E_VFQF_HLUT1_LUT1_SHIFT 8 2245#define I40E_VFQF_HLUT1_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT1_SHIFT) 2246#define I40E_VFQF_HLUT1_LUT2_SHIFT 16 2247#define I40E_VFQF_HLUT1_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT2_SHIFT) 2248#define I40E_VFQF_HLUT1_LUT3_SHIFT 24 2249#define I40E_VFQF_HLUT1_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT1_LUT3_SHIFT) 2250#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...7, _VF=0...127 */ /* Reset: CORER */ 2251#define I40E_VFQF_HREGION1_MAX_INDEX 7 2252#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0 2253#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT) 2254#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1 2255#define I40E_VFQF_HREGION1_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_0_SHIFT) 2256#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4 2257#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT) 2258#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5 2259#define I40E_VFQF_HREGION1_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_1_SHIFT) 2260#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8 2261#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT) 2262#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9 2263#define I40E_VFQF_HREGION1_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_2_SHIFT) 2264#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12 2265#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT) 2266#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13 2267#define I40E_VFQF_HREGION1_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_3_SHIFT) 2268#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16 2269#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT) 2270#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17 2271#define I40E_VFQF_HREGION1_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_4_SHIFT) 2272#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20 2273#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT) 2274#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21 2275#define I40E_VFQF_HREGION1_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_5_SHIFT) 2276#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24 2277#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT) 2278#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25 2279#define I40E_VFQF_HREGION1_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_6_SHIFT) 2280#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28 2281#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT) 2282#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29 2283#define I40E_VFQF_HREGION1_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION1_REGION_7_SHIFT) 2284#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: VFR */ 2285#define I40E_VPQF_CTL_MAX_INDEX 127 2286#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0 2287#define I40E_VPQF_CTL_PEHSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEHSIZE_SHIFT) 2288#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5 2289#define I40E_VPQF_CTL_PEDSIZE_MASK I40E_MASK(0x1F, I40E_VPQF_CTL_PEDSIZE_SHIFT) 2290#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10 2291#define I40E_VPQF_CTL_FCHSIZE_MASK I40E_MASK(0xF, I40E_VPQF_CTL_FCHSIZE_SHIFT) 2292#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14 2293#define I40E_VPQF_CTL_FCDSIZE_MASK I40E_MASK(0x3, I40E_VPQF_CTL_FCDSIZE_SHIFT) 2294#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: PFR */ 2295#define I40E_VSIQF_CTL_MAX_INDEX 383 2296#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0 2297#define I40E_VSIQF_CTL_FCOE_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_FCOE_ENA_SHIFT) 2298#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1 2299#define I40E_VSIQF_CTL_PETCP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PETCP_ENA_SHIFT) 2300#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2 2301#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT) 2302#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3 2303#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT) 2304#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4 2305#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT) 2306#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5 2307#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK I40E_MASK(0x1, I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT) 2308#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4)) /* _i=0...3, _VSI=0...383 */ /* Reset: PFR */ 2309#define I40E_VSIQF_TCREGION_MAX_INDEX 3 2310#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0 2311#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT) 2312#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9 2313#define I40E_VSIQF_TCREGION_TC_SIZE_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE_SHIFT) 2314#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16 2315#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK I40E_MASK(0x1FF, I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT) 2316#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25 2317#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK I40E_MASK(0x7, I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT) 2318#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2319#define I40E_GL_FCOECRC_MAX_INDEX 143 2320#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0 2321#define I40E_GL_FCOECRC_FCOECRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOECRC_FCOECRC_SHIFT) 2322#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2323#define I40E_GL_FCOEDDPC_MAX_INDEX 143 2324#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0 2325#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT) 2326#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2327#define I40E_GL_FCOEDIFEC_MAX_INDEX 143 2328#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0 2329#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT) 2330#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2331#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143 2332#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0 2333#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT) 2334#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2335#define I40E_GL_FCOEDIXEC_MAX_INDEX 143 2336#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0 2337#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT) 2338#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2339#define I40E_GL_FCOEDIXVC_MAX_INDEX 143 2340#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0 2341#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT) 2342#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2343#define I40E_GL_FCOEDWRCH_MAX_INDEX 143 2344#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0 2345#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT) 2346#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2347#define I40E_GL_FCOEDWRCL_MAX_INDEX 143 2348#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0 2349#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT) 2350#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2351#define I40E_GL_FCOEDWTCH_MAX_INDEX 143 2352#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0 2353#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK I40E_MASK(0xFFFF, I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT) 2354#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2355#define I40E_GL_FCOEDWTCL_MAX_INDEX 143 2356#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0 2357#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT) 2358#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2359#define I40E_GL_FCOELAST_MAX_INDEX 143 2360#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0 2361#define I40E_GL_FCOELAST_FCOELAST_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOELAST_FCOELAST_SHIFT) 2362#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2363#define I40E_GL_FCOEPRC_MAX_INDEX 143 2364#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0 2365#define I40E_GL_FCOEPRC_FCOEPRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPRC_FCOEPRC_SHIFT) 2366#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2367#define I40E_GL_FCOEPTC_MAX_INDEX 143 2368#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0 2369#define I40E_GL_FCOEPTC_FCOEPTC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOEPTC_FCOEPTC_SHIFT) 2370#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2371#define I40E_GL_FCOERPDC_MAX_INDEX 143 2372#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0 2373#define I40E_GL_FCOERPDC_FCOERPDC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_FCOERPDC_FCOERPDC_SHIFT) 2374#define I40E_GL_RXERR1_L(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2375#define I40E_GL_RXERR1_L_MAX_INDEX 143 2376#define I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT 0 2377#define I40E_GL_RXERR1_L_FCOEDIFRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR1_L_FCOEDIFRC_SHIFT) 2378#define I40E_GL_RXERR2_L(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */ /* Reset: CORER */ 2379#define I40E_GL_RXERR2_L_MAX_INDEX 143 2380#define I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT 0 2381#define I40E_GL_RXERR2_L_FCOEDIXAC_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_RXERR2_L_FCOEDIXAC_SHIFT) 2382#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2383#define I40E_GLPRT_BPRCH_MAX_INDEX 3 2384#define I40E_GLPRT_BPRCH_BPRCH_SHIFT 0 2385#define I40E_GLPRT_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPRCH_BPRCH_SHIFT) 2386#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2387#define I40E_GLPRT_BPRCL_MAX_INDEX 3 2388#define I40E_GLPRT_BPRCL_BPRCL_SHIFT 0 2389#define I40E_GLPRT_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPRCL_BPRCL_SHIFT) 2390#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2391#define I40E_GLPRT_BPTCH_MAX_INDEX 3 2392#define I40E_GLPRT_BPTCH_BPTCH_SHIFT 0 2393#define I40E_GLPRT_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_BPTCH_BPTCH_SHIFT) 2394#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2395#define I40E_GLPRT_BPTCL_MAX_INDEX 3 2396#define I40E_GLPRT_BPTCL_BPTCL_SHIFT 0 2397#define I40E_GLPRT_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_BPTCL_BPTCL_SHIFT) 2398#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2399#define I40E_GLPRT_CRCERRS_MAX_INDEX 3 2400#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0 2401#define I40E_GLPRT_CRCERRS_CRCERRS_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_CRCERRS_CRCERRS_SHIFT) 2402#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2403#define I40E_GLPRT_GORCH_MAX_INDEX 3 2404#define I40E_GLPRT_GORCH_GORCH_SHIFT 0 2405#define I40E_GLPRT_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GORCH_GORCH_SHIFT) 2406#define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2407#define I40E_GLPRT_GORCL_MAX_INDEX 3 2408#define I40E_GLPRT_GORCL_GORCL_SHIFT 0 2409#define I40E_GLPRT_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GORCL_GORCL_SHIFT) 2410#define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2411#define I40E_GLPRT_GOTCH_MAX_INDEX 3 2412#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0 2413#define I40E_GLPRT_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_GOTCH_GOTCH_SHIFT) 2414#define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2415#define I40E_GLPRT_GOTCL_MAX_INDEX 3 2416#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0 2417#define I40E_GLPRT_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_GOTCL_GOTCL_SHIFT) 2418#define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2419#define I40E_GLPRT_ILLERRC_MAX_INDEX 3 2420#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0 2421#define I40E_GLPRT_ILLERRC_ILLERRC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ILLERRC_ILLERRC_SHIFT) 2422#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2423#define I40E_GLPRT_LDPC_MAX_INDEX 3 2424#define I40E_GLPRT_LDPC_LDPC_SHIFT 0 2425#define I40E_GLPRT_LDPC_LDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LDPC_LDPC_SHIFT) 2426#define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2427#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3 2428#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0 2429#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT) 2430#define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2431#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3 2432#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0 2433#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT) 2434#define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2435#define I40E_GLPRT_LXONRXC_MAX_INDEX 3 2436#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0 2437#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT) 2438#define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2439#define I40E_GLPRT_LXONTXC_MAX_INDEX 3 2440#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0 2441#define I40E_GLPRT_LXONTXC_LXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_LXONTXC_LXONTXC_SHIFT) 2442#define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2443#define I40E_GLPRT_MLFC_MAX_INDEX 3 2444#define I40E_GLPRT_MLFC_MLFC_SHIFT 0 2445#define I40E_GLPRT_MLFC_MLFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MLFC_MLFC_SHIFT) 2446#define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2447#define I40E_GLPRT_MPRCH_MAX_INDEX 3 2448#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0 2449#define I40E_GLPRT_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPRCH_MPRCH_SHIFT) 2450#define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2451#define I40E_GLPRT_MPRCL_MAX_INDEX 3 2452#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0 2453#define I40E_GLPRT_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPRCL_MPRCL_SHIFT) 2454#define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2455#define I40E_GLPRT_MPTCH_MAX_INDEX 3 2456#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0 2457#define I40E_GLPRT_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_MPTCH_MPTCH_SHIFT) 2458#define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2459#define I40E_GLPRT_MPTCL_MAX_INDEX 3 2460#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0 2461#define I40E_GLPRT_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MPTCL_MPTCL_SHIFT) 2462#define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2463#define I40E_GLPRT_MRFC_MAX_INDEX 3 2464#define I40E_GLPRT_MRFC_MRFC_SHIFT 0 2465#define I40E_GLPRT_MRFC_MRFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_MRFC_MRFC_SHIFT) 2466#define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2467#define I40E_GLPRT_PRC1023H_MAX_INDEX 3 2468#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0 2469#define I40E_GLPRT_PRC1023H_PRC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1023H_PRC1023H_SHIFT) 2470#define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2471#define I40E_GLPRT_PRC1023L_MAX_INDEX 3 2472#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0 2473#define I40E_GLPRT_PRC1023L_PRC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1023L_PRC1023L_SHIFT) 2474#define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2475#define I40E_GLPRT_PRC127H_MAX_INDEX 3 2476#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0 2477#define I40E_GLPRT_PRC127H_PRC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC127H_PRC127H_SHIFT) 2478#define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2479#define I40E_GLPRT_PRC127L_MAX_INDEX 3 2480#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0 2481#define I40E_GLPRT_PRC127L_PRC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC127L_PRC127L_SHIFT) 2482#define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2483#define I40E_GLPRT_PRC1522H_MAX_INDEX 3 2484#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0 2485#define I40E_GLPRT_PRC1522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC1522H_PRC1522H_SHIFT) 2486#define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2487#define I40E_GLPRT_PRC1522L_MAX_INDEX 3 2488#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0 2489#define I40E_GLPRT_PRC1522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC1522L_PRC1522L_SHIFT) 2490#define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2491#define I40E_GLPRT_PRC255H_MAX_INDEX 3 2492#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0 2493#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT) 2494#define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2495#define I40E_GLPRT_PRC255L_MAX_INDEX 3 2496#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0 2497#define I40E_GLPRT_PRC255L_PRC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC255L_PRC255L_SHIFT) 2498#define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2499#define I40E_GLPRT_PRC511H_MAX_INDEX 3 2500#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0 2501#define I40E_GLPRT_PRC511H_PRC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC511H_PRC511H_SHIFT) 2502#define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2503#define I40E_GLPRT_PRC511L_MAX_INDEX 3 2504#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0 2505#define I40E_GLPRT_PRC511L_PRC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC511L_PRC511L_SHIFT) 2506#define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2507#define I40E_GLPRT_PRC64H_MAX_INDEX 3 2508#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0 2509#define I40E_GLPRT_PRC64H_PRC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC64H_PRC64H_SHIFT) 2510#define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2511#define I40E_GLPRT_PRC64L_MAX_INDEX 3 2512#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0 2513#define I40E_GLPRT_PRC64L_PRC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC64L_PRC64L_SHIFT) 2514#define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2515#define I40E_GLPRT_PRC9522H_MAX_INDEX 3 2516#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0 2517#define I40E_GLPRT_PRC9522H_PRC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PRC9522H_PRC1522H_SHIFT) 2518#define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2519#define I40E_GLPRT_PRC9522L_MAX_INDEX 3 2520#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0 2521#define I40E_GLPRT_PRC9522L_PRC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PRC9522L_PRC1522L_SHIFT) 2522#define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2523#define I40E_GLPRT_PTC1023H_MAX_INDEX 3 2524#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0 2525#define I40E_GLPRT_PTC1023H_PTC1023H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1023H_PTC1023H_SHIFT) 2526#define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2527#define I40E_GLPRT_PTC1023L_MAX_INDEX 3 2528#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0 2529#define I40E_GLPRT_PTC1023L_PTC1023L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1023L_PTC1023L_SHIFT) 2530#define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2531#define I40E_GLPRT_PTC127H_MAX_INDEX 3 2532#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0 2533#define I40E_GLPRT_PTC127H_PTC127H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC127H_PTC127H_SHIFT) 2534#define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2535#define I40E_GLPRT_PTC127L_MAX_INDEX 3 2536#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0 2537#define I40E_GLPRT_PTC127L_PTC127L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC127L_PTC127L_SHIFT) 2538#define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2539#define I40E_GLPRT_PTC1522H_MAX_INDEX 3 2540#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0 2541#define I40E_GLPRT_PTC1522H_PTC1522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC1522H_PTC1522H_SHIFT) 2542#define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2543#define I40E_GLPRT_PTC1522L_MAX_INDEX 3 2544#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0 2545#define I40E_GLPRT_PTC1522L_PTC1522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC1522L_PTC1522L_SHIFT) 2546#define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2547#define I40E_GLPRT_PTC255H_MAX_INDEX 3 2548#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0 2549#define I40E_GLPRT_PTC255H_PTC255H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC255H_PTC255H_SHIFT) 2550#define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2551#define I40E_GLPRT_PTC255L_MAX_INDEX 3 2552#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0 2553#define I40E_GLPRT_PTC255L_PTC255L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC255L_PTC255L_SHIFT) 2554#define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2555#define I40E_GLPRT_PTC511H_MAX_INDEX 3 2556#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0 2557#define I40E_GLPRT_PTC511H_PTC511H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC511H_PTC511H_SHIFT) 2558#define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2559#define I40E_GLPRT_PTC511L_MAX_INDEX 3 2560#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0 2561#define I40E_GLPRT_PTC511L_PTC511L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC511L_PTC511L_SHIFT) 2562#define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2563#define I40E_GLPRT_PTC64H_MAX_INDEX 3 2564#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0 2565#define I40E_GLPRT_PTC64H_PTC64H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC64H_PTC64H_SHIFT) 2566#define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2567#define I40E_GLPRT_PTC64L_MAX_INDEX 3 2568#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0 2569#define I40E_GLPRT_PTC64L_PTC64L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC64L_PTC64L_SHIFT) 2570#define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2571#define I40E_GLPRT_PTC9522H_MAX_INDEX 3 2572#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0 2573#define I40E_GLPRT_PTC9522H_PTC9522H_MASK I40E_MASK(0xFFFF, I40E_GLPRT_PTC9522H_PTC9522H_SHIFT) 2574#define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2575#define I40E_GLPRT_PTC9522L_MAX_INDEX 3 2576#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0 2577#define I40E_GLPRT_PTC9522L_PTC9522L_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PTC9522L_PTC9522L_SHIFT) 2578#define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2579#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3 2580#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0 2581#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT) 2582#define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2583#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3 2584#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0 2585#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT) 2586#define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2587#define I40E_GLPRT_PXONRXC_MAX_INDEX 3 2588#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0 2589#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT) 2590#define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2591#define I40E_GLPRT_PXONTXC_MAX_INDEX 3 2592#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0 2593#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT) 2594#define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2595#define I40E_GLPRT_RDPC_MAX_INDEX 3 2596#define I40E_GLPRT_RDPC_RDPC_SHIFT 0 2597#define I40E_GLPRT_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RDPC_RDPC_SHIFT) 2598#define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2599#define I40E_GLPRT_RFC_MAX_INDEX 3 2600#define I40E_GLPRT_RFC_RFC_SHIFT 0 2601#define I40E_GLPRT_RFC_RFC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RFC_RFC_SHIFT) 2602#define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2603#define I40E_GLPRT_RJC_MAX_INDEX 3 2604#define I40E_GLPRT_RJC_RJC_SHIFT 0 2605#define I40E_GLPRT_RJC_RJC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RJC_RJC_SHIFT) 2606#define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2607#define I40E_GLPRT_RLEC_MAX_INDEX 3 2608#define I40E_GLPRT_RLEC_RLEC_SHIFT 0 2609#define I40E_GLPRT_RLEC_RLEC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RLEC_RLEC_SHIFT) 2610#define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2611#define I40E_GLPRT_ROC_MAX_INDEX 3 2612#define I40E_GLPRT_ROC_ROC_SHIFT 0 2613#define I40E_GLPRT_ROC_ROC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_ROC_ROC_SHIFT) 2614#define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2615#define I40E_GLPRT_RUC_MAX_INDEX 3 2616#define I40E_GLPRT_RUC_RUC_SHIFT 0 2617#define I40E_GLPRT_RUC_RUC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUC_RUC_SHIFT) 2618#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2619#define I40E_GLPRT_RUPP_MAX_INDEX 3 2620#define I40E_GLPRT_RUPP_RUPP_SHIFT 0 2621#define I40E_GLPRT_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RUPP_RUPP_SHIFT) 2622#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32)) /* _i=0...3, _j=0...7 */ /* Reset: CORER */ 2623#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3 2624#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0 2625#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT) 2626#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2627#define I40E_GLPRT_TDOLD_MAX_INDEX 3 2628#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0 2629#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT) 2630#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2631#define I40E_GLPRT_UPRCH_MAX_INDEX 3 2632#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0 2633#define I40E_GLPRT_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPRCH_UPRCH_SHIFT) 2634#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2635#define I40E_GLPRT_UPRCL_MAX_INDEX 3 2636#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0 2637#define I40E_GLPRT_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPRCL_UPRCL_SHIFT) 2638#define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2639#define I40E_GLPRT_UPTCH_MAX_INDEX 3 2640#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0 2641#define I40E_GLPRT_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLPRT_UPTCH_UPTCH_SHIFT) 2642#define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */ /* Reset: CORER */ 2643#define I40E_GLPRT_UPTCL_MAX_INDEX 3 2644#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0 2645#define I40E_GLPRT_UPTCL_VUPTCH_MASK I40E_MASK(0xFFFFFFFF, I40E_GLPRT_UPTCL_VUPTCH_SHIFT) 2646#define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2647#define I40E_GLSW_BPRCH_MAX_INDEX 15 2648#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0 2649#define I40E_GLSW_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPRCH_BPRCH_SHIFT) 2650#define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2651#define I40E_GLSW_BPRCL_MAX_INDEX 15 2652#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0 2653#define I40E_GLSW_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPRCL_BPRCL_SHIFT) 2654#define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2655#define I40E_GLSW_BPTCH_MAX_INDEX 15 2656#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0 2657#define I40E_GLSW_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_BPTCH_BPTCH_SHIFT) 2658#define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2659#define I40E_GLSW_BPTCL_MAX_INDEX 15 2660#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0 2661#define I40E_GLSW_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_BPTCL_BPTCL_SHIFT) 2662#define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2663#define I40E_GLSW_GORCH_MAX_INDEX 15 2664#define I40E_GLSW_GORCH_GORCH_SHIFT 0 2665#define I40E_GLSW_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GORCH_GORCH_SHIFT) 2666#define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2667#define I40E_GLSW_GORCL_MAX_INDEX 15 2668#define I40E_GLSW_GORCL_GORCL_SHIFT 0 2669#define I40E_GLSW_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GORCL_GORCL_SHIFT) 2670#define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2671#define I40E_GLSW_GOTCH_MAX_INDEX 15 2672#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0 2673#define I40E_GLSW_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_GOTCH_GOTCH_SHIFT) 2674#define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2675#define I40E_GLSW_GOTCL_MAX_INDEX 15 2676#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0 2677#define I40E_GLSW_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_GOTCL_GOTCL_SHIFT) 2678#define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2679#define I40E_GLSW_MPRCH_MAX_INDEX 15 2680#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0 2681#define I40E_GLSW_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPRCH_MPRCH_SHIFT) 2682#define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2683#define I40E_GLSW_MPRCL_MAX_INDEX 15 2684#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0 2685#define I40E_GLSW_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPRCL_MPRCL_SHIFT) 2686#define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2687#define I40E_GLSW_MPTCH_MAX_INDEX 15 2688#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0 2689#define I40E_GLSW_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_MPTCH_MPTCH_SHIFT) 2690#define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2691#define I40E_GLSW_MPTCL_MAX_INDEX 15 2692#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0 2693#define I40E_GLSW_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_MPTCL_MPTCL_SHIFT) 2694#define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2695#define I40E_GLSW_RUPP_MAX_INDEX 15 2696#define I40E_GLSW_RUPP_RUPP_SHIFT 0 2697#define I40E_GLSW_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_RUPP_RUPP_SHIFT) 2698#define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2699#define I40E_GLSW_TDPC_MAX_INDEX 15 2700#define I40E_GLSW_TDPC_TDPC_SHIFT 0 2701#define I40E_GLSW_TDPC_TDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_TDPC_TDPC_SHIFT) 2702#define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2703#define I40E_GLSW_UPRCH_MAX_INDEX 15 2704#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0 2705#define I40E_GLSW_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPRCH_UPRCH_SHIFT) 2706#define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2707#define I40E_GLSW_UPRCL_MAX_INDEX 15 2708#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0 2709#define I40E_GLSW_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPRCL_UPRCL_SHIFT) 2710#define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2711#define I40E_GLSW_UPTCH_MAX_INDEX 15 2712#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0 2713#define I40E_GLSW_UPTCH_UPTCH_MASK I40E_MASK(0xFFFF, I40E_GLSW_UPTCH_UPTCH_SHIFT) 2714#define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: CORER */ 2715#define I40E_GLSW_UPTCL_MAX_INDEX 15 2716#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0 2717#define I40E_GLSW_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLSW_UPTCL_UPTCL_SHIFT) 2718#define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2719#define I40E_GLV_BPRCH_MAX_INDEX 383 2720#define I40E_GLV_BPRCH_BPRCH_SHIFT 0 2721#define I40E_GLV_BPRCH_BPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPRCH_BPRCH_SHIFT) 2722#define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2723#define I40E_GLV_BPRCL_MAX_INDEX 383 2724#define I40E_GLV_BPRCL_BPRCL_SHIFT 0 2725#define I40E_GLV_BPRCL_BPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPRCL_BPRCL_SHIFT) 2726#define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2727#define I40E_GLV_BPTCH_MAX_INDEX 383 2728#define I40E_GLV_BPTCH_BPTCH_SHIFT 0 2729#define I40E_GLV_BPTCH_BPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_BPTCH_BPTCH_SHIFT) 2730#define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2731#define I40E_GLV_BPTCL_MAX_INDEX 383 2732#define I40E_GLV_BPTCL_BPTCL_SHIFT 0 2733#define I40E_GLV_BPTCL_BPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_BPTCL_BPTCL_SHIFT) 2734#define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2735#define I40E_GLV_GORCH_MAX_INDEX 383 2736#define I40E_GLV_GORCH_GORCH_SHIFT 0 2737#define I40E_GLV_GORCH_GORCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GORCH_GORCH_SHIFT) 2738#define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2739#define I40E_GLV_GORCL_MAX_INDEX 383 2740#define I40E_GLV_GORCL_GORCL_SHIFT 0 2741#define I40E_GLV_GORCL_GORCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GORCL_GORCL_SHIFT) 2742#define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2743#define I40E_GLV_GOTCH_MAX_INDEX 383 2744#define I40E_GLV_GOTCH_GOTCH_SHIFT 0 2745#define I40E_GLV_GOTCH_GOTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_GOTCH_GOTCH_SHIFT) 2746#define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2747#define I40E_GLV_GOTCL_MAX_INDEX 383 2748#define I40E_GLV_GOTCL_GOTCL_SHIFT 0 2749#define I40E_GLV_GOTCL_GOTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_GOTCL_GOTCL_SHIFT) 2750#define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2751#define I40E_GLV_MPRCH_MAX_INDEX 383 2752#define I40E_GLV_MPRCH_MPRCH_SHIFT 0 2753#define I40E_GLV_MPRCH_MPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPRCH_MPRCH_SHIFT) 2754#define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2755#define I40E_GLV_MPRCL_MAX_INDEX 383 2756#define I40E_GLV_MPRCL_MPRCL_SHIFT 0 2757#define I40E_GLV_MPRCL_MPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPRCL_MPRCL_SHIFT) 2758#define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2759#define I40E_GLV_MPTCH_MAX_INDEX 383 2760#define I40E_GLV_MPTCH_MPTCH_SHIFT 0 2761#define I40E_GLV_MPTCH_MPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_MPTCH_MPTCH_SHIFT) 2762#define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2763#define I40E_GLV_MPTCL_MAX_INDEX 383 2764#define I40E_GLV_MPTCL_MPTCL_SHIFT 0 2765#define I40E_GLV_MPTCL_MPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_MPTCL_MPTCL_SHIFT) 2766#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2767#define I40E_GLV_RDPC_MAX_INDEX 383 2768#define I40E_GLV_RDPC_RDPC_SHIFT 0 2769#define I40E_GLV_RDPC_RDPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RDPC_RDPC_SHIFT) 2770#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2771#define I40E_GLV_RUPP_MAX_INDEX 383 2772#define I40E_GLV_RUPP_RUPP_SHIFT 0 2773#define I40E_GLV_RUPP_RUPP_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_RUPP_RUPP_SHIFT) 2774#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 4)) /* _i=0...383 */ /* Reset: CORER */ 2775#define I40E_GLV_TEPC_MAX_INDEX 383 2776#define I40E_GLV_TEPC_TEPC_SHIFT 0 2777#define I40E_GLV_TEPC_TEPC_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_TEPC_TEPC_SHIFT) 2778#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2779#define I40E_GLV_UPRCH_MAX_INDEX 383 2780#define I40E_GLV_UPRCH_UPRCH_SHIFT 0 2781#define I40E_GLV_UPRCH_UPRCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPRCH_UPRCH_SHIFT) 2782#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2783#define I40E_GLV_UPRCL_MAX_INDEX 383 2784#define I40E_GLV_UPRCL_UPRCL_SHIFT 0 2785#define I40E_GLV_UPRCL_UPRCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPRCL_UPRCL_SHIFT) 2786#define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2787#define I40E_GLV_UPTCH_MAX_INDEX 383 2788#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0 2789#define I40E_GLV_UPTCH_GLVUPTCH_MASK I40E_MASK(0xFFFF, I40E_GLV_UPTCH_GLVUPTCH_SHIFT) 2790#define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */ /* Reset: CORER */ 2791#define I40E_GLV_UPTCL_MAX_INDEX 383 2792#define I40E_GLV_UPTCL_UPTCL_SHIFT 0 2793#define I40E_GLV_UPTCL_UPTCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLV_UPTCL_UPTCL_SHIFT) 2794#define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2795#define I40E_GLVEBTC_RBCH_MAX_INDEX 7 2796#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0 2797#define I40E_GLVEBTC_RBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RBCH_TCBCH_SHIFT) 2798#define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2799#define I40E_GLVEBTC_RBCL_MAX_INDEX 7 2800#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0 2801#define I40E_GLVEBTC_RBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RBCL_TCBCL_SHIFT) 2802#define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2803#define I40E_GLVEBTC_RPCH_MAX_INDEX 7 2804#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0 2805#define I40E_GLVEBTC_RPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_RPCH_TCPCH_SHIFT) 2806#define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2807#define I40E_GLVEBTC_RPCL_MAX_INDEX 7 2808#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0 2809#define I40E_GLVEBTC_RPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_RPCL_TCPCL_SHIFT) 2810#define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2811#define I40E_GLVEBTC_TBCH_MAX_INDEX 7 2812#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0 2813#define I40E_GLVEBTC_TBCH_TCBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TBCH_TCBCH_SHIFT) 2814#define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2815#define I40E_GLVEBTC_TBCL_MAX_INDEX 7 2816#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0 2817#define I40E_GLVEBTC_TBCL_TCBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TBCL_TCBCL_SHIFT) 2818#define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2819#define I40E_GLVEBTC_TPCH_MAX_INDEX 7 2820#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0 2821#define I40E_GLVEBTC_TPCH_TCPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBTC_TPCH_TCPCH_SHIFT) 2822#define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */ /* Reset: CORER */ 2823#define I40E_GLVEBTC_TPCL_MAX_INDEX 7 2824#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0 2825#define I40E_GLVEBTC_TPCL_TCPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBTC_TPCL_TCPCL_SHIFT) 2826#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2827#define I40E_GLVEBVL_BPCH_MAX_INDEX 127 2828#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0 2829#define I40E_GLVEBVL_BPCH_VLBPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_BPCH_VLBPCH_SHIFT) 2830#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2831#define I40E_GLVEBVL_BPCL_MAX_INDEX 127 2832#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0 2833#define I40E_GLVEBVL_BPCL_VLBPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_BPCL_VLBPCL_SHIFT) 2834#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2835#define I40E_GLVEBVL_GORCH_MAX_INDEX 127 2836#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0 2837#define I40E_GLVEBVL_GORCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GORCH_VLBCH_SHIFT) 2838#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2839#define I40E_GLVEBVL_GORCL_MAX_INDEX 127 2840#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0 2841#define I40E_GLVEBVL_GORCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GORCL_VLBCL_SHIFT) 2842#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2843#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127 2844#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0 2845#define I40E_GLVEBVL_GOTCH_VLBCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_GOTCH_VLBCH_SHIFT) 2846#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2847#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127 2848#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0 2849#define I40E_GLVEBVL_GOTCL_VLBCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_GOTCL_VLBCL_SHIFT) 2850#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2851#define I40E_GLVEBVL_MPCH_MAX_INDEX 127 2852#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0 2853#define I40E_GLVEBVL_MPCH_VLMPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_MPCH_VLMPCH_SHIFT) 2854#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2855#define I40E_GLVEBVL_MPCL_MAX_INDEX 127 2856#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0 2857#define I40E_GLVEBVL_MPCL_VLMPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_MPCL_VLMPCL_SHIFT) 2858#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2859#define I40E_GLVEBVL_UPCH_MAX_INDEX 127 2860#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0 2861#define I40E_GLVEBVL_UPCH_VLUPCH_MASK I40E_MASK(0xFFFF, I40E_GLVEBVL_UPCH_VLUPCH_SHIFT) 2862#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */ /* Reset: CORER */ 2863#define I40E_GLVEBVL_UPCL_MAX_INDEX 127 2864#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0 2865#define I40E_GLVEBVL_UPCL_VLUPCL_MASK I40E_MASK(0xFFFFFFFF, I40E_GLVEBVL_UPCL_VLUPCL_SHIFT) 2866#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C /* Reset: CORER */ 2867#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0 2868#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK I40E_MASK(0xFFFF, I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT) 2869#define I40E_GL_SWR_DEF_ACT(_i) (0x00270200 + ((_i) * 4)) /* _i=0...35 */ /* Reset: CORER */ 2870#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 35 2871#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0 2872#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT) 2873#define I40E_GL_SWR_DEF_ACT_EN(_i) (0x0026CFB8 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 2874#define I40E_GL_SWR_DEF_ACT_EN_MAX_INDEX 1 2875#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0 2876#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK I40E_MASK(0xFFFFFFFF, I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT) 2877#define I40E_PRTTSYN_ADJ 0x001E4280 /* Reset: GLOBR */ 2878#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0 2879#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK I40E_MASK(0x7FFFFFFF, I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT) 2880#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31 2881#define I40E_PRTTSYN_ADJ_SIGN_MASK I40E_MASK(0x1, I40E_PRTTSYN_ADJ_SIGN_SHIFT) 2882#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2883#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1 2884#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0 2885#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT) 2886#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1 2887#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT) 2888#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3 2889#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT) 2890#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8 2891#define I40E_PRTTSYN_AUX_0_PULSEW_MASK I40E_MASK(0xF, I40E_PRTTSYN_AUX_0_PULSEW_SHIFT) 2892#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16 2893#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK I40E_MASK(0x3, I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT) 2894#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2895#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1 2896#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0 2897#define I40E_PRTTSYN_AUX_1_INSTNT_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_INSTNT_SHIFT) 2898#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1 2899#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT) 2900#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2901#define I40E_PRTTSYN_CLKO_MAX_INDEX 1 2902#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0 2903#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT) 2904#define I40E_PRTTSYN_CTL0 0x001E4200 /* Reset: GLOBR */ 2905#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0 2906#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT) 2907#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1 2908#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT) 2909#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2 2910#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT) 2911#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3 2912#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT) 2913#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8 2914#define I40E_PRTTSYN_CTL0_PF_ID_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL0_PF_ID_SHIFT) 2915#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12 2916#define I40E_PRTTSYN_CTL0_TSYNACT_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL0_TSYNACT_SHIFT) 2917#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31 2918#define I40E_PRTTSYN_CTL0_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL0_TSYNENA_SHIFT) 2919#define I40E_PRTTSYN_CTL1 0x00085020 /* Reset: CORER */ 2920#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0 2921#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT) 2922#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8 2923#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK I40E_MASK(0xFF, I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT) 2924#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16 2925#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT) 2926#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20 2927#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK I40E_MASK(0xF, I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT) 2928#define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24 2929#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT) 2930#define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26 2931#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK I40E_MASK(0x3, I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT) 2932#define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31 2933#define I40E_PRTTSYN_CTL1_TSYNENA_MASK I40E_MASK(0x1, I40E_PRTTSYN_CTL1_TSYNENA_SHIFT) 2934#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2935#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1 2936#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0 2937#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT) 2938#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2939#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1 2940#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0 2941#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT) 2942#define I40E_PRTTSYN_INC_H 0x001E4060 /* Reset: GLOBR */ 2943#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0 2944#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK I40E_MASK(0x3F, I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT) 2945#define I40E_PRTTSYN_INC_L 0x001E4040 /* Reset: GLOBR */ 2946#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0 2947#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT) 2948#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 2949#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3 2950#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0 2951#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT) 2952#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: CORER */ 2953#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3 2954#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0 2955#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT) 2956#define I40E_PRTTSYN_STAT_0 0x001E4220 /* Reset: GLOBR */ 2957#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0 2958#define I40E_PRTTSYN_STAT_0_EVENT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT0_SHIFT) 2959#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1 2960#define I40E_PRTTSYN_STAT_0_EVENT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_EVENT1_SHIFT) 2961#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2 2962#define I40E_PRTTSYN_STAT_0_TGT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT0_SHIFT) 2963#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3 2964#define I40E_PRTTSYN_STAT_0_TGT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TGT1_SHIFT) 2965#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4 2966#define I40E_PRTTSYN_STAT_0_TXTIME_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_0_TXTIME_SHIFT) 2967#define I40E_PRTTSYN_STAT_1 0x00085140 /* Reset: CORER */ 2968#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0 2969#define I40E_PRTTSYN_STAT_1_RXT0_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT0_SHIFT) 2970#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1 2971#define I40E_PRTTSYN_STAT_1_RXT1_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT1_SHIFT) 2972#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2 2973#define I40E_PRTTSYN_STAT_1_RXT2_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT2_SHIFT) 2974#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3 2975#define I40E_PRTTSYN_STAT_1_RXT3_MASK I40E_MASK(0x1, I40E_PRTTSYN_STAT_1_RXT3_SHIFT) 2976#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2977#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1 2978#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0 2979#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT) 2980#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */ /* Reset: GLOBR */ 2981#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1 2982#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0 2983#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT) 2984#define I40E_PRTTSYN_TIME_H 0x001E4120 /* Reset: GLOBR */ 2985#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0 2986#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT) 2987#define I40E_PRTTSYN_TIME_L 0x001E4100 /* Reset: GLOBR */ 2988#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0 2989#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT) 2990#define I40E_PRTTSYN_TXTIME_H 0x001E41E0 /* Reset: GLOBR */ 2991#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0 2992#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT) 2993#define I40E_PRTTSYN_TXTIME_L 0x001E41C0 /* Reset: GLOBR */ 2994#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0 2995#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT) 2996#define I40E_GL_MDET_RX 0x0012A510 /* Reset: CORER */ 2997#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0 2998#define I40E_GL_MDET_RX_FUNCTION_MASK I40E_MASK(0xFF, I40E_GL_MDET_RX_FUNCTION_SHIFT) 2999#define I40E_GL_MDET_RX_EVENT_SHIFT 8 3000#define I40E_GL_MDET_RX_EVENT_MASK I40E_MASK(0x1FF, I40E_GL_MDET_RX_EVENT_SHIFT) 3001#define I40E_GL_MDET_RX_QUEUE_SHIFT 17 3002#define I40E_GL_MDET_RX_QUEUE_MASK I40E_MASK(0x3FFF, I40E_GL_MDET_RX_QUEUE_SHIFT) 3003#define I40E_GL_MDET_RX_VALID_SHIFT 31 3004#define I40E_GL_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_RX_VALID_SHIFT) 3005#define I40E_GL_MDET_TX 0x000E6480 /* Reset: CORER */ 3006#define I40E_GL_MDET_TX_QUEUE_SHIFT 0 3007#define I40E_GL_MDET_TX_QUEUE_MASK I40E_MASK(0xFFF, I40E_GL_MDET_TX_QUEUE_SHIFT) 3008#define I40E_GL_MDET_TX_VF_NUM_SHIFT 12 3009#define I40E_GL_MDET_TX_VF_NUM_MASK I40E_MASK(0x1FF, I40E_GL_MDET_TX_VF_NUM_SHIFT) 3010#define I40E_GL_MDET_TX_PF_NUM_SHIFT 21 3011#define I40E_GL_MDET_TX_PF_NUM_MASK I40E_MASK(0xF, I40E_GL_MDET_TX_PF_NUM_SHIFT) 3012#define I40E_GL_MDET_TX_EVENT_SHIFT 25 3013#define I40E_GL_MDET_TX_EVENT_MASK I40E_MASK(0x1F, I40E_GL_MDET_TX_EVENT_SHIFT) 3014#define I40E_GL_MDET_TX_VALID_SHIFT 31 3015#define I40E_GL_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_GL_MDET_TX_VALID_SHIFT) 3016#define I40E_PF_MDET_RX 0x0012A400 /* Reset: CORER */ 3017#define I40E_PF_MDET_RX_VALID_SHIFT 0 3018#define I40E_PF_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_RX_VALID_SHIFT) 3019#define I40E_PF_MDET_TX 0x000E6400 /* Reset: CORER */ 3020#define I40E_PF_MDET_TX_VALID_SHIFT 0 3021#define I40E_PF_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_PF_MDET_TX_VALID_SHIFT) 3022#define I40E_PF_VT_PFALLOC 0x001C0500 /* Reset: CORER */ 3023#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0 3024#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT) 3025#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8 3026#define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT) 3027#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31 3028#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT) 3029#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3030#define I40E_VP_MDET_RX_MAX_INDEX 127 3031#define I40E_VP_MDET_RX_VALID_SHIFT 0 3032#define I40E_VP_MDET_RX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_RX_VALID_SHIFT) 3033#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */ 3034#define I40E_VP_MDET_TX_MAX_INDEX 127 3035#define I40E_VP_MDET_TX_VALID_SHIFT 0 3036#define I40E_VP_MDET_TX_VALID_MASK I40E_MASK(0x1, I40E_VP_MDET_TX_VALID_SHIFT) 3037#define I40E_GLPM_WUMC 0x0006C800 /* Reset: POR */ 3038#define I40E_GLPM_WUMC_NOTCO_SHIFT 0 3039#define I40E_GLPM_WUMC_NOTCO_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_NOTCO_SHIFT) 3040#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1 3041#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT) 3042#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2 3043#define I40E_GLPM_WUMC_ROL_MODE_MASK I40E_MASK(0x1, I40E_GLPM_WUMC_ROL_MODE_SHIFT) 3044#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3 3045#define I40E_GLPM_WUMC_RESERVED_4_MASK I40E_MASK(0x1FFF, I40E_GLPM_WUMC_RESERVED_4_SHIFT) 3046#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16 3047#define I40E_GLPM_WUMC_MNG_WU_PF_MASK I40E_MASK(0xFFFF, I40E_GLPM_WUMC_MNG_WU_PF_SHIFT) 3048#define I40E_PFPM_APM 0x000B8080 /* Reset: POR */ 3049#define I40E_PFPM_APM_APME_SHIFT 0 3050#define I40E_PFPM_APM_APME_MASK I40E_MASK(0x1, I40E_PFPM_APM_APME_SHIFT) 3051#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */ /* Reset: POR */ 3052#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7 3053#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0 3054#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK I40E_MASK(0xFF, I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT) 3055#define I40E_PFPM_WUC 0x0006B200 /* Reset: POR */ 3056#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5 3057#define I40E_PFPM_WUC_EN_APM_D0_MASK I40E_MASK(0x1, I40E_PFPM_WUC_EN_APM_D0_SHIFT) 3058#define I40E_PFPM_WUFC 0x0006B400 /* Reset: POR */ 3059#define I40E_PFPM_WUFC_LNKC_SHIFT 0 3060#define I40E_PFPM_WUFC_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_LNKC_SHIFT) 3061#define I40E_PFPM_WUFC_MAG_SHIFT 1 3062#define I40E_PFPM_WUFC_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MAG_SHIFT) 3063#define I40E_PFPM_WUFC_MNG_SHIFT 3 3064#define I40E_PFPM_WUFC_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_MNG_SHIFT) 3065#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4 3066#define I40E_PFPM_WUFC_FLX0_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_ACT_SHIFT) 3067#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5 3068#define I40E_PFPM_WUFC_FLX1_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_ACT_SHIFT) 3069#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6 3070#define I40E_PFPM_WUFC_FLX2_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_ACT_SHIFT) 3071#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7 3072#define I40E_PFPM_WUFC_FLX3_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_ACT_SHIFT) 3073#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8 3074#define I40E_PFPM_WUFC_FLX4_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_ACT_SHIFT) 3075#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9 3076#define I40E_PFPM_WUFC_FLX5_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_ACT_SHIFT) 3077#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10 3078#define I40E_PFPM_WUFC_FLX6_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_ACT_SHIFT) 3079#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11 3080#define I40E_PFPM_WUFC_FLX7_ACT_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_ACT_SHIFT) 3081#define I40E_PFPM_WUFC_FLX0_SHIFT 16 3082#define I40E_PFPM_WUFC_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX0_SHIFT) 3083#define I40E_PFPM_WUFC_FLX1_SHIFT 17 3084#define I40E_PFPM_WUFC_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX1_SHIFT) 3085#define I40E_PFPM_WUFC_FLX2_SHIFT 18 3086#define I40E_PFPM_WUFC_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX2_SHIFT) 3087#define I40E_PFPM_WUFC_FLX3_SHIFT 19 3088#define I40E_PFPM_WUFC_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX3_SHIFT) 3089#define I40E_PFPM_WUFC_FLX4_SHIFT 20 3090#define I40E_PFPM_WUFC_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX4_SHIFT) 3091#define I40E_PFPM_WUFC_FLX5_SHIFT 21 3092#define I40E_PFPM_WUFC_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX5_SHIFT) 3093#define I40E_PFPM_WUFC_FLX6_SHIFT 22 3094#define I40E_PFPM_WUFC_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX6_SHIFT) 3095#define I40E_PFPM_WUFC_FLX7_SHIFT 23 3096#define I40E_PFPM_WUFC_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FLX7_SHIFT) 3097#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31 3098#define I40E_PFPM_WUFC_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUFC_FW_RST_WK_SHIFT) 3099#define I40E_PFPM_WUS 0x0006B600 /* Reset: POR */ 3100#define I40E_PFPM_WUS_LNKC_SHIFT 0 3101#define I40E_PFPM_WUS_LNKC_MASK I40E_MASK(0x1, I40E_PFPM_WUS_LNKC_SHIFT) 3102#define I40E_PFPM_WUS_MAG_SHIFT 1 3103#define I40E_PFPM_WUS_MAG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MAG_SHIFT) 3104#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2 3105#define I40E_PFPM_WUS_PME_STATUS_MASK I40E_MASK(0x1, I40E_PFPM_WUS_PME_STATUS_SHIFT) 3106#define I40E_PFPM_WUS_MNG_SHIFT 3 3107#define I40E_PFPM_WUS_MNG_MASK I40E_MASK(0x1, I40E_PFPM_WUS_MNG_SHIFT) 3108#define I40E_PFPM_WUS_FLX0_SHIFT 16 3109#define I40E_PFPM_WUS_FLX0_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX0_SHIFT) 3110#define I40E_PFPM_WUS_FLX1_SHIFT 17 3111#define I40E_PFPM_WUS_FLX1_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX1_SHIFT) 3112#define I40E_PFPM_WUS_FLX2_SHIFT 18 3113#define I40E_PFPM_WUS_FLX2_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX2_SHIFT) 3114#define I40E_PFPM_WUS_FLX3_SHIFT 19 3115#define I40E_PFPM_WUS_FLX3_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX3_SHIFT) 3116#define I40E_PFPM_WUS_FLX4_SHIFT 20 3117#define I40E_PFPM_WUS_FLX4_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX4_SHIFT) 3118#define I40E_PFPM_WUS_FLX5_SHIFT 21 3119#define I40E_PFPM_WUS_FLX5_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX5_SHIFT) 3120#define I40E_PFPM_WUS_FLX6_SHIFT 22 3121#define I40E_PFPM_WUS_FLX6_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX6_SHIFT) 3122#define I40E_PFPM_WUS_FLX7_SHIFT 23 3123#define I40E_PFPM_WUS_FLX7_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FLX7_SHIFT) 3124#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31 3125#define I40E_PFPM_WUS_FW_RST_WK_MASK I40E_MASK(0x1, I40E_PFPM_WUS_FW_RST_WK_SHIFT) 3126#define I40E_PRTPM_FHFHR 0x0006C000 /* Reset: POR */ 3127#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0 3128#define I40E_PRTPM_FHFHR_UNICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_UNICAST_SHIFT) 3129#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1 3130#define I40E_PRTPM_FHFHR_MULTICAST_MASK I40E_MASK(0x1, I40E_PRTPM_FHFHR_MULTICAST_SHIFT) 3131#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */ 3132#define I40E_PRTPM_SAH_MAX_INDEX 3 3133#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0 3134#define I40E_PRTPM_SAH_PFPM_SAH_MASK I40E_MASK(0xFFFF, I40E_PRTPM_SAH_PFPM_SAH_SHIFT) 3135#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26 3136#define I40E_PRTPM_SAH_PF_NUM_MASK I40E_MASK(0xF, I40E_PRTPM_SAH_PF_NUM_SHIFT) 3137#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30 3138#define I40E_PRTPM_SAH_MC_MAG_EN_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_MC_MAG_EN_SHIFT) 3139#define I40E_PRTPM_SAH_AV_SHIFT 31 3140#define I40E_PRTPM_SAH_AV_MASK I40E_MASK(0x1, I40E_PRTPM_SAH_AV_SHIFT) 3141#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */ /* Reset: PFR */ 3142#define I40E_PRTPM_SAL_MAX_INDEX 3 3143#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0 3144#define I40E_PRTPM_SAL_PFPM_SAL_MASK I40E_MASK(0xFFFFFFFF, I40E_PRTPM_SAL_PFPM_SAL_SHIFT) 3145#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ 3146#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 3147#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT) 3148#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ 3149#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 3150#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT) 3151#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ 3152#define I40E_VF_ARQH1_ARQH_SHIFT 0 3153#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT) 3154#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ 3155#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 3156#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) 3157#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 3158#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) 3159#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 3160#define I40E_VF_ARQLEN1_ARQOVFL_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQOVFL_SHIFT) 3161#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30 3162#define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT) 3163#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 3164#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) 3165#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ 3166#define I40E_VF_ARQT1_ARQT_SHIFT 0 3167#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) 3168#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ 3169#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 3170#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) 3171#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ 3172#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 3173#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT) 3174#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ 3175#define I40E_VF_ATQH1_ATQH_SHIFT 0 3176#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT) 3177#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ 3178#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 3179#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) 3180#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 3181#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) 3182#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 3183#define I40E_VF_ATQLEN1_ATQOVFL_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQOVFL_SHIFT) 3184#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30 3185#define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT) 3186#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 3187#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) 3188#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ 3189#define I40E_VF_ATQT1_ATQT_SHIFT 0 3190#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) 3191#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ 3192#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 3193#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) 3194#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ 3195#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 3196#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT) 3197#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 3198#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) 3199#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 3200#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) 3201#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 3202#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) 3203#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 3204#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) 3205#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 3206#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) 3207#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 3208#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) 3209#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 3210#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) 3211#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ 3212#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 3213#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 3214#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) 3215#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 3216#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) 3217#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 3218#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) 3219#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 3220#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) 3221#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 3222#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) 3223#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 3224#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) 3225#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 3226#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) 3227#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 3228#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) 3229#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ 3230#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 3231#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) 3232#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 3233#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) 3234#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 3235#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) 3236#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ 3237#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 3238#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT) 3239#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 3240#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT) 3241#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 3242#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT) 3243#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 3244#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT) 3245#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 3246#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT) 3247#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 3248#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) 3249#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 3250#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT) 3251#define I40E_VFINT_ICR01_SWINT_SHIFT 31 3252#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT) 3253#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ 3254#define I40E_VFINT_ITR01_MAX_INDEX 2 3255#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 3256#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) 3257#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ 3258#define I40E_VFINT_ITRN1_MAX_INDEX 2 3259#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 3260#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) 3261#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ 3262#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 3263#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) 3264#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3265#define I40E_QRX_TAIL1_MAX_INDEX 15 3266#define I40E_QRX_TAIL1_TAIL_SHIFT 0 3267#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) 3268#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ 3269#define I40E_QTX_TAIL1_MAX_INDEX 15 3270#define I40E_QTX_TAIL1_TAIL_SHIFT 0 3271#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT) 3272#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ 3273#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 3274#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT) 3275#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3276#define I40E_VFMSIX_TADD_MAX_INDEX 16 3277#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 3278#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) 3279#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 3280#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT) 3281#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3282#define I40E_VFMSIX_TMSG_MAX_INDEX 16 3283#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 3284#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) 3285#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3286#define I40E_VFMSIX_TUADD_MAX_INDEX 16 3287#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 3288#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) 3289#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ 3290#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 3291#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 3292#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT) 3293#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ 3294#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 3295#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) 3296#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 3297#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) 3298#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 3299#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) 3300#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ 3301#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 3302#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) 3303#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 3304#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) 3305#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 3306#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) 3307#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 3308#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) 3309#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 3310#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) 3311#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ 3312#define I40E_VFQF_HENA_MAX_INDEX 1 3313#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 3314#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT) 3315#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ 3316#define I40E_VFQF_HKEY_MAX_INDEX 12 3317#define I40E_VFQF_HKEY_KEY_0_SHIFT 0 3318#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT) 3319#define I40E_VFQF_HKEY_KEY_1_SHIFT 8 3320#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT) 3321#define I40E_VFQF_HKEY_KEY_2_SHIFT 16 3322#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT) 3323#define I40E_VFQF_HKEY_KEY_3_SHIFT 24 3324#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT) 3325#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ 3326#define I40E_VFQF_HLUT_MAX_INDEX 15 3327#define I40E_VFQF_HLUT_LUT0_SHIFT 0 3328#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT) 3329#define I40E_VFQF_HLUT_LUT1_SHIFT 8 3330#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT) 3331#define I40E_VFQF_HLUT_LUT2_SHIFT 16 3332#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT) 3333#define I40E_VFQF_HLUT_LUT3_SHIFT 24 3334#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT) 3335#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ 3336#define I40E_VFQF_HREGION_MAX_INDEX 7 3337#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 3338#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) 3339#define I40E_VFQF_HREGION_REGION_0_SHIFT 1 3340#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT) 3341#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 3342#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) 3343#define I40E_VFQF_HREGION_REGION_1_SHIFT 5 3344#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT) 3345#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 3346#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) 3347#define I40E_VFQF_HREGION_REGION_2_SHIFT 9 3348#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT) 3349#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 3350#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) 3351#define I40E_VFQF_HREGION_REGION_3_SHIFT 13 3352#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT) 3353#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 3354#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) 3355#define I40E_VFQF_HREGION_REGION_4_SHIFT 17 3356#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT) 3357#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 3358#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) 3359#define I40E_VFQF_HREGION_REGION_5_SHIFT 21 3360#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT) 3361#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 3362#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) 3363#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 3364#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) 3365#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 3366#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) 3367#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 3368#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) 3369#endif 3370