1/* Copyright (c) 2014 Linaro Ltd. 2 * Copyright (c) 2014 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10#include <linux/module.h> 11#include <linux/interrupt.h> 12#include <linux/etherdevice.h> 13#include <linux/platform_device.h> 14#include <linux/of_net.h> 15#include <linux/of_mdio.h> 16#include <linux/clk.h> 17#include <linux/circ_buf.h> 18 19#define STATION_ADDR_LOW 0x0000 20#define STATION_ADDR_HIGH 0x0004 21#define MAC_DUPLEX_HALF_CTRL 0x0008 22#define MAX_FRM_SIZE 0x003c 23#define PORT_MODE 0x0040 24#define PORT_EN 0x0044 25#define BITS_TX_EN BIT(2) 26#define BITS_RX_EN BIT(1) 27#define REC_FILT_CONTROL 0x0064 28#define BIT_CRC_ERR_PASS BIT(5) 29#define BIT_PAUSE_FRM_PASS BIT(4) 30#define BIT_VLAN_DROP_EN BIT(3) 31#define BIT_BC_DROP_EN BIT(2) 32#define BIT_MC_MATCH_EN BIT(1) 33#define BIT_UC_MATCH_EN BIT(0) 34#define PORT_MC_ADDR_LOW 0x0068 35#define PORT_MC_ADDR_HIGH 0x006C 36#define CF_CRC_STRIP 0x01b0 37#define MODE_CHANGE_EN 0x01b4 38#define BIT_MODE_CHANGE_EN BIT(0) 39#define COL_SLOT_TIME 0x01c0 40#define RECV_CONTROL 0x01e0 41#define BIT_STRIP_PAD_EN BIT(3) 42#define BIT_RUNT_PKT_EN BIT(4) 43#define CONTROL_WORD 0x0214 44#define MDIO_SINGLE_CMD 0x03c0 45#define MDIO_SINGLE_DATA 0x03c4 46#define MDIO_CTRL 0x03cc 47#define MDIO_RDATA_STATUS 0x03d0 48 49#define MDIO_START BIT(20) 50#define MDIO_R_VALID BIT(0) 51#define MDIO_READ (BIT(17) | MDIO_START) 52#define MDIO_WRITE (BIT(16) | MDIO_START) 53 54#define RX_FQ_START_ADDR 0x0500 55#define RX_FQ_DEPTH 0x0504 56#define RX_FQ_WR_ADDR 0x0508 57#define RX_FQ_RD_ADDR 0x050c 58#define RX_FQ_VLDDESC_CNT 0x0510 59#define RX_FQ_ALEMPTY_TH 0x0514 60#define RX_FQ_REG_EN 0x0518 61#define BITS_RX_FQ_START_ADDR_EN BIT(2) 62#define BITS_RX_FQ_DEPTH_EN BIT(1) 63#define BITS_RX_FQ_RD_ADDR_EN BIT(0) 64#define RX_FQ_ALFULL_TH 0x051c 65#define RX_BQ_START_ADDR 0x0520 66#define RX_BQ_DEPTH 0x0524 67#define RX_BQ_WR_ADDR 0x0528 68#define RX_BQ_RD_ADDR 0x052c 69#define RX_BQ_FREE_DESC_CNT 0x0530 70#define RX_BQ_ALEMPTY_TH 0x0534 71#define RX_BQ_REG_EN 0x0538 72#define BITS_RX_BQ_START_ADDR_EN BIT(2) 73#define BITS_RX_BQ_DEPTH_EN BIT(1) 74#define BITS_RX_BQ_WR_ADDR_EN BIT(0) 75#define RX_BQ_ALFULL_TH 0x053c 76#define TX_BQ_START_ADDR 0x0580 77#define TX_BQ_DEPTH 0x0584 78#define TX_BQ_WR_ADDR 0x0588 79#define TX_BQ_RD_ADDR 0x058c 80#define TX_BQ_VLDDESC_CNT 0x0590 81#define TX_BQ_ALEMPTY_TH 0x0594 82#define TX_BQ_REG_EN 0x0598 83#define BITS_TX_BQ_START_ADDR_EN BIT(2) 84#define BITS_TX_BQ_DEPTH_EN BIT(1) 85#define BITS_TX_BQ_RD_ADDR_EN BIT(0) 86#define TX_BQ_ALFULL_TH 0x059c 87#define TX_RQ_START_ADDR 0x05a0 88#define TX_RQ_DEPTH 0x05a4 89#define TX_RQ_WR_ADDR 0x05a8 90#define TX_RQ_RD_ADDR 0x05ac 91#define TX_RQ_FREE_DESC_CNT 0x05b0 92#define TX_RQ_ALEMPTY_TH 0x05b4 93#define TX_RQ_REG_EN 0x05b8 94#define BITS_TX_RQ_START_ADDR_EN BIT(2) 95#define BITS_TX_RQ_DEPTH_EN BIT(1) 96#define BITS_TX_RQ_WR_ADDR_EN BIT(0) 97#define TX_RQ_ALFULL_TH 0x05bc 98#define RAW_PMU_INT 0x05c0 99#define ENA_PMU_INT 0x05c4 100#define STATUS_PMU_INT 0x05c8 101#define MAC_FIFO_ERR_IN BIT(30) 102#define TX_RQ_IN_TIMEOUT_INT BIT(29) 103#define RX_BQ_IN_TIMEOUT_INT BIT(28) 104#define TXOUTCFF_FULL_INT BIT(27) 105#define TXOUTCFF_EMPTY_INT BIT(26) 106#define TXCFF_FULL_INT BIT(25) 107#define TXCFF_EMPTY_INT BIT(24) 108#define RXOUTCFF_FULL_INT BIT(23) 109#define RXOUTCFF_EMPTY_INT BIT(22) 110#define RXCFF_FULL_INT BIT(21) 111#define RXCFF_EMPTY_INT BIT(20) 112#define TX_RQ_IN_INT BIT(19) 113#define TX_BQ_OUT_INT BIT(18) 114#define RX_BQ_IN_INT BIT(17) 115#define RX_FQ_OUT_INT BIT(16) 116#define TX_RQ_EMPTY_INT BIT(15) 117#define TX_RQ_FULL_INT BIT(14) 118#define TX_RQ_ALEMPTY_INT BIT(13) 119#define TX_RQ_ALFULL_INT BIT(12) 120#define TX_BQ_EMPTY_INT BIT(11) 121#define TX_BQ_FULL_INT BIT(10) 122#define TX_BQ_ALEMPTY_INT BIT(9) 123#define TX_BQ_ALFULL_INT BIT(8) 124#define RX_BQ_EMPTY_INT BIT(7) 125#define RX_BQ_FULL_INT BIT(6) 126#define RX_BQ_ALEMPTY_INT BIT(5) 127#define RX_BQ_ALFULL_INT BIT(4) 128#define RX_FQ_EMPTY_INT BIT(3) 129#define RX_FQ_FULL_INT BIT(2) 130#define RX_FQ_ALEMPTY_INT BIT(1) 131#define RX_FQ_ALFULL_INT BIT(0) 132 133#define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \ 134 TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT) 135 136#define DESC_WR_RD_ENA 0x05cc 137#define IN_QUEUE_TH 0x05d8 138#define OUT_QUEUE_TH 0x05dc 139#define QUEUE_TX_BQ_SHIFT 16 140#define RX_BQ_IN_TIMEOUT_TH 0x05e0 141#define TX_RQ_IN_TIMEOUT_TH 0x05e4 142#define STOP_CMD 0x05e8 143#define BITS_TX_STOP BIT(1) 144#define BITS_RX_STOP BIT(0) 145#define FLUSH_CMD 0x05eC 146#define BITS_TX_FLUSH_CMD BIT(5) 147#define BITS_RX_FLUSH_CMD BIT(4) 148#define BITS_TX_FLUSH_FLAG_DOWN BIT(3) 149#define BITS_TX_FLUSH_FLAG_UP BIT(2) 150#define BITS_RX_FLUSH_FLAG_DOWN BIT(1) 151#define BITS_RX_FLUSH_FLAG_UP BIT(0) 152#define RX_CFF_NUM_REG 0x05f0 153#define PMU_FSM_REG 0x05f8 154#define RX_FIFO_PKT_IN_NUM 0x05fc 155#define RX_FIFO_PKT_OUT_NUM 0x0600 156 157#define RGMII_SPEED_1000 0x2c 158#define RGMII_SPEED_100 0x2f 159#define RGMII_SPEED_10 0x2d 160#define MII_SPEED_100 0x0f 161#define MII_SPEED_10 0x0d 162#define GMAC_SPEED_1000 0x05 163#define GMAC_SPEED_100 0x01 164#define GMAC_SPEED_10 0x00 165#define GMAC_FULL_DUPLEX BIT(4) 166 167#define RX_BQ_INT_THRESHOLD 0x01 168#define TX_RQ_INT_THRESHOLD 0x01 169#define RX_BQ_IN_TIMEOUT 0x10000 170#define TX_RQ_IN_TIMEOUT 0x50000 171 172#define MAC_MAX_FRAME_SIZE 1600 173#define DESC_SIZE 32 174#define RX_DESC_NUM 1024 175#define TX_DESC_NUM 1024 176 177#define DESC_VLD_FREE 0 178#define DESC_VLD_BUSY 0x80000000 179#define DESC_FL_MID 0 180#define DESC_FL_LAST 0x20000000 181#define DESC_FL_FIRST 0x40000000 182#define DESC_FL_FULL 0x60000000 183#define DESC_DATA_LEN_OFF 16 184#define DESC_BUFF_LEN_OFF 0 185#define DESC_DATA_MASK 0x7ff 186 187/* DMA descriptor ring helpers */ 188#define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1)) 189#define dma_cnt(n) ((n) >> 5) 190#define dma_byte(n) ((n) << 5) 191 192struct hix5hd2_desc { 193 __le32 buff_addr; 194 __le32 cmd; 195} __aligned(32); 196 197struct hix5hd2_desc_sw { 198 struct hix5hd2_desc *desc; 199 dma_addr_t phys_addr; 200 unsigned int count; 201 unsigned int size; 202}; 203 204#define QUEUE_NUMS 4 205struct hix5hd2_priv { 206 struct hix5hd2_desc_sw pool[QUEUE_NUMS]; 207#define rx_fq pool[0] 208#define rx_bq pool[1] 209#define tx_bq pool[2] 210#define tx_rq pool[3] 211 212 void __iomem *base; 213 void __iomem *ctrl_base; 214 215 struct sk_buff *tx_skb[TX_DESC_NUM]; 216 struct sk_buff *rx_skb[RX_DESC_NUM]; 217 218 struct device *dev; 219 struct net_device *netdev; 220 221 struct phy_device *phy; 222 struct device_node *phy_node; 223 phy_interface_t phy_mode; 224 225 unsigned int speed; 226 unsigned int duplex; 227 228 struct clk *clk; 229 struct mii_bus *bus; 230 struct napi_struct napi; 231 struct work_struct tx_timeout_task; 232}; 233 234static void hix5hd2_config_port(struct net_device *dev, u32 speed, u32 duplex) 235{ 236 struct hix5hd2_priv *priv = netdev_priv(dev); 237 u32 val; 238 239 priv->speed = speed; 240 priv->duplex = duplex; 241 242 switch (priv->phy_mode) { 243 case PHY_INTERFACE_MODE_RGMII: 244 if (speed == SPEED_1000) 245 val = RGMII_SPEED_1000; 246 else if (speed == SPEED_100) 247 val = RGMII_SPEED_100; 248 else 249 val = RGMII_SPEED_10; 250 break; 251 case PHY_INTERFACE_MODE_MII: 252 if (speed == SPEED_100) 253 val = MII_SPEED_100; 254 else 255 val = MII_SPEED_10; 256 break; 257 default: 258 netdev_warn(dev, "not supported mode\n"); 259 val = MII_SPEED_10; 260 break; 261 } 262 263 if (duplex) 264 val |= GMAC_FULL_DUPLEX; 265 writel_relaxed(val, priv->ctrl_base); 266 267 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); 268 if (speed == SPEED_1000) 269 val = GMAC_SPEED_1000; 270 else if (speed == SPEED_100) 271 val = GMAC_SPEED_100; 272 else 273 val = GMAC_SPEED_10; 274 writel_relaxed(val, priv->base + PORT_MODE); 275 writel_relaxed(0, priv->base + MODE_CHANGE_EN); 276 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); 277} 278 279static void hix5hd2_set_desc_depth(struct hix5hd2_priv *priv, int rx, int tx) 280{ 281 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); 282 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); 283 writel_relaxed(0, priv->base + RX_FQ_REG_EN); 284 285 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); 286 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); 287 writel_relaxed(0, priv->base + RX_BQ_REG_EN); 288 289 writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN); 290 writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH); 291 writel_relaxed(0, priv->base + TX_BQ_REG_EN); 292 293 writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN); 294 writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH); 295 writel_relaxed(0, priv->base + TX_RQ_REG_EN); 296} 297 298static void hix5hd2_set_rx_fq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 299{ 300 writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN); 301 writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR); 302 writel_relaxed(0, priv->base + RX_FQ_REG_EN); 303} 304 305static void hix5hd2_set_rx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 306{ 307 writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN); 308 writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR); 309 writel_relaxed(0, priv->base + RX_BQ_REG_EN); 310} 311 312static void hix5hd2_set_tx_bq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 313{ 314 writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN); 315 writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR); 316 writel_relaxed(0, priv->base + TX_BQ_REG_EN); 317} 318 319static void hix5hd2_set_tx_rq(struct hix5hd2_priv *priv, dma_addr_t phy_addr) 320{ 321 writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN); 322 writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR); 323 writel_relaxed(0, priv->base + TX_RQ_REG_EN); 324} 325 326static void hix5hd2_set_desc_addr(struct hix5hd2_priv *priv) 327{ 328 hix5hd2_set_rx_fq(priv, priv->rx_fq.phys_addr); 329 hix5hd2_set_rx_bq(priv, priv->rx_bq.phys_addr); 330 hix5hd2_set_tx_rq(priv, priv->tx_rq.phys_addr); 331 hix5hd2_set_tx_bq(priv, priv->tx_bq.phys_addr); 332} 333 334static void hix5hd2_hw_init(struct hix5hd2_priv *priv) 335{ 336 u32 val; 337 338 /* disable and clear all interrupts */ 339 writel_relaxed(0, priv->base + ENA_PMU_INT); 340 writel_relaxed(~0, priv->base + RAW_PMU_INT); 341 342 writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL); 343 writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD); 344 writel_relaxed(0, priv->base + COL_SLOT_TIME); 345 346 val = RX_BQ_INT_THRESHOLD | TX_RQ_INT_THRESHOLD << QUEUE_TX_BQ_SHIFT; 347 writel_relaxed(val, priv->base + IN_QUEUE_TH); 348 349 writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH); 350 writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH); 351 352 hix5hd2_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); 353 hix5hd2_set_desc_addr(priv); 354} 355 356static void hix5hd2_irq_enable(struct hix5hd2_priv *priv) 357{ 358 writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT); 359} 360 361static void hix5hd2_irq_disable(struct hix5hd2_priv *priv) 362{ 363 writel_relaxed(0, priv->base + ENA_PMU_INT); 364} 365 366static void hix5hd2_port_enable(struct hix5hd2_priv *priv) 367{ 368 writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA); 369 writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN); 370} 371 372static void hix5hd2_port_disable(struct hix5hd2_priv *priv) 373{ 374 writel_relaxed(~(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN); 375 writel_relaxed(0, priv->base + DESC_WR_RD_ENA); 376} 377 378static void hix5hd2_hw_set_mac_addr(struct net_device *dev) 379{ 380 struct hix5hd2_priv *priv = netdev_priv(dev); 381 unsigned char *mac = dev->dev_addr; 382 u32 val; 383 384 val = mac[1] | (mac[0] << 8); 385 writel_relaxed(val, priv->base + STATION_ADDR_HIGH); 386 387 val = mac[5] | (mac[4] << 8) | (mac[3] << 16) | (mac[2] << 24); 388 writel_relaxed(val, priv->base + STATION_ADDR_LOW); 389} 390 391static int hix5hd2_net_set_mac_address(struct net_device *dev, void *p) 392{ 393 int ret; 394 395 ret = eth_mac_addr(dev, p); 396 if (!ret) 397 hix5hd2_hw_set_mac_addr(dev); 398 399 return ret; 400} 401 402static void hix5hd2_adjust_link(struct net_device *dev) 403{ 404 struct hix5hd2_priv *priv = netdev_priv(dev); 405 struct phy_device *phy = priv->phy; 406 407 if ((priv->speed != phy->speed) || (priv->duplex != phy->duplex)) { 408 hix5hd2_config_port(dev, phy->speed, phy->duplex); 409 phy_print_status(phy); 410 } 411} 412 413static void hix5hd2_rx_refill(struct hix5hd2_priv *priv) 414{ 415 struct hix5hd2_desc *desc; 416 struct sk_buff *skb; 417 u32 start, end, num, pos, i; 418 u32 len = MAC_MAX_FRAME_SIZE; 419 dma_addr_t addr; 420 421 /* software write pointer */ 422 start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR)); 423 /* logic read pointer */ 424 end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR)); 425 num = CIRC_SPACE(start, end, RX_DESC_NUM); 426 427 for (i = 0, pos = start; i < num; i++) { 428 if (priv->rx_skb[pos]) { 429 break; 430 } else { 431 skb = netdev_alloc_skb_ip_align(priv->netdev, len); 432 if (unlikely(skb == NULL)) 433 break; 434 } 435 436 addr = dma_map_single(priv->dev, skb->data, len, DMA_FROM_DEVICE); 437 if (dma_mapping_error(priv->dev, addr)) { 438 dev_kfree_skb_any(skb); 439 break; 440 } 441 442 desc = priv->rx_fq.desc + pos; 443 desc->buff_addr = cpu_to_le32(addr); 444 priv->rx_skb[pos] = skb; 445 desc->cmd = cpu_to_le32(DESC_VLD_FREE | 446 (len - 1) << DESC_BUFF_LEN_OFF); 447 pos = dma_ring_incr(pos, RX_DESC_NUM); 448 } 449 450 /* ensure desc updated */ 451 wmb(); 452 453 if (pos != start) 454 writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR); 455} 456 457static int hix5hd2_rx(struct net_device *dev, int limit) 458{ 459 struct hix5hd2_priv *priv = netdev_priv(dev); 460 struct sk_buff *skb; 461 struct hix5hd2_desc *desc; 462 dma_addr_t addr; 463 u32 start, end, num, pos, i, len; 464 465 /* software read pointer */ 466 start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR)); 467 /* logic write pointer */ 468 end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR)); 469 num = CIRC_CNT(end, start, RX_DESC_NUM); 470 if (num > limit) 471 num = limit; 472 473 /* ensure get updated desc */ 474 rmb(); 475 for (i = 0, pos = start; i < num; i++) { 476 skb = priv->rx_skb[pos]; 477 if (unlikely(!skb)) { 478 netdev_err(dev, "inconsistent rx_skb\n"); 479 break; 480 } 481 priv->rx_skb[pos] = NULL; 482 483 desc = priv->rx_bq.desc + pos; 484 len = (le32_to_cpu(desc->cmd) >> DESC_DATA_LEN_OFF) & 485 DESC_DATA_MASK; 486 addr = le32_to_cpu(desc->buff_addr); 487 dma_unmap_single(priv->dev, addr, MAC_MAX_FRAME_SIZE, 488 DMA_FROM_DEVICE); 489 490 skb_put(skb, len); 491 if (skb->len > MAC_MAX_FRAME_SIZE) { 492 netdev_err(dev, "rcv len err, len = %d\n", skb->len); 493 dev->stats.rx_errors++; 494 dev->stats.rx_length_errors++; 495 dev_kfree_skb_any(skb); 496 goto next; 497 } 498 499 skb->protocol = eth_type_trans(skb, dev); 500 napi_gro_receive(&priv->napi, skb); 501 dev->stats.rx_packets++; 502 dev->stats.rx_bytes += skb->len; 503 dev->last_rx = jiffies; 504next: 505 pos = dma_ring_incr(pos, RX_DESC_NUM); 506 } 507 508 if (pos != start) 509 writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR); 510 511 hix5hd2_rx_refill(priv); 512 513 return num; 514} 515 516static void hix5hd2_xmit_reclaim(struct net_device *dev) 517{ 518 struct sk_buff *skb; 519 struct hix5hd2_desc *desc; 520 struct hix5hd2_priv *priv = netdev_priv(dev); 521 unsigned int bytes_compl = 0, pkts_compl = 0; 522 u32 start, end, num, pos, i; 523 dma_addr_t addr; 524 525 netif_tx_lock(dev); 526 527 /* software read */ 528 start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR)); 529 /* logic write */ 530 end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR)); 531 num = CIRC_CNT(end, start, TX_DESC_NUM); 532 533 for (i = 0, pos = start; i < num; i++) { 534 skb = priv->tx_skb[pos]; 535 if (unlikely(!skb)) { 536 netdev_err(dev, "inconsistent tx_skb\n"); 537 break; 538 } 539 540 pkts_compl++; 541 bytes_compl += skb->len; 542 desc = priv->tx_rq.desc + pos; 543 addr = le32_to_cpu(desc->buff_addr); 544 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); 545 priv->tx_skb[pos] = NULL; 546 dev_consume_skb_any(skb); 547 pos = dma_ring_incr(pos, TX_DESC_NUM); 548 } 549 550 if (pos != start) 551 writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR); 552 553 netif_tx_unlock(dev); 554 555 if (pkts_compl || bytes_compl) 556 netdev_completed_queue(dev, pkts_compl, bytes_compl); 557 558 if (unlikely(netif_queue_stopped(priv->netdev)) && pkts_compl) 559 netif_wake_queue(priv->netdev); 560} 561 562static int hix5hd2_poll(struct napi_struct *napi, int budget) 563{ 564 struct hix5hd2_priv *priv = container_of(napi, 565 struct hix5hd2_priv, napi); 566 struct net_device *dev = priv->netdev; 567 int work_done = 0, task = budget; 568 int ints, num; 569 570 do { 571 hix5hd2_xmit_reclaim(dev); 572 num = hix5hd2_rx(dev, task); 573 work_done += num; 574 task -= num; 575 if ((work_done >= budget) || (num == 0)) 576 break; 577 578 ints = readl_relaxed(priv->base + RAW_PMU_INT); 579 writel_relaxed(ints, priv->base + RAW_PMU_INT); 580 } while (ints & DEF_INT_MASK); 581 582 if (work_done < budget) { 583 napi_complete(napi); 584 hix5hd2_irq_enable(priv); 585 } 586 587 return work_done; 588} 589 590static irqreturn_t hix5hd2_interrupt(int irq, void *dev_id) 591{ 592 struct net_device *dev = (struct net_device *)dev_id; 593 struct hix5hd2_priv *priv = netdev_priv(dev); 594 int ints = readl_relaxed(priv->base + RAW_PMU_INT); 595 596 writel_relaxed(ints, priv->base + RAW_PMU_INT); 597 if (likely(ints & DEF_INT_MASK)) { 598 hix5hd2_irq_disable(priv); 599 napi_schedule(&priv->napi); 600 } 601 602 return IRQ_HANDLED; 603} 604 605static int hix5hd2_net_xmit(struct sk_buff *skb, struct net_device *dev) 606{ 607 struct hix5hd2_priv *priv = netdev_priv(dev); 608 struct hix5hd2_desc *desc; 609 dma_addr_t addr; 610 u32 pos; 611 612 /* software write pointer */ 613 pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR)); 614 if (unlikely(priv->tx_skb[pos])) { 615 dev->stats.tx_dropped++; 616 dev->stats.tx_fifo_errors++; 617 netif_stop_queue(dev); 618 return NETDEV_TX_BUSY; 619 } 620 621 addr = dma_map_single(priv->dev, skb->data, skb->len, DMA_TO_DEVICE); 622 if (dma_mapping_error(priv->dev, addr)) { 623 dev_kfree_skb_any(skb); 624 return NETDEV_TX_OK; 625 } 626 627 desc = priv->tx_bq.desc + pos; 628 desc->buff_addr = cpu_to_le32(addr); 629 priv->tx_skb[pos] = skb; 630 desc->cmd = cpu_to_le32(DESC_VLD_BUSY | DESC_FL_FULL | 631 (skb->len & DESC_DATA_MASK) << DESC_DATA_LEN_OFF | 632 (skb->len & DESC_DATA_MASK) << DESC_BUFF_LEN_OFF); 633 634 /* ensure desc updated */ 635 wmb(); 636 637 pos = dma_ring_incr(pos, TX_DESC_NUM); 638 writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR); 639 640 dev->trans_start = jiffies; 641 dev->stats.tx_packets++; 642 dev->stats.tx_bytes += skb->len; 643 netdev_sent_queue(dev, skb->len); 644 645 return NETDEV_TX_OK; 646} 647 648static void hix5hd2_free_dma_desc_rings(struct hix5hd2_priv *priv) 649{ 650 struct hix5hd2_desc *desc; 651 dma_addr_t addr; 652 int i; 653 654 for (i = 0; i < RX_DESC_NUM; i++) { 655 struct sk_buff *skb = priv->rx_skb[i]; 656 if (skb == NULL) 657 continue; 658 659 desc = priv->rx_fq.desc + i; 660 addr = le32_to_cpu(desc->buff_addr); 661 dma_unmap_single(priv->dev, addr, 662 MAC_MAX_FRAME_SIZE, DMA_FROM_DEVICE); 663 dev_kfree_skb_any(skb); 664 priv->rx_skb[i] = NULL; 665 } 666 667 for (i = 0; i < TX_DESC_NUM; i++) { 668 struct sk_buff *skb = priv->tx_skb[i]; 669 if (skb == NULL) 670 continue; 671 672 desc = priv->tx_rq.desc + i; 673 addr = le32_to_cpu(desc->buff_addr); 674 dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); 675 dev_kfree_skb_any(skb); 676 priv->tx_skb[i] = NULL; 677 } 678} 679 680static int hix5hd2_net_open(struct net_device *dev) 681{ 682 struct hix5hd2_priv *priv = netdev_priv(dev); 683 int ret; 684 685 ret = clk_prepare_enable(priv->clk); 686 if (ret < 0) { 687 netdev_err(dev, "failed to enable clk %d\n", ret); 688 return ret; 689 } 690 691 priv->phy = of_phy_connect(dev, priv->phy_node, 692 &hix5hd2_adjust_link, 0, priv->phy_mode); 693 if (!priv->phy) 694 return -ENODEV; 695 696 phy_start(priv->phy); 697 hix5hd2_hw_init(priv); 698 hix5hd2_rx_refill(priv); 699 700 netdev_reset_queue(dev); 701 netif_start_queue(dev); 702 napi_enable(&priv->napi); 703 704 hix5hd2_port_enable(priv); 705 hix5hd2_irq_enable(priv); 706 707 return 0; 708} 709 710static int hix5hd2_net_close(struct net_device *dev) 711{ 712 struct hix5hd2_priv *priv = netdev_priv(dev); 713 714 hix5hd2_port_disable(priv); 715 hix5hd2_irq_disable(priv); 716 napi_disable(&priv->napi); 717 netif_stop_queue(dev); 718 hix5hd2_free_dma_desc_rings(priv); 719 720 if (priv->phy) { 721 phy_stop(priv->phy); 722 phy_disconnect(priv->phy); 723 } 724 725 clk_disable_unprepare(priv->clk); 726 727 return 0; 728} 729 730static void hix5hd2_tx_timeout_task(struct work_struct *work) 731{ 732 struct hix5hd2_priv *priv; 733 734 priv = container_of(work, struct hix5hd2_priv, tx_timeout_task); 735 hix5hd2_net_close(priv->netdev); 736 hix5hd2_net_open(priv->netdev); 737} 738 739static void hix5hd2_net_timeout(struct net_device *dev) 740{ 741 struct hix5hd2_priv *priv = netdev_priv(dev); 742 743 schedule_work(&priv->tx_timeout_task); 744} 745 746static const struct net_device_ops hix5hd2_netdev_ops = { 747 .ndo_open = hix5hd2_net_open, 748 .ndo_stop = hix5hd2_net_close, 749 .ndo_start_xmit = hix5hd2_net_xmit, 750 .ndo_tx_timeout = hix5hd2_net_timeout, 751 .ndo_set_mac_address = hix5hd2_net_set_mac_address, 752}; 753 754static int hix5hd2_get_settings(struct net_device *net_dev, 755 struct ethtool_cmd *cmd) 756{ 757 struct hix5hd2_priv *priv = netdev_priv(net_dev); 758 759 if (!priv->phy) 760 return -ENODEV; 761 762 return phy_ethtool_gset(priv->phy, cmd); 763} 764 765static int hix5hd2_set_settings(struct net_device *net_dev, 766 struct ethtool_cmd *cmd) 767{ 768 struct hix5hd2_priv *priv = netdev_priv(net_dev); 769 770 if (!priv->phy) 771 return -ENODEV; 772 773 return phy_ethtool_sset(priv->phy, cmd); 774} 775 776static struct ethtool_ops hix5hd2_ethtools_ops = { 777 .get_link = ethtool_op_get_link, 778 .get_settings = hix5hd2_get_settings, 779 .set_settings = hix5hd2_set_settings, 780}; 781 782static int hix5hd2_mdio_wait_ready(struct mii_bus *bus) 783{ 784 struct hix5hd2_priv *priv = bus->priv; 785 void __iomem *base = priv->base; 786 int i, timeout = 10000; 787 788 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { 789 if (i == timeout) 790 return -ETIMEDOUT; 791 usleep_range(10, 20); 792 } 793 794 return 0; 795} 796 797static int hix5hd2_mdio_read(struct mii_bus *bus, int phy, int reg) 798{ 799 struct hix5hd2_priv *priv = bus->priv; 800 void __iomem *base = priv->base; 801 int val, ret; 802 803 ret = hix5hd2_mdio_wait_ready(bus); 804 if (ret < 0) 805 goto out; 806 807 writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD); 808 ret = hix5hd2_mdio_wait_ready(bus); 809 if (ret < 0) 810 goto out; 811 812 val = readl_relaxed(base + MDIO_RDATA_STATUS); 813 if (val & MDIO_R_VALID) { 814 dev_err(bus->parent, "SMI bus read not valid\n"); 815 ret = -ENODEV; 816 goto out; 817 } 818 819 val = readl_relaxed(priv->base + MDIO_SINGLE_DATA); 820 ret = (val >> 16) & 0xFFFF; 821out: 822 return ret; 823} 824 825static int hix5hd2_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 826{ 827 struct hix5hd2_priv *priv = bus->priv; 828 void __iomem *base = priv->base; 829 int ret; 830 831 ret = hix5hd2_mdio_wait_ready(bus); 832 if (ret < 0) 833 goto out; 834 835 writel_relaxed(val, base + MDIO_SINGLE_DATA); 836 writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD); 837 ret = hix5hd2_mdio_wait_ready(bus); 838out: 839 return ret; 840} 841 842static void hix5hd2_destroy_hw_desc_queue(struct hix5hd2_priv *priv) 843{ 844 int i; 845 846 for (i = 0; i < QUEUE_NUMS; i++) { 847 if (priv->pool[i].desc) { 848 dma_free_coherent(priv->dev, priv->pool[i].size, 849 priv->pool[i].desc, 850 priv->pool[i].phys_addr); 851 priv->pool[i].desc = NULL; 852 } 853 } 854} 855 856static int hix5hd2_init_hw_desc_queue(struct hix5hd2_priv *priv) 857{ 858 struct device *dev = priv->dev; 859 struct hix5hd2_desc *virt_addr; 860 dma_addr_t phys_addr; 861 int size, i; 862 863 priv->rx_fq.count = RX_DESC_NUM; 864 priv->rx_bq.count = RX_DESC_NUM; 865 priv->tx_bq.count = TX_DESC_NUM; 866 priv->tx_rq.count = TX_DESC_NUM; 867 868 for (i = 0; i < QUEUE_NUMS; i++) { 869 size = priv->pool[i].count * sizeof(struct hix5hd2_desc); 870 virt_addr = dma_alloc_coherent(dev, size, &phys_addr, 871 GFP_KERNEL); 872 if (virt_addr == NULL) 873 goto error_free_pool; 874 875 memset(virt_addr, 0, size); 876 priv->pool[i].size = size; 877 priv->pool[i].desc = virt_addr; 878 priv->pool[i].phys_addr = phys_addr; 879 } 880 return 0; 881 882error_free_pool: 883 hix5hd2_destroy_hw_desc_queue(priv); 884 885 return -ENOMEM; 886} 887 888static int hix5hd2_dev_probe(struct platform_device *pdev) 889{ 890 struct device *dev = &pdev->dev; 891 struct device_node *node = dev->of_node; 892 struct net_device *ndev; 893 struct hix5hd2_priv *priv; 894 struct resource *res; 895 struct mii_bus *bus; 896 const char *mac_addr; 897 int ret; 898 899 ndev = alloc_etherdev(sizeof(struct hix5hd2_priv)); 900 if (!ndev) 901 return -ENOMEM; 902 903 platform_set_drvdata(pdev, ndev); 904 905 priv = netdev_priv(ndev); 906 priv->dev = dev; 907 priv->netdev = ndev; 908 909 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 910 priv->base = devm_ioremap_resource(dev, res); 911 if (IS_ERR(priv->base)) { 912 ret = PTR_ERR(priv->base); 913 goto out_free_netdev; 914 } 915 916 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 917 priv->ctrl_base = devm_ioremap_resource(dev, res); 918 if (IS_ERR(priv->ctrl_base)) { 919 ret = PTR_ERR(priv->ctrl_base); 920 goto out_free_netdev; 921 } 922 923 priv->clk = devm_clk_get(&pdev->dev, NULL); 924 if (IS_ERR(priv->clk)) { 925 netdev_err(ndev, "failed to get clk\n"); 926 ret = -ENODEV; 927 goto out_free_netdev; 928 } 929 930 ret = clk_prepare_enable(priv->clk); 931 if (ret < 0) { 932 netdev_err(ndev, "failed to enable clk %d\n", ret); 933 goto out_free_netdev; 934 } 935 936 bus = mdiobus_alloc(); 937 if (bus == NULL) { 938 ret = -ENOMEM; 939 goto out_free_netdev; 940 } 941 942 bus->priv = priv; 943 bus->name = "hix5hd2_mii_bus"; 944 bus->read = hix5hd2_mdio_read; 945 bus->write = hix5hd2_mdio_write; 946 bus->parent = &pdev->dev; 947 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(&pdev->dev)); 948 priv->bus = bus; 949 950 ret = of_mdiobus_register(bus, node); 951 if (ret) 952 goto err_free_mdio; 953 954 priv->phy_mode = of_get_phy_mode(node); 955 if (priv->phy_mode < 0) { 956 netdev_err(ndev, "not find phy-mode\n"); 957 ret = -EINVAL; 958 goto err_mdiobus; 959 } 960 961 priv->phy_node = of_parse_phandle(node, "phy-handle", 0); 962 if (!priv->phy_node) { 963 netdev_err(ndev, "not find phy-handle\n"); 964 ret = -EINVAL; 965 goto err_mdiobus; 966 } 967 968 ndev->irq = platform_get_irq(pdev, 0); 969 if (ndev->irq <= 0) { 970 netdev_err(ndev, "No irq resource\n"); 971 ret = -EINVAL; 972 goto out_phy_node; 973 } 974 975 ret = devm_request_irq(dev, ndev->irq, hix5hd2_interrupt, 976 0, pdev->name, ndev); 977 if (ret) { 978 netdev_err(ndev, "devm_request_irq failed\n"); 979 goto out_phy_node; 980 } 981 982 mac_addr = of_get_mac_address(node); 983 if (mac_addr) 984 ether_addr_copy(ndev->dev_addr, mac_addr); 985 if (!is_valid_ether_addr(ndev->dev_addr)) { 986 eth_hw_addr_random(ndev); 987 netdev_warn(ndev, "using random MAC address %pM\n", 988 ndev->dev_addr); 989 } 990 991 INIT_WORK(&priv->tx_timeout_task, hix5hd2_tx_timeout_task); 992 ndev->watchdog_timeo = 6 * HZ; 993 ndev->priv_flags |= IFF_UNICAST_FLT; 994 ndev->netdev_ops = &hix5hd2_netdev_ops; 995 ndev->ethtool_ops = &hix5hd2_ethtools_ops; 996 SET_NETDEV_DEV(ndev, dev); 997 998 ret = hix5hd2_init_hw_desc_queue(priv); 999 if (ret) 1000 goto out_phy_node; 1001 1002 netif_napi_add(ndev, &priv->napi, hix5hd2_poll, NAPI_POLL_WEIGHT); 1003 ret = register_netdev(priv->netdev); 1004 if (ret) { 1005 netdev_err(ndev, "register_netdev failed!"); 1006 goto out_destroy_queue; 1007 } 1008 1009 clk_disable_unprepare(priv->clk); 1010 1011 return ret; 1012 1013out_destroy_queue: 1014 netif_napi_del(&priv->napi); 1015 hix5hd2_destroy_hw_desc_queue(priv); 1016out_phy_node: 1017 of_node_put(priv->phy_node); 1018err_mdiobus: 1019 mdiobus_unregister(bus); 1020err_free_mdio: 1021 mdiobus_free(bus); 1022out_free_netdev: 1023 free_netdev(ndev); 1024 1025 return ret; 1026} 1027 1028static int hix5hd2_dev_remove(struct platform_device *pdev) 1029{ 1030 struct net_device *ndev = platform_get_drvdata(pdev); 1031 struct hix5hd2_priv *priv = netdev_priv(ndev); 1032 1033 netif_napi_del(&priv->napi); 1034 unregister_netdev(ndev); 1035 mdiobus_unregister(priv->bus); 1036 mdiobus_free(priv->bus); 1037 1038 hix5hd2_destroy_hw_desc_queue(priv); 1039 of_node_put(priv->phy_node); 1040 cancel_work_sync(&priv->tx_timeout_task); 1041 free_netdev(ndev); 1042 1043 return 0; 1044} 1045 1046static const struct of_device_id hix5hd2_of_match[] = { 1047 {.compatible = "hisilicon,hix5hd2-gmac",}, 1048 {}, 1049}; 1050 1051MODULE_DEVICE_TABLE(of, hix5hd2_of_match); 1052 1053static struct platform_driver hix5hd2_dev_driver = { 1054 .driver = { 1055 .name = "hix5hd2-gmac", 1056 .of_match_table = hix5hd2_of_match, 1057 }, 1058 .probe = hix5hd2_dev_probe, 1059 .remove = hix5hd2_dev_remove, 1060}; 1061 1062module_platform_driver(hix5hd2_dev_driver); 1063 1064MODULE_DESCRIPTION("HISILICON HIX5HD2 Ethernet driver"); 1065MODULE_LICENSE("GPL v2"); 1066MODULE_ALIAS("platform:hix5hd2-gmac"); 1067