1/* bnx2x_reg.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * The registers description starts with the register Access type followed 10 * by size in bits. For example [RW 32]. The access types are: 11 * R - Read only 12 * RC - Clear on read 13 * RW - Read/Write 14 * ST - Statistics register (clear on read) 15 * W - Write only 16 * WB - Wide bus register - the size is over 32 bits and it should be 17 * read/write in consecutive 32 bits accesses 18 * WR - Write Clear (write 1 to clear the bit) 19 * 20 */ 21#ifndef BNX2X_REG_H 22#define BNX2X_REG_H 23 24#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 25#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2) 26#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5) 27#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3) 28#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4) 29#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1) 30/* [RW 1] Initiate the ATC array - reset all the valid bits */ 31#define ATC_REG_ATC_INIT_ARRAY 0x1100b8 32/* [R 1] ATC initialization done */ 33#define ATC_REG_ATC_INIT_DONE 0x1100bc 34/* [RC 6] Interrupt register #0 read clear */ 35#define ATC_REG_ATC_INT_STS_CLR 0x1101c0 36/* [RW 5] Parity mask register #0 read/write */ 37#define ATC_REG_ATC_PRTY_MASK 0x1101d8 38/* [R 5] Parity register #0 read */ 39#define ATC_REG_ATC_PRTY_STS 0x1101cc 40/* [RC 5] Parity register #0 read clear */ 41#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 42/* [RW 19] Interrupt mask register #0 read/write */ 43#define BRB1_REG_BRB1_INT_MASK 0x60128 44/* [R 19] Interrupt register #0 read */ 45#define BRB1_REG_BRB1_INT_STS 0x6011c 46/* [RW 4] Parity mask register #0 read/write */ 47#define BRB1_REG_BRB1_PRTY_MASK 0x60138 48/* [R 4] Parity register #0 read */ 49#define BRB1_REG_BRB1_PRTY_STS 0x6012c 50/* [RC 4] Parity register #0 read clear */ 51#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130 52/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At 53 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address 54 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning - 55 * following reset the first rbc access to this reg must be write; there can 56 * be no more rbc writes after the first one; there can be any number of rbc 57 * read following the first write; rbc access not following these rules will 58 * result in hang condition. */ 59#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200 60/* [RW 10] The number of free blocks below which the full signal to class 0 61 * is asserted */ 62#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0 63#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230 64/* [RW 11] The number of free blocks above which the full signal to class 0 65 * is de-asserted */ 66#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4 67#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234 68/* [RW 11] The number of free blocks below which the full signal to class 1 69 * is asserted */ 70#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8 71#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238 72/* [RW 11] The number of free blocks above which the full signal to class 1 73 * is de-asserted */ 74#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc 75#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c 76/* [RW 11] The number of free blocks below which the full signal to the LB 77 * port is asserted */ 78#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0 79/* [RW 10] The number of free blocks above which the full signal to the LB 80 * port is de-asserted */ 81#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4 82/* [RW 10] The number of free blocks above which the High_llfc signal to 83 interface #n is de-asserted. */ 84#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c 85/* [RW 10] The number of free blocks below which the High_llfc signal to 86 interface #n is asserted. */ 87#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c 88/* [RW 11] The number of blocks guarantied for the LB port */ 89#define BRB1_REG_LB_GUARANTIED 0x601ec 90/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port 91 * before signaling XON. */ 92#define BRB1_REG_LB_GUARANTIED_HYST 0x60264 93/* [RW 24] LL RAM data. */ 94#define BRB1_REG_LL_RAM 0x61000 95/* [RW 10] The number of free blocks above which the Low_llfc signal to 96 interface #n is de-asserted. */ 97#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c 98/* [RW 10] The number of free blocks below which the Low_llfc signal to 99 interface #n is asserted. */ 100#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c 101/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The 102 * register is applicable only when per_class_guaranty_mode is set. */ 103#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244 104/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 105 * 1 before signaling XON. The register is applicable only when 106 * per_class_guaranty_mode is set. */ 107#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254 108/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The 109 * register is applicable only when per_class_guaranty_mode is set. */ 110#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248 111/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0 112 * before signaling XON. The register is applicable only when 113 * per_class_guaranty_mode is set. */ 114#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258 115/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register 116 * is applicable only when per_class_guaranty_mode is set. */ 117#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c 118/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC 119 * 1 before signaling XON. The register is applicable only when 120 * per_class_guaranty_mode is set. */ 121#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c 122/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The 123 * register is applicable only when per_class_guaranty_mode is set. */ 124#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250 125/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC 126 * 1 before signaling XON. The register is applicable only when 127 * per_class_guaranty_mode is set. */ 128#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260 129/* [RW 11] The number of blocks guarantied for the MAC port. The register is 130 * applicable only when per_class_guaranty_mode is reset. */ 131#define BRB1_REG_MAC_GUARANTIED_0 0x601e8 132#define BRB1_REG_MAC_GUARANTIED_1 0x60240 133/* [R 24] The number of full blocks. */ 134#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 135/* [ST 32] The number of cycles that the write_full signal towards MAC #0 136 was asserted. */ 137#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8 138#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc 139#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8 140/* [ST 32] The number of cycles that the pause signal towards MAC #0 was 141 asserted. */ 142#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8 143#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc 144/* [RW 10] The number of free blocks below which the pause signal to class 0 145 * is asserted */ 146#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0 147#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220 148/* [RW 11] The number of free blocks above which the pause signal to class 0 149 * is de-asserted */ 150#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4 151#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224 152/* [RW 11] The number of free blocks below which the pause signal to class 1 153 * is asserted */ 154#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8 155#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228 156/* [RW 11] The number of free blocks above which the pause signal to class 1 157 * is de-asserted */ 158#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc 159#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c 160/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 161#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 162#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c 163/* [RW 10] Write client 0: Assert pause threshold. */ 164#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 165/* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC 166 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC 167 * mode). 1=per-class guaranty mode (new mode). */ 168#define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268 169/* [R 24] The number of full blocks occpied by port. */ 170#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 171/* [RW 1] Reset the design by software. */ 172#define BRB1_REG_SOFT_RESET 0x600dc 173/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 174#define CCM_REG_CAM_OCCUP 0xd0188 175/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 176 acknowledge output is deasserted; all other signals are treated as usual; 177 if 1 - normal activity. */ 178#define CCM_REG_CCM_CFC_IFEN 0xd003c 179/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 180 disregarded; valid is deasserted; all other signals are treated as usual; 181 if 1 - normal activity. */ 182#define CCM_REG_CCM_CQM_IFEN 0xd000c 183/* [RW 1] If set the Q index; received from the QM is inserted to event ID. 184 Otherwise 0 is inserted. */ 185#define CCM_REG_CCM_CQM_USE_Q 0xd00c0 186/* [RW 11] Interrupt mask register #0 read/write */ 187#define CCM_REG_CCM_INT_MASK 0xd01e4 188/* [R 11] Interrupt register #0 read */ 189#define CCM_REG_CCM_INT_STS 0xd01d8 190/* [RW 27] Parity mask register #0 read/write */ 191#define CCM_REG_CCM_PRTY_MASK 0xd01f4 192/* [R 27] Parity register #0 read */ 193#define CCM_REG_CCM_PRTY_STS 0xd01e8 194/* [RC 27] Parity register #0 read clear */ 195#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec 196/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 197 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 198 Is used to determine the number of the AG context REG-pairs written back; 199 when the input message Reg1WbFlg isn't set. */ 200#define CCM_REG_CCM_REG0_SZ 0xd00c4 201/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 202 disregarded; valid is deasserted; all other signals are treated as usual; 203 if 1 - normal activity. */ 204#define CCM_REG_CCM_STORM0_IFEN 0xd0004 205/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 206 disregarded; valid is deasserted; all other signals are treated as usual; 207 if 1 - normal activity. */ 208#define CCM_REG_CCM_STORM1_IFEN 0xd0008 209/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 210 disregarded; valid output is deasserted; all other signals are treated as 211 usual; if 1 - normal activity. */ 212#define CCM_REG_CDU_AG_RD_IFEN 0xd0030 213/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 214 are disregarded; all other signals are treated as usual; if 1 - normal 215 activity. */ 216#define CCM_REG_CDU_AG_WR_IFEN 0xd002c 217/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 218 disregarded; valid output is deasserted; all other signals are treated as 219 usual; if 1 - normal activity. */ 220#define CCM_REG_CDU_SM_RD_IFEN 0xd0038 221/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 222 input is disregarded; all other signals are treated as usual; if 1 - 223 normal activity. */ 224#define CCM_REG_CDU_SM_WR_IFEN 0xd0034 225/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 226 the initial credit value; read returns the current value of the credit 227 counter. Must be initialized to 1 at start-up. */ 228#define CCM_REG_CFC_INIT_CRD 0xd0204 229/* [RW 2] Auxiliary counter flag Q number 1. */ 230#define CCM_REG_CNT_AUX1_Q 0xd00c8 231/* [RW 2] Auxiliary counter flag Q number 2. */ 232#define CCM_REG_CNT_AUX2_Q 0xd00cc 233/* [RW 28] The CM header value for QM request (primary). */ 234#define CCM_REG_CQM_CCM_HDR_P 0xd008c 235/* [RW 28] The CM header value for QM request (secondary). */ 236#define CCM_REG_CQM_CCM_HDR_S 0xd0090 237/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 238 acknowledge output is deasserted; all other signals are treated as usual; 239 if 1 - normal activity. */ 240#define CCM_REG_CQM_CCM_IFEN 0xd0014 241/* [RW 6] QM output initial credit. Max credit available - 32. Write writes 242 the initial credit value; read returns the current value of the credit 243 counter. Must be initialized to 32 at start-up. */ 244#define CCM_REG_CQM_INIT_CRD 0xd020c 245/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 246 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 247 prioritised); 2 stands for weight 2; tc. */ 248#define CCM_REG_CQM_P_WEIGHT 0xd00b8 249/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 250 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 251 prioritised); 2 stands for weight 2; tc. */ 252#define CCM_REG_CQM_S_WEIGHT 0xd00bc 253/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 254 acknowledge output is deasserted; all other signals are treated as usual; 255 if 1 - normal activity. */ 256#define CCM_REG_CSDM_IFEN 0xd0018 257/* [RC 1] Set when the message length mismatch (relative to last indication) 258 at the SDM interface is detected. */ 259#define CCM_REG_CSDM_LENGTH_MIS 0xd0170 260/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 261 weight 8 (the most prioritised); 1 stands for weight 1(least 262 prioritised); 2 stands for weight 2; tc. */ 263#define CCM_REG_CSDM_WEIGHT 0xd00b4 264/* [RW 28] The CM header for QM formatting in case of an error in the QM 265 inputs. */ 266#define CCM_REG_ERR_CCM_HDR 0xd0094 267/* [RW 8] The Event ID in case the input message ErrorFlg is set. */ 268#define CCM_REG_ERR_EVNT_ID 0xd0098 269/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 270 writes the initial credit value; read returns the current value of the 271 credit counter. Must be initialized to 64 at start-up. */ 272#define CCM_REG_FIC0_INIT_CRD 0xd0210 273/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 274 writes the initial credit value; read returns the current value of the 275 credit counter. Must be initialized to 64 at start-up. */ 276#define CCM_REG_FIC1_INIT_CRD 0xd0214 277/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 278 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr; 279 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and 280 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and 281 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */ 282#define CCM_REG_GR_ARB_TYPE 0xd015c 283/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 284 highest priority is 3. It is supposed; that the Store channel priority is 285 the compliment to 4 of the rest priorities - Aggregation channel; Load 286 (FIC0) channel and Load (FIC1). */ 287#define CCM_REG_GR_LD0_PR 0xd0164 288/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 289 highest priority is 3. It is supposed; that the Store channel priority is 290 the compliment to 4 of the rest priorities - Aggregation channel; Load 291 (FIC0) channel and Load (FIC1). */ 292#define CCM_REG_GR_LD1_PR 0xd0168 293/* [RW 2] General flags index. */ 294#define CCM_REG_INV_DONE_Q 0xd0108 295/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM 296 context and sent to STORM; for a specific connection type. The double 297 REG-pairs are used in order to align to STORM context row size of 128 298 bits. The offset of these data in the STORM context is always 0. Index 299 _(0..15) stands for the connection type (one of 16). */ 300#define CCM_REG_N_SM_CTX_LD_0 0xd004c 301#define CCM_REG_N_SM_CTX_LD_1 0xd0050 302#define CCM_REG_N_SM_CTX_LD_2 0xd0054 303#define CCM_REG_N_SM_CTX_LD_3 0xd0058 304#define CCM_REG_N_SM_CTX_LD_4 0xd005c 305/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 306 acknowledge output is deasserted; all other signals are treated as usual; 307 if 1 - normal activity. */ 308#define CCM_REG_PBF_IFEN 0xd0028 309/* [RC 1] Set when the message length mismatch (relative to last indication) 310 at the pbf interface is detected. */ 311#define CCM_REG_PBF_LENGTH_MIS 0xd0180 312/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 313 weight 8 (the most prioritised); 1 stands for weight 1(least 314 prioritised); 2 stands for weight 2; tc. */ 315#define CCM_REG_PBF_WEIGHT 0xd00ac 316#define CCM_REG_PHYS_QNUM1_0 0xd0134 317#define CCM_REG_PHYS_QNUM1_1 0xd0138 318#define CCM_REG_PHYS_QNUM2_0 0xd013c 319#define CCM_REG_PHYS_QNUM2_1 0xd0140 320#define CCM_REG_PHYS_QNUM3_0 0xd0144 321#define CCM_REG_PHYS_QNUM3_1 0xd0148 322#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114 323#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118 324#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c 325#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120 326#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124 327#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128 328#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c 329#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130 330/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 331 disregarded; acknowledge output is deasserted; all other signals are 332 treated as usual; if 1 - normal activity. */ 333#define CCM_REG_STORM_CCM_IFEN 0xd0010 334/* [RC 1] Set when the message length mismatch (relative to last indication) 335 at the STORM interface is detected. */ 336#define CCM_REG_STORM_LENGTH_MIS 0xd016c 337/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin) 338 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for 339 weight 1(least prioritised); 2 stands for weight 2 (more prioritised); 340 tc. */ 341#define CCM_REG_STORM_WEIGHT 0xd009c 342/* [RW 1] Input tsem Interface enable. If 0 - the valid input is 343 disregarded; acknowledge output is deasserted; all other signals are 344 treated as usual; if 1 - normal activity. */ 345#define CCM_REG_TSEM_IFEN 0xd001c 346/* [RC 1] Set when the message length mismatch (relative to last indication) 347 at the tsem interface is detected. */ 348#define CCM_REG_TSEM_LENGTH_MIS 0xd0174 349/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 350 weight 8 (the most prioritised); 1 stands for weight 1(least 351 prioritised); 2 stands for weight 2; tc. */ 352#define CCM_REG_TSEM_WEIGHT 0xd00a0 353/* [RW 1] Input usem Interface enable. If 0 - the valid input is 354 disregarded; acknowledge output is deasserted; all other signals are 355 treated as usual; if 1 - normal activity. */ 356#define CCM_REG_USEM_IFEN 0xd0024 357/* [RC 1] Set when message length mismatch (relative to last indication) at 358 the usem interface is detected. */ 359#define CCM_REG_USEM_LENGTH_MIS 0xd017c 360/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 361 weight 8 (the most prioritised); 1 stands for weight 1(least 362 prioritised); 2 stands for weight 2; tc. */ 363#define CCM_REG_USEM_WEIGHT 0xd00a8 364/* [RW 1] Input xsem Interface enable. If 0 - the valid input is 365 disregarded; acknowledge output is deasserted; all other signals are 366 treated as usual; if 1 - normal activity. */ 367#define CCM_REG_XSEM_IFEN 0xd0020 368/* [RC 1] Set when the message length mismatch (relative to last indication) 369 at the xsem interface is detected. */ 370#define CCM_REG_XSEM_LENGTH_MIS 0xd0178 371/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 372 weight 8 (the most prioritised); 1 stands for weight 1(least 373 prioritised); 2 stands for weight 2; tc. */ 374#define CCM_REG_XSEM_WEIGHT 0xd00a4 375/* [RW 19] Indirect access to the descriptor table of the XX protection 376 mechanism. The fields are: [5:0] - message length; [12:6] - message 377 pointer; 18:13] - next pointer. */ 378#define CCM_REG_XX_DESCR_TABLE 0xd0300 379#define CCM_REG_XX_DESCR_TABLE_SIZE 24 380/* [R 7] Used to read the value of XX protection Free counter. */ 381#define CCM_REG_XX_FREE 0xd0184 382/* [RW 6] Initial value for the credit counter; responsible for fulfilling 383 of the Input Stage XX protection buffer by the XX protection pending 384 messages. Max credit available - 127. Write writes the initial credit 385 value; read returns the current value of the credit counter. Must be 386 initialized to maximum XX protected message size - 2 at start-up. */ 387#define CCM_REG_XX_INIT_CRD 0xd0220 388/* [RW 7] The maximum number of pending messages; which may be stored in XX 389 protection. At read the ~ccm_registers_xx_free.xx_free counter is read. 390 At write comprises the start value of the ~ccm_registers_xx_free.xx_free 391 counter. */ 392#define CCM_REG_XX_MSG_NUM 0xd0224 393/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 394#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044 395/* [RW 18] Indirect access to the XX table of the XX protection mechanism. 396 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] - 397 header pointer. */ 398#define CCM_REG_XX_TABLE 0xd0280 399#define CDU_REG_CDU_CHK_MASK0 0x101000 400#define CDU_REG_CDU_CHK_MASK1 0x101004 401#define CDU_REG_CDU_CONTROL0 0x101008 402#define CDU_REG_CDU_DEBUG 0x101010 403#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 404/* [RW 7] Interrupt mask register #0 read/write */ 405#define CDU_REG_CDU_INT_MASK 0x10103c 406/* [R 7] Interrupt register #0 read */ 407#define CDU_REG_CDU_INT_STS 0x101030 408/* [RW 5] Parity mask register #0 read/write */ 409#define CDU_REG_CDU_PRTY_MASK 0x10104c 410/* [R 5] Parity register #0 read */ 411#define CDU_REG_CDU_PRTY_STS 0x101040 412/* [RC 5] Parity register #0 read clear */ 413#define CDU_REG_CDU_PRTY_STS_CLR 0x101044 414/* [RC 32] logging of error data in case of a CDU load error: 415 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 416 ype_error; ctual_active; ctual_compressed_context}; */ 417#define CDU_REG_ERROR_DATA 0x101014 418/* [WB 216] L1TT ram access. each entry has the following format : 419 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0]; 420 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */ 421#define CDU_REG_L1TT 0x101800 422/* [WB 24] MATT ram access. each entry has the following 423 format:{RegionLength[11:0]; egionOffset[11:0]} */ 424#define CDU_REG_MATT 0x101100 425/* [RW 1] when this bit is set the CDU operates in e1hmf mode */ 426#define CDU_REG_MF_MODE 0x101050 427/* [R 1] indication the initializing the activity counter by the hardware 428 was done. */ 429#define CFC_REG_AC_INIT_DONE 0x104078 430/* [RW 13] activity counter ram access */ 431#define CFC_REG_ACTIVITY_COUNTER 0x104400 432#define CFC_REG_ACTIVITY_COUNTER_SIZE 256 433/* [R 1] indication the initializing the cams by the hardware was done. */ 434#define CFC_REG_CAM_INIT_DONE 0x10407c 435/* [RW 2] Interrupt mask register #0 read/write */ 436#define CFC_REG_CFC_INT_MASK 0x104108 437/* [R 2] Interrupt register #0 read */ 438#define CFC_REG_CFC_INT_STS 0x1040fc 439/* [RC 2] Interrupt register #0 read clear */ 440#define CFC_REG_CFC_INT_STS_CLR 0x104100 441/* [RW 4] Parity mask register #0 read/write */ 442#define CFC_REG_CFC_PRTY_MASK 0x104118 443/* [R 4] Parity register #0 read */ 444#define CFC_REG_CFC_PRTY_STS 0x10410c 445/* [RC 4] Parity register #0 read clear */ 446#define CFC_REG_CFC_PRTY_STS_CLR 0x104110 447/* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 448#define CFC_REG_CID_CAM 0x104800 449#define CFC_REG_CONTROL0 0x104028 450#define CFC_REG_DEBUG0 0x104050 451/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error 452 vector) whether the cfc should be disabled upon it */ 453#define CFC_REG_DISABLE_ON_ERROR 0x104044 454/* [RC 14] CFC error vector. when the CFC detects an internal error it will 455 set one of these bits. the bit description can be found in CFC 456 specifications */ 457#define CFC_REG_ERROR_VECTOR 0x10403c 458/* [WB 93] LCID info ram access */ 459#define CFC_REG_INFO_RAM 0x105000 460#define CFC_REG_INFO_RAM_SIZE 1024 461#define CFC_REG_INIT_REG 0x10404c 462#define CFC_REG_INTERFACES 0x104058 463/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this 464 field allows changing the priorities of the weighted-round-robin arbiter 465 which selects which CFC load client should be served next */ 466#define CFC_REG_LCREQ_WEIGHTS 0x104084 467/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */ 468#define CFC_REG_LINK_LIST 0x104c00 469#define CFC_REG_LINK_LIST_SIZE 256 470/* [R 1] indication the initializing the link list by the hardware was done. */ 471#define CFC_REG_LL_INIT_DONE 0x104074 472/* [R 9] Number of allocated LCIDs which are at empty state */ 473#define CFC_REG_NUM_LCIDS_ALLOC 0x104020 474/* [R 9] Number of Arriving LCIDs in Link List Block */ 475#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 476#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120 477/* [R 9] Number of Leaving LCIDs in Link List Block */ 478#define CFC_REG_NUM_LCIDS_LEAVING 0x104018 479#define CFC_REG_WEAK_ENABLE_PF 0x104124 480/* [RW 8] The event id for aggregated interrupt 0 */ 481#define CSDM_REG_AGG_INT_EVENT_0 0xc2038 482#define CSDM_REG_AGG_INT_EVENT_10 0xc2060 483#define CSDM_REG_AGG_INT_EVENT_11 0xc2064 484#define CSDM_REG_AGG_INT_EVENT_12 0xc2068 485#define CSDM_REG_AGG_INT_EVENT_13 0xc206c 486#define CSDM_REG_AGG_INT_EVENT_14 0xc2070 487#define CSDM_REG_AGG_INT_EVENT_15 0xc2074 488#define CSDM_REG_AGG_INT_EVENT_16 0xc2078 489#define CSDM_REG_AGG_INT_EVENT_2 0xc2040 490#define CSDM_REG_AGG_INT_EVENT_3 0xc2044 491#define CSDM_REG_AGG_INT_EVENT_4 0xc2048 492#define CSDM_REG_AGG_INT_EVENT_5 0xc204c 493#define CSDM_REG_AGG_INT_EVENT_6 0xc2050 494#define CSDM_REG_AGG_INT_EVENT_7 0xc2054 495#define CSDM_REG_AGG_INT_EVENT_8 0xc2058 496#define CSDM_REG_AGG_INT_EVENT_9 0xc205c 497/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 498 or auto-mask-mode (1) */ 499#define CSDM_REG_AGG_INT_MODE_10 0xc21e0 500#define CSDM_REG_AGG_INT_MODE_11 0xc21e4 501#define CSDM_REG_AGG_INT_MODE_12 0xc21e8 502#define CSDM_REG_AGG_INT_MODE_13 0xc21ec 503#define CSDM_REG_AGG_INT_MODE_14 0xc21f0 504#define CSDM_REG_AGG_INT_MODE_15 0xc21f4 505#define CSDM_REG_AGG_INT_MODE_16 0xc21f8 506#define CSDM_REG_AGG_INT_MODE_6 0xc21d0 507#define CSDM_REG_AGG_INT_MODE_7 0xc21d4 508#define CSDM_REG_AGG_INT_MODE_8 0xc21d8 509#define CSDM_REG_AGG_INT_MODE_9 0xc21dc 510/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 511#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008 512/* [RW 16] The maximum value of the completion counter #0 */ 513#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c 514/* [RW 16] The maximum value of the completion counter #1 */ 515#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020 516/* [RW 16] The maximum value of the completion counter #2 */ 517#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024 518/* [RW 16] The maximum value of the completion counter #3 */ 519#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028 520/* [RW 13] The start address in the internal RAM for the completion 521 counters. */ 522#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c 523/* [RW 32] Interrupt mask register #0 read/write */ 524#define CSDM_REG_CSDM_INT_MASK_0 0xc229c 525#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 526/* [R 32] Interrupt register #0 read */ 527#define CSDM_REG_CSDM_INT_STS_0 0xc2290 528#define CSDM_REG_CSDM_INT_STS_1 0xc22a0 529/* [RW 11] Parity mask register #0 read/write */ 530#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 531/* [R 11] Parity register #0 read */ 532#define CSDM_REG_CSDM_PRTY_STS 0xc22b0 533/* [RC 11] Parity register #0 read clear */ 534#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4 535#define CSDM_REG_ENABLE_IN1 0xc2238 536#define CSDM_REG_ENABLE_IN2 0xc223c 537#define CSDM_REG_ENABLE_OUT1 0xc2240 538#define CSDM_REG_ENABLE_OUT2 0xc2244 539/* [RW 4] The initial number of messages that can be sent to the pxp control 540 interface without receiving any ACK. */ 541#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc 542/* [ST 32] The number of ACK after placement messages received */ 543#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c 544/* [ST 32] The number of packet end messages received from the parser */ 545#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274 546/* [ST 32] The number of requests received from the pxp async if */ 547#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278 548/* [ST 32] The number of commands received in queue 0 */ 549#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248 550/* [ST 32] The number of commands received in queue 10 */ 551#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c 552/* [ST 32] The number of commands received in queue 11 */ 553#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270 554/* [ST 32] The number of commands received in queue 1 */ 555#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c 556/* [ST 32] The number of commands received in queue 3 */ 557#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250 558/* [ST 32] The number of commands received in queue 4 */ 559#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254 560/* [ST 32] The number of commands received in queue 5 */ 561#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258 562/* [ST 32] The number of commands received in queue 6 */ 563#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c 564/* [ST 32] The number of commands received in queue 7 */ 565#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260 566/* [ST 32] The number of commands received in queue 8 */ 567#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264 568/* [ST 32] The number of commands received in queue 9 */ 569#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268 570/* [RW 13] The start address in the internal RAM for queue counters */ 571#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010 572/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 573#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 574/* [R 1] parser fifo empty in sdm_sync block */ 575#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 576/* [R 1] parser serial fifo empty in sdm_sync block */ 577#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 578/* [RW 32] Tick for timer counter. Applicable only when 579 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */ 580#define CSDM_REG_TIMER_TICK 0xc2000 581/* [RW 5] The number of time_slots in the arbitration cycle */ 582#define CSEM_REG_ARB_CYCLE_SIZE 0x200034 583/* [RW 3] The source that is associated with arbitration element 0. Source 584 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 585 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 586#define CSEM_REG_ARB_ELEMENT0 0x200020 587/* [RW 3] The source that is associated with arbitration element 1. Source 588 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 589 sleeping thread with priority 1; 4- sleeping thread with priority 2. 590 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */ 591#define CSEM_REG_ARB_ELEMENT1 0x200024 592/* [RW 3] The source that is associated with arbitration element 2. Source 593 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 594 sleeping thread with priority 1; 4- sleeping thread with priority 2. 595 Could not be equal to register ~csem_registers_arb_element0.arb_element0 596 and ~csem_registers_arb_element1.arb_element1 */ 597#define CSEM_REG_ARB_ELEMENT2 0x200028 598/* [RW 3] The source that is associated with arbitration element 3. Source 599 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 600 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 601 not be equal to register ~csem_registers_arb_element0.arb_element0 and 602 ~csem_registers_arb_element1.arb_element1 and 603 ~csem_registers_arb_element2.arb_element2 */ 604#define CSEM_REG_ARB_ELEMENT3 0x20002c 605/* [RW 3] The source that is associated with arbitration element 4. Source 606 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 607 sleeping thread with priority 1; 4- sleeping thread with priority 2. 608 Could not be equal to register ~csem_registers_arb_element0.arb_element0 609 and ~csem_registers_arb_element1.arb_element1 and 610 ~csem_registers_arb_element2.arb_element2 and 611 ~csem_registers_arb_element3.arb_element3 */ 612#define CSEM_REG_ARB_ELEMENT4 0x200030 613/* [RW 32] Interrupt mask register #0 read/write */ 614#define CSEM_REG_CSEM_INT_MASK_0 0x200110 615#define CSEM_REG_CSEM_INT_MASK_1 0x200120 616/* [R 32] Interrupt register #0 read */ 617#define CSEM_REG_CSEM_INT_STS_0 0x200104 618#define CSEM_REG_CSEM_INT_STS_1 0x200114 619/* [RW 32] Parity mask register #0 read/write */ 620#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 621#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 622/* [R 32] Parity register #0 read */ 623#define CSEM_REG_CSEM_PRTY_STS_0 0x200124 624#define CSEM_REG_CSEM_PRTY_STS_1 0x200134 625/* [RC 32] Parity register #0 read clear */ 626#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128 627#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138 628#define CSEM_REG_ENABLE_IN 0x2000a4 629#define CSEM_REG_ENABLE_OUT 0x2000a8 630/* [RW 32] This address space contains all registers and memories that are 631 placed in SEM_FAST block. The SEM_FAST registers are described in 632 appendix B. In order to access the sem_fast registers the base address 633 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 634#define CSEM_REG_FAST_MEMORY 0x220000 635/* [RW 1] Disables input messages from FIC0 May be updated during run_time 636 by the microcode */ 637#define CSEM_REG_FIC0_DISABLE 0x200224 638/* [RW 1] Disables input messages from FIC1 May be updated during run_time 639 by the microcode */ 640#define CSEM_REG_FIC1_DISABLE 0x200234 641/* [RW 15] Interrupt table Read and write access to it is not possible in 642 the middle of the work */ 643#define CSEM_REG_INT_TABLE 0x200400 644/* [ST 24] Statistics register. The number of messages that entered through 645 FIC0 */ 646#define CSEM_REG_MSG_NUM_FIC0 0x200000 647/* [ST 24] Statistics register. The number of messages that entered through 648 FIC1 */ 649#define CSEM_REG_MSG_NUM_FIC1 0x200004 650/* [ST 24] Statistics register. The number of messages that were sent to 651 FOC0 */ 652#define CSEM_REG_MSG_NUM_FOC0 0x200008 653/* [ST 24] Statistics register. The number of messages that were sent to 654 FOC1 */ 655#define CSEM_REG_MSG_NUM_FOC1 0x20000c 656/* [ST 24] Statistics register. The number of messages that were sent to 657 FOC2 */ 658#define CSEM_REG_MSG_NUM_FOC2 0x200010 659/* [ST 24] Statistics register. The number of messages that were sent to 660 FOC3 */ 661#define CSEM_REG_MSG_NUM_FOC3 0x200014 662/* [RW 1] Disables input messages from the passive buffer May be updated 663 during run_time by the microcode */ 664#define CSEM_REG_PAS_DISABLE 0x20024c 665/* [WB 128] Debug only. Passive buffer memory */ 666#define CSEM_REG_PASSIVE_BUFFER 0x202000 667/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 668#define CSEM_REG_PRAM 0x240000 669/* [R 16] Valid sleeping threads indication have bit per thread */ 670#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 671/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 672#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 673/* [RW 16] List of free threads . There is a bit per thread. */ 674#define CSEM_REG_THREADS_LIST 0x2002e4 675/* [RW 3] The arbitration scheme of time_slot 0 */ 676#define CSEM_REG_TS_0_AS 0x200038 677/* [RW 3] The arbitration scheme of time_slot 10 */ 678#define CSEM_REG_TS_10_AS 0x200060 679/* [RW 3] The arbitration scheme of time_slot 11 */ 680#define CSEM_REG_TS_11_AS 0x200064 681/* [RW 3] The arbitration scheme of time_slot 12 */ 682#define CSEM_REG_TS_12_AS 0x200068 683/* [RW 3] The arbitration scheme of time_slot 13 */ 684#define CSEM_REG_TS_13_AS 0x20006c 685/* [RW 3] The arbitration scheme of time_slot 14 */ 686#define CSEM_REG_TS_14_AS 0x200070 687/* [RW 3] The arbitration scheme of time_slot 15 */ 688#define CSEM_REG_TS_15_AS 0x200074 689/* [RW 3] The arbitration scheme of time_slot 16 */ 690#define CSEM_REG_TS_16_AS 0x200078 691/* [RW 3] The arbitration scheme of time_slot 17 */ 692#define CSEM_REG_TS_17_AS 0x20007c 693/* [RW 3] The arbitration scheme of time_slot 18 */ 694#define CSEM_REG_TS_18_AS 0x200080 695/* [RW 3] The arbitration scheme of time_slot 1 */ 696#define CSEM_REG_TS_1_AS 0x20003c 697/* [RW 3] The arbitration scheme of time_slot 2 */ 698#define CSEM_REG_TS_2_AS 0x200040 699/* [RW 3] The arbitration scheme of time_slot 3 */ 700#define CSEM_REG_TS_3_AS 0x200044 701/* [RW 3] The arbitration scheme of time_slot 4 */ 702#define CSEM_REG_TS_4_AS 0x200048 703/* [RW 3] The arbitration scheme of time_slot 5 */ 704#define CSEM_REG_TS_5_AS 0x20004c 705/* [RW 3] The arbitration scheme of time_slot 6 */ 706#define CSEM_REG_TS_6_AS 0x200050 707/* [RW 3] The arbitration scheme of time_slot 7 */ 708#define CSEM_REG_TS_7_AS 0x200054 709/* [RW 3] The arbitration scheme of time_slot 8 */ 710#define CSEM_REG_TS_8_AS 0x200058 711/* [RW 3] The arbitration scheme of time_slot 9 */ 712#define CSEM_REG_TS_9_AS 0x20005c 713/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 714 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 715#define CSEM_REG_VFPF_ERR_NUM 0x200380 716/* [RW 1] Parity mask register #0 read/write */ 717#define DBG_REG_DBG_PRTY_MASK 0xc0a8 718/* [R 1] Parity register #0 read */ 719#define DBG_REG_DBG_PRTY_STS 0xc09c 720/* [RC 1] Parity register #0 read clear */ 721#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0 722/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The 723 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0; 724 * 4.Completion function=0; 5.Error handling=0 */ 725#define DMAE_REG_BACKWARD_COMP_EN 0x10207c 726/* [RW 32] Commands memory. The address to command X; row Y is to calculated 727 as 14*X+Y. */ 728#define DMAE_REG_CMD_MEM 0x102400 729#define DMAE_REG_CMD_MEM_SIZE 224 730/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c 731 initial value is all ones. */ 732#define DMAE_REG_CRC16C_INIT 0x10201c 733/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the 734 CRC-16 T10 initial value is all ones. */ 735#define DMAE_REG_CRC16T10_INIT 0x102020 736/* [RW 2] Interrupt mask register #0 read/write */ 737#define DMAE_REG_DMAE_INT_MASK 0x102054 738/* [RW 4] Parity mask register #0 read/write */ 739#define DMAE_REG_DMAE_PRTY_MASK 0x102064 740/* [R 4] Parity register #0 read */ 741#define DMAE_REG_DMAE_PRTY_STS 0x102058 742/* [RC 4] Parity register #0 read clear */ 743#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c 744/* [RW 1] Command 0 go. */ 745#define DMAE_REG_GO_C0 0x102080 746/* [RW 1] Command 1 go. */ 747#define DMAE_REG_GO_C1 0x102084 748/* [RW 1] Command 10 go. */ 749#define DMAE_REG_GO_C10 0x102088 750/* [RW 1] Command 11 go. */ 751#define DMAE_REG_GO_C11 0x10208c 752/* [RW 1] Command 12 go. */ 753#define DMAE_REG_GO_C12 0x102090 754/* [RW 1] Command 13 go. */ 755#define DMAE_REG_GO_C13 0x102094 756/* [RW 1] Command 14 go. */ 757#define DMAE_REG_GO_C14 0x102098 758/* [RW 1] Command 15 go. */ 759#define DMAE_REG_GO_C15 0x10209c 760/* [RW 1] Command 2 go. */ 761#define DMAE_REG_GO_C2 0x1020a0 762/* [RW 1] Command 3 go. */ 763#define DMAE_REG_GO_C3 0x1020a4 764/* [RW 1] Command 4 go. */ 765#define DMAE_REG_GO_C4 0x1020a8 766/* [RW 1] Command 5 go. */ 767#define DMAE_REG_GO_C5 0x1020ac 768/* [RW 1] Command 6 go. */ 769#define DMAE_REG_GO_C6 0x1020b0 770/* [RW 1] Command 7 go. */ 771#define DMAE_REG_GO_C7 0x1020b4 772/* [RW 1] Command 8 go. */ 773#define DMAE_REG_GO_C8 0x1020b8 774/* [RW 1] Command 9 go. */ 775#define DMAE_REG_GO_C9 0x1020bc 776/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge 777 input is disregarded; valid is deasserted; all other signals are treated 778 as usual; if 1 - normal activity. */ 779#define DMAE_REG_GRC_IFEN 0x102008 780/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the 781 acknowledge input is disregarded; valid is deasserted; full is asserted; 782 all other signals are treated as usual; if 1 - normal activity. */ 783#define DMAE_REG_PCI_IFEN 0x102004 784/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the 785 initial value to the credit counter; related to the address. Read returns 786 the current value of the counter. */ 787#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0 788/* [RW 8] Aggregation command. */ 789#define DORQ_REG_AGG_CMD0 0x170060 790/* [RW 8] Aggregation command. */ 791#define DORQ_REG_AGG_CMD1 0x170064 792/* [RW 8] Aggregation command. */ 793#define DORQ_REG_AGG_CMD2 0x170068 794/* [RW 8] Aggregation command. */ 795#define DORQ_REG_AGG_CMD3 0x17006c 796/* [RW 28] UCM Header. */ 797#define DORQ_REG_CMHEAD_RX 0x170050 798/* [RW 32] Doorbell address for RBC doorbells (function 0). */ 799#define DORQ_REG_DB_ADDR0 0x17008c 800/* [RW 5] Interrupt mask register #0 read/write */ 801#define DORQ_REG_DORQ_INT_MASK 0x170180 802/* [R 5] Interrupt register #0 read */ 803#define DORQ_REG_DORQ_INT_STS 0x170174 804/* [RC 5] Interrupt register #0 read clear */ 805#define DORQ_REG_DORQ_INT_STS_CLR 0x170178 806/* [RW 2] Parity mask register #0 read/write */ 807#define DORQ_REG_DORQ_PRTY_MASK 0x170190 808/* [R 2] Parity register #0 read */ 809#define DORQ_REG_DORQ_PRTY_STS 0x170184 810/* [RC 2] Parity register #0 read clear */ 811#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188 812/* [RW 8] The address to write the DPM CID to STORM. */ 813#define DORQ_REG_DPM_CID_ADDR 0x170044 814/* [RW 5] The DPM mode CID extraction offset. */ 815#define DORQ_REG_DPM_CID_OFST 0x170030 816/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */ 817#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c 818/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */ 819#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078 820/* [R 13] Current value of the DQ FIFO fill level according to following 821 pointer. The range is 0 - 256 FIFO rows; where each row stands for the 822 doorbell. */ 823#define DORQ_REG_DQ_FILL_LVLF 0x1700a4 824/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 825 equal to full threshold; reset on full clear. */ 826#define DORQ_REG_DQ_FULL_ST 0x1700c0 827/* [RW 28] The value sent to CM header in the case of CFC load error. */ 828#define DORQ_REG_ERR_CMHEAD 0x170058 829#define DORQ_REG_IF_EN 0x170004 830#define DORQ_REG_MAX_RVFID_SIZE 0x1701ec 831#define DORQ_REG_MODE_ACT 0x170008 832/* [RW 5] The normal mode CID extraction offset. */ 833#define DORQ_REG_NORM_CID_OFST 0x17002c 834/* [RW 28] TCM Header when only TCP context is loaded. */ 835#define DORQ_REG_NORM_CMHEAD_TX 0x17004c 836/* [RW 3] The number of simultaneous outstanding requests to Context Fetch 837 Interface. */ 838#define DORQ_REG_OUTST_REQ 0x17003c 839#define DORQ_REG_PF_USAGE_CNT 0x1701d0 840#define DORQ_REG_REGN 0x170038 841/* [R 4] Current value of response A counter credit. Initial credit is 842 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 843 register. */ 844#define DORQ_REG_RSPA_CRD_CNT 0x1700ac 845/* [R 4] Current value of response B counter credit. Initial credit is 846 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 847 register. */ 848#define DORQ_REG_RSPB_CRD_CNT 0x1700b0 849/* [RW 4] The initial credit at the Doorbell Response Interface. The write 850 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The 851 read reads this written value. */ 852#define DORQ_REG_RSP_INIT_CRD 0x170048 853#define DORQ_REG_RSPB_CRD_CNT 0x1700b0 854#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0 855#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4 856#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4 857#define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4 858#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8 859/* [RW 10] VF type validation mask value */ 860#define DORQ_REG_VF_TYPE_MASK_0 0x170218 861/* [RW 17] VF type validation Min MCID value */ 862#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8 863/* [RW 17] VF type validation Max MCID value */ 864#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298 865/* [RW 10] VF type validation comp value */ 866#define DORQ_REG_VF_TYPE_VALUE_0 0x170258 867#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340 868 869/* [RW 4] Initial activity counter value on the load request; when the 870 shortcut is done. */ 871#define DORQ_REG_SHRT_ACT_CNT 0x170070 872/* [RW 28] TCM Header when both ULP and TCP context is loaded. */ 873#define DORQ_REG_SHRT_CMHEAD 0x170054 874#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4) 875#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0) 876#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3) 877#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7) 878#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2) 879#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1) 880#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0) 881#define DORQ_REG_VF_USAGE_CNT 0x170320 882#define HC_REG_AGG_INT_0 0x108050 883#define HC_REG_AGG_INT_1 0x108054 884#define HC_REG_ATTN_BIT 0x108120 885#define HC_REG_ATTN_IDX 0x108100 886#define HC_REG_ATTN_MSG0_ADDR_L 0x108018 887#define HC_REG_ATTN_MSG1_ADDR_L 0x108020 888#define HC_REG_ATTN_NUM_P0 0x108038 889#define HC_REG_ATTN_NUM_P1 0x10803c 890#define HC_REG_COMMAND_REG 0x108180 891#define HC_REG_CONFIG_0 0x108000 892#define HC_REG_CONFIG_1 0x108004 893#define HC_REG_FUNC_NUM_P0 0x1080ac 894#define HC_REG_FUNC_NUM_P1 0x1080b0 895/* [RW 3] Parity mask register #0 read/write */ 896#define HC_REG_HC_PRTY_MASK 0x1080a0 897/* [R 3] Parity register #0 read */ 898#define HC_REG_HC_PRTY_STS 0x108094 899/* [RC 3] Parity register #0 read clear */ 900#define HC_REG_HC_PRTY_STS_CLR 0x108098 901#define HC_REG_INT_MASK 0x108108 902#define HC_REG_LEADING_EDGE_0 0x108040 903#define HC_REG_LEADING_EDGE_1 0x108048 904#define HC_REG_MAIN_MEMORY 0x108800 905#define HC_REG_MAIN_MEMORY_SIZE 152 906#define HC_REG_P0_PROD_CONS 0x108200 907#define HC_REG_P1_PROD_CONS 0x108400 908#define HC_REG_PBA_COMMAND 0x108140 909#define HC_REG_PCI_CONFIG_0 0x108010 910#define HC_REG_PCI_CONFIG_1 0x108014 911#define HC_REG_STATISTIC_COUNTERS 0x109000 912#define HC_REG_TRAILING_EDGE_0 0x108044 913#define HC_REG_TRAILING_EDGE_1 0x10804c 914#define HC_REG_UC_RAM_ADDR_0 0x108028 915#define HC_REG_UC_RAM_ADDR_1 0x108030 916#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068 917#define HC_REG_VQID_0 0x108008 918#define HC_REG_VQID_1 0x10800c 919#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1) 920#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0) 921#define IGU_REG_ATTENTION_ACK_BITS 0x130108 922/* [R 4] Debug: attn_fsm */ 923#define IGU_REG_ATTN_FSM 0x130054 924#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c 925#define IGU_REG_ATTN_MSG_ADDR_L 0x130120 926/* [R 4] Debug: [3] - attention write done message is pending (0-no pending; 927 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but 928 * write done didn't receive. */ 929#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030 930#define IGU_REG_BLOCK_CONFIGURATION 0x130000 931#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124 932#define IGU_REG_COMMAND_REG_CTRL 0x13012c 933/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit 934 * is clear. The bits in this registers are set and clear via the producer 935 * command. Data valid only in addresses 0-4. all the rest are zero. */ 936#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200 937/* [R 5] Debug: ctrl_fsm */ 938#define IGU_REG_CTRL_FSM 0x130064 939/* [R 1] data available for error memory. If this bit is clear do not red 940 * from error_handling_memory. */ 941#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130 942/* [RW 11] Parity mask register #0 read/write */ 943#define IGU_REG_IGU_PRTY_MASK 0x1300a8 944/* [R 11] Parity register #0 read */ 945#define IGU_REG_IGU_PRTY_STS 0x13009c 946/* [RC 11] Parity register #0 read clear */ 947#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0 948/* [R 4] Debug: int_handle_fsm */ 949#define IGU_REG_INT_HANDLE_FSM 0x130050 950#define IGU_REG_LEADING_EDGE_LATCH 0x130134 951/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. 952 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF 953 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */ 954#define IGU_REG_MAPPING_MEMORY 0x131000 955#define IGU_REG_MAPPING_MEMORY_SIZE 136 956#define IGU_REG_PBA_STATUS_LSB 0x130138 957#define IGU_REG_PBA_STATUS_MSB 0x13013c 958#define IGU_REG_PCI_PF_MSI_EN 0x130140 959#define IGU_REG_PCI_PF_MSIX_EN 0x130144 960#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148 961/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no 962 * pending; 1 = pending. Pendings means interrupt was asserted; and write 963 * done was not received. Data valid only in addresses 0-4. all the rest are 964 * zero. */ 965#define IGU_REG_PENDING_BITS_STATUS 0x130300 966#define IGU_REG_PF_CONFIGURATION 0x130154 967/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping 968 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default 969 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 970 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode 971 * - In backward compatible mode; for non default SB; each even line in the 972 * memory holds the U producer and each odd line hold the C producer. The 973 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The 974 * last 20 producers are for the DSB for each PF. each PF has five segments 975 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 976 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */ 977#define IGU_REG_PROD_CONS_MEMORY 0x132000 978/* [R 3] Debug: pxp_arb_fsm */ 979#define IGU_REG_PXP_ARB_FSM 0x130068 980/* [RW 6] Write one for each bit will reset the appropriate memory. When the 981 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping 982 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 983 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */ 984#define IGU_REG_RESET_MEMORIES 0x130158 985/* [R 4] Debug: sb_ctrl_fsm */ 986#define IGU_REG_SB_CTRL_FSM 0x13004c 987#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c 988#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160 989#define IGU_REG_SB_MASK_LSB 0x130164 990#define IGU_REG_SB_MASK_MSB 0x130168 991/* [RW 16] Number of command that were dropped without causing an interrupt 992 * due to: read access for WO BAR address; or write access for RO BAR 993 * address or any access for reserved address or PCI function error is set 994 * and address is not MSIX; PBA or cleanup */ 995#define IGU_REG_SILENT_DROP 0x13016c 996/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - 997 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per 998 * PF; 68-71 number of ATTN messages per PF */ 999#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800 1000/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a 1001 * timer mask command arrives. Value must be bigger than 100. */ 1002#define IGU_REG_TIMER_MASKING_VALUE 0x13003c 1003#define IGU_REG_TRAILING_EDGE_LATCH 0x130104 1004#define IGU_REG_VF_CONFIGURATION 0x130170 1005/* [WB_R 32] Each bit represent write done pending bits status for that SB 1006 * (MSI/MSIX message was sent and write done was not received yet). 0 = 1007 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */ 1008#define IGU_REG_WRITE_DONE_PENDING 0x130480 1009#define MCP_A_REG_MCPR_SCRATCH 0x3a0000 1010#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c 1011#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 1012#define MCP_REG_MCPR_GP_INPUTS 0x800c0 1013#define MCP_REG_MCPR_GP_OENABLE 0x800c8 1014#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4 1015#define MCP_REG_MCPR_IMC_COMMAND 0x85900 1016#define MCP_REG_MCPR_IMC_DATAREG0 0x85920 1017#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904 1018#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 1019#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 1020#define MCP_REG_MCPR_NVM_ADDR 0x8640c 1021#define MCP_REG_MCPR_NVM_CFG4 0x8642c 1022#define MCP_REG_MCPR_NVM_COMMAND 0x86400 1023#define MCP_REG_MCPR_NVM_READ 0x86410 1024#define MCP_REG_MCPR_NVM_SW_ARB 0x86420 1025#define MCP_REG_MCPR_NVM_WRITE 0x86408 1026#define MCP_REG_MCPR_SCRATCH 0xa0000 1027#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1) 1028#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0) 1029/* [R 32] read first 32 bit after inversion of function 0. mapped as 1030 follows: [0] NIG attention for function0; [1] NIG attention for 1031 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; 1032 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] 1033 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE 1034 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; 1035 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] 1036 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB 1037 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw 1038 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity 1039 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw 1040 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF 1041 Parity error; [31] PBF Hw interrupt; */ 1042#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c 1043#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 1044/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] 1045 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1046 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1047 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1048 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1049 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1050 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1051 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1052 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1053 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1054 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1055 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1056 interrupt; */ 1057#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 1058/* [R 32] read second 32 bit after inversion of function 0. mapped as 1059 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1060 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1061 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1062 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1063 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1064 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1065 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1066 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1067 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1068 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1069 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1070 interrupt; */ 1071#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 1072#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c 1073/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] 1074 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error; 1075 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; 1076 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] 1077 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1078 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1079 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1080 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1081 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1082 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1083 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1084 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1085#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 1086/* [R 32] read third 32 bit after inversion of function 0. mapped as 1087 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity 1088 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] 1089 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1090 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1091 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1092 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1093 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1094 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1095 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1096 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1097 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1098 attn1; */ 1099#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 1100#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 1101/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] 1102 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP 1103 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient 1104 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity 1105 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw 1106 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] 1107 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] 1108 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW 1109 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 1110 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 1111 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW 1112 timers attn_4 func1; [30] General attn0; [31] General attn1; */ 1113#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c 1114/* [R 32] read fourth 32 bit after inversion of function 0. mapped as 1115 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1116 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1117 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1118 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1119 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1120 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1121 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1122 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1123 Latched timeout attention; [27] GRC Latched reserved access attention; 1124 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1125 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1126#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 1127#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 1128/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] 1129 General attn2; [1] General attn3; [2] General attn4; [3] General attn5; 1130 [4] General attn6; [5] General attn7; [6] General attn8; [7] General 1131 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] 1132 General attn13; [12] General attn14; [13] General attn15; [14] General 1133 attn16; [15] General attn17; [16] General attn18; [17] General attn19; 1134 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] 1135 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] 1136 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout 1137 attention; [27] GRC Latched reserved access attention; [28] MCP Latched 1138 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 1139 ump_tx_parity; [31] MCP Latched scpad_parity; */ 1140#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 1141/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as 1142 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1143 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1144 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */ 1145#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700 1146/* [W 14] write to this register results with the clear of the latched 1147 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 1148 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 1149 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 1150 GRC Latched reserved access attention; one in d7 clears Latched 1151 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 1152 Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both 1153 ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears 1154 pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read 1155 from this register return zero */ 1156#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 1157/* [RW 32] first 32b for enabling the output for function 0 output0. mapped 1158 as follows: [0] NIG attention for function0; [1] NIG attention for 1159 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1160 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1161 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1162 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1163 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1164 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1165 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1166 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1167 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1168 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1169 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1170#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 1171#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 1172#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c 1173#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c 1174#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc 1175#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc 1176#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc 1177/* [RW 32] first 32b for enabling the output for function 1 output0. mapped 1178 as follows: [0] NIG attention for function0; [1] NIG attention for 1179 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 1180 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1181 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1182 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1183 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1184 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X 1185 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1186 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1187 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1188 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1189 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1190#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 1191#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 1192#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c 1193#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c 1194#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c 1195#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c 1196#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c 1197/* [RW 32] first 32b for enabling the output for close the gate nig. mapped 1198 as follows: [0] NIG attention for function0; [1] NIG attention for 1199 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1200 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1201 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1202 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1203 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1204 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1205 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1206 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1207 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1208 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1209 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1210#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec 1211#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c 1212/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped 1213 as follows: [0] NIG attention for function0; [1] NIG attention for 1214 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 1215 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 1216 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1217 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1218 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1219 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 1220 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 1221 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 1222 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 1223 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 1224 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1225#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc 1226#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c 1227/* [RW 32] second 32b for enabling the output for function 0 output0. mapped 1228 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1229 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1230 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1231 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1232 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1233 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1234 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1235 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1236 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1237 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1238 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1239 interrupt; */ 1240#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070 1241#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080 1242/* [RW 32] second 32b for enabling the output for function 1 output0. mapped 1243 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1244 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1245 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1246 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1247 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1248 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1249 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1250 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1251 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1252 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1253 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1254 interrupt; */ 1255#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110 1256#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120 1257/* [RW 32] second 32b for enabling the output for close the gate nig. mapped 1258 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1259 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1260 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1261 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1262 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1263 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1264 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1265 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1266 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1267 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1268 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1269 interrupt; */ 1270#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0 1271#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190 1272/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped 1273 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM 1274 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw 1275 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity 1276 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw 1277 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] 1278 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; 1279 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw 1280 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM 1281 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI 1282 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM 1283 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw 1284 interrupt; */ 1285#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100 1286#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0 1287/* [RW 32] third 32b for enabling the output for function 0 output0. mapped 1288 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1289 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1290 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1291 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1292 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1293 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1294 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1295 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1296 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1297 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1298 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1299 attn1; */ 1300#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074 1301#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084 1302/* [RW 32] third 32b for enabling the output for function 1 output0. mapped 1303 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1304 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1305 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1306 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1307 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1308 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1309 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1310 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1311 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1312 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1313 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1314 attn1; */ 1315#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114 1316#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124 1317/* [RW 32] third 32b for enabling the output for close the gate nig. mapped 1318 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1319 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1320 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1321 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1322 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1323 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1324 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1325 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1326 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1327 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1328 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1329 attn1; */ 1330#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4 1331#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194 1332/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped 1333 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP 1334 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; 1335 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 1336 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 1337 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 1338 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 1339 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 1340 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 1341 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 1342 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 1343 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 1344 attn1; */ 1345#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104 1346#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4 1347/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 1348 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1349 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1350 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1351 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1352 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1353 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1354 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1355 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1356 Latched timeout attention; [27] GRC Latched reserved access attention; 1357 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1358 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1359#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 1360#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098 1361#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8 1362#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8 1363#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8 1364#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8 1365/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 1366 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1367 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1368 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1369 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1370 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1371 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1372 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1373 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1374 Latched timeout attention; [27] GRC Latched reserved access attention; 1375 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1376 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1377#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 1378#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138 1379#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158 1380#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168 1381#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178 1382#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188 1383/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped 1384 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1385 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1386 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1387 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1388 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1389 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1390 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1391 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1392 Latched timeout attention; [27] GRC Latched reserved access attention; 1393 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1394 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1395#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 1396#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 1397/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped 1398 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 1399 General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 1400 [7] General attn9; [8] General attn10; [9] General attn11; [10] General 1401 attn12; [11] General attn13; [12] General attn14; [13] General attn15; 1402 [14] General attn16; [15] General attn17; [16] General attn18; [17] 1403 General attn19; [18] General attn20; [19] General attn21; [20] Main power 1404 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 1405 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 1406 Latched timeout attention; [27] GRC Latched reserved access attention; 1407 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 1408 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */ 1409#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 1410#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 1411/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped 1412 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1413 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1414 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1415 * parity; [31-10] Reserved; */ 1416#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 1417/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped 1418 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 1419 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 1420 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 1421 * parity; [31-10] Reserved; */ 1422#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 1423/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 1424 128 bit vector */ 1425#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 1426#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 1427#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 1428#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 1429#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 1430#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 1431#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 1432#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 1433#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 1434#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 1435#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 1436#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 1437#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 1438#define MISC_REG_AEU_GENERAL_MASK 0xa61c 1439/* [RW 32] first 32b for inverting the input for function 0; for each bit: 1440 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for 1441 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; 1442 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; 1443 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 1444 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 1445 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 1446 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication 1447 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS 1448 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw 1449 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM 1450 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI 1451 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */ 1452#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c 1453#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c 1454/* [RW 32] second 32b for inverting the input for function 0; for each bit: 1455 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity 1456 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw 1457 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM 1458 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw 1459 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 1460 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 1461 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 1462 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 1463 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 1464 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 1465 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 1466 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */ 1467#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230 1468#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240 1469/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 1470 [9:8] = raserved. Zero = mask; one = unmask */ 1471#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 1472#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 1473/* [RW 1] If set a system kill occurred */ 1474#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 1475/* [RW 32] Represent the status of the input vector to the AEU when a system 1476 kill occurred. The register is reset in por reset. Mapped as follows: [0] 1477 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 1478 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 1479 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 1480 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 1481 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 1482 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 1483 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 1484 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 1485 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 1486 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 1487 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw 1488 interrupt; */ 1489#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 1490#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 1491#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 1492#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c 1493/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1 1494 Port. */ 1495#define MISC_REG_BOND_ID 0xa400 1496/* [R 16] These bits indicate the part number for the chip. */ 1497#define MISC_REG_CHIP_NUM 0xa408 1498/* [R 4] These bits indicate the base revision of the chip. This value 1499 starts at 0x0 for the A0 tape-out and increments by one for each 1500 all-layer tape-out. */ 1501#define MISC_REG_CHIP_REV 0xa40c 1502/* [R 14] otp_misc_do[100:0] spare bits collection: 13:11- 1503 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72]; 1504 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */ 1505#define MISC_REG_CHIP_TYPE 0xac60 1506#define MISC_REG_CHIP_TYPE_57811_MASK (1<<1) 1507#define MISC_REG_CPMU_LP_DR_ENABLE 0xa858 1508/* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled 1509 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 1510 * 25MHz. Reset on hard reset. */ 1511#define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c 1512/* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI 1513 * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */ 1514#define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0 1515/* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that 1516 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM 1517 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that 1518 * the FW command that all Queues are empty is disabled. When 0 indicates 1519 * that the FW command that all Queues are empty is enabled. [2] - FW Early 1520 * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early 1521 * Exit command is disabled. When 0 indicates that the FW Early Exit command 1522 * is enabled. This bit applicable only in the EXIT Events Mask registers. 1523 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication 1524 * is disabled. When 0 indicates that the PBF Request indication is enabled. 1525 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF 1526 * Request indication is disabled. When 0 indicates that the Tx Other Than 1527 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 1528 * indicates that the RX EEE LPI Status indication is disabled. When 0 1529 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT 1530 * Events Masks registers; this bit masks the falling edge detect of the LPI 1531 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that 1532 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause 1533 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the 1534 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY 1535 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM 1536 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication 1537 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 1538 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 1539 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 1540 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE 1541 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication 1542 * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this 1543 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11] 1544 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE 1545 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI 1546 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 1547 * indicates that the P0 EEE LPI REQ indication is disabled. When =0 1548 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE 1549 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is 1550 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is 1551 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE 1552 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ 1553 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 1554 * REQ indication is disabled. When =0 indicates that the L1 indication is 1555 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates 1556 * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx 1557 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status 1558 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This 1559 * bit is applicable only in the EXIT Events Masks registers. [17] - L1 1560 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling 1561 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). 1562 * When =0 indicates that the L1 Status Falling Edge Detect indication from 1563 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in 1564 * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */ 1565#define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880 1566/* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates 1567 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain 1568 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates 1569 * that the FW command that all Queues are empty is disabled. When 0 1570 * indicates that the FW command that all Queues are empty is enabled. [2] - 1571 * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW 1572 * Early Exit command is disabled. When 0 indicates that the FW Early Exit 1573 * command is enabled. This bit applicable only in the EXIT Events Mask 1574 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request 1575 * indication is disabled. When 0 indicates that the PBF Request indication 1576 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other 1577 * Than PBF Request indication is disabled. When 0 indicates that the Tx 1578 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status 1579 * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. 1580 * When 0 indicates that the RX LPI Status indication is enabled. In the 1581 * EXIT Events Masks registers; this bit masks the falling edge detect of 1582 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 1583 * indicates that the Tx Pause indication is disabled. When 0 indicates that 1584 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 1585 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates 1586 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 1587 * indicates that the QM IDLE indication is disabled. When 0 indicates that 1588 * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] 1589 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for 1590 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for 1591 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 1592 * Status indication from the PCIE CORE is disabled. When 0 indicates that 1593 * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the 1594 * EXIT Events Masks registers; this bit masks the falling edge detect of 1595 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When 1596 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When 1597 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 1598 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication 1599 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is 1600 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE 1601 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ 1602 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates 1603 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that 1604 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 1605 * indicates that the L1 REQ indication is disabled. When =0 indicates that 1606 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. 1607 * When =1 indicates that the RX EEE LPI Status Falling Edge Detect 1608 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that 1609 * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE 1610 * LPI is on - off). This bit is applicable only in the EXIT Events Masks 1611 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the 1612 * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled 1613 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge 1614 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This 1615 * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz. 1616 * Reset on hard reset. */ 1617#define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888 1618/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number 1619 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only 1620 * register. Reset on hard reset. */ 1621#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8 1622/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number 1623 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only 1624 * register. Reset on hard reset. */ 1625#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc 1626/* [RW 32] The following driver registers(1...16) represent 16 drivers and 1627 32 clients. Each client can be controlled by one driver only. One in each 1628 bit represent that this driver control the appropriate client (Ex: bit 5 1629 is set means this driver control client number 5). addr1 = set; addr0 = 1630 clear; read from both addresses will give the same result = status. write 1631 to address 1 will set a request to control all the clients that their 1632 appropriate bit (in the write command) is set. if the client is free (the 1633 appropriate bit in all the other drivers is clear) one will be written to 1634 that driver register; if the client isn't free the bit will remain zero. 1635 if the appropriate bit is set (the driver request to gain control on a 1636 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 1637 interrupt will be asserted). write to address 0 will set a request to 1638 free all the clients that their appropriate bit (in the write command) is 1639 set. if the appropriate bit is clear (the driver request to free a client 1640 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 1641 be asserted). */ 1642#define MISC_REG_DRIVER_CONTROL_1 0xa510 1643#define MISC_REG_DRIVER_CONTROL_7 0xa3c8 1644/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0 1645 only. */ 1646#define MISC_REG_E1HMF_MODE 0xa5f8 1647/* [R 1] Status of four port mode path swap input pin. */ 1648#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c 1649/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - 1650 the path_swap output is equal to 4 port mode path swap input pin; if it 1651 is 1 - the path_swap output is equal to bit[1] of this register; [1] - 1652 Overwrite value. If bit[0] of this register is 1 this is the value that 1653 receives the path_swap output. Reset on Hard reset. */ 1654#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738 1655/* [R 1] Status of 4 port mode port swap input pin. */ 1656#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754 1657/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - 1658 the port_swap output is equal to 4 port mode port swap input pin; if it 1659 is 1 - the port_swap output is equal to bit[1] of this register; [1] - 1660 Overwrite value. If bit[0] of this register is 1 this is the value that 1661 receives the port_swap output. Reset on Hard reset. */ 1662#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734 1663/* [RW 32] Debug only: spare RW register reset by core reset */ 1664#define MISC_REG_GENERIC_CR_0 0xa460 1665#define MISC_REG_GENERIC_CR_1 0xa464 1666/* [RW 32] Debug only: spare RW register reset by por reset */ 1667#define MISC_REG_GENERIC_POR_1 0xa474 1668/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to 1669 use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO 1670 can not be configured as an output. Each output has its output enable in 1671 the MCP register space; but this bit needs to be set to make use of that. 1672 Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When 1673 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. 1674 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change 1675 the i/o to an output and will drive the TimeSync output. Bit[31:7]: 1676 spare. Global register. Reset by hard reset. */ 1677#define MISC_REG_GEN_PURP_HWG 0xa9a0 1678/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1679 these bits is written as a '1'; the corresponding SPIO bit will turn off 1680 it's drivers and become an input. This is the reset state of all GPIO 1681 pins. The read value of these bits will be a '1' if that last command 1682 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). 1683 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written 1684 as a '1'; the corresponding GPIO bit will drive low. The read value of 1685 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for 1686 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; 1687 SET When any of these bits is written as a '1'; the corresponding GPIO 1688 bit will drive high (if it has that capability). The read value of these 1689 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this 1690 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; 1691 RO; These bits indicate the read value of each of the eight GPIO pins. 1692 This is the result value of the pin; not the drive value. Writing these 1693 bits will have not effect. */ 1694#define MISC_REG_GPIO 0xa490 1695/* [RW 8] These bits enable the GPIO_INTs to signals event to the 1696 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] 1697 p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; 1698 [7] p1_gpio_3; */ 1699#define MISC_REG_GPIO_EVENT_EN 0xa2bc 1700/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a 1701 '1' to these bit clears the corresponding bit in the #OLD_VALUE register. 1702 This will acknowledge an interrupt on the falling edge of corresponding 1703 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; 1704 Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE 1705 register. This will acknowledge an interrupt on the rising edge of 1706 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; 1707 OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input 1708 value. When the ~INT_STATE bit is set; this bit indicates the OLD value 1709 of the pin such that if ~INT_STATE is set and this bit is '0'; then the 1710 interrupt is due to a low to high edge. If ~INT_STATE is set and this bit 1711 is '1'; then the interrupt is due to a high to low edge (reset value 0). 1712 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the 1713 current GPIO interrupt state for each GPIO pin. This bit is cleared when 1714 the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is 1715 set when the GPIO input does not match the current value in #OLD_VALUE 1716 (reset value 0). */ 1717#define MISC_REG_GPIO_INT 0xa494 1718/* [R 28] this field hold the last information that caused reserved 1719 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1720 [27:24] the master that caused the attention - according to the following 1721 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1722 dbu; 8 = dmae */ 1723#define MISC_REG_GRC_RSV_ATTN 0xa3c0 1724/* [R 28] this field hold the last information that caused timeout 1725 attention. bits [19:0] - address; [22:20] function; [23] reserved; 1726 [27:24] the master that caused the attention - according to the following 1727 encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1728 dbu; 8 = dmae */ 1729#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1730/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any 1731 access that does not finish within 1732 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is 1733 cleared; this timeout is disabled. If this timeout occurs; the GRC shall 1734 assert it attention output. */ 1735#define MISC_REG_GRC_TIMEOUT_EN 0xa280 1736/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of 1737 the bits is: [2:0] OAC reset value 001) CML output buffer bias control; 1738 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl 1739 (reset value 001) Charge pump current control; 111 for 720u; 011 for 1740 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00) 1741 Global bias control; When bit 7 is high bias current will be 10 0gh; When 1742 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8] 1743 Pll_observe (reset value 010) Bits to control observability. bit 10 is 1744 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl 1745 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V 1746 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning 1747 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted 1748 internally). [14] reserved (reset value 0) Reset for VCO sequencer is 1749 connected to RESET input directly. [15] capRetry_en (reset value 0) 1750 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset 1751 value 0) bit to continuously monitor vco freq (inverted). [17] 1752 freqDetRestart_en (reset value 0) bit to enable restart when not freq 1753 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable 1754 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value 1755 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20] 1756 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass 1757 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value 1758 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0) 1759 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to 1760 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force 1761 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to 1762 restart. [27] capSelectM_en (reset value 0) bit to enable cap select 1763 register bits. */ 1764#define MISC_REG_LCPLL_CTRL_1 0xa2a4 1765#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8 1766/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR 1767 * reset. */ 1768#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74 1769/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */ 1770#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78 1771/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR 1772 * reset. */ 1773#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c 1774/* [RW 4] Interrupt mask register #0 read/write */ 1775#define MISC_REG_MISC_INT_MASK 0xa388 1776/* [RW 1] Parity mask register #0 read/write */ 1777#define MISC_REG_MISC_PRTY_MASK 0xa398 1778/* [R 1] Parity register #0 read */ 1779#define MISC_REG_MISC_PRTY_STS 0xa38c 1780/* [RC 1] Parity register #0 read clear */ 1781#define MISC_REG_MISC_PRTY_STS_CLR 0xa390 1782#define MISC_REG_NIG_WOL_P0 0xa270 1783#define MISC_REG_NIG_WOL_P1 0xa274 1784/* [R 1] If set indicate that the pcie_rst_b was asserted without perst 1785 assertion */ 1786#define MISC_REG_PCIE_HOT_RESET 0xa618 1787/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911. 1788 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1 1789 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1 1790 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2 1791 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2 1792 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9] 1793 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1] 1794 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value 1795 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16] 1796 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset 1797 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value 1798 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0); 1799 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25] 1800 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27] 1801 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29] 1802 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31] 1803 testa_en (reset value 0); */ 1804#define MISC_REG_PLL_STORM_CTRL_1 0xa294 1805#define MISC_REG_PLL_STORM_CTRL_2 0xa298 1806#define MISC_REG_PLL_STORM_CTRL_3 0xa29c 1807#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0 1808/* [R 1] Status of 4 port mode enable input pin. */ 1809#define MISC_REG_PORT4MODE_EN 0xa750 1810/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - 1811 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 - 1812 * the port4mode_en output is equal to bit[1] of this register; [1] - 1813 * Overwrite value. If bit[0] of this register is 1 this is the value that 1814 * receives the port4mode_en output . */ 1815#define MISC_REG_PORT4MODE_EN_OVWR 0xa720 1816/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset; 1817 write/read zero = the specific block is in reset; addr 0-wr- the write 1818 value will be written to the register; addr 1-set - one will be written 1819 to all the bits that have the value of one in the data written (bits that 1820 have the value of zero will not be change) ; addr 2-clear - zero will be 1821 written to all the bits that have the value of one in the data written 1822 (bits that have the value of zero will not be change); addr 3-ignore; 1823 read ignore from all addr except addr 00; inside order of the bits is: 1824 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc; 1825 [5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7] 1826 rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn; 1827 [10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13] 1828 Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16] 1829 rst_pxp_rq_rd_wr; 31:17] reserved */ 1830#define MISC_REG_RESET_REG_1 0xa580 1831#define MISC_REG_RESET_REG_2 0xa590 1832/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is 1833 shared with the driver resides */ 1834#define MISC_REG_SHARED_MEM_ADDR 0xa2b4 1835/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; 1836 the corresponding SPIO bit will turn off it's drivers and become an 1837 input. This is the reset state of all SPIO pins. The read value of these 1838 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this 1839 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits 1840 is written as a '1'; the corresponding SPIO bit will drive low. The read 1841 value of these bits will be a '1' if that last command (#SET; #CLR; or 1842#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of 1843 these bits is written as a '1'; the corresponding SPIO bit will drive 1844 high (if it has that capability). The read value of these bits will be a 1845 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. 1846 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of 1847 each of the eight SPIO pins. This is the result value of the pin; not the 1848 drive value. Writing these bits will have not effect. Each 8 bits field 1849 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply 1850 from VAUX. (This is an output pin only; the FLOAT field is not applicable 1851 for this pin); [1] VAUX Disable; when pulsed low; disables supply form 1852 VAUX. (This is an output pin only; FLOAT field is not applicable for this 1853 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to 1854 select VAUX supply. (This is an output pin only; it is not controlled by 1855 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1856 field is not applicable for this pin; only the VALUE fields is relevant - 1857 it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] 1858 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1859 device ID select; read by UMP firmware. */ 1860#define MISC_REG_SPIO 0xa4fc 1861/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. 1862 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; 1863 [7:0] reserved */ 1864#define MISC_REG_SPIO_EVENT_EN 0xa2b8 1865/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the 1866 corresponding bit in the #OLD_VALUE register. This will acknowledge an 1867 interrupt on the falling edge of corresponding SPIO input (reset value 1868 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit 1869 in the #OLD_VALUE register. This will acknowledge an interrupt on the 1870 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE 1871 RO; These bits indicate the old value of the SPIO input value. When the 1872 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such 1873 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due 1874 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the 1875 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE 1876 RO; These bits indicate the current SPIO interrupt state for each SPIO 1877 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR 1878 command bit is written. This bit is set when the SPIO input does not 1879 match the current value in #OLD_VALUE (reset value 0). */ 1880#define MISC_REG_SPIO_INT 0xa500 1881/* [RW 32] reload value for counter 4 if reload; the value will be reload if 1882 the counter reached zero and the reload bit 1883 (~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */ 1884#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc 1885/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses 1886 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 - 1887 timer 8 */ 1888#define MISC_REG_SW_TIMER_VAL 0xa5c0 1889/* [R 1] Status of two port mode path swap input pin. */ 1890#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758 1891/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the 1892 path_swap output is equal to 2 port mode path swap input pin; if it is 1 1893 - the path_swap output is equal to bit[1] of this register; [1] - 1894 Overwrite value. If bit[0] of this register is 1 this is the value that 1895 receives the path_swap output. Reset on Hard reset. */ 1896#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c 1897/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1898 loaded; 0-prepare; -unprepare */ 1899#define MISC_REG_UNPREPARED 0xa424 1900#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1901#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1902#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1903#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1904#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1905/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or 1906 * not it is the recipient of the message on the MDIO interface. The value 1907 * is compared to the value on ctrl_md_devad. Drives output 1908 * misc_xgxs0_phy_addr. Global register. */ 1909#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc 1910#define MISC_REG_WC0_RESET 0xac30 1911/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system 1912 side. This should be less than or equal to phy_port_mode; if some of the 1913 ports are not used. This enables reduction of frequency on the core side. 1914 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - 1915 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap 1916 input for the XMAC_MP core; and should be changed only while reset is 1917 held low. Reset on Hard reset. */ 1918#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964 1919/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp 1920 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 1921 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the 1922 XMAC_MP core; and should be changed only while reset is held low. Reset 1923 on Hard reset. */ 1924#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960 1925/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. 1926 * Reads from this register will clear bits 31:0. */ 1927#define MSTAT_REG_RX_STAT_GR64_LO 0x200 1928/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits 1929 * 31:0. Reads from this register will clear bits 31:0. */ 1930#define MSTAT_REG_TX_STAT_GTXPOK_LO 0 1931#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0) 1932#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1) 1933#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4) 1934#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2) 1935#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3) 1936#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0) 1937#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0) 1938#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0) 1939#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9) 1940#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15) 1941#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18) 1942/* [RW 1] Input enable for RX_BMAC0 IF */ 1943#define NIG_REG_BMAC0_IN_EN 0x100ac 1944/* [RW 1] output enable for TX_BMAC0 IF */ 1945#define NIG_REG_BMAC0_OUT_EN 0x100e0 1946/* [RW 1] output enable for TX BMAC pause port 0 IF */ 1947#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 1948/* [RW 1] output enable for RX_BMAC0_REGS IF */ 1949#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 1950/* [RW 1] output enable for RX BRB1 port0 IF */ 1951#define NIG_REG_BRB0_OUT_EN 0x100f8 1952/* [RW 1] Input enable for TX BRB1 pause port 0 IF */ 1953#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 1954/* [RW 1] output enable for RX BRB1 port1 IF */ 1955#define NIG_REG_BRB1_OUT_EN 0x100fc 1956/* [RW 1] Input enable for TX BRB1 pause port 1 IF */ 1957#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1958/* [RW 1] output enable for RX BRB1 LP IF */ 1959#define NIG_REG_BRB_LB_OUT_EN 0x10100 1960/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1961 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 1962 72:73]-vnic_num; 81:74]-sideband_info */ 1963#define NIG_REG_DEBUG_PACKET_LB 0x10800 1964/* [RW 1] Input enable for TX Debug packet */ 1965#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc 1966/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all 1967 packets from PBFare not forwarded to the MAC and just deleted from FIFO. 1968 First packet may be deleted from the middle. And last packet will be 1969 always deleted till the end. */ 1970#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 1971/* [RW 1] Output enable to EMAC0 */ 1972#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 1973/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1974 to emac for port0; other way to bmac for port0 */ 1975#define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1976/* [RW 1] Input enable for TX PBF user packet port0 IF */ 1977#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc 1978/* [RW 1] Input enable for TX PBF user packet port1 IF */ 1979#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0 1980/* [RW 1] Input enable for TX UMP management packet port0 IF */ 1981#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4 1982/* [RW 1] Input enable for RX_EMAC0 IF */ 1983#define NIG_REG_EMAC0_IN_EN 0x100a4 1984/* [RW 1] output enable for TX EMAC pause port 0 IF */ 1985#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 1986/* [R 1] status from emac0. This bit is set when MDINT from either the 1987 EXT_MDINT pin or from the Copper PHY is driven low. This condition must 1988 be cleared in the attached PHY device that is driving the MINT pin. */ 1989#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 1990/* [WB 48] This address space contains BMAC0 registers. The BMAC registers 1991 are described in appendix A. In order to access the BMAC0 registers; the 1992 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be 1993 added to each BMAC register offset */ 1994#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 1995/* [WB 48] This address space contains BMAC1 registers. The BMAC registers 1996 are described in appendix A. In order to access the BMAC0 registers; the 1997 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be 1998 added to each BMAC register offset */ 1999#define NIG_REG_INGRESS_BMAC1_MEM 0x11000 2000/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ 2001#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 2002/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data 2003 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */ 2004#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 2005/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch 2006 logic for interrupts must be used. Enable per bit of interrupt of 2007 ~latch_status.latch_status */ 2008#define NIG_REG_LATCH_BC_0 0x16210 2009/* [RW 27] Latch for each interrupt from Unicore.b[0] 2010 status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; 2011 b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; 2012 b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; 2013 b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; 2014 b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; 2015 b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; 2016 b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; 2017 b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; 2018 b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; 2019 b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; 2020 b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; 2021 b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */ 2022#define NIG_REG_LATCH_STATUS_0 0x18000 2023/* [RW 1] led 10g for port 0 */ 2024#define NIG_REG_LED_10G_P0 0x10320 2025/* [RW 1] led 10g for port 1 */ 2026#define NIG_REG_LED_10G_P1 0x10324 2027/* [RW 1] Port0: This bit is set to enable the use of the 2028 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 2029 defined below. If this bit is cleared; then the blink rate will be about 2030 8Hz. */ 2031#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 2032/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for 2033 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field 2034 is reset to 0x080; giving a default blink period of approximately 8Hz. */ 2035#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 2036/* [RW 1] Port0: If set along with the 2037 ~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0 2038 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 2039 bit; the Traffic LED will blink with the blink rate specified in 2040 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 2041 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 2042 fields. */ 2043#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 2044/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The 2045 Traffic LED will then be controlled via bit ~nig_registers_ 2046 led_control_traffic_p0.led_control_traffic_p0 and bit 2047 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */ 2048#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 2049/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; 2050 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also 2051 set; the LED will blink with blink rate specified in 2052 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 2053 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 2054 fields. */ 2055#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 2056/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 2057 9-11PHY7; 12 MAC4; 13-15 PHY10; */ 2058#define NIG_REG_LED_MODE_P0 0x102f0 2059/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- 2060 tsdm enable; b2- usdm enable */ 2061#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 2062#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074 2063/* [RW 1] SAFC enable for port0. This register may get 1 only when 2064 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same 2065 port */ 2066#define NIG_REG_LLFC_ENABLE_0 0x16208 2067#define NIG_REG_LLFC_ENABLE_1 0x1620c 2068/* [RW 16] classes are high-priority for port0 */ 2069#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 2070#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c 2071/* [RW 16] classes are low-priority for port0 */ 2072#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 2073#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064 2074/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ 2075#define NIG_REG_LLFC_OUT_EN_0 0x160c8 2076#define NIG_REG_LLFC_OUT_EN_1 0x160cc 2077#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c 2078#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 2079#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 2080#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 2081/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 2082#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 2083/* [RW 2] Determine the classification participants. 0: no classification.1: 2084 classification upon VLAN id. 2: classification upon MAC address. 3: 2085 classification upon both VLAN id & MAC addr. */ 2086#define NIG_REG_LLH0_CLS_TYPE 0x16080 2087/* [RW 32] cm header for llh0 */ 2088#define NIG_REG_LLH0_CM_HEADER 0x1007c 2089#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc 2090#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 2091/* [RW 16] destination TCP address 1. The LLH will look for this address in 2092 all incoming packets. */ 2093#define NIG_REG_LLH0_DEST_TCP_0 0x10220 2094/* [RW 16] destination UDP address 1 The LLH will look for this address in 2095 all incoming packets. */ 2096#define NIG_REG_LLH0_DEST_UDP_0 0x10214 2097#define NIG_REG_LLH0_ERROR_MASK 0x1008c 2098/* [RW 8] event id for llh0 */ 2099#define NIG_REG_LLH0_EVENT_ID 0x10084 2100#define NIG_REG_LLH0_FUNC_EN 0x160fc 2101#define NIG_REG_LLH0_FUNC_MEM 0x16180 2102#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140 2103#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 2104/* [RW 1] Determine the IP version to look for in 2105 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */ 2106#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 2107/* [RW 1] t bit for llh0 */ 2108#define NIG_REG_LLH0_T_BIT 0x10074 2109/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ 2110#define NIG_REG_LLH0_VLAN_ID_0 0x1022c 2111/* [RW 8] init credit counter for port0 in LLH */ 2112#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554 2113#define NIG_REG_LLH0_XCM_MASK 0x10130 2114#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248 2115/* [RW 1] send to BRB1 if no match on any of RMP rules. */ 2116#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 2117/* [RW 2] Determine the classification participants. 0: no classification.1: 2118 classification upon VLAN id. 2: classification upon MAC address. 3: 2119 classification upon both VLAN id & MAC addr. */ 2120#define NIG_REG_LLH1_CLS_TYPE 0x16084 2121/* [RW 32] cm header for llh1 */ 2122#define NIG_REG_LLH1_CM_HEADER 0x10080 2123#define NIG_REG_LLH1_ERROR_MASK 0x10090 2124/* [RW 8] event id for llh1 */ 2125#define NIG_REG_LLH1_EVENT_ID 0x10088 2126#define NIG_REG_LLH1_FUNC_EN 0x16104 2127#define NIG_REG_LLH1_FUNC_MEM 0x161c0 2128#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160 2129#define NIG_REG_LLH1_FUNC_MEM_SIZE 16 2130/* [RW 1] When this bit is set; the LLH will classify the packet before 2131 * sending it to the BRB or calculating WoL on it. This bit controls port 1 2132 * only. The legacy llh_multi_function_mode bit controls port 0. */ 2133#define NIG_REG_LLH1_MF_MODE 0x18614 2134/* [RW 8] init credit counter for port1 in LLH */ 2135#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564 2136#define NIG_REG_LLH1_XCM_MASK 0x10134 2137/* [RW 1] When this bit is set; the LLH will expect all packets to be with 2138 e1hov */ 2139#define NIG_REG_LLH_E1HOV_MODE 0x160d8 2140/* [RW 1] When this bit is set; the LLH will classify the packet before 2141 sending it to the BRB or calculating WoL on it. */ 2142#define NIG_REG_LLH_MF_MODE 0x16024 2143#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 2144#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 2145/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 2146#define NIG_REG_NIG_EMAC0_EN 0x1003c 2147/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */ 2148#define NIG_REG_NIG_EMAC1_EN 0x10040 2149/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the 2150 EMAC0 to strip the CRC from the ingress packets. */ 2151#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 2152/* [R 32] Interrupt register #0 read */ 2153#define NIG_REG_NIG_INT_STS_0 0x103b0 2154#define NIG_REG_NIG_INT_STS_1 0x103c0 2155/* [RC 32] Interrupt register #0 read clear */ 2156#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4 2157/* [R 32] Legacy E1 and E1H location for parity error mask register. */ 2158#define NIG_REG_NIG_PRTY_MASK 0x103dc 2159/* [RW 32] Parity mask register #0 read/write */ 2160#define NIG_REG_NIG_PRTY_MASK_0 0x183c8 2161#define NIG_REG_NIG_PRTY_MASK_1 0x183d8 2162/* [R 32] Legacy E1 and E1H location for parity error status register. */ 2163#define NIG_REG_NIG_PRTY_STS 0x103d0 2164/* [R 32] Parity register #0 read */ 2165#define NIG_REG_NIG_PRTY_STS_0 0x183bc 2166#define NIG_REG_NIG_PRTY_STS_1 0x183cc 2167/* [R 32] Legacy E1 and E1H location for parity error status clear register. */ 2168#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4 2169/* [RC 32] Parity register #0 read clear */ 2170#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0 2171#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0 2172#define MCPR_IMC_COMMAND_ENABLE (1L<<31) 2173#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 2174#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 2175#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 2176/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2177 * Ethernet header. */ 2178#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 2179/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in 2180 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be 2181 * disabled when this bit is set. */ 2182#define NIG_REG_P0_HWPFC_ENABLE 0x18078 2183#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 2184#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440 2185/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for 2186 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16 2187 * indicates the validity of the data in the buffer. Writing a 1 to bit 16 2188 * will clear the buffer. 2189 */ 2190#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c 2191/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2192 * the host. This location returns the lower 32 bits of timestamp value. 2193 */ 2194#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754 2195/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2196 * the host. This location returns the upper 32 bits of timestamp value. 2197 */ 2198#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758 2199/* [RW 11] Mask register for the various parameters used in determining PTP 2200 * packet presence. Set each bit to 1 to mask out the particular parameter. 2201 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 2202 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 2203 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 2204 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 2205 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 2206 * MAC DA 2. The reset default is set to mask out all parameters. 2207 */ 2208#define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0 2209/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 2210 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 2211 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 2212 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 2213 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 2214 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 2215 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 2216 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4 2217 * packets only and require that the packet is IPv4 for the rules to match. 2218 * Note that rules 4-7 are for IPv6 packets only and require that the packet 2219 * is IPv6 for the rules to match. 2220 */ 2221#define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4 2222/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */ 2223#define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac 2224/* [RW 1] Input enable for RX MAC interface. */ 2225#define NIG_REG_P0_MAC_IN_EN 0x185ac 2226/* [RW 1] Output enable for TX MAC interface */ 2227#define NIG_REG_P0_MAC_OUT_EN 0x185b0 2228/* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2229#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4 2230/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2231 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2232 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2233 * priority field is extracted from the outer-most VLAN in receive packet. 2234 * Only COS 0 and COS 1 are supported in E2. */ 2235#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054 2236/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits 2237 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables 2238 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2 2239 * frame format in timesync event detection on RX side. Bit 3 enables 2240 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event 2241 * detection on TX side. Bit 5 enables V2 frame format in timesync event 2242 * detection on TX side. Note that for HW to detect PTP packet and extract 2243 * data from the packet, at least one of the version bits of that traffic 2244 * direction has to be enabled. 2245 */ 2246#define NIG_REG_P0_PTP_EN 0x18788 2247/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2248 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2249 * than one bit may be set; allowing multiple priorities to be mapped to one 2250 * COS. */ 2251#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058 2252/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2253 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2254 * than one bit may be set; allowing multiple priorities to be mapped to one 2255 * COS. */ 2256#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c 2257/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2258 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2259 * than one bit may be set; allowing multiple priorities to be mapped to one 2260 * COS. */ 2261#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0 2262/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A 2263 * priority is mapped to COS 3 when the corresponding mask bit is 1. More 2264 * than one bit may be set; allowing multiple priorities to be mapped to one 2265 * COS. */ 2266#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4 2267/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A 2268 * priority is mapped to COS 4 when the corresponding mask bit is 1. More 2269 * than one bit may be set; allowing multiple priorities to be mapped to one 2270 * COS. */ 2271#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8 2272/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A 2273 * priority is mapped to COS 5 when the corresponding mask bit is 1. More 2274 * than one bit may be set; allowing multiple priorities to be mapped to one 2275 * COS. */ 2276#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc 2277/* [R 1] RX FIFO for receiving data from MAC is empty. */ 2278/* [RW 15] Specify which of the credit registers the client is to be mapped 2279 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 2280 * clients that are not subject to WFQ credit blocking - their 2281 * specifications here are not used. */ 2282#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0 2283/* [RW 32] Specify which of the credit registers the client is to be mapped 2284 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2285 * for client 0; bits [35:32] are for client 8. For clients that are not 2286 * subject to WFQ credit blocking - their specifications here are not used. 2287 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2288 * input clients to ETS arbiter. The reset default is set for management and 2289 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2290 * use credit registers 0-5 respectively (0x543210876). Note that credit 2291 * registers can not be shared between clients. */ 2292#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688 2293/* [RW 4] Specify which of the credit registers the client is to be mapped 2294 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2295 * for client 0; bits [35:32] are for client 8. For clients that are not 2296 * subject to WFQ credit blocking - their specifications here are not used. 2297 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2298 * input clients to ETS arbiter. The reset default is set for management and 2299 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2300 * use credit registers 0-5 respectively (0x543210876). Note that credit 2301 * registers can not be shared between clients. */ 2302#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c 2303/* [RW 5] Specify whether the client competes directly in the strict 2304 * priority arbiter. The bits are mapped according to client ID (client IDs 2305 * are defined in tx_arb_priority_client). Default value is set to enable 2306 * strict priorities for clients 0-2 -- management and debug traffic. */ 2307#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8 2308/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The 2309 * bits are mapped according to client ID (client IDs are defined in 2310 * tx_arb_priority_client). Default value is 0 for not using WFQ credit 2311 * blocking. */ 2312#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec 2313/* [RW 32] Specify the upper bound that credit register 0 is allowed to 2314 * reach. */ 2315#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c 2316#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110 2317#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114 2318#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118 2319#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c 2320#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0 2321#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4 2322#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8 2323#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac 2324/* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2325 * when it is time to increment. */ 2326#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8 2327#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc 2328#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100 2329#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104 2330#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108 2331#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690 2332#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694 2333#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698 2334#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c 2335/* [RW 12] Specify the number of strict priority arbitration slots between 2336 * two round-robin arbitration slots to avoid starvation. A value of 0 means 2337 * no strict priority cycles - the strict priority with anti-starvation 2338 * arbiter becomes a round-robin arbiter. */ 2339#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4 2340/* [RW 15] Specify the client number to be assigned to each priority of the 2341 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] 2342 * are for priority 0 client; bits [14:12] are for priority 4 client. The 2343 * clients are assigned the following IDs: 0-management; 1-debug traffic 2344 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2345 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) 2346 * for management at priority 0; debug traffic at priorities 1 and 2; COS0 2347 * traffic at priority 3; and COS1 traffic at priority 4. */ 2348#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4 2349/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2350 * Ethernet header. */ 2351#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c 2352#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 2353#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460a 2354/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for 2355 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16 2356 * indicates the validity of the data in the buffer. Writing a 1 to bit 16 2357 * will clear the buffer. 2358 */ 2359#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774 2360/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2361 * the host. This location returns the lower 32 bits of timestamp value. 2362 */ 2363#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c 2364/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2365 * the host. This location returns the upper 32 bits of timestamp value. 2366 */ 2367#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770 2368/* [RW 11] Mask register for the various parameters used in determining PTP 2369 * packet presence. Set each bit to 1 to mask out the particular parameter. 2370 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 2371 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 2372 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 2373 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 2374 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 2375 * MAC DA 2. The reset default is set to mask out all parameters. 2376 */ 2377#define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8 2378/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 2379 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 2380 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 2381 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 2382 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 2383 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 2384 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 2385 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4 2386 * packets only and require that the packet is IPv4 for the rules to match. 2387 * Note that rules 4-7 are for IPv6 packets only and require that the packet 2388 * is IPv6 for the rules to match. 2389 */ 2390#define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc 2391/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */ 2392#define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4 2393/* [RW 32] Specify the client number to be assigned to each priority of the 2394 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2395 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2396 * client; bits [35-32] are for priority 8 client. The clients are assigned 2397 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2398 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2399 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2400 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2401 * accommodate the 9 input clients to ETS arbiter. */ 2402#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680 2403/* [RW 4] Specify the client number to be assigned to each priority of the 2404 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2405 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2406 * client; bits [35-32] are for priority 8 client. The clients are assigned 2407 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2408 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2409 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2410 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2411 * accommodate the 9 input clients to ETS arbiter. */ 2412#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684 2413/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP 2414 * packets to BRB LB interface to forward the packet to the host. All 2415 * packets from MCP are forwarded to the network when this bit is cleared - 2416 * regardless of the configured destination in tx_mng_destination register. 2417 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter 2418 * for BRB LB interface is bypassed and PBF LB traffic is always selected to 2419 * send to BRB LB. 2420 */ 2421#define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4 2422#define NIG_REG_P1_HWPFC_ENABLE 0x181d0 2423#define NIG_REG_P1_MAC_IN_EN 0x185c0 2424/* [RW 1] Output enable for TX MAC interface */ 2425#define NIG_REG_P1_MAC_OUT_EN 0x185c4 2426/* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 2427#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8 2428/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 2429 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the 2430 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 2431 * priority field is extracted from the outer-most VLAN in receive packet. 2432 * Only COS 0 and COS 1 are supported in E2. */ 2433#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8 2434/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits 2435 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables 2436 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2 2437 * frame format in timesync event detection on RX side. Bit 3 enables 2438 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event 2439 * detection on TX side. Bit 5 enables V2 frame format in timesync event 2440 * detection on TX side. Note that for HW to detect PTP packet and extract 2441 * data from the packet, at least one of the version bits of that traffic 2442 * direction has to be enabled. 2443 */ 2444#define NIG_REG_P1_PTP_EN 0x187b0 2445/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 2446 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 2447 * than one bit may be set; allowing multiple priorities to be mapped to one 2448 * COS. */ 2449#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac 2450/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 2451 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 2452 * than one bit may be set; allowing multiple priorities to be mapped to one 2453 * COS. */ 2454#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0 2455/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 2456 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 2457 * than one bit may be set; allowing multiple priorities to be mapped to one 2458 * COS. */ 2459#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8 2460/* [R 1] RX FIFO for receiving data from MAC is empty. */ 2461#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c 2462/* [R 1] TLLH FIFO is empty. */ 2463#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338 2464/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for 2465 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 2466 * indicates the validity of the data in the buffer. Bit 17 indicates that 2467 * the sequence ID is valid and it is waiting for the TX timestamp value. 2468 * Bit 18 indicates whether the timestamp is from a SW request (value of 1) 2469 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. 2470 */ 2471#define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0 2472/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2473 * MCP. This location returns the lower 32 bits of timestamp value. 2474 */ 2475#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8 2476/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2477 * MCP. This location returns the upper 32 bits of timestamp value. 2478 */ 2479#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc 2480/* [RW 11] Mask register for the various parameters used in determining PTP 2481 * packet presence. Set each bit to 1 to mask out the particular parameter. 2482 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 2483 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 2484 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 2485 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 2486 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 2487 * MAC DA 2. The reset default is set to mask out all parameters. 2488 */ 2489#define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0 2490/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 2491 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 2492 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 2493 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 2494 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 2495 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 2496 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 2497 * default is to mask out all of the rules. 2498 */ 2499#define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4 2500/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for 2501 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 2502 * indicates the validity of the data in the buffer. Bit 17 indicates that 2503 * the sequence ID is valid and it is waiting for the TX timestamp value. 2504 * Bit 18 indicates whether the timestamp is from a SW request (value of 1) 2505 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. 2506 */ 2507#define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec 2508/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2509 * MCP. This location returns the lower 32 bits of timestamp value. 2510 */ 2511#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4 2512/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 2513 * MCP. This location returns the upper 32 bits of timestamp value. 2514 */ 2515#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8 2516/* [RW 11] Mask register for the various parameters used in determining PTP 2517 * packet presence. Set each bit to 1 to mask out the particular parameter. 2518 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 2519 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 2520 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 2521 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 2522 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 2523 * MAC DA 2. The reset default is set to mask out all parameters. 2524 */ 2525#define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8 2526/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 2527 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 2528 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 2529 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 2530 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 2531 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 2532 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 2533 * default is to mask out all of the rules. 2534 */ 2535#define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc 2536/* [RW 32] Specify which of the credit registers the client is to be mapped 2537 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 2538 * for client 0; bits [35:32] are for client 8. For clients that are not 2539 * subject to WFQ credit blocking - their specifications here are not used. 2540 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2541 * input clients to ETS arbiter. The reset default is set for management and 2542 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2543 * use credit registers 0-5 respectively (0x543210876). Note that credit 2544 * registers can not be shared between clients. Note also that there are 2545 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2546 * credit registers 0-5 are valid. This register should be configured 2547 * appropriately before enabling WFQ. */ 2548#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8 2549/* [RW 4] Specify which of the credit registers the client is to be mapped 2550 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 2551 * for client 0; bits [35:32] are for client 8. For clients that are not 2552 * subject to WFQ credit blocking - their specifications here are not used. 2553 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 2554 * input clients to ETS arbiter. The reset default is set for management and 2555 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 2556 * use credit registers 0-5 respectively (0x543210876). Note that credit 2557 * registers can not be shared between clients. Note also that there are 2558 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 2559 * credit registers 0-5 are valid. This register should be configured 2560 * appropriately before enabling WFQ. */ 2561#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec 2562/* [RW 9] Specify whether the client competes directly in the strict 2563 * priority arbiter. The bits are mapped according to client ID (client IDs 2564 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic 2565 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 2566 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. 2567 * Default value is set to enable strict priorities for all clients. */ 2568#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234 2569/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The 2570 * bits are mapped according to client ID (client IDs are defined in 2571 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 2572 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 2573 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 2574 * 0 for not using WFQ credit blocking. */ 2575#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238 2576#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258 2577#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c 2578#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260 2579#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264 2580#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268 2581#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4 2582/* [RW 32] Specify the weight (in bytes) to be added to credit register 0 2583 * when it is time to increment. */ 2584#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244 2585#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248 2586#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c 2587#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250 2588#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254 2589#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0 2590/* [RW 12] Specify the number of strict priority arbitration slots between 2591 two round-robin arbitration slots to avoid starvation. A value of 0 means 2592 no strict priority cycles - the strict priority with anti-starvation 2593 arbiter becomes a round-robin arbiter. */ 2594#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240 2595/* [RW 32] Specify the client number to be assigned to each priority of the 2596 strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2597 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2598 client; bits [35-32] are for priority 8 client. The clients are assigned 2599 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2600 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2601 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2602 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2603 accommodate the 9 input clients to ETS arbiter. Note that this register 2604 is the same as the one for port 0, except that port 1 only has COS 0-2 2605 traffic. There is no traffic for COS 3-5 of port 1. */ 2606#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0 2607/* [RW 4] Specify the client number to be assigned to each priority of the 2608 strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2609 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2610 client; bits [35-32] are for priority 8 client. The clients are assigned 2611 the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2612 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2613 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2614 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2615 accommodate the 9 input clients to ETS arbiter. Note that this register 2616 is the same as the one for port 0, except that port 1 only has COS 0-2 2617 traffic. There is no traffic for COS 3-5 of port 1. */ 2618#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4 2619/* [R 1] TX FIFO for transmitting data to MAC is empty. */ 2620#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594 2621/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP 2622 * packets to BRB LB interface to forward the packet to the host. All 2623 * packets from MCP are forwarded to the network when this bit is cleared - 2624 * regardless of the configured destination in tx_mng_destination register. 2625 */ 2626#define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8 2627/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets 2628 forwarded to the host. */ 2629#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8 2630/* [RW 32] Specify the upper bound that credit register 0 is allowed to 2631 * reach. */ 2632/* [RW 1] Pause enable for port0. This register may get 1 only when 2633 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2634 port */ 2635#define NIG_REG_PAUSE_ENABLE_0 0x160c0 2636#define NIG_REG_PAUSE_ENABLE_1 0x160c4 2637/* [RW 1] Input enable for RX PBF LP IF */ 2638#define NIG_REG_PBF_LB_IN_EN 0x100b4 2639/* [RW 1] Value of this register will be transmitted to port swap when 2640 ~nig_registers_strap_override.strap_override =1 */ 2641#define NIG_REG_PORT_SWAP 0x10394 2642/* [RW 1] PPP enable for port0. This register may get 1 only when 2643 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the 2644 * same port */ 2645#define NIG_REG_PPP_ENABLE_0 0x160b0 2646#define NIG_REG_PPP_ENABLE_1 0x160b4 2647/* [RW 1] output enable for RX parser descriptor IF */ 2648#define NIG_REG_PRS_EOP_OUT_EN 0x10104 2649/* [RW 1] Input enable for RX parser request IF */ 2650#define NIG_REG_PRS_REQ_IN_EN 0x100b8 2651/* [RW 5] control to serdes - CL45 DEVAD */ 2652#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 2653/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */ 2654#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c 2655/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ 2656#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 2657/* [R 1] status from serdes0 that inputs to interrupt logic of link status */ 2658#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 2659/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2660 for port0 */ 2661#define NIG_REG_STAT0_BRB_DISCARD 0x105f0 2662/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure 2663 for port0 */ 2664#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 2665/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2666 between 1024 and 1522 bytes for port0 */ 2667#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 2668/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2669 between 1523 bytes and above for port0 */ 2670#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 2671/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2672 for port1 */ 2673#define NIG_REG_STAT1_BRB_DISCARD 0x10628 2674/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2675 between 1024 and 1522 bytes for port1 */ 2676#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 2677/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2678 between 1523 bytes and above for port1 */ 2679#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 2680/* [WB_R 64] Rx statistics : User octets received for LP */ 2681#define NIG_REG_STAT2_BRB_OCTET 0x107e0 2682#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 2683#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c 2684/* [RW 1] port swap mux selection. If this register equal to 0 then port 2685 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then 2686 ort swap is equal to ~nig_registers_port_swap.port_swap */ 2687#define NIG_REG_STRAP_OVERRIDE 0x10398 2688/* [WB 64] Addresses for TimeSync related registers in the timesync 2689 * generator sub-module. 2690 */ 2691#define NIG_REG_TIMESYNC_GEN_REG 0x18800 2692/* [RW 1] output enable for RX_XCM0 IF */ 2693#define NIG_REG_XCM0_OUT_EN 0x100f0 2694/* [RW 1] output enable for RX_XCM1 IF */ 2695#define NIG_REG_XCM1_OUT_EN 0x100f4 2696/* [RW 1] control to xgxs - remote PHY in-band MDIO */ 2697#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 2698/* [RW 5] control to xgxs - CL45 DEVAD */ 2699#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 2700/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ 2701#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 2702/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 2703#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 2704/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 2705#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 2706/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ 2707#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 2708/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */ 2709#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 2710/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ 2711#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 2712#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0) 2713#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9) 2714#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15) 2715#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18) 2716#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 2717/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */ 2718#define PBF_REG_COS0_UPPER_BOUND 0x15c05c 2719/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2720 * of port 0. */ 2721#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc 2722/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2723 * of port 1. */ 2724#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4 2725/* [RW 31] The weight of COS0 in the ETS command arbiter. */ 2726#define PBF_REG_COS0_WEIGHT 0x15c054 2727/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */ 2728#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8 2729/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */ 2730#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0 2731/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */ 2732#define PBF_REG_COS1_UPPER_BOUND 0x15c060 2733/* [RW 31] The weight of COS1 in the ETS command arbiter. */ 2734#define PBF_REG_COS1_WEIGHT 0x15c058 2735/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */ 2736#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac 2737/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */ 2738#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4 2739/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */ 2740#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0 2741/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */ 2742#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8 2743/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */ 2744#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4 2745/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */ 2746#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8 2747/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */ 2748#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc 2749/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte 2750 * lines. */ 2751#define PBF_REG_CREDIT_LB_Q 0x140338 2752/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte 2753 * lines. */ 2754#define PBF_REG_CREDIT_Q0 0x14033c 2755/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte 2756 * lines. */ 2757#define PBF_REG_CREDIT_Q1 0x140340 2758/* [RW 1] Disable processing further tasks from port 0 (after ending the 2759 current task in process). */ 2760#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 2761/* [RW 1] Disable processing further tasks from port 1 (after ending the 2762 current task in process). */ 2763#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 2764/* [RW 1] Disable processing further tasks from port 4 (after ending the 2765 current task in process). */ 2766#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c 2767#define PBF_REG_DISABLE_PF 0x1402e8 2768#define PBF_REG_DISABLE_VF 0x1402ec 2769/* [RW 18] For port 0: For each client that is subject to WFQ (the 2770 * corresponding bit is 1); indicates to which of the credit registers this 2771 * client is mapped. For clients which are not credit blocked; their mapping 2772 * is dont care. */ 2773#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288 2774/* [RW 9] For port 1: For each client that is subject to WFQ (the 2775 * corresponding bit is 1); indicates to which of the credit registers this 2776 * client is mapped. For clients which are not credit blocked; their mapping 2777 * is dont care. */ 2778#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c 2779/* [RW 6] For port 0: Bit per client to indicate if the client competes in 2780 * the strict priority arbiter directly (corresponding bit = 1); or first 2781 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2782 * lowest priority in the strict-priority arbiter. */ 2783#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278 2784/* [RW 3] For port 1: Bit per client to indicate if the client competes in 2785 * the strict priority arbiter directly (corresponding bit = 1); or first 2786 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2787 * lowest priority in the strict-priority arbiter. */ 2788#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c 2789/* [RW 6] For port 0: Bit per client to indicate if the client is subject to 2790 * WFQ credit blocking (corresponding bit = 1). */ 2791#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280 2792/* [RW 3] For port 0: Bit per client to indicate if the client is subject to 2793 * WFQ credit blocking (corresponding bit = 1). */ 2794#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284 2795/* [RW 16] For port 0: The number of strict priority arbitration slots 2796 * between 2 RR arbitration slots. A value of 0 means no strict priority 2797 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2798 * arbiter. */ 2799#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0 2800/* [RW 16] For port 1: The number of strict priority arbitration slots 2801 * between 2 RR arbitration slots. A value of 0 means no strict priority 2802 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2803 * arbiter. */ 2804#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4 2805/* [RW 18] For port 0: Indicates which client is connected to each priority 2806 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2807 * priority 5 is the lowest; to which the RR output is connected to (this is 2808 * not configurable). */ 2809#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270 2810/* [RW 9] For port 1: Indicates which client is connected to each priority 2811 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2812 * priority 5 is the lowest; to which the RR output is connected to (this is 2813 * not configurable). */ 2814#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274 2815/* [RW 1] Indicates that ETS is performed between the COSes in the command 2816 * arbiter. If reset strict priority w/ anti-starvation will be performed 2817 * w/o WFQ. */ 2818#define PBF_REG_ETS_ENABLED 0x15c050 2819/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2820 * Ethernet header. */ 2821#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8 2822/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2823#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8 2824/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest 2825 * priority in the command arbiter. */ 2826#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c 2827#define PBF_REG_IF_ENABLE_REG 0x140044 2828/* [RW 1] Init bit. When set the initial credits are copied to the credit 2829 registers (except the port credits). Should be set and then reset after 2830 the configuration of the block has ended. */ 2831#define PBF_REG_INIT 0x140000 2832/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte 2833 * lines. */ 2834#define PBF_REG_INIT_CRD_LB_Q 0x15c248 2835/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte 2836 * lines. */ 2837#define PBF_REG_INIT_CRD_Q0 0x15c230 2838/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte 2839 * lines. */ 2840#define PBF_REG_INIT_CRD_Q1 0x15c234 2841/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is 2842 copied to the credit register. Should be set and then reset after the 2843 configuration of the port has ended. */ 2844#define PBF_REG_INIT_P0 0x140004 2845/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is 2846 copied to the credit register. Should be set and then reset after the 2847 configuration of the port has ended. */ 2848#define PBF_REG_INIT_P1 0x140008 2849/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is 2850 copied to the credit register. Should be set and then reset after the 2851 configuration of the port has ended. */ 2852#define PBF_REG_INIT_P4 0x14000c 2853/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2854 * the LB queue. Reset upon init. */ 2855#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354 2856/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2857 * queue 0. Reset upon init. */ 2858#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358 2859/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2860 * queue 1. Reset upon init. */ 2861#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c 2862/* [RW 1] Enable for mac interface 0. */ 2863#define PBF_REG_MAC_IF0_ENABLE 0x140030 2864/* [RW 1] Enable for mac interface 1. */ 2865#define PBF_REG_MAC_IF1_ENABLE 0x140034 2866/* [RW 1] Enable for the loopback interface. */ 2867#define PBF_REG_MAC_LB_ENABLE 0x140040 2868/* [RW 6] Bit-map indicating which headers must appear in the packet */ 2869#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4 2870/* [RW 16] The number of strict priority arbitration slots between 2 RR 2871 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the 2872 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */ 2873#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064 2874/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause 2875 not suppoterd. */ 2876#define PBF_REG_P0_ARB_THRSH 0x1400e4 2877/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */ 2878#define PBF_REG_P0_CREDIT 0x140200 2879/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte 2880 lines. */ 2881#define PBF_REG_P0_INIT_CRD 0x1400d0 2882/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2883 * port 0. Reset upon init. */ 2884#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308 2885/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */ 2886#define PBF_REG_P0_PAUSE_ENABLE 0x140014 2887/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */ 2888#define PBF_REG_P0_TASK_CNT 0x140204 2889/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2890 * freed from the task queue of port 0. Reset upon init. */ 2891#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0 2892/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */ 2893#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc 2894/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port 2895 * buffers in 16 byte lines. */ 2896#define PBF_REG_P1_CREDIT 0x140208 2897/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2898 * buffers in 16 byte lines. */ 2899#define PBF_REG_P1_INIT_CRD 0x1400d4 2900/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2901 * port 1. Reset upon init. */ 2902#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c 2903/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */ 2904#define PBF_REG_P1_TASK_CNT 0x14020c 2905/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2906 * freed from the task queue of port 1. Reset upon init. */ 2907#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4 2908/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */ 2909#define PBF_REG_P1_TQ_OCCUPANCY 0x140300 2910/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */ 2911#define PBF_REG_P4_CREDIT 0x140210 2912/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte 2913 lines. */ 2914#define PBF_REG_P4_INIT_CRD 0x1400e0 2915/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2916 * port 4. Reset upon init. */ 2917#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310 2918/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */ 2919#define PBF_REG_P4_TASK_CNT 0x140214 2920/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2921 * freed from the task queue of port 4. Reset upon init. */ 2922#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8 2923/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */ 2924#define PBF_REG_P4_TQ_OCCUPANCY 0x140304 2925/* [RW 5] Interrupt mask register #0 read/write */ 2926#define PBF_REG_PBF_INT_MASK 0x1401d4 2927/* [R 5] Interrupt register #0 read */ 2928#define PBF_REG_PBF_INT_STS 0x1401c8 2929/* [RW 20] Parity mask register #0 read/write */ 2930#define PBF_REG_PBF_PRTY_MASK 0x1401e4 2931/* [R 28] Parity register #0 read */ 2932#define PBF_REG_PBF_PRTY_STS 0x1401d8 2933/* [RC 20] Parity register #0 read clear */ 2934#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc 2935/* [RW 16] The Ethernet type value for L2 tag 0 */ 2936#define PBF_REG_TAG_ETHERTYPE_0 0x15c090 2937/* [RW 4] The length of the info field for L2 tag 0. The length is between 2938 * 2B and 14B; in 2B granularity */ 2939#define PBF_REG_TAG_LEN_0 0x15c09c 2940/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task 2941 * queue. Reset upon init. */ 2942#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c 2943/* [R 32] Cyclic counter for number of 8 byte lines freed from the task 2944 * queue 0. Reset upon init. */ 2945#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390 2946/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1. 2947 * Reset upon init. */ 2948#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394 2949/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB 2950 * queue. */ 2951#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8 2952/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */ 2953#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac 2954/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */ 2955#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0 2956#define PB_REG_CONTROL 0 2957/* [RW 2] Interrupt mask register #0 read/write */ 2958#define PB_REG_PB_INT_MASK 0x28 2959/* [R 2] Interrupt register #0 read */ 2960#define PB_REG_PB_INT_STS 0x1c 2961/* [RW 4] Parity mask register #0 read/write */ 2962#define PB_REG_PB_PRTY_MASK 0x38 2963/* [R 4] Parity register #0 read */ 2964#define PB_REG_PB_PRTY_STS 0x2c 2965/* [RC 4] Parity register #0 read clear */ 2966#define PB_REG_PB_PRTY_STS_CLR 0x30 2967#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0) 2968#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8) 2969#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1) 2970#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6) 2971#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7) 2972#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4) 2973#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3) 2974#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5) 2975#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2) 2976/* [R 8] Config space A attention dirty bits. Each bit indicates that the 2977 * corresponding PF generates config space A attention. Set by PXP. Reset by 2978 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits 2979 * from both paths. */ 2980#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010 2981/* [R 8] Config space B attention dirty bits. Each bit indicates that the 2982 * corresponding PF generates config space B attention. Set by PXP. Reset by 2983 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits 2984 * from both paths. */ 2985#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014 2986/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1 2987 * - enable. */ 2988#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194 2989/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask; 2990 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */ 2991#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c 2992/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1 2993 * - enable. */ 2994#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c 2995/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */ 2996#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100 2997/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */ 2998#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108 2999/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */ 3000#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110 3001/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 3002#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac 3003/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates 3004 * that the FLR register of the corresponding PF was set. Set by PXP. Reset 3005 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits 3006 * from both paths. */ 3007#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028 3008/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 3009 * to a bit in this register in order to clear the corresponding bit in 3010 * flr_request_pf_7_0 register. Note: register contains bits from both 3011 * paths. */ 3012#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418 3013/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit 3014 * indicates that the FLR register of the corresponding VF was set. Set by 3015 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */ 3016#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024 3017/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit 3018 * indicates that the FLR register of the corresponding VF was set. Set by 3019 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */ 3020#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018 3021/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit 3022 * indicates that the FLR register of the corresponding VF was set. Set by 3023 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */ 3024#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c 3025/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit 3026 * indicates that the FLR register of the corresponding VF was set. Set by 3027 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */ 3028#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020 3029/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit 3030 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target 3031 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW 3032 * arrived with a correctable error. Bit 3 - Configuration RW arrived with 3033 * an uncorrectable error. Bit 4 - Completion with Configuration Request 3034 * Retry Status. Bit 5 - Expansion ROM access received with a write request. 3035 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and 3036 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; 3037 * and pcie_rx_last not asserted. */ 3038#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068 3039#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c 3040#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430 3041#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434 3042#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438 3043/* [W 7] Writing 1 to each bit in this register clears a corresponding error 3044 * details register and enables logging new error details. Bit 0 - clears 3045 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears 3046 * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS 3047 * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32 3048 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 - 3049 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears 3050 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6 3051 * - clears TCPL_IN_TWO_RCBS_DETAILS. */ 3052#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c 3053 3054/* [R 9] Interrupt register #0 read */ 3055#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298 3056/* [RC 9] Interrupt register #0 read clear */ 3057#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c 3058/* [RW 2] Parity mask register #0 read/write */ 3059#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4 3060/* [R 2] Parity register #0 read */ 3061#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8 3062/* [RC 2] Parity register #0 read clear */ 3063#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac 3064/* [R 13] Details of first request received with error. [2:0] - PFID. [3] - 3065 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion 3066 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - 3067 * completer abort. 3 - Illegal value for this field. [12] valid - indicates 3068 * if there was a completion error since the last time this register was 3069 * cleared. */ 3070#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080 3071/* [R 18] Details of first ATS Translation Completion request received with 3072 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 3073 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - 3074 * unsupported request. 2 - completer abort. 3 - Illegal value for this 3075 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a 3076 * completion error since the last time this register was cleared. */ 3077#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084 3078/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to 3079 * a bit in this register in order to clear the corresponding bit in 3080 * shadow_bme_pf_7_0 register. MCP should never use this unless a 3081 * work-around is needed. Note: register contains bits from both paths. */ 3082#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458 3083/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the 3084 * VF enable register of the corresponding PF is written to 0 and was 3085 * previously 1. Set by PXP. Reset by MCP writing 1 to 3086 * sr_iov_disabled_request_clr. Note: register contains bits from both 3087 * paths. */ 3088#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030 3089/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read 3090 * completion did not return yet. 1 - tag is unused. Same functionality as 3091 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */ 3092#define PGLUE_B_REG_TAGS_63_32 0x9244 3093/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1 3094 * - enable. */ 3095#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170 3096/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */ 3097#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4 3098/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */ 3099#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc 3100/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */ 3101#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4 3102/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 3103#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0 3104/* [R 32] Address [31:0] of first read request not submitted due to error */ 3105#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098 3106/* [R 32] Address [63:32] of first read request not submitted due to error */ 3107#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c 3108/* [R 31] Details of first read request not submitted due to error. [4:0] 3109 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. 3110 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - 3111 * VFID. */ 3112#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0 3113/* [R 26] Details of first read request not submitted due to error. [15:0] 3114 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 3115 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 3116 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 3117 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 3118 * indicates if there was a request not submitted due to error since the 3119 * last time this register was cleared. */ 3120#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4 3121/* [R 32] Address [31:0] of first write request not submitted due to error */ 3122#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088 3123/* [R 32] Address [63:32] of first write request not submitted due to error */ 3124#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c 3125/* [R 31] Details of first write request not submitted due to error. [4:0] 3126 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] 3127 * - VFID. */ 3128#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090 3129/* [R 26] Details of first write request not submitted due to error. [15:0] 3130 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 3131 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 3132 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 3133 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 3134 * indicates if there was a request not submitted due to error since the 3135 * last time this register was cleared. */ 3136#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094 3137/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask; 3138 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any 3139 * value (Byte resolution address). */ 3140#define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128 3141#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c 3142#define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130 3143#define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134 3144#define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138 3145#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c 3146#define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140 3147/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1 3148 * - enable. */ 3149#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c 3150/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1 3151 * - enable. */ 3152#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180 3153/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1 3154 * - enable. */ 3155#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184 3156/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */ 3157#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8 3158/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */ 3159#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0 3160/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */ 3161#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8 3162/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 3163#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4 3164/* [R 26] Details of first target VF request accessing VF GRC space that 3165 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. 3166 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a 3167 * request accessing VF GRC space that failed permission check since the 3168 * last time this register was cleared. Permission checks are: function 3169 * permission; R/W permission; address range permission. */ 3170#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234 3171/* [R 31] Details of first target VF request with length violation (too many 3172 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). 3173 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] 3174 * valid - indicates if there was a request with length violation since the 3175 * last time this register was cleared. Length violations: length of more 3176 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and 3177 * length is more than 1 DW. */ 3178#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230 3179/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates 3180 * that there was a completion with uncorrectable error for the 3181 * corresponding PF. Set by PXP. Reset by MCP writing 1 to 3182 * was_error_pf_7_0_clr. */ 3183#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c 3184/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 3185 * to a bit in this register in order to clear the corresponding bit in 3186 * flr_request_pf_7_0 register. */ 3187#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470 3188/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit 3189 * indicates that there was a completion with uncorrectable error for the 3190 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 3191 * was_error_vf_127_96_clr. */ 3192#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078 3193/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP 3194 * writes 1 to a bit in this register in order to clear the corresponding 3195 * bit in was_error_vf_127_96 register. */ 3196#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474 3197/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit 3198 * indicates that there was a completion with uncorrectable error for the 3199 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 3200 * was_error_vf_31_0_clr. */ 3201#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c 3202/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 3203 * 1 to a bit in this register in order to clear the corresponding bit in 3204 * was_error_vf_31_0 register. */ 3205#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478 3206/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit 3207 * indicates that there was a completion with uncorrectable error for the 3208 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 3209 * was_error_vf_63_32_clr. */ 3210#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070 3211/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 3212 * 1 to a bit in this register in order to clear the corresponding bit in 3213 * was_error_vf_63_32 register. */ 3214#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c 3215/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit 3216 * indicates that there was a completion with uncorrectable error for the 3217 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 3218 * was_error_vf_95_64_clr. */ 3219#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074 3220/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 3221 * 1 to a bit in this register in order to clear the corresponding bit in 3222 * was_error_vf_95_64 register. */ 3223#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480 3224/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1 3225 * - enable. */ 3226#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188 3227/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */ 3228#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec 3229/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */ 3230#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4 3231/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */ 3232#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc 3233/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */ 3234#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8 3235#define PRS_REG_A_PRSU_20 0x40134 3236/* [R 8] debug only: CFC load request current credit. Transaction based. */ 3237#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 3238/* [R 8] debug only: CFC search request current credit. Transaction based. */ 3239#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 3240/* [RW 6] The initial credit for the search message to the CFC interface. 3241 Credit is transaction based. */ 3242#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 3243/* [RW 24] CID for port 0 if no match */ 3244#define PRS_REG_CID_PORT_0 0x400fc 3245/* [RW 32] The CM header for flush message where 'load existed' bit in CFC 3246 load response is reset and packet type is 0. Used in packet start message 3247 to TCM. */ 3248#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc 3249#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0 3250#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4 3251#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8 3252#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec 3253#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0 3254/* [RW 32] The CM header for flush message where 'load existed' bit in CFC 3255 load response is set and packet type is 0. Used in packet start message 3256 to TCM. */ 3257#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc 3258#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0 3259#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4 3260#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8 3261#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc 3262#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0 3263/* [RW 32] The CM header for a match and packet type 1 for loopback port. 3264 Used in packet start message to TCM. */ 3265#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c 3266#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0 3267#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4 3268#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8 3269/* [RW 32] The CM header for a match and packet type 0. Used in packet start 3270 message to TCM. */ 3271#define PRS_REG_CM_HDR_TYPE_0 0x40078 3272#define PRS_REG_CM_HDR_TYPE_1 0x4007c 3273#define PRS_REG_CM_HDR_TYPE_2 0x40080 3274#define PRS_REG_CM_HDR_TYPE_3 0x40084 3275#define PRS_REG_CM_HDR_TYPE_4 0x40088 3276/* [RW 32] The CM header in case there was not a match on the connection */ 3277#define PRS_REG_CM_NO_MATCH_HDR 0x400b8 3278/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */ 3279#define PRS_REG_E1HOV_MODE 0x401c8 3280/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet 3281 start message to TCM. */ 3282#define PRS_REG_EVENT_ID_1 0x40054 3283#define PRS_REG_EVENT_ID_2 0x40058 3284#define PRS_REG_EVENT_ID_3 0x4005c 3285/* [RW 16] The Ethernet type value for FCoE */ 3286#define PRS_REG_FCOE_TYPE 0x401d0 3287/* [RW 8] Context region for flush packet with packet type 0. Used in CFC 3288 load request message. */ 3289#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004 3290#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008 3291#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c 3292#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010 3293#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014 3294#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018 3295#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c 3296#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020 3297/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 3298 * Ethernet header. */ 3299#define PRS_REG_HDRS_AFTER_BASIC 0x40238 3300/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 3301 * Ethernet header for port 0 packets. */ 3302#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270 3303#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290 3304/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 3305#define PRS_REG_HDRS_AFTER_TAG_0 0x40248 3306/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for 3307 * port 0 packets */ 3308#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280 3309#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0 3310/* [RW 4] The increment value to send in the CFC load request message */ 3311#define PRS_REG_INC_VALUE 0x40048 3312/* [RW 6] Bit-map indicating which headers must appear in the packet */ 3313#define PRS_REG_MUST_HAVE_HDRS 0x40254 3314/* [RW 6] Bit-map indicating which headers must appear in the packet for 3315 * port 0 packets */ 3316#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c 3317#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac 3318#define PRS_REG_NIC_MODE 0x40138 3319/* [RW 8] The 8-bit event ID for cases where there is no match on the 3320 connection. Used in packet start message to TCM. */ 3321#define PRS_REG_NO_MATCH_EVENT_ID 0x40070 3322/* [ST 24] The number of input CFC flush packets */ 3323#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128 3324/* [ST 32] The number of cycles the Parser halted its operation since it 3325 could not allocate the next serial number */ 3326#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130 3327/* [ST 24] The number of input packets */ 3328#define PRS_REG_NUM_OF_PACKETS 0x40124 3329/* [ST 24] The number of input transparent flush packets */ 3330#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c 3331/* [RW 8] Context region for received Ethernet packet with a match and 3332 packet type 0. Used in CFC load request message */ 3333#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028 3334#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c 3335#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030 3336#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034 3337#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038 3338#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c 3339#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040 3340#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044 3341/* [R 2] debug only: Number of pending requests for CAC on port 0. */ 3342#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 3343/* [R 2] debug only: Number of pending requests for header parsing. */ 3344#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 3345/* [R 1] Interrupt register #0 read */ 3346#define PRS_REG_PRS_INT_STS 0x40188 3347/* [RW 8] Parity mask register #0 read/write */ 3348#define PRS_REG_PRS_PRTY_MASK 0x401a4 3349/* [R 8] Parity register #0 read */ 3350#define PRS_REG_PRS_PRTY_STS 0x40198 3351/* [RC 8] Parity register #0 read clear */ 3352#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c 3353/* [RW 8] Context region for pure acknowledge packets. Used in CFC load 3354 request message */ 3355#define PRS_REG_PURE_REGIONS 0x40024 3356/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this 3357 serail number was released by SDM but cannot be used because a previous 3358 serial number was not released. */ 3359#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 3360/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this 3361 serail number was released by SDM but cannot be used because a previous 3362 serial number was not released. */ 3363#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 3364/* [R 4] debug only: SRC current credit. Transaction based. */ 3365#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 3366/* [RW 16] The Ethernet type value for L2 tag 0 */ 3367#define PRS_REG_TAG_ETHERTYPE_0 0x401d4 3368/* [RW 4] The length of the info field for L2 tag 0. The length is between 3369 * 2B and 14B; in 2B granularity */ 3370#define PRS_REG_TAG_LEN_0 0x4022c 3371/* [R 8] debug only: TCM current credit. Cycle based. */ 3372#define PRS_REG_TCM_CURRENT_CREDIT 0x40160 3373/* [R 8] debug only: TSDM current credit. Transaction based. */ 3374#define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c 3375#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19) 3376#define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20) 3377#define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22) 3378#define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23) 3379#define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24) 3380#define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3381#define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7) 3382/* [R 6] Debug only: Number of used entries in the data FIFO */ 3383#define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 3384/* [R 7] Debug only: Number of used entries in the header FIFO */ 3385#define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 3386#define PXP2_REG_PGL_ADDR_88_F0 0x120534 3387/* [R 32] GRC address for configuration access to PCIE config address 0x88. 3388 * any write to this PCIE address will cause a GRC write access to the 3389 * address that's in t this register */ 3390#define PXP2_REG_PGL_ADDR_88_F1 0x120544 3391#define PXP2_REG_PGL_ADDR_8C_F0 0x120538 3392/* [R 32] GRC address for configuration access to PCIE config address 0x8c. 3393 * any write to this PCIE address will cause a GRC write access to the 3394 * address that's in t this register */ 3395#define PXP2_REG_PGL_ADDR_8C_F1 0x120548 3396#define PXP2_REG_PGL_ADDR_90_F0 0x12053c 3397/* [R 32] GRC address for configuration access to PCIE config address 0x90. 3398 * any write to this PCIE address will cause a GRC write access to the 3399 * address that's in t this register */ 3400#define PXP2_REG_PGL_ADDR_90_F1 0x12054c 3401#define PXP2_REG_PGL_ADDR_94_F0 0x120540 3402/* [R 32] GRC address for configuration access to PCIE config address 0x94. 3403 * any write to this PCIE address will cause a GRC write access to the 3404 * address that's in t this register */ 3405#define PXP2_REG_PGL_ADDR_94_F1 0x120550 3406#define PXP2_REG_PGL_CONTROL0 0x120490 3407#define PXP2_REG_PGL_CONTROL1 0x120514 3408#define PXP2_REG_PGL_DEBUG 0x120520 3409/* [RW 32] third dword data of expansion rom request. this register is 3410 special. reading from it provides a vector outstanding read requests. if 3411 a bit is zero it means that a read request on the corresponding tag did 3412 not finish yet (not all completions have arrived for it) */ 3413#define PXP2_REG_PGL_EXP_ROM2 0x120808 3414/* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask; 3415 its[15:0]-address */ 3416#define PXP2_REG_PGL_INT_CSDM_0 0x1204f4 3417#define PXP2_REG_PGL_INT_CSDM_1 0x1204f8 3418#define PXP2_REG_PGL_INT_CSDM_2 0x1204fc 3419#define PXP2_REG_PGL_INT_CSDM_3 0x120500 3420#define PXP2_REG_PGL_INT_CSDM_4 0x120504 3421#define PXP2_REG_PGL_INT_CSDM_5 0x120508 3422#define PXP2_REG_PGL_INT_CSDM_6 0x12050c 3423#define PXP2_REG_PGL_INT_CSDM_7 0x120510 3424/* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask; 3425 its[15:0]-address */ 3426#define PXP2_REG_PGL_INT_TSDM_0 0x120494 3427#define PXP2_REG_PGL_INT_TSDM_1 0x120498 3428#define PXP2_REG_PGL_INT_TSDM_2 0x12049c 3429#define PXP2_REG_PGL_INT_TSDM_3 0x1204a0 3430#define PXP2_REG_PGL_INT_TSDM_4 0x1204a4 3431#define PXP2_REG_PGL_INT_TSDM_5 0x1204a8 3432#define PXP2_REG_PGL_INT_TSDM_6 0x1204ac 3433#define PXP2_REG_PGL_INT_TSDM_7 0x1204b0 3434/* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask; 3435 its[15:0]-address */ 3436#define PXP2_REG_PGL_INT_USDM_0 0x1204b4 3437#define PXP2_REG_PGL_INT_USDM_1 0x1204b8 3438#define PXP2_REG_PGL_INT_USDM_2 0x1204bc 3439#define PXP2_REG_PGL_INT_USDM_3 0x1204c0 3440#define PXP2_REG_PGL_INT_USDM_4 0x1204c4 3441#define PXP2_REG_PGL_INT_USDM_5 0x1204c8 3442#define PXP2_REG_PGL_INT_USDM_6 0x1204cc 3443#define PXP2_REG_PGL_INT_USDM_7 0x1204d0 3444/* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask; 3445 its[15:0]-address */ 3446#define PXP2_REG_PGL_INT_XSDM_0 0x1204d4 3447#define PXP2_REG_PGL_INT_XSDM_1 0x1204d8 3448#define PXP2_REG_PGL_INT_XSDM_2 0x1204dc 3449#define PXP2_REG_PGL_INT_XSDM_3 0x1204e0 3450#define PXP2_REG_PGL_INT_XSDM_4 0x1204e4 3451#define PXP2_REG_PGL_INT_XSDM_5 0x1204e8 3452#define PXP2_REG_PGL_INT_XSDM_6 0x1204ec 3453#define PXP2_REG_PGL_INT_XSDM_7 0x1204f0 3454/* [RW 3] this field allows one function to pretend being another function 3455 when accessing any BAR mapped resource within the device. the value of 3456 the field is the number of the function that will be accessed 3457 effectively. after software write to this bit it must read it in order to 3458 know that the new value is updated */ 3459#define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 3460#define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 3461#define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c 3462#define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680 3463#define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684 3464#define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688 3465#define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c 3466#define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690 3467/* [R 1] this bit indicates that a read request was blocked because of 3468 bus_master_en was deasserted */ 3469#define PXP2_REG_PGL_READ_BLOCKED 0x120568 3470#define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 3471/* [R 18] debug only */ 3472#define PXP2_REG_PGL_TXW_CDTS 0x12052c 3473/* [R 1] this bit indicates that a write request was blocked because of 3474 bus_master_en was deasserted */ 3475#define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 3476#define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 3477#define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 3478#define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 3479#define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 3480#define PXP2_REG_PSWRQ_BW_ADD28 0x120228 3481#define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 3482#define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 3483#define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 3484#define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc 3485#define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 3486#define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c 3487#define PXP2_REG_PSWRQ_BW_L1 0x1202b0 3488#define PXP2_REG_PSWRQ_BW_L10 0x1202d4 3489#define PXP2_REG_PSWRQ_BW_L11 0x1202d8 3490#define PXP2_REG_PSWRQ_BW_L2 0x1202b4 3491#define PXP2_REG_PSWRQ_BW_L28 0x120318 3492#define PXP2_REG_PSWRQ_BW_L3 0x1202b8 3493#define PXP2_REG_PSWRQ_BW_L6 0x1202c4 3494#define PXP2_REG_PSWRQ_BW_L7 0x1202c8 3495#define PXP2_REG_PSWRQ_BW_L8 0x1202cc 3496#define PXP2_REG_PSWRQ_BW_L9 0x1202d0 3497#define PXP2_REG_PSWRQ_BW_RD 0x120324 3498#define PXP2_REG_PSWRQ_BW_UB1 0x120238 3499#define PXP2_REG_PSWRQ_BW_UB10 0x12025c 3500#define PXP2_REG_PSWRQ_BW_UB11 0x120260 3501#define PXP2_REG_PSWRQ_BW_UB2 0x12023c 3502#define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 3503#define PXP2_REG_PSWRQ_BW_UB3 0x120240 3504#define PXP2_REG_PSWRQ_BW_UB6 0x12024c 3505#define PXP2_REG_PSWRQ_BW_UB7 0x120250 3506#define PXP2_REG_PSWRQ_BW_UB8 0x120254 3507#define PXP2_REG_PSWRQ_BW_UB9 0x120258 3508#define PXP2_REG_PSWRQ_BW_WR 0x120328 3509#define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 3510#define PXP2_REG_PSWRQ_QM0_L2P 0x120038 3511#define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 3512#define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 3513#define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 3514/* [RW 32] Interrupt mask register #0 read/write */ 3515#define PXP2_REG_PXP2_INT_MASK_0 0x120578 3516/* [R 32] Interrupt register #0 read */ 3517#define PXP2_REG_PXP2_INT_STS_0 0x12056c 3518#define PXP2_REG_PXP2_INT_STS_1 0x120608 3519/* [RC 32] Interrupt register #0 read clear */ 3520#define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 3521/* [RW 32] Parity mask register #0 read/write */ 3522#define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 3523#define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 3524/* [R 32] Parity register #0 read */ 3525#define PXP2_REG_PXP2_PRTY_STS_0 0x12057c 3526#define PXP2_REG_PXP2_PRTY_STS_1 0x12058c 3527/* [RC 32] Parity register #0 read clear */ 3528#define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580 3529#define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590 3530/* [R 1] Debug only: The 'almost full' indication from each fifo (gives 3531 indication about backpressure) */ 3532#define PXP2_REG_RD_ALMOST_FULL_0 0x120424 3533/* [R 8] Debug only: The blocks counter - number of unused block ids */ 3534#define PXP2_REG_RD_BLK_CNT 0x120418 3535/* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. 3536 Must be bigger than 6. Normally should not be changed. */ 3537#define PXP2_REG_RD_BLK_NUM_CFG 0x12040c 3538/* [RW 2] CDU byte swapping mode configuration for master read requests */ 3539#define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 3540/* [RW 1] When '1'; inputs to the PSWRD block are ignored */ 3541#define PXP2_REG_RD_DISABLE_INPUTS 0x120374 3542/* [R 1] PSWRD internal memories initialization is done */ 3543#define PXP2_REG_RD_INIT_DONE 0x120370 3544/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3545 allocated for vq10 */ 3546#define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0 3547/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3548 allocated for vq11 */ 3549#define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4 3550/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3551 allocated for vq17 */ 3552#define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc 3553/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3554 allocated for vq18 */ 3555#define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0 3556/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3557 allocated for vq19 */ 3558#define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4 3559/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3560 allocated for vq22 */ 3561#define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0 3562/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3563 allocated for vq25 */ 3564#define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc 3565/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3566 allocated for vq6 */ 3567#define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390 3568/* [RW 8] The maximum number of blocks in Tetris Buffer that can be 3569 allocated for vq9 */ 3570#define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c 3571/* [RW 2] PBF byte swapping mode configuration for master read requests */ 3572#define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4 3573/* [R 1] Debug only: Indication if delivery ports are idle */ 3574#define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c 3575#define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 3576/* [RW 2] QM byte swapping mode configuration for master read requests */ 3577#define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 3578/* [R 7] Debug only: The SR counter - number of unused sub request ids */ 3579#define PXP2_REG_RD_SR_CNT 0x120414 3580/* [RW 2] SRC byte swapping mode configuration for master read requests */ 3581#define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 3582/* [RW 7] Debug only: Total number of available PCI read sub-requests. Must 3583 be bigger than 1. Normally should not be changed. */ 3584#define PXP2_REG_RD_SR_NUM_CFG 0x120408 3585/* [RW 1] Signals the PSWRD block to start initializing internal memories */ 3586#define PXP2_REG_RD_START_INIT 0x12036c 3587/* [RW 2] TM byte swapping mode configuration for master read requests */ 3588#define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc 3589/* [RW 10] Bandwidth addition to VQ0 write requests */ 3590#define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc 3591/* [RW 10] Bandwidth addition to VQ12 read requests */ 3592#define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec 3593/* [RW 10] Bandwidth addition to VQ13 read requests */ 3594#define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 3595/* [RW 10] Bandwidth addition to VQ14 read requests */ 3596#define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 3597/* [RW 10] Bandwidth addition to VQ15 read requests */ 3598#define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 3599/* [RW 10] Bandwidth addition to VQ16 read requests */ 3600#define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc 3601/* [RW 10] Bandwidth addition to VQ17 read requests */ 3602#define PXP2_REG_RQ_BW_RD_ADD17 0x120200 3603/* [RW 10] Bandwidth addition to VQ18 read requests */ 3604#define PXP2_REG_RQ_BW_RD_ADD18 0x120204 3605/* [RW 10] Bandwidth addition to VQ19 read requests */ 3606#define PXP2_REG_RQ_BW_RD_ADD19 0x120208 3607/* [RW 10] Bandwidth addition to VQ20 read requests */ 3608#define PXP2_REG_RQ_BW_RD_ADD20 0x12020c 3609/* [RW 10] Bandwidth addition to VQ22 read requests */ 3610#define PXP2_REG_RQ_BW_RD_ADD22 0x120210 3611/* [RW 10] Bandwidth addition to VQ23 read requests */ 3612#define PXP2_REG_RQ_BW_RD_ADD23 0x120214 3613/* [RW 10] Bandwidth addition to VQ24 read requests */ 3614#define PXP2_REG_RQ_BW_RD_ADD24 0x120218 3615/* [RW 10] Bandwidth addition to VQ25 read requests */ 3616#define PXP2_REG_RQ_BW_RD_ADD25 0x12021c 3617/* [RW 10] Bandwidth addition to VQ26 read requests */ 3618#define PXP2_REG_RQ_BW_RD_ADD26 0x120220 3619/* [RW 10] Bandwidth addition to VQ27 read requests */ 3620#define PXP2_REG_RQ_BW_RD_ADD27 0x120224 3621/* [RW 10] Bandwidth addition to VQ4 read requests */ 3622#define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc 3623/* [RW 10] Bandwidth addition to VQ5 read requests */ 3624#define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 3625/* [RW 10] Bandwidth Typical L for VQ0 Read requests */ 3626#define PXP2_REG_RQ_BW_RD_L0 0x1202ac 3627/* [RW 10] Bandwidth Typical L for VQ12 Read requests */ 3628#define PXP2_REG_RQ_BW_RD_L12 0x1202dc 3629/* [RW 10] Bandwidth Typical L for VQ13 Read requests */ 3630#define PXP2_REG_RQ_BW_RD_L13 0x1202e0 3631/* [RW 10] Bandwidth Typical L for VQ14 Read requests */ 3632#define PXP2_REG_RQ_BW_RD_L14 0x1202e4 3633/* [RW 10] Bandwidth Typical L for VQ15 Read requests */ 3634#define PXP2_REG_RQ_BW_RD_L15 0x1202e8 3635/* [RW 10] Bandwidth Typical L for VQ16 Read requests */ 3636#define PXP2_REG_RQ_BW_RD_L16 0x1202ec 3637/* [RW 10] Bandwidth Typical L for VQ17 Read requests */ 3638#define PXP2_REG_RQ_BW_RD_L17 0x1202f0 3639/* [RW 10] Bandwidth Typical L for VQ18 Read requests */ 3640#define PXP2_REG_RQ_BW_RD_L18 0x1202f4 3641/* [RW 10] Bandwidth Typical L for VQ19 Read requests */ 3642#define PXP2_REG_RQ_BW_RD_L19 0x1202f8 3643/* [RW 10] Bandwidth Typical L for VQ20 Read requests */ 3644#define PXP2_REG_RQ_BW_RD_L20 0x1202fc 3645/* [RW 10] Bandwidth Typical L for VQ22 Read requests */ 3646#define PXP2_REG_RQ_BW_RD_L22 0x120300 3647/* [RW 10] Bandwidth Typical L for VQ23 Read requests */ 3648#define PXP2_REG_RQ_BW_RD_L23 0x120304 3649/* [RW 10] Bandwidth Typical L for VQ24 Read requests */ 3650#define PXP2_REG_RQ_BW_RD_L24 0x120308 3651/* [RW 10] Bandwidth Typical L for VQ25 Read requests */ 3652#define PXP2_REG_RQ_BW_RD_L25 0x12030c 3653/* [RW 10] Bandwidth Typical L for VQ26 Read requests */ 3654#define PXP2_REG_RQ_BW_RD_L26 0x120310 3655/* [RW 10] Bandwidth Typical L for VQ27 Read requests */ 3656#define PXP2_REG_RQ_BW_RD_L27 0x120314 3657/* [RW 10] Bandwidth Typical L for VQ4 Read requests */ 3658#define PXP2_REG_RQ_BW_RD_L4 0x1202bc 3659/* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ 3660#define PXP2_REG_RQ_BW_RD_L5 0x1202c0 3661/* [RW 7] Bandwidth upper bound for VQ0 read requests */ 3662#define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 3663/* [RW 7] Bandwidth upper bound for VQ12 read requests */ 3664#define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 3665/* [RW 7] Bandwidth upper bound for VQ13 read requests */ 3666#define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 3667/* [RW 7] Bandwidth upper bound for VQ14 read requests */ 3668#define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c 3669/* [RW 7] Bandwidth upper bound for VQ15 read requests */ 3670#define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 3671/* [RW 7] Bandwidth upper bound for VQ16 read requests */ 3672#define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 3673/* [RW 7] Bandwidth upper bound for VQ17 read requests */ 3674#define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 3675/* [RW 7] Bandwidth upper bound for VQ18 read requests */ 3676#define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c 3677/* [RW 7] Bandwidth upper bound for VQ19 read requests */ 3678#define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 3679/* [RW 7] Bandwidth upper bound for VQ20 read requests */ 3680#define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 3681/* [RW 7] Bandwidth upper bound for VQ22 read requests */ 3682#define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 3683/* [RW 7] Bandwidth upper bound for VQ23 read requests */ 3684#define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c 3685/* [RW 7] Bandwidth upper bound for VQ24 read requests */ 3686#define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 3687/* [RW 7] Bandwidth upper bound for VQ25 read requests */ 3688#define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 3689/* [RW 7] Bandwidth upper bound for VQ26 read requests */ 3690#define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 3691/* [RW 7] Bandwidth upper bound for VQ27 read requests */ 3692#define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c 3693/* [RW 7] Bandwidth upper bound for VQ4 read requests */ 3694#define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 3695/* [RW 7] Bandwidth upper bound for VQ5 read requests */ 3696#define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 3697/* [RW 10] Bandwidth addition to VQ29 write requests */ 3698#define PXP2_REG_RQ_BW_WR_ADD29 0x12022c 3699/* [RW 10] Bandwidth addition to VQ30 write requests */ 3700#define PXP2_REG_RQ_BW_WR_ADD30 0x120230 3701/* [RW 10] Bandwidth Typical L for VQ29 Write requests */ 3702#define PXP2_REG_RQ_BW_WR_L29 0x12031c 3703/* [RW 10] Bandwidth Typical L for VQ30 Write requests */ 3704#define PXP2_REG_RQ_BW_WR_L30 0x120320 3705/* [RW 7] Bandwidth upper bound for VQ29 */ 3706#define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 3707/* [RW 7] Bandwidth upper bound for VQ30 */ 3708#define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 3709/* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ 3710#define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 3711/* [RW 2] Endian mode for cdu */ 3712#define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 3713#define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c 3714#define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 3715/* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 3716 -128k */ 3717#define PXP2_REG_RQ_CDU_P_SIZE 0x120018 3718/* [R 1] 1' indicates that the requester has finished its internal 3719 configuration */ 3720#define PXP2_REG_RQ_CFG_DONE 0x1201b4 3721/* [RW 2] Endian mode for debug */ 3722#define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 3723/* [RW 1] When '1'; requests will enter input buffers but wont get out 3724 towards the glue */ 3725#define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 3726/* [RW 4] Determines alignment of write SRs when a request is split into 3727 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3728 * aligned. 4 - 512B aligned. */ 3729#define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 3730/* [RW 4] Determines alignment of read SRs when a request is split into 3731 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3732 * aligned. 4 - 512B aligned. */ 3733#define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c 3734/* [RW 1] when set the new alignment method (E2) will be applied; when reset 3735 * the original alignment method (E1 E1H) will be applied */ 3736#define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930 3737/* [RW 1] If 1 ILT failiue will not result in ELT access; An interrupt will 3738 be asserted */ 3739#define PXP2_REG_RQ_ELT_DISABLE 0x12066c 3740/* [RW 2] Endian mode for hc */ 3741#define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 3742/* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back 3743 compatibility needs; Note that different registers are used per mode */ 3744#define PXP2_REG_RQ_ILT_MODE 0x1205b4 3745/* [WB 53] Onchip address table */ 3746#define PXP2_REG_RQ_ONCHIP_AT 0x122000 3747/* [WB 53] Onchip address table - B0 */ 3748#define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 3749/* [RW 13] Pending read limiter threshold; in Dwords */ 3750#define PXP2_REG_RQ_PDR_LIMIT 0x12033c 3751/* [RW 2] Endian mode for qm */ 3752#define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 3753#define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 3754#define PXP2_REG_RQ_QM_LAST_ILT 0x120638 3755/* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 3756 -128k */ 3757#define PXP2_REG_RQ_QM_P_SIZE 0x120050 3758/* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ 3759#define PXP2_REG_RQ_RBC_DONE 0x1201b0 3760/* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 3761 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3762#define PXP2_REG_RQ_RD_MBS0 0x120160 3763/* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 3764 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */ 3765#define PXP2_REG_RQ_RD_MBS1 0x120168 3766/* [RW 2] Endian mode for src */ 3767#define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 3768#define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c 3769#define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 3770/* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 3771 -128k */ 3772#define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 3773/* [RW 2] Endian mode for tm */ 3774#define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 3775#define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 3776#define PXP2_REG_RQ_TM_LAST_ILT 0x120648 3777/* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 3778 -128k */ 3779#define PXP2_REG_RQ_TM_P_SIZE 0x120034 3780/* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 3781#define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 3782/* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ 3783#define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 3784/* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 3785#define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 3786/* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 3787#define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 3788/* [R 8] Number of entries occupied by vq 11 in pswrq memory */ 3789#define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 3790/* [R 8] Number of entries occupied by vq 12 in pswrq memory */ 3791#define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 3792/* [R 8] Number of entries occupied by vq 13 in pswrq memory */ 3793#define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 3794/* [R 8] Number of entries occupied by vq 14 in pswrq memory */ 3795#define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 3796/* [R 8] Number of entries occupied by vq 15 in pswrq memory */ 3797#define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 3798/* [R 8] Number of entries occupied by vq 16 in pswrq memory */ 3799#define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 3800/* [R 8] Number of entries occupied by vq 17 in pswrq memory */ 3801#define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 3802/* [R 8] Number of entries occupied by vq 18 in pswrq memory */ 3803#define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 3804/* [R 8] Number of entries occupied by vq 19 in pswrq memory */ 3805#define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 3806/* [R 8] Number of entries occupied by vq 1 in pswrq memory */ 3807#define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 3808/* [R 8] Number of entries occupied by vq 20 in pswrq memory */ 3809#define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 3810/* [R 8] Number of entries occupied by vq 21 in pswrq memory */ 3811#define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 3812/* [R 8] Number of entries occupied by vq 22 in pswrq memory */ 3813#define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 3814/* [R 8] Number of entries occupied by vq 23 in pswrq memory */ 3815#define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 3816/* [R 8] Number of entries occupied by vq 24 in pswrq memory */ 3817#define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 3818/* [R 8] Number of entries occupied by vq 25 in pswrq memory */ 3819#define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 3820/* [R 8] Number of entries occupied by vq 26 in pswrq memory */ 3821#define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 3822/* [R 8] Number of entries occupied by vq 27 in pswrq memory */ 3823#define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 3824/* [R 8] Number of entries occupied by vq 28 in pswrq memory */ 3825#define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 3826/* [R 8] Number of entries occupied by vq 29 in pswrq memory */ 3827#define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 3828/* [R 8] Number of entries occupied by vq 2 in pswrq memory */ 3829#define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 3830/* [R 8] Number of entries occupied by vq 30 in pswrq memory */ 3831#define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 3832/* [R 8] Number of entries occupied by vq 31 in pswrq memory */ 3833#define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 3834/* [R 8] Number of entries occupied by vq 3 in pswrq memory */ 3835#define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 3836/* [R 8] Number of entries occupied by vq 4 in pswrq memory */ 3837#define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 3838/* [R 8] Number of entries occupied by vq 5 in pswrq memory */ 3839#define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 3840/* [R 8] Number of entries occupied by vq 6 in pswrq memory */ 3841#define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 3842/* [R 8] Number of entries occupied by vq 7 in pswrq memory */ 3843#define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 3844/* [R 8] Number of entries occupied by vq 8 in pswrq memory */ 3845#define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 3846/* [R 8] Number of entries occupied by vq 9 in pswrq memory */ 3847#define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 3848/* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 3849 001:256B; 010: 512B; */ 3850#define PXP2_REG_RQ_WR_MBS0 0x12015c 3851/* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 3852 001:256B; 010: 512B; */ 3853#define PXP2_REG_RQ_WR_MBS1 0x120164 3854/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3855 buffer reaches this number has_payload will be asserted */ 3856#define PXP2_REG_WR_CDU_MPS 0x1205f0 3857/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3858 buffer reaches this number has_payload will be asserted */ 3859#define PXP2_REG_WR_CSDM_MPS 0x1205d0 3860/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3861 buffer reaches this number has_payload will be asserted */ 3862#define PXP2_REG_WR_DBG_MPS 0x1205e8 3863/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3864 buffer reaches this number has_payload will be asserted */ 3865#define PXP2_REG_WR_DMAE_MPS 0x1205ec 3866/* [RW 10] if Number of entries in dmae fifo will be higher than this 3867 threshold then has_payload indication will be asserted; the default value 3868 should be equal to > write MBS size! */ 3869#define PXP2_REG_WR_DMAE_TH 0x120368 3870/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3871 buffer reaches this number has_payload will be asserted */ 3872#define PXP2_REG_WR_HC_MPS 0x1205c8 3873/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3874 buffer reaches this number has_payload will be asserted */ 3875#define PXP2_REG_WR_QM_MPS 0x1205dc 3876/* [RW 1] 0 - working in A0 mode; - working in B0 mode */ 3877#define PXP2_REG_WR_REV_MODE 0x120670 3878/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3879 buffer reaches this number has_payload will be asserted */ 3880#define PXP2_REG_WR_SRC_MPS 0x1205e4 3881/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3882 buffer reaches this number has_payload will be asserted */ 3883#define PXP2_REG_WR_TM_MPS 0x1205e0 3884/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3885 buffer reaches this number has_payload will be asserted */ 3886#define PXP2_REG_WR_TSDM_MPS 0x1205d4 3887/* [RW 10] if Number of entries in usdmdp fifo will be higher than this 3888 threshold then has_payload indication will be asserted; the default value 3889 should be equal to > write MBS size! */ 3890#define PXP2_REG_WR_USDMDP_TH 0x120348 3891/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3892 buffer reaches this number has_payload will be asserted */ 3893#define PXP2_REG_WR_USDM_MPS 0x1205cc 3894/* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3895 buffer reaches this number has_payload will be asserted */ 3896#define PXP2_REG_WR_XSDM_MPS 0x1205d8 3897/* [R 1] debug only: Indication if PSWHST arbiter is idle */ 3898#define PXP_REG_HST_ARB_IS_IDLE 0x103004 3899/* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 3900 this client is waiting for the arbiter. */ 3901#define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 3902/* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue 3903 block. Should be used for close the gates. */ 3904#define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4 3905/* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit 3906 should update according to 'hst_discard_doorbells' register when the state 3907 machine is idle */ 3908#define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 3909/* [RW 1] When 1; new internal writes arriving to the block are discarded. 3910 Should be used for close the gates. */ 3911#define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8 3912/* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' 3913 means this PSWHST is discarding inputs from this client. Each bit should 3914 update according to 'hst_discard_internal_writes' register when the state 3915 machine is idle. */ 3916#define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c 3917/* [WB 160] Used for initialization of the inbound interrupts memory */ 3918#define PXP_REG_HST_INBOUND_INT 0x103800 3919/* [RW 7] Indirect access to the permission table. The fields are : {Valid; 3920 * VFID[5:0]} 3921 */ 3922#define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400 3923/* [RW 32] Interrupt mask register #0 read/write */ 3924#define PXP_REG_PXP_INT_MASK_0 0x103074 3925#define PXP_REG_PXP_INT_MASK_1 0x103084 3926/* [R 32] Interrupt register #0 read */ 3927#define PXP_REG_PXP_INT_STS_0 0x103068 3928#define PXP_REG_PXP_INT_STS_1 0x103078 3929/* [RC 32] Interrupt register #0 read clear */ 3930#define PXP_REG_PXP_INT_STS_CLR_0 0x10306c 3931#define PXP_REG_PXP_INT_STS_CLR_1 0x10307c 3932/* [RW 27] Parity mask register #0 read/write */ 3933#define PXP_REG_PXP_PRTY_MASK 0x103094 3934/* [R 26] Parity register #0 read */ 3935#define PXP_REG_PXP_PRTY_STS 0x103088 3936/* [RC 27] Parity register #0 read clear */ 3937#define PXP_REG_PXP_PRTY_STS_CLR 0x10308c 3938/* [RW 4] The activity counter initial increment value sent in the load 3939 request */ 3940#define QM_REG_ACTCTRINITVAL_0 0x168040 3941#define QM_REG_ACTCTRINITVAL_1 0x168044 3942#define QM_REG_ACTCTRINITVAL_2 0x168048 3943#define QM_REG_ACTCTRINITVAL_3 0x16804c 3944/* [RW 32] The base logical address (in bytes) of each physical queue. The 3945 index I represents the physical queue number. The 12 lsbs are ignore and 3946 considered zero so practically there are only 20 bits in this register; 3947 queues 63-0 */ 3948#define QM_REG_BASEADDR 0x168900 3949/* [RW 32] The base logical address (in bytes) of each physical queue. The 3950 index I represents the physical queue number. The 12 lsbs are ignore and 3951 considered zero so practically there are only 20 bits in this register; 3952 queues 127-64 */ 3953#define QM_REG_BASEADDR_EXT_A 0x16e100 3954/* [RW 16] The byte credit cost for each task. This value is for both ports */ 3955#define QM_REG_BYTECRDCOST 0x168234 3956/* [RW 16] The initial byte credit value for both ports. */ 3957#define QM_REG_BYTECRDINITVAL 0x168238 3958/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3959 queue uses port 0 else it uses port 1; queues 31-0 */ 3960#define QM_REG_BYTECRDPORT_LSB 0x168228 3961/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3962 queue uses port 0 else it uses port 1; queues 95-64 */ 3963#define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520 3964/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3965 queue uses port 0 else it uses port 1; queues 63-32 */ 3966#define QM_REG_BYTECRDPORT_MSB 0x168224 3967/* [RW 32] A bit per physical queue. If the bit is cleared then the physical 3968 queue uses port 0 else it uses port 1; queues 127-96 */ 3969#define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c 3970/* [RW 16] The byte credit value that if above the QM is considered almost 3971 full */ 3972#define QM_REG_BYTECREDITAFULLTHR 0x168094 3973/* [RW 4] The initial credit for interface */ 3974#define QM_REG_CMINITCRD_0 0x1680cc 3975#define QM_REG_BYTECRDCMDQ_0 0x16e6e8 3976#define QM_REG_CMINITCRD_1 0x1680d0 3977#define QM_REG_CMINITCRD_2 0x1680d4 3978#define QM_REG_CMINITCRD_3 0x1680d8 3979#define QM_REG_CMINITCRD_4 0x1680dc 3980#define QM_REG_CMINITCRD_5 0x1680e0 3981#define QM_REG_CMINITCRD_6 0x1680e4 3982#define QM_REG_CMINITCRD_7 0x1680e8 3983/* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface 3984 is masked */ 3985#define QM_REG_CMINTEN 0x1680ec 3986/* [RW 12] A bit vector which indicates which one of the queues are tied to 3987 interface 0 */ 3988#define QM_REG_CMINTVOQMASK_0 0x1681f4 3989#define QM_REG_CMINTVOQMASK_1 0x1681f8 3990#define QM_REG_CMINTVOQMASK_2 0x1681fc 3991#define QM_REG_CMINTVOQMASK_3 0x168200 3992#define QM_REG_CMINTVOQMASK_4 0x168204 3993#define QM_REG_CMINTVOQMASK_5 0x168208 3994#define QM_REG_CMINTVOQMASK_6 0x16820c 3995#define QM_REG_CMINTVOQMASK_7 0x168210 3996/* [RW 20] The number of connections divided by 16 which dictates the size 3997 of each queue which belongs to even function number. */ 3998#define QM_REG_CONNNUM_0 0x168020 3999/* [R 6] Keep the fill level of the fifo from write client 4 */ 4000#define QM_REG_CQM_WRC_FIFOLVL 0x168018 4001/* [RW 8] The context regions sent in the CFC load request */ 4002#define QM_REG_CTXREG_0 0x168030 4003#define QM_REG_CTXREG_1 0x168034 4004#define QM_REG_CTXREG_2 0x168038 4005#define QM_REG_CTXREG_3 0x16803c 4006/* [RW 12] The VOQ mask used to select the VOQs which needs to be full for 4007 bypass enable */ 4008#define QM_REG_ENBYPVOQMASK 0x16823c 4009/* [RW 32] A bit mask per each physical queue. If a bit is set then the 4010 physical queue uses the byte credit; queues 31-0 */ 4011#define QM_REG_ENBYTECRD_LSB 0x168220 4012/* [RW 32] A bit mask per each physical queue. If a bit is set then the 4013 physical queue uses the byte credit; queues 95-64 */ 4014#define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518 4015/* [RW 32] A bit mask per each physical queue. If a bit is set then the 4016 physical queue uses the byte credit; queues 63-32 */ 4017#define QM_REG_ENBYTECRD_MSB 0x16821c 4018/* [RW 32] A bit mask per each physical queue. If a bit is set then the 4019 physical queue uses the byte credit; queues 127-96 */ 4020#define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514 4021/* [RW 4] If cleared then the secondary interface will not be served by the 4022 RR arbiter */ 4023#define QM_REG_ENSEC 0x1680f0 4024/* [RW 32] NA */ 4025#define QM_REG_FUNCNUMSEL_LSB 0x168230 4026/* [RW 32] NA */ 4027#define QM_REG_FUNCNUMSEL_MSB 0x16822c 4028/* [RW 32] A mask register to mask the Almost empty signals which will not 4029 be use for the almost empty indication to the HW block; queues 31:0 */ 4030#define QM_REG_HWAEMPTYMASK_LSB 0x168218 4031/* [RW 32] A mask register to mask the Almost empty signals which will not 4032 be use for the almost empty indication to the HW block; queues 95-64 */ 4033#define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510 4034/* [RW 32] A mask register to mask the Almost empty signals which will not 4035 be use for the almost empty indication to the HW block; queues 63:32 */ 4036#define QM_REG_HWAEMPTYMASK_MSB 0x168214 4037/* [RW 32] A mask register to mask the Almost empty signals which will not 4038 be use for the almost empty indication to the HW block; queues 127-96 */ 4039#define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c 4040/* [RW 4] The number of outstanding request to CFC */ 4041#define QM_REG_OUTLDREQ 0x168804 4042/* [RC 1] A flag to indicate that overflow error occurred in one of the 4043 queues. */ 4044#define QM_REG_OVFERROR 0x16805c 4045/* [RC 7] the Q where the overflow occurs */ 4046#define QM_REG_OVFQNUM 0x168058 4047/* [R 16] Pause state for physical queues 15-0 */ 4048#define QM_REG_PAUSESTATE0 0x168410 4049/* [R 16] Pause state for physical queues 31-16 */ 4050#define QM_REG_PAUSESTATE1 0x168414 4051/* [R 16] Pause state for physical queues 47-32 */ 4052#define QM_REG_PAUSESTATE2 0x16e684 4053/* [R 16] Pause state for physical queues 63-48 */ 4054#define QM_REG_PAUSESTATE3 0x16e688 4055/* [R 16] Pause state for physical queues 79-64 */ 4056#define QM_REG_PAUSESTATE4 0x16e68c 4057/* [R 16] Pause state for physical queues 95-80 */ 4058#define QM_REG_PAUSESTATE5 0x16e690 4059/* [R 16] Pause state for physical queues 111-96 */ 4060#define QM_REG_PAUSESTATE6 0x16e694 4061/* [R 16] Pause state for physical queues 127-112 */ 4062#define QM_REG_PAUSESTATE7 0x16e698 4063/* [RW 2] The PCI attributes field used in the PCI request. */ 4064#define QM_REG_PCIREQAT 0x168054 4065#define QM_REG_PF_EN 0x16e70c 4066/* [R 24] The number of tasks stored in the QM for the PF. only even 4067 * functions are valid in E2 (odd I registers will be hard wired to 0) */ 4068#define QM_REG_PF_USG_CNT_0 0x16e040 4069/* [R 16] NOT USED */ 4070#define QM_REG_PORT0BYTECRD 0x168300 4071/* [R 16] The byte credit of port 1 */ 4072#define QM_REG_PORT1BYTECRD 0x168304 4073/* [RW 3] pci function number of queues 15-0 */ 4074#define QM_REG_PQ2PCIFUNC_0 0x16e6bc 4075#define QM_REG_PQ2PCIFUNC_1 0x16e6c0 4076#define QM_REG_PQ2PCIFUNC_2 0x16e6c4 4077#define QM_REG_PQ2PCIFUNC_3 0x16e6c8 4078#define QM_REG_PQ2PCIFUNC_4 0x16e6cc 4079#define QM_REG_PQ2PCIFUNC_5 0x16e6d0 4080#define QM_REG_PQ2PCIFUNC_6 0x16e6d4 4081#define QM_REG_PQ2PCIFUNC_7 0x16e6d8 4082/* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: 4083 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 4084 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 4085#define QM_REG_PTRTBL 0x168a00 4086/* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow: 4087 ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 4088 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */ 4089#define QM_REG_PTRTBL_EXT_A 0x16e200 4090/* [RW 2] Interrupt mask register #0 read/write */ 4091#define QM_REG_QM_INT_MASK 0x168444 4092/* [R 2] Interrupt register #0 read */ 4093#define QM_REG_QM_INT_STS 0x168438 4094/* [RW 12] Parity mask register #0 read/write */ 4095#define QM_REG_QM_PRTY_MASK 0x168454 4096/* [R 12] Parity register #0 read */ 4097#define QM_REG_QM_PRTY_STS 0x168448 4098/* [RC 12] Parity register #0 read clear */ 4099#define QM_REG_QM_PRTY_STS_CLR 0x16844c 4100/* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 4101#define QM_REG_QSTATUS_HIGH 0x16802c 4102/* [R 32] Current queues in pipeline: Queues from 96 to 127 */ 4103#define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 4104/* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 4105#define QM_REG_QSTATUS_LOW 0x168028 4106/* [R 32] Current queues in pipeline: Queues from 64 to 95 */ 4107#define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 4108/* [R 24] The number of tasks queued for each queue; queues 63-0 */ 4109#define QM_REG_QTASKCTR_0 0x168308 4110/* [R 24] The number of tasks queued for each queue; queues 127-64 */ 4111#define QM_REG_QTASKCTR_EXT_A_0 0x16e584 4112/* [RW 4] Queue tied to VOQ */ 4113#define QM_REG_QVOQIDX_0 0x1680f4 4114#define QM_REG_QVOQIDX_10 0x16811c 4115#define QM_REG_QVOQIDX_100 0x16e49c 4116#define QM_REG_QVOQIDX_101 0x16e4a0 4117#define QM_REG_QVOQIDX_102 0x16e4a4 4118#define QM_REG_QVOQIDX_103 0x16e4a8 4119#define QM_REG_QVOQIDX_104 0x16e4ac 4120#define QM_REG_QVOQIDX_105 0x16e4b0 4121#define QM_REG_QVOQIDX_106 0x16e4b4 4122#define QM_REG_QVOQIDX_107 0x16e4b8 4123#define QM_REG_QVOQIDX_108 0x16e4bc 4124#define QM_REG_QVOQIDX_109 0x16e4c0 4125#define QM_REG_QVOQIDX_11 0x168120 4126#define QM_REG_QVOQIDX_110 0x16e4c4 4127#define QM_REG_QVOQIDX_111 0x16e4c8 4128#define QM_REG_QVOQIDX_112 0x16e4cc 4129#define QM_REG_QVOQIDX_113 0x16e4d0 4130#define QM_REG_QVOQIDX_114 0x16e4d4 4131#define QM_REG_QVOQIDX_115 0x16e4d8 4132#define QM_REG_QVOQIDX_116 0x16e4dc 4133#define QM_REG_QVOQIDX_117 0x16e4e0 4134#define QM_REG_QVOQIDX_118 0x16e4e4 4135#define QM_REG_QVOQIDX_119 0x16e4e8 4136#define QM_REG_QVOQIDX_12 0x168124 4137#define QM_REG_QVOQIDX_120 0x16e4ec 4138#define QM_REG_QVOQIDX_121 0x16e4f0 4139#define QM_REG_QVOQIDX_122 0x16e4f4 4140#define QM_REG_QVOQIDX_123 0x16e4f8 4141#define QM_REG_QVOQIDX_124 0x16e4fc 4142#define QM_REG_QVOQIDX_125 0x16e500 4143#define QM_REG_QVOQIDX_126 0x16e504 4144#define QM_REG_QVOQIDX_127 0x16e508 4145#define QM_REG_QVOQIDX_13 0x168128 4146#define QM_REG_QVOQIDX_14 0x16812c 4147#define QM_REG_QVOQIDX_15 0x168130 4148#define QM_REG_QVOQIDX_16 0x168134 4149#define QM_REG_QVOQIDX_17 0x168138 4150#define QM_REG_QVOQIDX_21 0x168148 4151#define QM_REG_QVOQIDX_22 0x16814c 4152#define QM_REG_QVOQIDX_23 0x168150 4153#define QM_REG_QVOQIDX_24 0x168154 4154#define QM_REG_QVOQIDX_25 0x168158 4155#define QM_REG_QVOQIDX_26 0x16815c 4156#define QM_REG_QVOQIDX_27 0x168160 4157#define QM_REG_QVOQIDX_28 0x168164 4158#define QM_REG_QVOQIDX_29 0x168168 4159#define QM_REG_QVOQIDX_30 0x16816c 4160#define QM_REG_QVOQIDX_31 0x168170 4161#define QM_REG_QVOQIDX_32 0x168174 4162#define QM_REG_QVOQIDX_33 0x168178 4163#define QM_REG_QVOQIDX_34 0x16817c 4164#define QM_REG_QVOQIDX_35 0x168180 4165#define QM_REG_QVOQIDX_36 0x168184 4166#define QM_REG_QVOQIDX_37 0x168188 4167#define QM_REG_QVOQIDX_38 0x16818c 4168#define QM_REG_QVOQIDX_39 0x168190 4169#define QM_REG_QVOQIDX_40 0x168194 4170#define QM_REG_QVOQIDX_41 0x168198 4171#define QM_REG_QVOQIDX_42 0x16819c 4172#define QM_REG_QVOQIDX_43 0x1681a0 4173#define QM_REG_QVOQIDX_44 0x1681a4 4174#define QM_REG_QVOQIDX_45 0x1681a8 4175#define QM_REG_QVOQIDX_46 0x1681ac 4176#define QM_REG_QVOQIDX_47 0x1681b0 4177#define QM_REG_QVOQIDX_48 0x1681b4 4178#define QM_REG_QVOQIDX_49 0x1681b8 4179#define QM_REG_QVOQIDX_5 0x168108 4180#define QM_REG_QVOQIDX_50 0x1681bc 4181#define QM_REG_QVOQIDX_51 0x1681c0 4182#define QM_REG_QVOQIDX_52 0x1681c4 4183#define QM_REG_QVOQIDX_53 0x1681c8 4184#define QM_REG_QVOQIDX_54 0x1681cc 4185#define QM_REG_QVOQIDX_55 0x1681d0 4186#define QM_REG_QVOQIDX_56 0x1681d4 4187#define QM_REG_QVOQIDX_57 0x1681d8 4188#define QM_REG_QVOQIDX_58 0x1681dc 4189#define QM_REG_QVOQIDX_59 0x1681e0 4190#define QM_REG_QVOQIDX_6 0x16810c 4191#define QM_REG_QVOQIDX_60 0x1681e4 4192#define QM_REG_QVOQIDX_61 0x1681e8 4193#define QM_REG_QVOQIDX_62 0x1681ec 4194#define QM_REG_QVOQIDX_63 0x1681f0 4195#define QM_REG_QVOQIDX_64 0x16e40c 4196#define QM_REG_QVOQIDX_65 0x16e410 4197#define QM_REG_QVOQIDX_69 0x16e420 4198#define QM_REG_QVOQIDX_7 0x168110 4199#define QM_REG_QVOQIDX_70 0x16e424 4200#define QM_REG_QVOQIDX_71 0x16e428 4201#define QM_REG_QVOQIDX_72 0x16e42c 4202#define QM_REG_QVOQIDX_73 0x16e430 4203#define QM_REG_QVOQIDX_74 0x16e434 4204#define QM_REG_QVOQIDX_75 0x16e438 4205#define QM_REG_QVOQIDX_76 0x16e43c 4206#define QM_REG_QVOQIDX_77 0x16e440 4207#define QM_REG_QVOQIDX_78 0x16e444 4208#define QM_REG_QVOQIDX_79 0x16e448 4209#define QM_REG_QVOQIDX_8 0x168114 4210#define QM_REG_QVOQIDX_80 0x16e44c 4211#define QM_REG_QVOQIDX_81 0x16e450 4212#define QM_REG_QVOQIDX_85 0x16e460 4213#define QM_REG_QVOQIDX_86 0x16e464 4214#define QM_REG_QVOQIDX_87 0x16e468 4215#define QM_REG_QVOQIDX_88 0x16e46c 4216#define QM_REG_QVOQIDX_89 0x16e470 4217#define QM_REG_QVOQIDX_9 0x168118 4218#define QM_REG_QVOQIDX_90 0x16e474 4219#define QM_REG_QVOQIDX_91 0x16e478 4220#define QM_REG_QVOQIDX_92 0x16e47c 4221#define QM_REG_QVOQIDX_93 0x16e480 4222#define QM_REG_QVOQIDX_94 0x16e484 4223#define QM_REG_QVOQIDX_95 0x16e488 4224#define QM_REG_QVOQIDX_96 0x16e48c 4225#define QM_REG_QVOQIDX_97 0x16e490 4226#define QM_REG_QVOQIDX_98 0x16e494 4227#define QM_REG_QVOQIDX_99 0x16e498 4228/* [RW 1] Initialization bit command */ 4229#define QM_REG_SOFT_RESET 0x168428 4230/* [RW 8] The credit cost per every task in the QM. A value per each VOQ */ 4231#define QM_REG_TASKCRDCOST_0 0x16809c 4232#define QM_REG_TASKCRDCOST_1 0x1680a0 4233#define QM_REG_TASKCRDCOST_2 0x1680a4 4234#define QM_REG_TASKCRDCOST_4 0x1680ac 4235#define QM_REG_TASKCRDCOST_5 0x1680b0 4236/* [R 6] Keep the fill level of the fifo from write client 3 */ 4237#define QM_REG_TQM_WRC_FIFOLVL 0x168010 4238/* [R 6] Keep the fill level of the fifo from write client 2 */ 4239#define QM_REG_UQM_WRC_FIFOLVL 0x168008 4240/* [RC 32] Credit update error register */ 4241#define QM_REG_VOQCRDERRREG 0x168408 4242/* [R 16] The credit value for each VOQ */ 4243#define QM_REG_VOQCREDIT_0 0x1682d0 4244#define QM_REG_VOQCREDIT_1 0x1682d4 4245#define QM_REG_VOQCREDIT_4 0x1682e0 4246/* [RW 16] The credit value that if above the QM is considered almost full */ 4247#define QM_REG_VOQCREDITAFULLTHR 0x168090 4248/* [RW 16] The init and maximum credit for each VoQ */ 4249#define QM_REG_VOQINITCREDIT_0 0x168060 4250#define QM_REG_VOQINITCREDIT_1 0x168064 4251#define QM_REG_VOQINITCREDIT_2 0x168068 4252#define QM_REG_VOQINITCREDIT_4 0x168070 4253#define QM_REG_VOQINITCREDIT_5 0x168074 4254/* [RW 1] The port of which VOQ belongs */ 4255#define QM_REG_VOQPORT_0 0x1682a0 4256#define QM_REG_VOQPORT_1 0x1682a4 4257#define QM_REG_VOQPORT_2 0x1682a8 4258/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4259#define QM_REG_VOQQMASK_0_LSB 0x168240 4260/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4261#define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524 4262/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4263#define QM_REG_VOQQMASK_0_MSB 0x168244 4264/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4265#define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528 4266/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4267#define QM_REG_VOQQMASK_10_LSB 0x168290 4268/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4269#define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574 4270/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4271#define QM_REG_VOQQMASK_10_MSB 0x168294 4272/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4273#define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578 4274/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4275#define QM_REG_VOQQMASK_11_LSB 0x168298 4276/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4277#define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c 4278/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4279#define QM_REG_VOQQMASK_11_MSB 0x16829c 4280/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4281#define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580 4282/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4283#define QM_REG_VOQQMASK_1_LSB 0x168248 4284/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4285#define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c 4286/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4287#define QM_REG_VOQQMASK_1_MSB 0x16824c 4288/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4289#define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530 4290/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4291#define QM_REG_VOQQMASK_2_LSB 0x168250 4292/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4293#define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534 4294/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4295#define QM_REG_VOQQMASK_2_MSB 0x168254 4296/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4297#define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538 4298/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4299#define QM_REG_VOQQMASK_3_LSB 0x168258 4300/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4301#define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c 4302/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4303#define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540 4304/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4305#define QM_REG_VOQQMASK_4_LSB 0x168260 4306/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4307#define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544 4308/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4309#define QM_REG_VOQQMASK_4_MSB 0x168264 4310/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4311#define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548 4312/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4313#define QM_REG_VOQQMASK_5_LSB 0x168268 4314/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4315#define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c 4316/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4317#define QM_REG_VOQQMASK_5_MSB 0x16826c 4318/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4319#define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550 4320/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4321#define QM_REG_VOQQMASK_6_LSB 0x168270 4322/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4323#define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554 4324/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4325#define QM_REG_VOQQMASK_6_MSB 0x168274 4326/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4327#define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558 4328/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4329#define QM_REG_VOQQMASK_7_LSB 0x168278 4330/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4331#define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c 4332/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4333#define QM_REG_VOQQMASK_7_MSB 0x16827c 4334/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4335#define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560 4336/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4337#define QM_REG_VOQQMASK_8_LSB 0x168280 4338/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4339#define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564 4340/* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */ 4341#define QM_REG_VOQQMASK_8_MSB 0x168284 4342/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4343#define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568 4344/* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 4345#define QM_REG_VOQQMASK_9_LSB 0x168288 4346/* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */ 4347#define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c 4348/* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */ 4349#define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570 4350/* [RW 32] Wrr weights */ 4351#define QM_REG_WRRWEIGHTS_0 0x16880c 4352#define QM_REG_WRRWEIGHTS_1 0x168810 4353#define QM_REG_WRRWEIGHTS_10 0x168814 4354#define QM_REG_WRRWEIGHTS_11 0x168818 4355#define QM_REG_WRRWEIGHTS_12 0x16881c 4356#define QM_REG_WRRWEIGHTS_13 0x168820 4357#define QM_REG_WRRWEIGHTS_14 0x168824 4358#define QM_REG_WRRWEIGHTS_15 0x168828 4359#define QM_REG_WRRWEIGHTS_16 0x16e000 4360#define QM_REG_WRRWEIGHTS_17 0x16e004 4361#define QM_REG_WRRWEIGHTS_18 0x16e008 4362#define QM_REG_WRRWEIGHTS_19 0x16e00c 4363#define QM_REG_WRRWEIGHTS_2 0x16882c 4364#define QM_REG_WRRWEIGHTS_20 0x16e010 4365#define QM_REG_WRRWEIGHTS_21 0x16e014 4366#define QM_REG_WRRWEIGHTS_22 0x16e018 4367#define QM_REG_WRRWEIGHTS_23 0x16e01c 4368#define QM_REG_WRRWEIGHTS_24 0x16e020 4369#define QM_REG_WRRWEIGHTS_25 0x16e024 4370#define QM_REG_WRRWEIGHTS_26 0x16e028 4371#define QM_REG_WRRWEIGHTS_27 0x16e02c 4372#define QM_REG_WRRWEIGHTS_28 0x16e030 4373#define QM_REG_WRRWEIGHTS_29 0x16e034 4374#define QM_REG_WRRWEIGHTS_3 0x168830 4375#define QM_REG_WRRWEIGHTS_30 0x16e038 4376#define QM_REG_WRRWEIGHTS_31 0x16e03c 4377#define QM_REG_WRRWEIGHTS_4 0x168834 4378#define QM_REG_WRRWEIGHTS_5 0x168838 4379#define QM_REG_WRRWEIGHTS_6 0x16883c 4380#define QM_REG_WRRWEIGHTS_7 0x168840 4381#define QM_REG_WRRWEIGHTS_8 0x168844 4382#define QM_REG_WRRWEIGHTS_9 0x168848 4383/* [R 6] Keep the fill level of the fifo from write client 1 */ 4384#define QM_REG_XQM_WRC_FIFOLVL 0x168000 4385/* [W 1] reset to parity interrupt */ 4386#define SEM_FAST_REG_PARITY_RST 0x18840 4387#define SRC_REG_COUNTFREE0 0x40500 4388/* [RW 1] If clr the searcher is compatible to E1 A0 - support only two 4389 ports. If set the searcher support 8 functions. */ 4390#define SRC_REG_E1HMF_ENABLE 0x404cc 4391#define SRC_REG_FIRSTFREE0 0x40510 4392#define SRC_REG_KEYRSS0_0 0x40408 4393#define SRC_REG_KEYRSS0_7 0x40424 4394#define SRC_REG_KEYRSS1_9 0x40454 4395#define SRC_REG_KEYSEARCH_0 0x40458 4396#define SRC_REG_KEYSEARCH_1 0x4045c 4397#define SRC_REG_KEYSEARCH_2 0x40460 4398#define SRC_REG_KEYSEARCH_3 0x40464 4399#define SRC_REG_KEYSEARCH_4 0x40468 4400#define SRC_REG_KEYSEARCH_5 0x4046c 4401#define SRC_REG_KEYSEARCH_6 0x40470 4402#define SRC_REG_KEYSEARCH_7 0x40474 4403#define SRC_REG_KEYSEARCH_8 0x40478 4404#define SRC_REG_KEYSEARCH_9 0x4047c 4405#define SRC_REG_LASTFREE0 0x40530 4406#define SRC_REG_NUMBER_HASH_BITS0 0x40400 4407/* [RW 1] Reset internal state machines. */ 4408#define SRC_REG_SOFT_RST 0x4049c 4409/* [R 3] Interrupt register #0 read */ 4410#define SRC_REG_SRC_INT_STS 0x404ac 4411/* [RW 3] Parity mask register #0 read/write */ 4412#define SRC_REG_SRC_PRTY_MASK 0x404c8 4413/* [R 3] Parity register #0 read */ 4414#define SRC_REG_SRC_PRTY_STS 0x404bc 4415/* [RC 3] Parity register #0 read clear */ 4416#define SRC_REG_SRC_PRTY_STS_CLR 0x404c0 4417/* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ 4418#define TCM_REG_CAM_OCCUP 0x5017c 4419/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4420 disregarded; valid output is deasserted; all other signals are treated as 4421 usual; if 1 - normal activity. */ 4422#define TCM_REG_CDU_AG_RD_IFEN 0x50034 4423/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4424 are disregarded; all other signals are treated as usual; if 1 - normal 4425 activity. */ 4426#define TCM_REG_CDU_AG_WR_IFEN 0x50030 4427/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4428 disregarded; valid output is deasserted; all other signals are treated as 4429 usual; if 1 - normal activity. */ 4430#define TCM_REG_CDU_SM_RD_IFEN 0x5003c 4431/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4432 input is disregarded; all other signals are treated as usual; if 1 - 4433 normal activity. */ 4434#define TCM_REG_CDU_SM_WR_IFEN 0x50038 4435/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4436 the initial credit value; read returns the current value of the credit 4437 counter. Must be initialized to 1 at start-up. */ 4438#define TCM_REG_CFC_INIT_CRD 0x50204 4439/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4440 weight 8 (the most prioritised); 1 stands for weight 1(least 4441 prioritised); 2 stands for weight 2; tc. */ 4442#define TCM_REG_CP_WEIGHT 0x500c0 4443/* [RW 1] Input csem Interface enable. If 0 - the valid input is 4444 disregarded; acknowledge output is deasserted; all other signals are 4445 treated as usual; if 1 - normal activity. */ 4446#define TCM_REG_CSEM_IFEN 0x5002c 4447/* [RC 1] Message length mismatch (relative to last indication) at the In#9 4448 interface. */ 4449#define TCM_REG_CSEM_LENGTH_MIS 0x50174 4450/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4451 weight 8 (the most prioritised); 1 stands for weight 1(least 4452 prioritised); 2 stands for weight 2; tc. */ 4453#define TCM_REG_CSEM_WEIGHT 0x500bc 4454/* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */ 4455#define TCM_REG_ERR_EVNT_ID 0x500a0 4456/* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4457#define TCM_REG_ERR_TCM_HDR 0x5009c 4458/* [RW 8] The Event ID for Timers expiration. */ 4459#define TCM_REG_EXPR_EVNT_ID 0x500a4 4460/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4461 writes the initial credit value; read returns the current value of the 4462 credit counter. Must be initialized to 64 at start-up. */ 4463#define TCM_REG_FIC0_INIT_CRD 0x5020c 4464/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4465 writes the initial credit value; read returns the current value of the 4466 credit counter. Must be initialized to 64 at start-up. */ 4467#define TCM_REG_FIC1_INIT_CRD 0x50210 4468/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 4469 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr; 4470 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and 4471 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */ 4472#define TCM_REG_GR_ARB_TYPE 0x50114 4473/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 4474 highest priority is 3. It is supposed that the Store channel is the 4475 compliment of the other 3 groups. */ 4476#define TCM_REG_GR_LD0_PR 0x5011c 4477/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 4478 highest priority is 3. It is supposed that the Store channel is the 4479 compliment of the other 3 groups. */ 4480#define TCM_REG_GR_LD1_PR 0x50120 4481/* [RW 4] The number of double REG-pairs; loaded from the STORM context and 4482 sent to STORM; for a specific connection type. The double REG-pairs are 4483 used to align to STORM context row size of 128 bits. The offset of these 4484 data in the STORM context is always 0. Index _i stands for the connection 4485 type (one of 16). */ 4486#define TCM_REG_N_SM_CTX_LD_0 0x50050 4487#define TCM_REG_N_SM_CTX_LD_1 0x50054 4488#define TCM_REG_N_SM_CTX_LD_2 0x50058 4489#define TCM_REG_N_SM_CTX_LD_3 0x5005c 4490#define TCM_REG_N_SM_CTX_LD_4 0x50060 4491#define TCM_REG_N_SM_CTX_LD_5 0x50064 4492/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 4493 acknowledge output is deasserted; all other signals are treated as usual; 4494 if 1 - normal activity. */ 4495#define TCM_REG_PBF_IFEN 0x50024 4496/* [RC 1] Message length mismatch (relative to last indication) at the In#7 4497 interface. */ 4498#define TCM_REG_PBF_LENGTH_MIS 0x5016c 4499/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 4500 weight 8 (the most prioritised); 1 stands for weight 1(least 4501 prioritised); 2 stands for weight 2; tc. */ 4502#define TCM_REG_PBF_WEIGHT 0x500b4 4503#define TCM_REG_PHYS_QNUM0_0 0x500e0 4504#define TCM_REG_PHYS_QNUM0_1 0x500e4 4505#define TCM_REG_PHYS_QNUM1_0 0x500e8 4506#define TCM_REG_PHYS_QNUM1_1 0x500ec 4507#define TCM_REG_PHYS_QNUM2_0 0x500f0 4508#define TCM_REG_PHYS_QNUM2_1 0x500f4 4509#define TCM_REG_PHYS_QNUM3_0 0x500f8 4510#define TCM_REG_PHYS_QNUM3_1 0x500fc 4511/* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 4512 acknowledge output is deasserted; all other signals are treated as usual; 4513 if 1 - normal activity. */ 4514#define TCM_REG_PRS_IFEN 0x50020 4515/* [RC 1] Message length mismatch (relative to last indication) at the In#6 4516 interface. */ 4517#define TCM_REG_PRS_LENGTH_MIS 0x50168 4518/* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for 4519 weight 8 (the most prioritised); 1 stands for weight 1(least 4520 prioritised); 2 stands for weight 2; tc. */ 4521#define TCM_REG_PRS_WEIGHT 0x500b0 4522/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 4523#define TCM_REG_STOP_EVNT_ID 0x500a8 4524/* [RC 1] Message length mismatch (relative to last indication) at the STORM 4525 interface. */ 4526#define TCM_REG_STORM_LENGTH_MIS 0x50160 4527/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 4528 disregarded; acknowledge output is deasserted; all other signals are 4529 treated as usual; if 1 - normal activity. */ 4530#define TCM_REG_STORM_TCM_IFEN 0x50010 4531/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 4532 weight 8 (the most prioritised); 1 stands for weight 1(least 4533 prioritised); 2 stands for weight 2; tc. */ 4534#define TCM_REG_STORM_WEIGHT 0x500ac 4535/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 4536 acknowledge output is deasserted; all other signals are treated as usual; 4537 if 1 - normal activity. */ 4538#define TCM_REG_TCM_CFC_IFEN 0x50040 4539/* [RW 11] Interrupt mask register #0 read/write */ 4540#define TCM_REG_TCM_INT_MASK 0x501dc 4541/* [R 11] Interrupt register #0 read */ 4542#define TCM_REG_TCM_INT_STS 0x501d0 4543/* [RW 27] Parity mask register #0 read/write */ 4544#define TCM_REG_TCM_PRTY_MASK 0x501ec 4545/* [R 27] Parity register #0 read */ 4546#define TCM_REG_TCM_PRTY_STS 0x501e0 4547/* [RC 27] Parity register #0 read clear */ 4548#define TCM_REG_TCM_PRTY_STS_CLR 0x501e4 4549/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS 4550 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 4551 Is used to determine the number of the AG context REG-pairs written back; 4552 when the input message Reg1WbFlg isn't set. */ 4553#define TCM_REG_TCM_REG0_SZ 0x500d8 4554/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 4555 disregarded; valid is deasserted; all other signals are treated as usual; 4556 if 1 - normal activity. */ 4557#define TCM_REG_TCM_STORM0_IFEN 0x50004 4558/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 4559 disregarded; valid is deasserted; all other signals are treated as usual; 4560 if 1 - normal activity. */ 4561#define TCM_REG_TCM_STORM1_IFEN 0x50008 4562/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 4563 disregarded; valid is deasserted; all other signals are treated as usual; 4564 if 1 - normal activity. */ 4565#define TCM_REG_TCM_TQM_IFEN 0x5000c 4566/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 4567#define TCM_REG_TCM_TQM_USE_Q 0x500d4 4568/* [RW 28] The CM header for Timers expiration command. */ 4569#define TCM_REG_TM_TCM_HDR 0x50098 4570/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 4571 disregarded; acknowledge output is deasserted; all other signals are 4572 treated as usual; if 1 - normal activity. */ 4573#define TCM_REG_TM_TCM_IFEN 0x5001c 4574/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 4575 weight 8 (the most prioritised); 1 stands for weight 1(least 4576 prioritised); 2 stands for weight 2; tc. */ 4577#define TCM_REG_TM_WEIGHT 0x500d0 4578/* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4579 the initial credit value; read returns the current value of the credit 4580 counter. Must be initialized to 32 at start-up. */ 4581#define TCM_REG_TQM_INIT_CRD 0x5021c 4582/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 4583 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4584 prioritised); 2 stands for weight 2; tc. */ 4585#define TCM_REG_TQM_P_WEIGHT 0x500c8 4586/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 4587 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 4588 prioritised); 2 stands for weight 2; tc. */ 4589#define TCM_REG_TQM_S_WEIGHT 0x500cc 4590/* [RW 28] The CM header value for QM request (primary). */ 4591#define TCM_REG_TQM_TCM_HDR_P 0x50090 4592/* [RW 28] The CM header value for QM request (secondary). */ 4593#define TCM_REG_TQM_TCM_HDR_S 0x50094 4594/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 4595 acknowledge output is deasserted; all other signals are treated as usual; 4596 if 1 - normal activity. */ 4597#define TCM_REG_TQM_TCM_IFEN 0x50014 4598/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 4599 acknowledge output is deasserted; all other signals are treated as usual; 4600 if 1 - normal activity. */ 4601#define TCM_REG_TSDM_IFEN 0x50018 4602/* [RC 1] Message length mismatch (relative to last indication) at the SDM 4603 interface. */ 4604#define TCM_REG_TSDM_LENGTH_MIS 0x50164 4605/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 4606 weight 8 (the most prioritised); 1 stands for weight 1(least 4607 prioritised); 2 stands for weight 2; tc. */ 4608#define TCM_REG_TSDM_WEIGHT 0x500c4 4609/* [RW 1] Input usem Interface enable. If 0 - the valid input is 4610 disregarded; acknowledge output is deasserted; all other signals are 4611 treated as usual; if 1 - normal activity. */ 4612#define TCM_REG_USEM_IFEN 0x50028 4613/* [RC 1] Message length mismatch (relative to last indication) at the In#8 4614 interface. */ 4615#define TCM_REG_USEM_LENGTH_MIS 0x50170 4616/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 4617 weight 8 (the most prioritised); 1 stands for weight 1(least 4618 prioritised); 2 stands for weight 2; tc. */ 4619#define TCM_REG_USEM_WEIGHT 0x500b8 4620/* [RW 21] Indirect access to the descriptor table of the XX protection 4621 mechanism. The fields are: [5:0] - length of the message; 15:6] - message 4622 pointer; 20:16] - next pointer. */ 4623#define TCM_REG_XX_DESCR_TABLE 0x50280 4624#define TCM_REG_XX_DESCR_TABLE_SIZE 29 4625/* [R 6] Use to read the value of XX protection Free counter. */ 4626#define TCM_REG_XX_FREE 0x50178 4627/* [RW 6] Initial value for the credit counter; responsible for fulfilling 4628 of the Input Stage XX protection buffer by the XX protection pending 4629 messages. Max credit available - 127.Write writes the initial credit 4630 value; read returns the current value of the credit counter. Must be 4631 initialized to 19 at start-up. */ 4632#define TCM_REG_XX_INIT_CRD 0x50220 4633/* [RW 6] Maximum link list size (messages locked) per connection in the XX 4634 protection. */ 4635#define TCM_REG_XX_MAX_LL_SZ 0x50044 4636/* [RW 6] The maximum number of pending messages; which may be stored in XX 4637 protection. ~tcm_registers_xx_free.xx_free is read on read. */ 4638#define TCM_REG_XX_MSG_NUM 0x50224 4639/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 4640#define TCM_REG_XX_OVFL_EVNT_ID 0x50048 4641/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 4642 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] - 4643 header pointer. */ 4644#define TCM_REG_XX_TABLE 0x50240 4645/* [RW 4] Load value for cfc ac credit cnt. */ 4646#define TM_REG_CFC_AC_CRDCNT_VAL 0x164208 4647/* [RW 4] Load value for cfc cld credit cnt. */ 4648#define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210 4649/* [RW 8] Client0 context region. */ 4650#define TM_REG_CL0_CONT_REGION 0x164030 4651/* [RW 8] Client1 context region. */ 4652#define TM_REG_CL1_CONT_REGION 0x164034 4653/* [RW 8] Client2 context region. */ 4654#define TM_REG_CL2_CONT_REGION 0x164038 4655/* [RW 2] Client in High priority client number. */ 4656#define TM_REG_CLIN_PRIOR0_CLIENT 0x164024 4657/* [RW 4] Load value for clout0 cred cnt. */ 4658#define TM_REG_CLOUT_CRDCNT0_VAL 0x164220 4659/* [RW 4] Load value for clout1 cred cnt. */ 4660#define TM_REG_CLOUT_CRDCNT1_VAL 0x164228 4661/* [RW 4] Load value for clout2 cred cnt. */ 4662#define TM_REG_CLOUT_CRDCNT2_VAL 0x164230 4663/* [RW 1] Enable client0 input. */ 4664#define TM_REG_EN_CL0_INPUT 0x164008 4665/* [RW 1] Enable client1 input. */ 4666#define TM_REG_EN_CL1_INPUT 0x16400c 4667/* [RW 1] Enable client2 input. */ 4668#define TM_REG_EN_CL2_INPUT 0x164010 4669#define TM_REG_EN_LINEAR0_TIMER 0x164014 4670/* [RW 1] Enable real time counter. */ 4671#define TM_REG_EN_REAL_TIME_CNT 0x1640d8 4672/* [RW 1] Enable for Timers state machines. */ 4673#define TM_REG_EN_TIMERS 0x164000 4674/* [RW 4] Load value for expiration credit cnt. CFC max number of 4675 outstanding load requests for timers (expiration) context loading. */ 4676#define TM_REG_EXP_CRDCNT_VAL 0x164238 4677/* [RW 32] Linear0 logic address. */ 4678#define TM_REG_LIN0_LOGIC_ADDR 0x164240 4679/* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 4680#define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 4681/* [ST 16] Linear0 Number of scans counter. */ 4682#define TM_REG_LIN0_NUM_SCANS 0x1640a0 4683/* [WB 64] Linear0 phy address. */ 4684#define TM_REG_LIN0_PHY_ADDR 0x164270 4685/* [RW 1] Linear0 physical address valid. */ 4686#define TM_REG_LIN0_PHY_ADDR_VALID 0x164248 4687#define TM_REG_LIN0_SCAN_ON 0x1640d0 4688/* [RW 24] Linear0 array scan timeout. */ 4689#define TM_REG_LIN0_SCAN_TIME 0x16403c 4690#define TM_REG_LIN0_VNIC_UC 0x164128 4691/* [RW 32] Linear1 logic address. */ 4692#define TM_REG_LIN1_LOGIC_ADDR 0x164250 4693/* [WB 64] Linear1 phy address. */ 4694#define TM_REG_LIN1_PHY_ADDR 0x164280 4695/* [RW 1] Linear1 physical address valid. */ 4696#define TM_REG_LIN1_PHY_ADDR_VALID 0x164258 4697/* [RW 6] Linear timer set_clear fifo threshold. */ 4698#define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070 4699/* [RW 2] Load value for pci arbiter credit cnt. */ 4700#define TM_REG_PCIARB_CRDCNT_VAL 0x164260 4701/* [RW 20] The amount of hardware cycles for each timer tick. */ 4702#define TM_REG_TIMER_TICK_SIZE 0x16401c 4703/* [RW 8] Timers Context region. */ 4704#define TM_REG_TM_CONTEXT_REGION 0x164044 4705/* [RW 1] Interrupt mask register #0 read/write */ 4706#define TM_REG_TM_INT_MASK 0x1640fc 4707/* [R 1] Interrupt register #0 read */ 4708#define TM_REG_TM_INT_STS 0x1640f0 4709/* [RW 7] Parity mask register #0 read/write */ 4710#define TM_REG_TM_PRTY_MASK 0x16410c 4711/* [R 7] Parity register #0 read */ 4712#define TM_REG_TM_PRTY_STS 0x164100 4713/* [RC 7] Parity register #0 read clear */ 4714#define TM_REG_TM_PRTY_STS_CLR 0x164104 4715/* [RW 8] The event id for aggregated interrupt 0 */ 4716#define TSDM_REG_AGG_INT_EVENT_0 0x42038 4717#define TSDM_REG_AGG_INT_EVENT_1 0x4203c 4718#define TSDM_REG_AGG_INT_EVENT_2 0x42040 4719#define TSDM_REG_AGG_INT_EVENT_3 0x42044 4720#define TSDM_REG_AGG_INT_EVENT_4 0x42048 4721/* [RW 1] The T bit for aggregated interrupt 0 */ 4722#define TSDM_REG_AGG_INT_T_0 0x420b8 4723#define TSDM_REG_AGG_INT_T_1 0x420bc 4724/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 4725#define TSDM_REG_CFC_RSP_START_ADDR 0x42008 4726/* [RW 16] The maximum value of the completion counter #0 */ 4727#define TSDM_REG_CMP_COUNTER_MAX0 0x4201c 4728/* [RW 16] The maximum value of the completion counter #1 */ 4729#define TSDM_REG_CMP_COUNTER_MAX1 0x42020 4730/* [RW 16] The maximum value of the completion counter #2 */ 4731#define TSDM_REG_CMP_COUNTER_MAX2 0x42024 4732/* [RW 16] The maximum value of the completion counter #3 */ 4733#define TSDM_REG_CMP_COUNTER_MAX3 0x42028 4734/* [RW 13] The start address in the internal RAM for the completion 4735 counters. */ 4736#define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c 4737#define TSDM_REG_ENABLE_IN1 0x42238 4738#define TSDM_REG_ENABLE_IN2 0x4223c 4739#define TSDM_REG_ENABLE_OUT1 0x42240 4740#define TSDM_REG_ENABLE_OUT2 0x42244 4741/* [RW 4] The initial number of messages that can be sent to the pxp control 4742 interface without receiving any ACK. */ 4743#define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc 4744/* [ST 32] The number of ACK after placement messages received */ 4745#define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c 4746/* [ST 32] The number of packet end messages received from the parser */ 4747#define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274 4748/* [ST 32] The number of requests received from the pxp async if */ 4749#define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278 4750/* [ST 32] The number of commands received in queue 0 */ 4751#define TSDM_REG_NUM_OF_Q0_CMD 0x42248 4752/* [ST 32] The number of commands received in queue 10 */ 4753#define TSDM_REG_NUM_OF_Q10_CMD 0x4226c 4754/* [ST 32] The number of commands received in queue 11 */ 4755#define TSDM_REG_NUM_OF_Q11_CMD 0x42270 4756/* [ST 32] The number of commands received in queue 1 */ 4757#define TSDM_REG_NUM_OF_Q1_CMD 0x4224c 4758/* [ST 32] The number of commands received in queue 3 */ 4759#define TSDM_REG_NUM_OF_Q3_CMD 0x42250 4760/* [ST 32] The number of commands received in queue 4 */ 4761#define TSDM_REG_NUM_OF_Q4_CMD 0x42254 4762/* [ST 32] The number of commands received in queue 5 */ 4763#define TSDM_REG_NUM_OF_Q5_CMD 0x42258 4764/* [ST 32] The number of commands received in queue 6 */ 4765#define TSDM_REG_NUM_OF_Q6_CMD 0x4225c 4766/* [ST 32] The number of commands received in queue 7 */ 4767#define TSDM_REG_NUM_OF_Q7_CMD 0x42260 4768/* [ST 32] The number of commands received in queue 8 */ 4769#define TSDM_REG_NUM_OF_Q8_CMD 0x42264 4770/* [ST 32] The number of commands received in queue 9 */ 4771#define TSDM_REG_NUM_OF_Q9_CMD 0x42268 4772/* [RW 13] The start address in the internal RAM for the packet end message */ 4773#define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014 4774/* [RW 13] The start address in the internal RAM for queue counters */ 4775#define TSDM_REG_Q_COUNTER_START_ADDR 0x42010 4776/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4777#define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 4778/* [R 1] parser fifo empty in sdm_sync block */ 4779#define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 4780/* [R 1] parser serial fifo empty in sdm_sync block */ 4781#define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 4782/* [RW 32] Tick for timer counter. Applicable only when 4783 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 4784#define TSDM_REG_TIMER_TICK 0x42000 4785/* [RW 32] Interrupt mask register #0 read/write */ 4786#define TSDM_REG_TSDM_INT_MASK_0 0x4229c 4787#define TSDM_REG_TSDM_INT_MASK_1 0x422ac 4788/* [R 32] Interrupt register #0 read */ 4789#define TSDM_REG_TSDM_INT_STS_0 0x42290 4790#define TSDM_REG_TSDM_INT_STS_1 0x422a0 4791/* [RW 11] Parity mask register #0 read/write */ 4792#define TSDM_REG_TSDM_PRTY_MASK 0x422bc 4793/* [R 11] Parity register #0 read */ 4794#define TSDM_REG_TSDM_PRTY_STS 0x422b0 4795/* [RC 11] Parity register #0 read clear */ 4796#define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4 4797/* [RW 5] The number of time_slots in the arbitration cycle */ 4798#define TSEM_REG_ARB_CYCLE_SIZE 0x180034 4799/* [RW 3] The source that is associated with arbitration element 0. Source 4800 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4801 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 4802#define TSEM_REG_ARB_ELEMENT0 0x180020 4803/* [RW 3] The source that is associated with arbitration element 1. Source 4804 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4805 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4806 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */ 4807#define TSEM_REG_ARB_ELEMENT1 0x180024 4808/* [RW 3] The source that is associated with arbitration element 2. Source 4809 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4810 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4811 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4812 and ~tsem_registers_arb_element1.arb_element1 */ 4813#define TSEM_REG_ARB_ELEMENT2 0x180028 4814/* [RW 3] The source that is associated with arbitration element 3. Source 4815 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4816 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 4817 not be equal to register ~tsem_registers_arb_element0.arb_element0 and 4818 ~tsem_registers_arb_element1.arb_element1 and 4819 ~tsem_registers_arb_element2.arb_element2 */ 4820#define TSEM_REG_ARB_ELEMENT3 0x18002c 4821/* [RW 3] The source that is associated with arbitration element 4. Source 4822 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 4823 sleeping thread with priority 1; 4- sleeping thread with priority 2. 4824 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 4825 and ~tsem_registers_arb_element1.arb_element1 and 4826 ~tsem_registers_arb_element2.arb_element2 and 4827 ~tsem_registers_arb_element3.arb_element3 */ 4828#define TSEM_REG_ARB_ELEMENT4 0x180030 4829#define TSEM_REG_ENABLE_IN 0x1800a4 4830#define TSEM_REG_ENABLE_OUT 0x1800a8 4831/* [RW 32] This address space contains all registers and memories that are 4832 placed in SEM_FAST block. The SEM_FAST registers are described in 4833 appendix B. In order to access the sem_fast registers the base address 4834 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 4835#define TSEM_REG_FAST_MEMORY 0x1a0000 4836/* [RW 1] Disables input messages from FIC0 May be updated during run_time 4837 by the microcode */ 4838#define TSEM_REG_FIC0_DISABLE 0x180224 4839/* [RW 1] Disables input messages from FIC1 May be updated during run_time 4840 by the microcode */ 4841#define TSEM_REG_FIC1_DISABLE 0x180234 4842/* [RW 15] Interrupt table Read and write access to it is not possible in 4843 the middle of the work */ 4844#define TSEM_REG_INT_TABLE 0x180400 4845/* [ST 24] Statistics register. The number of messages that entered through 4846 FIC0 */ 4847#define TSEM_REG_MSG_NUM_FIC0 0x180000 4848/* [ST 24] Statistics register. The number of messages that entered through 4849 FIC1 */ 4850#define TSEM_REG_MSG_NUM_FIC1 0x180004 4851/* [ST 24] Statistics register. The number of messages that were sent to 4852 FOC0 */ 4853#define TSEM_REG_MSG_NUM_FOC0 0x180008 4854/* [ST 24] Statistics register. The number of messages that were sent to 4855 FOC1 */ 4856#define TSEM_REG_MSG_NUM_FOC1 0x18000c 4857/* [ST 24] Statistics register. The number of messages that were sent to 4858 FOC2 */ 4859#define TSEM_REG_MSG_NUM_FOC2 0x180010 4860/* [ST 24] Statistics register. The number of messages that were sent to 4861 FOC3 */ 4862#define TSEM_REG_MSG_NUM_FOC3 0x180014 4863/* [RW 1] Disables input messages from the passive buffer May be updated 4864 during run_time by the microcode */ 4865#define TSEM_REG_PAS_DISABLE 0x18024c 4866/* [WB 128] Debug only. Passive buffer memory */ 4867#define TSEM_REG_PASSIVE_BUFFER 0x181000 4868/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4869#define TSEM_REG_PRAM 0x1c0000 4870/* [R 8] Valid sleeping threads indication have bit per thread */ 4871#define TSEM_REG_SLEEP_THREADS_VALID 0x18026c 4872/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4873#define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 4874/* [RW 8] List of free threads . There is a bit per thread. */ 4875#define TSEM_REG_THREADS_LIST 0x1802e4 4876/* [RC 32] Parity register #0 read clear */ 4877#define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118 4878#define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128 4879/* [RW 3] The arbitration scheme of time_slot 0 */ 4880#define TSEM_REG_TS_0_AS 0x180038 4881/* [RW 3] The arbitration scheme of time_slot 10 */ 4882#define TSEM_REG_TS_10_AS 0x180060 4883/* [RW 3] The arbitration scheme of time_slot 11 */ 4884#define TSEM_REG_TS_11_AS 0x180064 4885/* [RW 3] The arbitration scheme of time_slot 12 */ 4886#define TSEM_REG_TS_12_AS 0x180068 4887/* [RW 3] The arbitration scheme of time_slot 13 */ 4888#define TSEM_REG_TS_13_AS 0x18006c 4889/* [RW 3] The arbitration scheme of time_slot 14 */ 4890#define TSEM_REG_TS_14_AS 0x180070 4891/* [RW 3] The arbitration scheme of time_slot 15 */ 4892#define TSEM_REG_TS_15_AS 0x180074 4893/* [RW 3] The arbitration scheme of time_slot 16 */ 4894#define TSEM_REG_TS_16_AS 0x180078 4895/* [RW 3] The arbitration scheme of time_slot 17 */ 4896#define TSEM_REG_TS_17_AS 0x18007c 4897/* [RW 3] The arbitration scheme of time_slot 18 */ 4898#define TSEM_REG_TS_18_AS 0x180080 4899/* [RW 3] The arbitration scheme of time_slot 1 */ 4900#define TSEM_REG_TS_1_AS 0x18003c 4901/* [RW 3] The arbitration scheme of time_slot 2 */ 4902#define TSEM_REG_TS_2_AS 0x180040 4903/* [RW 3] The arbitration scheme of time_slot 3 */ 4904#define TSEM_REG_TS_3_AS 0x180044 4905/* [RW 3] The arbitration scheme of time_slot 4 */ 4906#define TSEM_REG_TS_4_AS 0x180048 4907/* [RW 3] The arbitration scheme of time_slot 5 */ 4908#define TSEM_REG_TS_5_AS 0x18004c 4909/* [RW 3] The arbitration scheme of time_slot 6 */ 4910#define TSEM_REG_TS_6_AS 0x180050 4911/* [RW 3] The arbitration scheme of time_slot 7 */ 4912#define TSEM_REG_TS_7_AS 0x180054 4913/* [RW 3] The arbitration scheme of time_slot 8 */ 4914#define TSEM_REG_TS_8_AS 0x180058 4915/* [RW 3] The arbitration scheme of time_slot 9 */ 4916#define TSEM_REG_TS_9_AS 0x18005c 4917/* [RW 32] Interrupt mask register #0 read/write */ 4918#define TSEM_REG_TSEM_INT_MASK_0 0x180100 4919#define TSEM_REG_TSEM_INT_MASK_1 0x180110 4920/* [R 32] Interrupt register #0 read */ 4921#define TSEM_REG_TSEM_INT_STS_0 0x1800f4 4922#define TSEM_REG_TSEM_INT_STS_1 0x180104 4923/* [RW 32] Parity mask register #0 read/write */ 4924#define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 4925#define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 4926/* [R 32] Parity register #0 read */ 4927#define TSEM_REG_TSEM_PRTY_STS_0 0x180114 4928#define TSEM_REG_TSEM_PRTY_STS_1 0x180124 4929/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 4930 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 4931#define TSEM_REG_VFPF_ERR_NUM 0x180380 4932/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 4933 * [10:8] of the address should be the offset within the accessed LCID 4934 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 4935 * LCID100. The RBC address should be 12'ha64. */ 4936#define UCM_REG_AG_CTX 0xe2000 4937/* [R 5] Used to read the XX protection CAM occupancy counter. */ 4938#define UCM_REG_CAM_OCCUP 0xe0170 4939/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 4940 disregarded; valid output is deasserted; all other signals are treated as 4941 usual; if 1 - normal activity. */ 4942#define UCM_REG_CDU_AG_RD_IFEN 0xe0038 4943/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 4944 are disregarded; all other signals are treated as usual; if 1 - normal 4945 activity. */ 4946#define UCM_REG_CDU_AG_WR_IFEN 0xe0034 4947/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 4948 disregarded; valid output is deasserted; all other signals are treated as 4949 usual; if 1 - normal activity. */ 4950#define UCM_REG_CDU_SM_RD_IFEN 0xe0040 4951/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 4952 input is disregarded; all other signals are treated as usual; if 1 - 4953 normal activity. */ 4954#define UCM_REG_CDU_SM_WR_IFEN 0xe003c 4955/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 4956 the initial credit value; read returns the current value of the credit 4957 counter. Must be initialized to 1 at start-up. */ 4958#define UCM_REG_CFC_INIT_CRD 0xe0204 4959/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 4960 weight 8 (the most prioritised); 1 stands for weight 1(least 4961 prioritised); 2 stands for weight 2; tc. */ 4962#define UCM_REG_CP_WEIGHT 0xe00c4 4963/* [RW 1] Input csem Interface enable. If 0 - the valid input is 4964 disregarded; acknowledge output is deasserted; all other signals are 4965 treated as usual; if 1 - normal activity. */ 4966#define UCM_REG_CSEM_IFEN 0xe0028 4967/* [RC 1] Set when the message length mismatch (relative to last indication) 4968 at the csem interface is detected. */ 4969#define UCM_REG_CSEM_LENGTH_MIS 0xe0160 4970/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 4971 weight 8 (the most prioritised); 1 stands for weight 1(least 4972 prioritised); 2 stands for weight 2; tc. */ 4973#define UCM_REG_CSEM_WEIGHT 0xe00b8 4974/* [RW 1] Input dorq Interface enable. If 0 - the valid input is 4975 disregarded; acknowledge output is deasserted; all other signals are 4976 treated as usual; if 1 - normal activity. */ 4977#define UCM_REG_DORQ_IFEN 0xe0030 4978/* [RC 1] Set when the message length mismatch (relative to last indication) 4979 at the dorq interface is detected. */ 4980#define UCM_REG_DORQ_LENGTH_MIS 0xe0168 4981/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 4982 weight 8 (the most prioritised); 1 stands for weight 1(least 4983 prioritised); 2 stands for weight 2; tc. */ 4984#define UCM_REG_DORQ_WEIGHT 0xe00c0 4985/* [RW 8] The Event ID in case ErrorFlg input message bit is set. */ 4986#define UCM_REG_ERR_EVNT_ID 0xe00a4 4987/* [RW 28] The CM erroneous header for QM and Timers formatting. */ 4988#define UCM_REG_ERR_UCM_HDR 0xe00a0 4989/* [RW 8] The Event ID for Timers expiration. */ 4990#define UCM_REG_EXPR_EVNT_ID 0xe00a8 4991/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 4992 writes the initial credit value; read returns the current value of the 4993 credit counter. Must be initialized to 64 at start-up. */ 4994#define UCM_REG_FIC0_INIT_CRD 0xe020c 4995/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4996 writes the initial credit value; read returns the current value of the 4997 credit counter. Must be initialized to 64 at start-up. */ 4998#define UCM_REG_FIC1_INIT_CRD 0xe0210 4999/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1 5000 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr; 5001 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and 5002 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */ 5003#define UCM_REG_GR_ARB_TYPE 0xe0144 5004/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 5005 highest priority is 3. It is supposed that the Store channel group is 5006 compliment to the others. */ 5007#define UCM_REG_GR_LD0_PR 0xe014c 5008/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 5009 highest priority is 3. It is supposed that the Store channel group is 5010 compliment to the others. */ 5011#define UCM_REG_GR_LD1_PR 0xe0150 5012/* [RW 2] The queue index for invalidate counter flag decision. */ 5013#define UCM_REG_INV_CFLG_Q 0xe00e4 5014/* [RW 5] The number of double REG-pairs; loaded from the STORM context and 5015 sent to STORM; for a specific connection type. the double REG-pairs are 5016 used in order to align to STORM context row size of 128 bits. The offset 5017 of these data in the STORM context is always 0. Index _i stands for the 5018 connection type (one of 16). */ 5019#define UCM_REG_N_SM_CTX_LD_0 0xe0054 5020#define UCM_REG_N_SM_CTX_LD_1 0xe0058 5021#define UCM_REG_N_SM_CTX_LD_2 0xe005c 5022#define UCM_REG_N_SM_CTX_LD_3 0xe0060 5023#define UCM_REG_N_SM_CTX_LD_4 0xe0064 5024#define UCM_REG_N_SM_CTX_LD_5 0xe0068 5025#define UCM_REG_PHYS_QNUM0_0 0xe0110 5026#define UCM_REG_PHYS_QNUM0_1 0xe0114 5027#define UCM_REG_PHYS_QNUM1_0 0xe0118 5028#define UCM_REG_PHYS_QNUM1_1 0xe011c 5029#define UCM_REG_PHYS_QNUM2_0 0xe0120 5030#define UCM_REG_PHYS_QNUM2_1 0xe0124 5031#define UCM_REG_PHYS_QNUM3_0 0xe0128 5032#define UCM_REG_PHYS_QNUM3_1 0xe012c 5033/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 5034#define UCM_REG_STOP_EVNT_ID 0xe00ac 5035/* [RC 1] Set when the message length mismatch (relative to last indication) 5036 at the STORM interface is detected. */ 5037#define UCM_REG_STORM_LENGTH_MIS 0xe0154 5038/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 5039 disregarded; acknowledge output is deasserted; all other signals are 5040 treated as usual; if 1 - normal activity. */ 5041#define UCM_REG_STORM_UCM_IFEN 0xe0010 5042/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 5043 weight 8 (the most prioritised); 1 stands for weight 1(least 5044 prioritised); 2 stands for weight 2; tc. */ 5045#define UCM_REG_STORM_WEIGHT 0xe00b0 5046/* [RW 4] Timers output initial credit. Max credit available - 15.Write 5047 writes the initial credit value; read returns the current value of the 5048 credit counter. Must be initialized to 4 at start-up. */ 5049#define UCM_REG_TM_INIT_CRD 0xe021c 5050/* [RW 28] The CM header for Timers expiration command. */ 5051#define UCM_REG_TM_UCM_HDR 0xe009c 5052/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 5053 disregarded; acknowledge output is deasserted; all other signals are 5054 treated as usual; if 1 - normal activity. */ 5055#define UCM_REG_TM_UCM_IFEN 0xe001c 5056/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 5057 weight 8 (the most prioritised); 1 stands for weight 1(least 5058 prioritised); 2 stands for weight 2; tc. */ 5059#define UCM_REG_TM_WEIGHT 0xe00d4 5060/* [RW 1] Input tsem Interface enable. If 0 - the valid input is 5061 disregarded; acknowledge output is deasserted; all other signals are 5062 treated as usual; if 1 - normal activity. */ 5063#define UCM_REG_TSEM_IFEN 0xe0024 5064/* [RC 1] Set when the message length mismatch (relative to last indication) 5065 at the tsem interface is detected. */ 5066#define UCM_REG_TSEM_LENGTH_MIS 0xe015c 5067/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 5068 weight 8 (the most prioritised); 1 stands for weight 1(least 5069 prioritised); 2 stands for weight 2; tc. */ 5070#define UCM_REG_TSEM_WEIGHT 0xe00b4 5071/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 5072 acknowledge output is deasserted; all other signals are treated as usual; 5073 if 1 - normal activity. */ 5074#define UCM_REG_UCM_CFC_IFEN 0xe0044 5075/* [RW 11] Interrupt mask register #0 read/write */ 5076#define UCM_REG_UCM_INT_MASK 0xe01d4 5077/* [R 11] Interrupt register #0 read */ 5078#define UCM_REG_UCM_INT_STS 0xe01c8 5079/* [RW 27] Parity mask register #0 read/write */ 5080#define UCM_REG_UCM_PRTY_MASK 0xe01e4 5081/* [R 27] Parity register #0 read */ 5082#define UCM_REG_UCM_PRTY_STS 0xe01d8 5083/* [RC 27] Parity register #0 read clear */ 5084#define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc 5085/* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS 5086 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 5087 Is used to determine the number of the AG context REG-pairs written back; 5088 when the Reg1WbFlg isn't set. */ 5089#define UCM_REG_UCM_REG0_SZ 0xe00dc 5090/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 5091 disregarded; valid is deasserted; all other signals are treated as usual; 5092 if 1 - normal activity. */ 5093#define UCM_REG_UCM_STORM0_IFEN 0xe0004 5094/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 5095 disregarded; valid is deasserted; all other signals are treated as usual; 5096 if 1 - normal activity. */ 5097#define UCM_REG_UCM_STORM1_IFEN 0xe0008 5098/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 5099 disregarded; acknowledge output is deasserted; all other signals are 5100 treated as usual; if 1 - normal activity. */ 5101#define UCM_REG_UCM_TM_IFEN 0xe0020 5102/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 5103 disregarded; valid is deasserted; all other signals are treated as usual; 5104 if 1 - normal activity. */ 5105#define UCM_REG_UCM_UQM_IFEN 0xe000c 5106/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 5107#define UCM_REG_UCM_UQM_USE_Q 0xe00d8 5108/* [RW 6] QM output initial credit. Max credit available - 32.Write writes 5109 the initial credit value; read returns the current value of the credit 5110 counter. Must be initialized to 32 at start-up. */ 5111#define UCM_REG_UQM_INIT_CRD 0xe0220 5112/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 5113 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5114 prioritised); 2 stands for weight 2; tc. */ 5115#define UCM_REG_UQM_P_WEIGHT 0xe00cc 5116/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 5117 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5118 prioritised); 2 stands for weight 2; tc. */ 5119#define UCM_REG_UQM_S_WEIGHT 0xe00d0 5120/* [RW 28] The CM header value for QM request (primary). */ 5121#define UCM_REG_UQM_UCM_HDR_P 0xe0094 5122/* [RW 28] The CM header value for QM request (secondary). */ 5123#define UCM_REG_UQM_UCM_HDR_S 0xe0098 5124/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 5125 acknowledge output is deasserted; all other signals are treated as usual; 5126 if 1 - normal activity. */ 5127#define UCM_REG_UQM_UCM_IFEN 0xe0014 5128/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 5129 acknowledge output is deasserted; all other signals are treated as usual; 5130 if 1 - normal activity. */ 5131#define UCM_REG_USDM_IFEN 0xe0018 5132/* [RC 1] Set when the message length mismatch (relative to last indication) 5133 at the SDM interface is detected. */ 5134#define UCM_REG_USDM_LENGTH_MIS 0xe0158 5135/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 5136 weight 8 (the most prioritised); 1 stands for weight 1(least 5137 prioritised); 2 stands for weight 2; tc. */ 5138#define UCM_REG_USDM_WEIGHT 0xe00c8 5139/* [RW 1] Input xsem Interface enable. If 0 - the valid input is 5140 disregarded; acknowledge output is deasserted; all other signals are 5141 treated as usual; if 1 - normal activity. */ 5142#define UCM_REG_XSEM_IFEN 0xe002c 5143/* [RC 1] Set when the message length mismatch (relative to last indication) 5144 at the xsem interface isdetected. */ 5145#define UCM_REG_XSEM_LENGTH_MIS 0xe0164 5146/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for 5147 weight 8 (the most prioritised); 1 stands for weight 1(least 5148 prioritised); 2 stands for weight 2; tc. */ 5149#define UCM_REG_XSEM_WEIGHT 0xe00bc 5150/* [RW 20] Indirect access to the descriptor table of the XX protection 5151 mechanism. The fields are:[5:0] - message length; 14:6] - message 5152 pointer; 19:15] - next pointer. */ 5153#define UCM_REG_XX_DESCR_TABLE 0xe0280 5154#define UCM_REG_XX_DESCR_TABLE_SIZE 27 5155/* [R 6] Use to read the XX protection Free counter. */ 5156#define UCM_REG_XX_FREE 0xe016c 5157/* [RW 6] Initial value for the credit counter; responsible for fulfilling 5158 of the Input Stage XX protection buffer by the XX protection pending 5159 messages. Write writes the initial credit value; read returns the current 5160 value of the credit counter. Must be initialized to 12 at start-up. */ 5161#define UCM_REG_XX_INIT_CRD 0xe0224 5162/* [RW 6] The maximum number of pending messages; which may be stored in XX 5163 protection. ~ucm_registers_xx_free.xx_free read on read. */ 5164#define UCM_REG_XX_MSG_NUM 0xe0228 5165/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5166#define UCM_REG_XX_OVFL_EVNT_ID 0xe004c 5167/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5168 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] - 5169 header pointer. */ 5170#define UCM_REG_XX_TABLE 0xe0300 5171#define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10) 5172#define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28) 5173#define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15) 5174#define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24) 5175#define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5) 5176#define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8) 5177#define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4) 5178#define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1) 5179#define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13) 5180#define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0) 5181#define UMAC_REG_COMMAND_CONFIG 0x8 5182/* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE 5183 * state from LPI state when it receives packet for transmission. The 5184 * decrement unit is 1 micro-second. */ 5185#define UMAC_REG_EEE_WAKE_TIMER 0x6c 5186/* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers 5187 * to bit 17 of the MAC address etc. */ 5188#define UMAC_REG_MAC_ADDR0 0xc 5189/* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 5190 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. */ 5191#define UMAC_REG_MAC_ADDR1 0x10 5192/* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive 5193 * logic to check frames. */ 5194#define UMAC_REG_MAXFR 0x14 5195#define UMAC_REG_UMAC_EEE_CTRL 0x64 5196#define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3) 5197/* [RW 8] The event id for aggregated interrupt 0 */ 5198#define USDM_REG_AGG_INT_EVENT_0 0xc4038 5199#define USDM_REG_AGG_INT_EVENT_1 0xc403c 5200#define USDM_REG_AGG_INT_EVENT_2 0xc4040 5201#define USDM_REG_AGG_INT_EVENT_4 0xc4048 5202#define USDM_REG_AGG_INT_EVENT_5 0xc404c 5203#define USDM_REG_AGG_INT_EVENT_6 0xc4050 5204/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 5205 or auto-mask-mode (1) */ 5206#define USDM_REG_AGG_INT_MODE_0 0xc41b8 5207#define USDM_REG_AGG_INT_MODE_1 0xc41bc 5208#define USDM_REG_AGG_INT_MODE_4 0xc41c8 5209#define USDM_REG_AGG_INT_MODE_5 0xc41cc 5210#define USDM_REG_AGG_INT_MODE_6 0xc41d0 5211/* [RW 1] The T bit for aggregated interrupt 5 */ 5212#define USDM_REG_AGG_INT_T_5 0xc40cc 5213#define USDM_REG_AGG_INT_T_6 0xc40d0 5214/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 5215#define USDM_REG_CFC_RSP_START_ADDR 0xc4008 5216/* [RW 16] The maximum value of the completion counter #0 */ 5217#define USDM_REG_CMP_COUNTER_MAX0 0xc401c 5218/* [RW 16] The maximum value of the completion counter #1 */ 5219#define USDM_REG_CMP_COUNTER_MAX1 0xc4020 5220/* [RW 16] The maximum value of the completion counter #2 */ 5221#define USDM_REG_CMP_COUNTER_MAX2 0xc4024 5222/* [RW 16] The maximum value of the completion counter #3 */ 5223#define USDM_REG_CMP_COUNTER_MAX3 0xc4028 5224/* [RW 13] The start address in the internal RAM for the completion 5225 counters. */ 5226#define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c 5227#define USDM_REG_ENABLE_IN1 0xc4238 5228#define USDM_REG_ENABLE_IN2 0xc423c 5229#define USDM_REG_ENABLE_OUT1 0xc4240 5230#define USDM_REG_ENABLE_OUT2 0xc4244 5231/* [RW 4] The initial number of messages that can be sent to the pxp control 5232 interface without receiving any ACK. */ 5233#define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0 5234/* [ST 32] The number of ACK after placement messages received */ 5235#define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280 5236/* [ST 32] The number of packet end messages received from the parser */ 5237#define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278 5238/* [ST 32] The number of requests received from the pxp async if */ 5239#define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c 5240/* [ST 32] The number of commands received in queue 0 */ 5241#define USDM_REG_NUM_OF_Q0_CMD 0xc4248 5242/* [ST 32] The number of commands received in queue 10 */ 5243#define USDM_REG_NUM_OF_Q10_CMD 0xc4270 5244/* [ST 32] The number of commands received in queue 11 */ 5245#define USDM_REG_NUM_OF_Q11_CMD 0xc4274 5246/* [ST 32] The number of commands received in queue 1 */ 5247#define USDM_REG_NUM_OF_Q1_CMD 0xc424c 5248/* [ST 32] The number of commands received in queue 2 */ 5249#define USDM_REG_NUM_OF_Q2_CMD 0xc4250 5250/* [ST 32] The number of commands received in queue 3 */ 5251#define USDM_REG_NUM_OF_Q3_CMD 0xc4254 5252/* [ST 32] The number of commands received in queue 4 */ 5253#define USDM_REG_NUM_OF_Q4_CMD 0xc4258 5254/* [ST 32] The number of commands received in queue 5 */ 5255#define USDM_REG_NUM_OF_Q5_CMD 0xc425c 5256/* [ST 32] The number of commands received in queue 6 */ 5257#define USDM_REG_NUM_OF_Q6_CMD 0xc4260 5258/* [ST 32] The number of commands received in queue 7 */ 5259#define USDM_REG_NUM_OF_Q7_CMD 0xc4264 5260/* [ST 32] The number of commands received in queue 8 */ 5261#define USDM_REG_NUM_OF_Q8_CMD 0xc4268 5262/* [ST 32] The number of commands received in queue 9 */ 5263#define USDM_REG_NUM_OF_Q9_CMD 0xc426c 5264/* [RW 13] The start address in the internal RAM for the packet end message */ 5265#define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014 5266/* [RW 13] The start address in the internal RAM for queue counters */ 5267#define USDM_REG_Q_COUNTER_START_ADDR 0xc4010 5268/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5269#define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 5270/* [R 1] parser fifo empty in sdm_sync block */ 5271#define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 5272/* [R 1] parser serial fifo empty in sdm_sync block */ 5273#define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 5274/* [RW 32] Tick for timer counter. Applicable only when 5275 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */ 5276#define USDM_REG_TIMER_TICK 0xc4000 5277/* [RW 32] Interrupt mask register #0 read/write */ 5278#define USDM_REG_USDM_INT_MASK_0 0xc42a0 5279#define USDM_REG_USDM_INT_MASK_1 0xc42b0 5280/* [R 32] Interrupt register #0 read */ 5281#define USDM_REG_USDM_INT_STS_0 0xc4294 5282#define USDM_REG_USDM_INT_STS_1 0xc42a4 5283/* [RW 11] Parity mask register #0 read/write */ 5284#define USDM_REG_USDM_PRTY_MASK 0xc42c0 5285/* [R 11] Parity register #0 read */ 5286#define USDM_REG_USDM_PRTY_STS 0xc42b4 5287/* [RC 11] Parity register #0 read clear */ 5288#define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8 5289/* [RW 5] The number of time_slots in the arbitration cycle */ 5290#define USEM_REG_ARB_CYCLE_SIZE 0x300034 5291/* [RW 3] The source that is associated with arbitration element 0. Source 5292 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5293 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 5294#define USEM_REG_ARB_ELEMENT0 0x300020 5295/* [RW 3] The source that is associated with arbitration element 1. Source 5296 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5297 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5298 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */ 5299#define USEM_REG_ARB_ELEMENT1 0x300024 5300/* [RW 3] The source that is associated with arbitration element 2. Source 5301 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5302 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5303 Could not be equal to register ~usem_registers_arb_element0.arb_element0 5304 and ~usem_registers_arb_element1.arb_element1 */ 5305#define USEM_REG_ARB_ELEMENT2 0x300028 5306/* [RW 3] The source that is associated with arbitration element 3. Source 5307 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5308 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 5309 not be equal to register ~usem_registers_arb_element0.arb_element0 and 5310 ~usem_registers_arb_element1.arb_element1 and 5311 ~usem_registers_arb_element2.arb_element2 */ 5312#define USEM_REG_ARB_ELEMENT3 0x30002c 5313/* [RW 3] The source that is associated with arbitration element 4. Source 5314 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5315 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5316 Could not be equal to register ~usem_registers_arb_element0.arb_element0 5317 and ~usem_registers_arb_element1.arb_element1 and 5318 ~usem_registers_arb_element2.arb_element2 and 5319 ~usem_registers_arb_element3.arb_element3 */ 5320#define USEM_REG_ARB_ELEMENT4 0x300030 5321#define USEM_REG_ENABLE_IN 0x3000a4 5322#define USEM_REG_ENABLE_OUT 0x3000a8 5323/* [RW 32] This address space contains all registers and memories that are 5324 placed in SEM_FAST block. The SEM_FAST registers are described in 5325 appendix B. In order to access the sem_fast registers the base address 5326 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 5327#define USEM_REG_FAST_MEMORY 0x320000 5328/* [RW 1] Disables input messages from FIC0 May be updated during run_time 5329 by the microcode */ 5330#define USEM_REG_FIC0_DISABLE 0x300224 5331/* [RW 1] Disables input messages from FIC1 May be updated during run_time 5332 by the microcode */ 5333#define USEM_REG_FIC1_DISABLE 0x300234 5334/* [RW 15] Interrupt table Read and write access to it is not possible in 5335 the middle of the work */ 5336#define USEM_REG_INT_TABLE 0x300400 5337/* [ST 24] Statistics register. The number of messages that entered through 5338 FIC0 */ 5339#define USEM_REG_MSG_NUM_FIC0 0x300000 5340/* [ST 24] Statistics register. The number of messages that entered through 5341 FIC1 */ 5342#define USEM_REG_MSG_NUM_FIC1 0x300004 5343/* [ST 24] Statistics register. The number of messages that were sent to 5344 FOC0 */ 5345#define USEM_REG_MSG_NUM_FOC0 0x300008 5346/* [ST 24] Statistics register. The number of messages that were sent to 5347 FOC1 */ 5348#define USEM_REG_MSG_NUM_FOC1 0x30000c 5349/* [ST 24] Statistics register. The number of messages that were sent to 5350 FOC2 */ 5351#define USEM_REG_MSG_NUM_FOC2 0x300010 5352/* [ST 24] Statistics register. The number of messages that were sent to 5353 FOC3 */ 5354#define USEM_REG_MSG_NUM_FOC3 0x300014 5355/* [RW 1] Disables input messages from the passive buffer May be updated 5356 during run_time by the microcode */ 5357#define USEM_REG_PAS_DISABLE 0x30024c 5358/* [WB 128] Debug only. Passive buffer memory */ 5359#define USEM_REG_PASSIVE_BUFFER 0x302000 5360/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5361#define USEM_REG_PRAM 0x340000 5362/* [R 16] Valid sleeping threads indication have bit per thread */ 5363#define USEM_REG_SLEEP_THREADS_VALID 0x30026c 5364/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5365#define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 5366/* [RW 16] List of free threads . There is a bit per thread. */ 5367#define USEM_REG_THREADS_LIST 0x3002e4 5368/* [RW 3] The arbitration scheme of time_slot 0 */ 5369#define USEM_REG_TS_0_AS 0x300038 5370/* [RW 3] The arbitration scheme of time_slot 10 */ 5371#define USEM_REG_TS_10_AS 0x300060 5372/* [RW 3] The arbitration scheme of time_slot 11 */ 5373#define USEM_REG_TS_11_AS 0x300064 5374/* [RW 3] The arbitration scheme of time_slot 12 */ 5375#define USEM_REG_TS_12_AS 0x300068 5376/* [RW 3] The arbitration scheme of time_slot 13 */ 5377#define USEM_REG_TS_13_AS 0x30006c 5378/* [RW 3] The arbitration scheme of time_slot 14 */ 5379#define USEM_REG_TS_14_AS 0x300070 5380/* [RW 3] The arbitration scheme of time_slot 15 */ 5381#define USEM_REG_TS_15_AS 0x300074 5382/* [RW 3] The arbitration scheme of time_slot 16 */ 5383#define USEM_REG_TS_16_AS 0x300078 5384/* [RW 3] The arbitration scheme of time_slot 17 */ 5385#define USEM_REG_TS_17_AS 0x30007c 5386/* [RW 3] The arbitration scheme of time_slot 18 */ 5387#define USEM_REG_TS_18_AS 0x300080 5388/* [RW 3] The arbitration scheme of time_slot 1 */ 5389#define USEM_REG_TS_1_AS 0x30003c 5390/* [RW 3] The arbitration scheme of time_slot 2 */ 5391#define USEM_REG_TS_2_AS 0x300040 5392/* [RW 3] The arbitration scheme of time_slot 3 */ 5393#define USEM_REG_TS_3_AS 0x300044 5394/* [RW 3] The arbitration scheme of time_slot 4 */ 5395#define USEM_REG_TS_4_AS 0x300048 5396/* [RW 3] The arbitration scheme of time_slot 5 */ 5397#define USEM_REG_TS_5_AS 0x30004c 5398/* [RW 3] The arbitration scheme of time_slot 6 */ 5399#define USEM_REG_TS_6_AS 0x300050 5400/* [RW 3] The arbitration scheme of time_slot 7 */ 5401#define USEM_REG_TS_7_AS 0x300054 5402/* [RW 3] The arbitration scheme of time_slot 8 */ 5403#define USEM_REG_TS_8_AS 0x300058 5404/* [RW 3] The arbitration scheme of time_slot 9 */ 5405#define USEM_REG_TS_9_AS 0x30005c 5406/* [RW 32] Interrupt mask register #0 read/write */ 5407#define USEM_REG_USEM_INT_MASK_0 0x300110 5408#define USEM_REG_USEM_INT_MASK_1 0x300120 5409/* [R 32] Interrupt register #0 read */ 5410#define USEM_REG_USEM_INT_STS_0 0x300104 5411#define USEM_REG_USEM_INT_STS_1 0x300114 5412/* [RW 32] Parity mask register #0 read/write */ 5413#define USEM_REG_USEM_PRTY_MASK_0 0x300130 5414#define USEM_REG_USEM_PRTY_MASK_1 0x300140 5415/* [R 32] Parity register #0 read */ 5416#define USEM_REG_USEM_PRTY_STS_0 0x300124 5417#define USEM_REG_USEM_PRTY_STS_1 0x300134 5418/* [RC 32] Parity register #0 read clear */ 5419#define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128 5420#define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138 5421/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5422 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5423#define USEM_REG_VFPF_ERR_NUM 0x300380 5424#define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0) 5425#define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1) 5426#define VFC_REG_MEMORIES_RST 0x1943c 5427/* [RW 32] Indirect access to AG context with 32-bits granularity. The bits 5428 * [12:8] of the address should be the offset within the accessed LCID 5429 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10 5430 * LCID100. The RBC address should be 13'ha64. */ 5431#define XCM_REG_AG_CTX 0x28000 5432/* [RW 2] The queue index for registration on Aux1 counter flag. */ 5433#define XCM_REG_AUX1_Q 0x20134 5434/* [RW 2] Per each decision rule the queue index to register to. */ 5435#define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0 5436/* [R 5] Used to read the XX protection CAM occupancy counter. */ 5437#define XCM_REG_CAM_OCCUP 0x20244 5438/* [RW 1] CDU AG read Interface enable. If 0 - the request input is 5439 disregarded; valid output is deasserted; all other signals are treated as 5440 usual; if 1 - normal activity. */ 5441#define XCM_REG_CDU_AG_RD_IFEN 0x20044 5442/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input 5443 are disregarded; all other signals are treated as usual; if 1 - normal 5444 activity. */ 5445#define XCM_REG_CDU_AG_WR_IFEN 0x20040 5446/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is 5447 disregarded; valid output is deasserted; all other signals are treated as 5448 usual; if 1 - normal activity. */ 5449#define XCM_REG_CDU_SM_RD_IFEN 0x2004c 5450/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid 5451 input is disregarded; all other signals are treated as usual; if 1 - 5452 normal activity. */ 5453#define XCM_REG_CDU_SM_WR_IFEN 0x20048 5454/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 5455 the initial credit value; read returns the current value of the credit 5456 counter. Must be initialized to 1 at start-up. */ 5457#define XCM_REG_CFC_INIT_CRD 0x20404 5458/* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for 5459 weight 8 (the most prioritised); 1 stands for weight 1(least 5460 prioritised); 2 stands for weight 2; tc. */ 5461#define XCM_REG_CP_WEIGHT 0x200dc 5462/* [RW 1] Input csem Interface enable. If 0 - the valid input is 5463 disregarded; acknowledge output is deasserted; all other signals are 5464 treated as usual; if 1 - normal activity. */ 5465#define XCM_REG_CSEM_IFEN 0x20028 5466/* [RC 1] Set at message length mismatch (relative to last indication) at 5467 the csem interface. */ 5468#define XCM_REG_CSEM_LENGTH_MIS 0x20228 5469/* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for 5470 weight 8 (the most prioritised); 1 stands for weight 1(least 5471 prioritised); 2 stands for weight 2; tc. */ 5472#define XCM_REG_CSEM_WEIGHT 0x200c4 5473/* [RW 1] Input dorq Interface enable. If 0 - the valid input is 5474 disregarded; acknowledge output is deasserted; all other signals are 5475 treated as usual; if 1 - normal activity. */ 5476#define XCM_REG_DORQ_IFEN 0x20030 5477/* [RC 1] Set at message length mismatch (relative to last indication) at 5478 the dorq interface. */ 5479#define XCM_REG_DORQ_LENGTH_MIS 0x20230 5480/* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for 5481 weight 8 (the most prioritised); 1 stands for weight 1(least 5482 prioritised); 2 stands for weight 2; tc. */ 5483#define XCM_REG_DORQ_WEIGHT 0x200cc 5484/* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */ 5485#define XCM_REG_ERR_EVNT_ID 0x200b0 5486/* [RW 28] The CM erroneous header for QM and Timers formatting. */ 5487#define XCM_REG_ERR_XCM_HDR 0x200ac 5488/* [RW 8] The Event ID for Timers expiration. */ 5489#define XCM_REG_EXPR_EVNT_ID 0x200b4 5490/* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 5491 writes the initial credit value; read returns the current value of the 5492 credit counter. Must be initialized to 64 at start-up. */ 5493#define XCM_REG_FIC0_INIT_CRD 0x2040c 5494/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 5495 writes the initial credit value; read returns the current value of the 5496 credit counter. Must be initialized to 64 at start-up. */ 5497#define XCM_REG_FIC1_INIT_CRD 0x20410 5498#define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 5499#define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c 5500#define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108 5501#define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c 5502/* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1 5503 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr; 5504 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and 5505 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */ 5506#define XCM_REG_GR_ARB_TYPE 0x2020c 5507/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the 5508 highest priority is 3. It is supposed that the Channel group is the 5509 compliment of the other 3 groups. */ 5510#define XCM_REG_GR_LD0_PR 0x20214 5511/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the 5512 highest priority is 3. It is supposed that the Channel group is the 5513 compliment of the other 3 groups. */ 5514#define XCM_REG_GR_LD1_PR 0x20218 5515/* [RW 1] Input nig0 Interface enable. If 0 - the valid input is 5516 disregarded; acknowledge output is deasserted; all other signals are 5517 treated as usual; if 1 - normal activity. */ 5518#define XCM_REG_NIG0_IFEN 0x20038 5519/* [RC 1] Set at message length mismatch (relative to last indication) at 5520 the nig0 interface. */ 5521#define XCM_REG_NIG0_LENGTH_MIS 0x20238 5522/* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for 5523 weight 8 (the most prioritised); 1 stands for weight 1(least 5524 prioritised); 2 stands for weight 2; tc. */ 5525#define XCM_REG_NIG0_WEIGHT 0x200d4 5526/* [RW 1] Input nig1 Interface enable. If 0 - the valid input is 5527 disregarded; acknowledge output is deasserted; all other signals are 5528 treated as usual; if 1 - normal activity. */ 5529#define XCM_REG_NIG1_IFEN 0x2003c 5530/* [RC 1] Set at message length mismatch (relative to last indication) at 5531 the nig1 interface. */ 5532#define XCM_REG_NIG1_LENGTH_MIS 0x2023c 5533/* [RW 5] The number of double REG-pairs; loaded from the STORM context and 5534 sent to STORM; for a specific connection type. The double REG-pairs are 5535 used in order to align to STORM context row size of 128 bits. The offset 5536 of these data in the STORM context is always 0. Index _i stands for the 5537 connection type (one of 16). */ 5538#define XCM_REG_N_SM_CTX_LD_0 0x20060 5539#define XCM_REG_N_SM_CTX_LD_1 0x20064 5540#define XCM_REG_N_SM_CTX_LD_2 0x20068 5541#define XCM_REG_N_SM_CTX_LD_3 0x2006c 5542#define XCM_REG_N_SM_CTX_LD_4 0x20070 5543#define XCM_REG_N_SM_CTX_LD_5 0x20074 5544/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded; 5545 acknowledge output is deasserted; all other signals are treated as usual; 5546 if 1 - normal activity. */ 5547#define XCM_REG_PBF_IFEN 0x20034 5548/* [RC 1] Set at message length mismatch (relative to last indication) at 5549 the pbf interface. */ 5550#define XCM_REG_PBF_LENGTH_MIS 0x20234 5551/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for 5552 weight 8 (the most prioritised); 1 stands for weight 1(least 5553 prioritised); 2 stands for weight 2; tc. */ 5554#define XCM_REG_PBF_WEIGHT 0x200d0 5555#define XCM_REG_PHYS_QNUM3_0 0x20100 5556#define XCM_REG_PHYS_QNUM3_1 0x20104 5557/* [RW 8] The Event ID for Timers formatting in case of stop done. */ 5558#define XCM_REG_STOP_EVNT_ID 0x200b8 5559/* [RC 1] Set at message length mismatch (relative to last indication) at 5560 the STORM interface. */ 5561#define XCM_REG_STORM_LENGTH_MIS 0x2021c 5562/* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for 5563 weight 8 (the most prioritised); 1 stands for weight 1(least 5564 prioritised); 2 stands for weight 2; tc. */ 5565#define XCM_REG_STORM_WEIGHT 0x200bc 5566/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is 5567 disregarded; acknowledge output is deasserted; all other signals are 5568 treated as usual; if 1 - normal activity. */ 5569#define XCM_REG_STORM_XCM_IFEN 0x20010 5570/* [RW 4] Timers output initial credit. Max credit available - 15.Write 5571 writes the initial credit value; read returns the current value of the 5572 credit counter. Must be initialized to 4 at start-up. */ 5573#define XCM_REG_TM_INIT_CRD 0x2041c 5574/* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for 5575 weight 8 (the most prioritised); 1 stands for weight 1(least 5576 prioritised); 2 stands for weight 2; tc. */ 5577#define XCM_REG_TM_WEIGHT 0x200ec 5578/* [RW 28] The CM header for Timers expiration command. */ 5579#define XCM_REG_TM_XCM_HDR 0x200a8 5580/* [RW 1] Timers - CM Interface enable. If 0 - the valid input is 5581 disregarded; acknowledge output is deasserted; all other signals are 5582 treated as usual; if 1 - normal activity. */ 5583#define XCM_REG_TM_XCM_IFEN 0x2001c 5584/* [RW 1] Input tsem Interface enable. If 0 - the valid input is 5585 disregarded; acknowledge output is deasserted; all other signals are 5586 treated as usual; if 1 - normal activity. */ 5587#define XCM_REG_TSEM_IFEN 0x20024 5588/* [RC 1] Set at message length mismatch (relative to last indication) at 5589 the tsem interface. */ 5590#define XCM_REG_TSEM_LENGTH_MIS 0x20224 5591/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for 5592 weight 8 (the most prioritised); 1 stands for weight 1(least 5593 prioritised); 2 stands for weight 2; tc. */ 5594#define XCM_REG_TSEM_WEIGHT 0x200c0 5595/* [RW 2] The queue index for registration on UNA greater NXT decision rule. */ 5596#define XCM_REG_UNA_GT_NXT_Q 0x20120 5597/* [RW 1] Input usem Interface enable. If 0 - the valid input is 5598 disregarded; acknowledge output is deasserted; all other signals are 5599 treated as usual; if 1 - normal activity. */ 5600#define XCM_REG_USEM_IFEN 0x2002c 5601/* [RC 1] Message length mismatch (relative to last indication) at the usem 5602 interface. */ 5603#define XCM_REG_USEM_LENGTH_MIS 0x2022c 5604/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for 5605 weight 8 (the most prioritised); 1 stands for weight 1(least 5606 prioritised); 2 stands for weight 2; tc. */ 5607#define XCM_REG_USEM_WEIGHT 0x200c8 5608#define XCM_REG_WU_DA_CNT_CMD00 0x201d4 5609#define XCM_REG_WU_DA_CNT_CMD01 0x201d8 5610#define XCM_REG_WU_DA_CNT_CMD10 0x201dc 5611#define XCM_REG_WU_DA_CNT_CMD11 0x201e0 5612#define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4 5613#define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8 5614#define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec 5615#define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0 5616#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 5617#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8 5618#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc 5619#define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0 5620/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded; 5621 acknowledge output is deasserted; all other signals are treated as usual; 5622 if 1 - normal activity. */ 5623#define XCM_REG_XCM_CFC_IFEN 0x20050 5624/* [RW 14] Interrupt mask register #0 read/write */ 5625#define XCM_REG_XCM_INT_MASK 0x202b4 5626/* [R 14] Interrupt register #0 read */ 5627#define XCM_REG_XCM_INT_STS 0x202a8 5628/* [RW 30] Parity mask register #0 read/write */ 5629#define XCM_REG_XCM_PRTY_MASK 0x202c4 5630/* [R 30] Parity register #0 read */ 5631#define XCM_REG_XCM_PRTY_STS 0x202b8 5632/* [RC 30] Parity register #0 read clear */ 5633#define XCM_REG_XCM_PRTY_STS_CLR 0x202bc 5634 5635/* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS 5636 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5). 5637 Is used to determine the number of the AG context REG-pairs written back; 5638 when the Reg1WbFlg isn't set. */ 5639#define XCM_REG_XCM_REG0_SZ 0x200f4 5640/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is 5641 disregarded; valid is deasserted; all other signals are treated as usual; 5642 if 1 - normal activity. */ 5643#define XCM_REG_XCM_STORM0_IFEN 0x20004 5644/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is 5645 disregarded; valid is deasserted; all other signals are treated as usual; 5646 if 1 - normal activity. */ 5647#define XCM_REG_XCM_STORM1_IFEN 0x20008 5648/* [RW 1] CM - Timers Interface enable. If 0 - the valid input is 5649 disregarded; acknowledge output is deasserted; all other signals are 5650 treated as usual; if 1 - normal activity. */ 5651#define XCM_REG_XCM_TM_IFEN 0x20020 5652/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is 5653 disregarded; valid is deasserted; all other signals are treated as usual; 5654 if 1 - normal activity. */ 5655#define XCM_REG_XCM_XQM_IFEN 0x2000c 5656/* [RW 1] If set the Q index; received from the QM is inserted to event ID. */ 5657#define XCM_REG_XCM_XQM_USE_Q 0x200f0 5658/* [RW 4] The value by which CFC updates the activity counter at QM bypass. */ 5659#define XCM_REG_XQM_BYP_ACT_UPD 0x200fc 5660/* [RW 6] QM output initial credit. Max credit available - 32.Write writes 5661 the initial credit value; read returns the current value of the credit 5662 counter. Must be initialized to 32 at start-up. */ 5663#define XCM_REG_XQM_INIT_CRD 0x20420 5664/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0 5665 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5666 prioritised); 2 stands for weight 2; tc. */ 5667#define XCM_REG_XQM_P_WEIGHT 0x200e4 5668/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0 5669 stands for weight 8 (the most prioritised); 1 stands for weight 1(least 5670 prioritised); 2 stands for weight 2; tc. */ 5671#define XCM_REG_XQM_S_WEIGHT 0x200e8 5672/* [RW 28] The CM header value for QM request (primary). */ 5673#define XCM_REG_XQM_XCM_HDR_P 0x200a0 5674/* [RW 28] The CM header value for QM request (secondary). */ 5675#define XCM_REG_XQM_XCM_HDR_S 0x200a4 5676/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded; 5677 acknowledge output is deasserted; all other signals are treated as usual; 5678 if 1 - normal activity. */ 5679#define XCM_REG_XQM_XCM_IFEN 0x20014 5680/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded; 5681 acknowledge output is deasserted; all other signals are treated as usual; 5682 if 1 - normal activity. */ 5683#define XCM_REG_XSDM_IFEN 0x20018 5684/* [RC 1] Set at message length mismatch (relative to last indication) at 5685 the SDM interface. */ 5686#define XCM_REG_XSDM_LENGTH_MIS 0x20220 5687/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for 5688 weight 8 (the most prioritised); 1 stands for weight 1(least 5689 prioritised); 2 stands for weight 2; tc. */ 5690#define XCM_REG_XSDM_WEIGHT 0x200e0 5691/* [RW 17] Indirect access to the descriptor table of the XX protection 5692 mechanism. The fields are: [5:0] - message length; 11:6] - message 5693 pointer; 16:12] - next pointer. */ 5694#define XCM_REG_XX_DESCR_TABLE 0x20480 5695#define XCM_REG_XX_DESCR_TABLE_SIZE 32 5696/* [R 6] Used to read the XX protection Free counter. */ 5697#define XCM_REG_XX_FREE 0x20240 5698/* [RW 6] Initial value for the credit counter; responsible for fulfilling 5699 of the Input Stage XX protection buffer by the XX protection pending 5700 messages. Max credit available - 3.Write writes the initial credit value; 5701 read returns the current value of the credit counter. Must be initialized 5702 to 2 at start-up. */ 5703#define XCM_REG_XX_INIT_CRD 0x20424 5704/* [RW 6] The maximum number of pending messages; which may be stored in XX 5705 protection. ~xcm_registers_xx_free.xx_free read on read. */ 5706#define XCM_REG_XX_MSG_NUM 0x20428 5707/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */ 5708#define XCM_REG_XX_OVFL_EVNT_ID 0x20058 5709#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0) 5710#define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1) 5711#define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2) 5712#define XMAC_CTRL_REG_RX_EN (0x1<<1) 5713#define XMAC_CTRL_REG_SOFT_RESET (0x1<<6) 5714#define XMAC_CTRL_REG_TX_EN (0x1<<0) 5715#define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7) 5716#define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18) 5717#define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17) 5718#define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1) 5719#define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0) 5720#define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3) 5721#define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4) 5722#define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5) 5723#define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60 5724#define XMAC_REG_CTRL 0 5725/* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5726 * packets transmitted by the MAC */ 5727#define XMAC_REG_CTRL_SA_HI 0x2c 5728/* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 5729 * packets transmitted by the MAC */ 5730#define XMAC_REG_CTRL_SA_LO 0x28 5731#define XMAC_REG_EEE_CTRL 0xd8 5732#define XMAC_REG_EEE_TIMERS_HI 0xe4 5733#define XMAC_REG_PAUSE_CTRL 0x68 5734#define XMAC_REG_PFC_CTRL 0x70 5735#define XMAC_REG_PFC_CTRL_HI 0x74 5736#define XMAC_REG_RX_LSS_CTRL 0x50 5737#define XMAC_REG_RX_LSS_STATUS 0x58 5738/* [RW 14] Maximum packet size in receive direction; exclusive of preamble & 5739 * CRC in strip mode */ 5740#define XMAC_REG_RX_MAX_SIZE 0x40 5741#define XMAC_REG_TX_CTRL 0x20 5742#define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0) 5743#define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1) 5744/* [RW 16] Indirect access to the XX table of the XX protection mechanism. 5745 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] - 5746 header pointer. */ 5747#define XCM_REG_XX_TABLE 0x20500 5748/* [RW 8] The event id for aggregated interrupt 0 */ 5749#define XSDM_REG_AGG_INT_EVENT_0 0x166038 5750#define XSDM_REG_AGG_INT_EVENT_1 0x16603c 5751#define XSDM_REG_AGG_INT_EVENT_10 0x166060 5752#define XSDM_REG_AGG_INT_EVENT_11 0x166064 5753#define XSDM_REG_AGG_INT_EVENT_12 0x166068 5754#define XSDM_REG_AGG_INT_EVENT_13 0x16606c 5755#define XSDM_REG_AGG_INT_EVENT_14 0x166070 5756#define XSDM_REG_AGG_INT_EVENT_2 0x166040 5757#define XSDM_REG_AGG_INT_EVENT_3 0x166044 5758#define XSDM_REG_AGG_INT_EVENT_4 0x166048 5759#define XSDM_REG_AGG_INT_EVENT_5 0x16604c 5760#define XSDM_REG_AGG_INT_EVENT_6 0x166050 5761#define XSDM_REG_AGG_INT_EVENT_7 0x166054 5762#define XSDM_REG_AGG_INT_EVENT_8 0x166058 5763#define XSDM_REG_AGG_INT_EVENT_9 0x16605c 5764/* [RW 1] For each aggregated interrupt index whether the mode is normal (0) 5765 or auto-mask-mode (1) */ 5766#define XSDM_REG_AGG_INT_MODE_0 0x1661b8 5767#define XSDM_REG_AGG_INT_MODE_1 0x1661bc 5768/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */ 5769#define XSDM_REG_CFC_RSP_START_ADDR 0x166008 5770/* [RW 16] The maximum value of the completion counter #0 */ 5771#define XSDM_REG_CMP_COUNTER_MAX0 0x16601c 5772/* [RW 16] The maximum value of the completion counter #1 */ 5773#define XSDM_REG_CMP_COUNTER_MAX1 0x166020 5774/* [RW 16] The maximum value of the completion counter #2 */ 5775#define XSDM_REG_CMP_COUNTER_MAX2 0x166024 5776/* [RW 16] The maximum value of the completion counter #3 */ 5777#define XSDM_REG_CMP_COUNTER_MAX3 0x166028 5778/* [RW 13] The start address in the internal RAM for the completion 5779 counters. */ 5780#define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c 5781#define XSDM_REG_ENABLE_IN1 0x166238 5782#define XSDM_REG_ENABLE_IN2 0x16623c 5783#define XSDM_REG_ENABLE_OUT1 0x166240 5784#define XSDM_REG_ENABLE_OUT2 0x166244 5785/* [RW 4] The initial number of messages that can be sent to the pxp control 5786 interface without receiving any ACK. */ 5787#define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc 5788/* [ST 32] The number of ACK after placement messages received */ 5789#define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c 5790/* [ST 32] The number of packet end messages received from the parser */ 5791#define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274 5792/* [ST 32] The number of requests received from the pxp async if */ 5793#define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278 5794/* [ST 32] The number of commands received in queue 0 */ 5795#define XSDM_REG_NUM_OF_Q0_CMD 0x166248 5796/* [ST 32] The number of commands received in queue 10 */ 5797#define XSDM_REG_NUM_OF_Q10_CMD 0x16626c 5798/* [ST 32] The number of commands received in queue 11 */ 5799#define XSDM_REG_NUM_OF_Q11_CMD 0x166270 5800/* [ST 32] The number of commands received in queue 1 */ 5801#define XSDM_REG_NUM_OF_Q1_CMD 0x16624c 5802/* [ST 32] The number of commands received in queue 3 */ 5803#define XSDM_REG_NUM_OF_Q3_CMD 0x166250 5804/* [ST 32] The number of commands received in queue 4 */ 5805#define XSDM_REG_NUM_OF_Q4_CMD 0x166254 5806/* [ST 32] The number of commands received in queue 5 */ 5807#define XSDM_REG_NUM_OF_Q5_CMD 0x166258 5808/* [ST 32] The number of commands received in queue 6 */ 5809#define XSDM_REG_NUM_OF_Q6_CMD 0x16625c 5810/* [ST 32] The number of commands received in queue 7 */ 5811#define XSDM_REG_NUM_OF_Q7_CMD 0x166260 5812/* [ST 32] The number of commands received in queue 8 */ 5813#define XSDM_REG_NUM_OF_Q8_CMD 0x166264 5814/* [ST 32] The number of commands received in queue 9 */ 5815#define XSDM_REG_NUM_OF_Q9_CMD 0x166268 5816/* [RW 13] The start address in the internal RAM for queue counters */ 5817#define XSDM_REG_Q_COUNTER_START_ADDR 0x166010 5818/* [W 17] Generate an operation after completion; bit-16 is 5819 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and 5820 * bits 4:0 are the T124Param[4:0] */ 5821#define XSDM_REG_OPERATION_GEN 0x1664c4 5822/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 5823#define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 5824/* [R 1] parser fifo empty in sdm_sync block */ 5825#define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 5826/* [R 1] parser serial fifo empty in sdm_sync block */ 5827#define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 5828/* [RW 32] Tick for timer counter. Applicable only when 5829 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */ 5830#define XSDM_REG_TIMER_TICK 0x166000 5831/* [RW 32] Interrupt mask register #0 read/write */ 5832#define XSDM_REG_XSDM_INT_MASK_0 0x16629c 5833#define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 5834/* [R 32] Interrupt register #0 read */ 5835#define XSDM_REG_XSDM_INT_STS_0 0x166290 5836#define XSDM_REG_XSDM_INT_STS_1 0x1662a0 5837/* [RW 11] Parity mask register #0 read/write */ 5838#define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 5839/* [R 11] Parity register #0 read */ 5840#define XSDM_REG_XSDM_PRTY_STS 0x1662b0 5841/* [RC 11] Parity register #0 read clear */ 5842#define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4 5843/* [RW 5] The number of time_slots in the arbitration cycle */ 5844#define XSEM_REG_ARB_CYCLE_SIZE 0x280034 5845/* [RW 3] The source that is associated with arbitration element 0. Source 5846 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5847 sleeping thread with priority 1; 4- sleeping thread with priority 2 */ 5848#define XSEM_REG_ARB_ELEMENT0 0x280020 5849/* [RW 3] The source that is associated with arbitration element 1. Source 5850 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5851 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5852 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */ 5853#define XSEM_REG_ARB_ELEMENT1 0x280024 5854/* [RW 3] The source that is associated with arbitration element 2. Source 5855 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5856 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5857 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5858 and ~xsem_registers_arb_element1.arb_element1 */ 5859#define XSEM_REG_ARB_ELEMENT2 0x280028 5860/* [RW 3] The source that is associated with arbitration element 3. Source 5861 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5862 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could 5863 not be equal to register ~xsem_registers_arb_element0.arb_element0 and 5864 ~xsem_registers_arb_element1.arb_element1 and 5865 ~xsem_registers_arb_element2.arb_element2 */ 5866#define XSEM_REG_ARB_ELEMENT3 0x28002c 5867/* [RW 3] The source that is associated with arbitration element 4. Source 5868 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3- 5869 sleeping thread with priority 1; 4- sleeping thread with priority 2. 5870 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 5871 and ~xsem_registers_arb_element1.arb_element1 and 5872 ~xsem_registers_arb_element2.arb_element2 and 5873 ~xsem_registers_arb_element3.arb_element3 */ 5874#define XSEM_REG_ARB_ELEMENT4 0x280030 5875#define XSEM_REG_ENABLE_IN 0x2800a4 5876#define XSEM_REG_ENABLE_OUT 0x2800a8 5877/* [RW 32] This address space contains all registers and memories that are 5878 placed in SEM_FAST block. The SEM_FAST registers are described in 5879 appendix B. In order to access the sem_fast registers the base address 5880 ~fast_memory.fast_memory should be added to eachsem_fast register offset. */ 5881#define XSEM_REG_FAST_MEMORY 0x2a0000 5882/* [RW 1] Disables input messages from FIC0 May be updated during run_time 5883 by the microcode */ 5884#define XSEM_REG_FIC0_DISABLE 0x280224 5885/* [RW 1] Disables input messages from FIC1 May be updated during run_time 5886 by the microcode */ 5887#define XSEM_REG_FIC1_DISABLE 0x280234 5888/* [RW 15] Interrupt table Read and write access to it is not possible in 5889 the middle of the work */ 5890#define XSEM_REG_INT_TABLE 0x280400 5891/* [ST 24] Statistics register. The number of messages that entered through 5892 FIC0 */ 5893#define XSEM_REG_MSG_NUM_FIC0 0x280000 5894/* [ST 24] Statistics register. The number of messages that entered through 5895 FIC1 */ 5896#define XSEM_REG_MSG_NUM_FIC1 0x280004 5897/* [ST 24] Statistics register. The number of messages that were sent to 5898 FOC0 */ 5899#define XSEM_REG_MSG_NUM_FOC0 0x280008 5900/* [ST 24] Statistics register. The number of messages that were sent to 5901 FOC1 */ 5902#define XSEM_REG_MSG_NUM_FOC1 0x28000c 5903/* [ST 24] Statistics register. The number of messages that were sent to 5904 FOC2 */ 5905#define XSEM_REG_MSG_NUM_FOC2 0x280010 5906/* [ST 24] Statistics register. The number of messages that were sent to 5907 FOC3 */ 5908#define XSEM_REG_MSG_NUM_FOC3 0x280014 5909/* [RW 1] Disables input messages from the passive buffer May be updated 5910 during run_time by the microcode */ 5911#define XSEM_REG_PAS_DISABLE 0x28024c 5912/* [WB 128] Debug only. Passive buffer memory */ 5913#define XSEM_REG_PASSIVE_BUFFER 0x282000 5914/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 5915#define XSEM_REG_PRAM 0x2c0000 5916/* [R 16] Valid sleeping threads indication have bit per thread */ 5917#define XSEM_REG_SLEEP_THREADS_VALID 0x28026c 5918/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 5919#define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 5920/* [RW 16] List of free threads . There is a bit per thread. */ 5921#define XSEM_REG_THREADS_LIST 0x2802e4 5922/* [RW 3] The arbitration scheme of time_slot 0 */ 5923#define XSEM_REG_TS_0_AS 0x280038 5924/* [RW 3] The arbitration scheme of time_slot 10 */ 5925#define XSEM_REG_TS_10_AS 0x280060 5926/* [RW 3] The arbitration scheme of time_slot 11 */ 5927#define XSEM_REG_TS_11_AS 0x280064 5928/* [RW 3] The arbitration scheme of time_slot 12 */ 5929#define XSEM_REG_TS_12_AS 0x280068 5930/* [RW 3] The arbitration scheme of time_slot 13 */ 5931#define XSEM_REG_TS_13_AS 0x28006c 5932/* [RW 3] The arbitration scheme of time_slot 14 */ 5933#define XSEM_REG_TS_14_AS 0x280070 5934/* [RW 3] The arbitration scheme of time_slot 15 */ 5935#define XSEM_REG_TS_15_AS 0x280074 5936/* [RW 3] The arbitration scheme of time_slot 16 */ 5937#define XSEM_REG_TS_16_AS 0x280078 5938/* [RW 3] The arbitration scheme of time_slot 17 */ 5939#define XSEM_REG_TS_17_AS 0x28007c 5940/* [RW 3] The arbitration scheme of time_slot 18 */ 5941#define XSEM_REG_TS_18_AS 0x280080 5942/* [RW 3] The arbitration scheme of time_slot 1 */ 5943#define XSEM_REG_TS_1_AS 0x28003c 5944/* [RW 3] The arbitration scheme of time_slot 2 */ 5945#define XSEM_REG_TS_2_AS 0x280040 5946/* [RW 3] The arbitration scheme of time_slot 3 */ 5947#define XSEM_REG_TS_3_AS 0x280044 5948/* [RW 3] The arbitration scheme of time_slot 4 */ 5949#define XSEM_REG_TS_4_AS 0x280048 5950/* [RW 3] The arbitration scheme of time_slot 5 */ 5951#define XSEM_REG_TS_5_AS 0x28004c 5952/* [RW 3] The arbitration scheme of time_slot 6 */ 5953#define XSEM_REG_TS_6_AS 0x280050 5954/* [RW 3] The arbitration scheme of time_slot 7 */ 5955#define XSEM_REG_TS_7_AS 0x280054 5956/* [RW 3] The arbitration scheme of time_slot 8 */ 5957#define XSEM_REG_TS_8_AS 0x280058 5958/* [RW 3] The arbitration scheme of time_slot 9 */ 5959#define XSEM_REG_TS_9_AS 0x28005c 5960/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 5961 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */ 5962#define XSEM_REG_VFPF_ERR_NUM 0x280380 5963/* [RW 32] Interrupt mask register #0 read/write */ 5964#define XSEM_REG_XSEM_INT_MASK_0 0x280110 5965#define XSEM_REG_XSEM_INT_MASK_1 0x280120 5966/* [R 32] Interrupt register #0 read */ 5967#define XSEM_REG_XSEM_INT_STS_0 0x280104 5968#define XSEM_REG_XSEM_INT_STS_1 0x280114 5969/* [RW 32] Parity mask register #0 read/write */ 5970#define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 5971#define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 5972/* [R 32] Parity register #0 read */ 5973#define XSEM_REG_XSEM_PRTY_STS_0 0x280124 5974#define XSEM_REG_XSEM_PRTY_STS_1 0x280134 5975/* [RC 32] Parity register #0 read clear */ 5976#define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128 5977#define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138 5978#define MCPR_ACCESS_LOCK_LOCK (1L<<31) 5979#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0) 5980#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1) 5981#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) 5982#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0) 5983#define MCPR_NVM_COMMAND_DOIT (1L<<4) 5984#define MCPR_NVM_COMMAND_DONE (1L<<3) 5985#define MCPR_NVM_COMMAND_FIRST (1L<<7) 5986#define MCPR_NVM_COMMAND_LAST (1L<<8) 5987#define MCPR_NVM_COMMAND_WR (1L<<5) 5988#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9) 5989#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) 5990#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) 5991#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) 5992#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 5993#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) 5994#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3) 5995#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3) 5996#define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3) 5997#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3) 5998#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3) 5999#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3) 6000#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) 6001#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) 6002#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) 6003#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) 6004#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3) 6005#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3) 6006#define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3) 6007#define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) 6008#define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3) 6009#define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3) 6010#define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3) 6011#define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3) 6012#define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3) 6013#define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3) 6014#define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3) 6015#define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3) 6016#define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3) 6017#define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3) 6018#define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3) 6019#define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3) 6020#define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3) 6021#define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3) 6022#define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3) 6023#define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3) 6024#define EMAC_LED_1000MB_OVERRIDE (1L<<1) 6025#define EMAC_LED_100MB_OVERRIDE (1L<<2) 6026#define EMAC_LED_10MB_OVERRIDE (1L<<3) 6027#define EMAC_LED_2500MB_OVERRIDE (1L<<12) 6028#define EMAC_LED_OVERRIDE (1L<<0) 6029#define EMAC_LED_TRAFFIC (1L<<6) 6030#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26) 6031#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26) 6032#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26) 6033#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26) 6034#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26) 6035#define EMAC_MDIO_COMM_DATA (0xffffL<<0) 6036#define EMAC_MDIO_COMM_START_BUSY (1L<<29) 6037#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4) 6038#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31) 6039#define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16) 6040#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 6041#define EMAC_MDIO_STATUS_10MB (1L<<1) 6042#define EMAC_MODE_25G_MODE (1L<<5) 6043#define EMAC_MODE_HALF_DUPLEX (1L<<1) 6044#define EMAC_MODE_PORT_GMII (2L<<2) 6045#define EMAC_MODE_PORT_MII (1L<<2) 6046#define EMAC_MODE_PORT_MII_10M (3L<<2) 6047#define EMAC_MODE_RESET (1L<<0) 6048#define EMAC_REG_EMAC_LED 0xc 6049#define EMAC_REG_EMAC_MAC_MATCH 0x10 6050#define EMAC_REG_EMAC_MDIO_COMM 0xac 6051#define EMAC_REG_EMAC_MDIO_MODE 0xb4 6052#define EMAC_REG_EMAC_MDIO_STATUS 0xb0 6053#define EMAC_REG_EMAC_MODE 0x0 6054#define EMAC_REG_EMAC_RX_MODE 0xc8 6055#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 6056#define EMAC_REG_EMAC_RX_STAT_AC 0x180 6057#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 6058#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 6059#define EMAC_REG_EMAC_TX_MODE 0xbc 6060#define EMAC_REG_EMAC_TX_STAT_AC 0x280 6061#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 6062#define EMAC_REG_RX_PFC_MODE 0x320 6063#define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L<<2) 6064#define EMAC_REG_RX_PFC_MODE_RX_EN (1L<<1) 6065#define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0) 6066#define EMAC_REG_RX_PFC_PARAM 0x324 6067#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 6068#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 6069#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 6070#define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0) 6071#define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 6072#define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0) 6073#define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 6074#define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0) 6075#define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 6076#define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0) 6077#define EMAC_RX_MODE_FLOW_EN (1L<<2) 6078#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3) 6079#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) 6080#define EMAC_RX_MODE_PROMISCUOUS (1L<<8) 6081#define EMAC_RX_MODE_RESET (1L<<0) 6082#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) 6083#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) 6084#define EMAC_TX_MODE_FLOW_EN (1L<<4) 6085#define EMAC_TX_MODE_RESET (1L<<0) 6086#define MISC_REGISTERS_GPIO_0 0 6087#define MISC_REGISTERS_GPIO_1 1 6088#define MISC_REGISTERS_GPIO_2 2 6089#define MISC_REGISTERS_GPIO_3 3 6090#define MISC_REGISTERS_GPIO_CLR_POS 16 6091#define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24) 6092#define MISC_REGISTERS_GPIO_FLOAT_POS 24 6093#define MISC_REGISTERS_GPIO_HIGH 1 6094#define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 6095#define MISC_REGISTERS_GPIO_INT_CLR_POS 24 6096#define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 6097#define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 6098#define MISC_REGISTERS_GPIO_INT_SET_POS 16 6099#define MISC_REGISTERS_GPIO_LOW 0 6100#define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 6101#define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 6102#define MISC_REGISTERS_GPIO_PORT_SHIFT 4 6103#define MISC_REGISTERS_GPIO_SET_POS 8 6104#define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 6105#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0) 6106#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19) 6107#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29) 6108#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7) 6109#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26) 6110#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27) 6111#define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22) 6112#define MISC_REGISTERS_RESET_REG_1_SET 0x584 6113#define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 6114#define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24) 6115#define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25) 6116#define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19) 6117#define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17) 6118#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0) 6119#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1) 6120#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2) 6121#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14) 6122#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3) 6123#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15) 6124#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4) 6125#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6) 6126#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8) 6127#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7) 6128#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5) 6129#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13) 6130#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11) 6131#define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13) 6132#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9) 6133#define MISC_REGISTERS_RESET_REG_2_SET 0x594 6134#define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20) 6135#define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21) 6136#define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22) 6137#define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23) 6138#define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 6139#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1) 6140#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2) 6141#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3) 6142#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0) 6143#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5) 6144#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6) 6145#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7) 6146#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4) 6147#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8) 6148#define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 6149#define MISC_REGISTERS_SPIO_4 4 6150#define MISC_REGISTERS_SPIO_5 5 6151#define MISC_REGISTERS_SPIO_7 7 6152#define MISC_REGISTERS_SPIO_CLR_POS 16 6153#define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24) 6154#define MISC_REGISTERS_SPIO_FLOAT_POS 24 6155#define MISC_REGISTERS_SPIO_INPUT_HI_Z 2 6156#define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16 6157#define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1 6158#define MISC_REGISTERS_SPIO_OUTPUT_LOW 0 6159#define MISC_REGISTERS_SPIO_SET_POS 8 6160#define MISC_SPIO_CLR_POS 16 6161#define MISC_SPIO_FLOAT (0xffL<<24) 6162#define MISC_SPIO_FLOAT_POS 24 6163#define MISC_SPIO_INPUT_HI_Z 2 6164#define MISC_SPIO_INT_OLD_SET_POS 16 6165#define MISC_SPIO_OUTPUT_HIGH 1 6166#define MISC_SPIO_OUTPUT_LOW 0 6167#define MISC_SPIO_SET_POS 8 6168#define MISC_SPIO_SPIO4 0x10 6169#define MISC_SPIO_SPIO5 0x20 6170#define HW_LOCK_MAX_RESOURCE_VALUE 31 6171#define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13 6172#define HW_LOCK_RESOURCE_DRV_FLAGS 10 6173#define HW_LOCK_RESOURCE_GPIO 1 6174#define HW_LOCK_RESOURCE_MDIO 0 6175#define HW_LOCK_RESOURCE_NVRAM 12 6176#define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 6177#define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 6178#define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 6179#define HW_LOCK_RESOURCE_RECOVERY_REG 11 6180#define HW_LOCK_RESOURCE_RESET 5 6181#define HW_LOCK_RESOURCE_SPIO 2 6182#define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4) 6183#define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5) 6184#define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19) 6185#define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18) 6186#define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31) 6187#define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30) 6188#define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9) 6189#define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8) 6190#define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7) 6191#define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6) 6192#define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29) 6193#define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28) 6194#define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1) 6195#define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0) 6196#define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18) 6197#define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11) 6198#define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10) 6199#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13) 6200#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12) 6201#define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2) 6202#define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12) 6203#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28) 6204#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1<<31) 6205#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29) 6206#define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30) 6207#define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15) 6208#define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14) 6209#define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14) 6210#define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20) 6211#define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31) 6212#define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30) 6213#define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0) 6214#define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2) 6215#define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3) 6216#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5) 6217#define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4) 6218#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3) 6219#define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2) 6220#define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3) 6221#define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2) 6222#define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22) 6223#define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15) 6224#define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27) 6225#define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26) 6226#define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5) 6227#define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4) 6228#define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25) 6229#define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24) 6230#define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29) 6231#define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28) 6232#define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23) 6233#define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22) 6234#define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27) 6235#define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26) 6236#define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21) 6237#define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20) 6238#define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25) 6239#define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24) 6240#define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16) 6241#define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9) 6242#define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8) 6243#define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7) 6244#define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6) 6245#define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11) 6246#define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10) 6247 6248#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5) 6249#define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9) 6250 6251#define RESERVED_GENERAL_ATTENTION_BIT_0 0 6252 6253#define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 6254#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 6255 6256#define RESERVED_GENERAL_ATTENTION_BIT_6 6 6257#define RESERVED_GENERAL_ATTENTION_BIT_7 7 6258#define RESERVED_GENERAL_ATTENTION_BIT_8 8 6259#define RESERVED_GENERAL_ATTENTION_BIT_9 9 6260#define RESERVED_GENERAL_ATTENTION_BIT_10 10 6261#define RESERVED_GENERAL_ATTENTION_BIT_11 11 6262#define RESERVED_GENERAL_ATTENTION_BIT_12 12 6263#define RESERVED_GENERAL_ATTENTION_BIT_13 13 6264#define RESERVED_GENERAL_ATTENTION_BIT_14 14 6265#define RESERVED_GENERAL_ATTENTION_BIT_15 15 6266#define RESERVED_GENERAL_ATTENTION_BIT_16 16 6267#define RESERVED_GENERAL_ATTENTION_BIT_17 17 6268#define RESERVED_GENERAL_ATTENTION_BIT_18 18 6269#define RESERVED_GENERAL_ATTENTION_BIT_19 19 6270#define RESERVED_GENERAL_ATTENTION_BIT_20 20 6271#define RESERVED_GENERAL_ATTENTION_BIT_21 21 6272 6273/* storm asserts attention bits */ 6274#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 6275#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 6276#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 6277#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 6278 6279/* mcp error attention bit */ 6280#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 6281 6282/*E1H NIG status sync attention mapped to group 4-7*/ 6283#define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 6284#define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 6285#define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 6286#define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 6287#define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 6288#define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 6289#define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 6290#define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 6291 6292 6293#define LATCHED_ATTN_RBCR 23 6294#define LATCHED_ATTN_RBCT 24 6295#define LATCHED_ATTN_RBCN 25 6296#define LATCHED_ATTN_RBCU 26 6297#define LATCHED_ATTN_RBCP 27 6298#define LATCHED_ATTN_TIMEOUT_GRC 28 6299#define LATCHED_ATTN_RSVD_GRC 29 6300#define LATCHED_ATTN_ROM_PARITY_MCP 30 6301#define LATCHED_ATTN_UM_RX_PARITY_MCP 31 6302#define LATCHED_ATTN_UM_TX_PARITY_MCP 32 6303#define LATCHED_ATTN_SCPAD_PARITY_MCP 33 6304 6305#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 6306#define GENERAL_ATTEN_OFFSET(atten_name)\ 6307 (1UL << ((94 + atten_name) % 32)) 6308/* 6309 * This file defines GRC base address for every block. 6310 * This file is included by chipsim, asm microcode and cpp microcode. 6311 * These values are used in Design.xml on regBase attribute 6312 * Use the base with the generated offsets of specific registers. 6313 */ 6314 6315#define GRCBASE_PXPCS 0x000000 6316#define GRCBASE_PCICONFIG 0x002000 6317#define GRCBASE_PCIREG 0x002400 6318#define GRCBASE_EMAC0 0x008000 6319#define GRCBASE_EMAC1 0x008400 6320#define GRCBASE_DBU 0x008800 6321#define GRCBASE_MISC 0x00A000 6322#define GRCBASE_DBG 0x00C000 6323#define GRCBASE_NIG 0x010000 6324#define GRCBASE_XCM 0x020000 6325#define GRCBASE_PRS 0x040000 6326#define GRCBASE_SRCH 0x040400 6327#define GRCBASE_TSDM 0x042000 6328#define GRCBASE_TCM 0x050000 6329#define GRCBASE_BRB1 0x060000 6330#define GRCBASE_MCP 0x080000 6331#define GRCBASE_UPB 0x0C1000 6332#define GRCBASE_CSDM 0x0C2000 6333#define GRCBASE_USDM 0x0C4000 6334#define GRCBASE_CCM 0x0D0000 6335#define GRCBASE_UCM 0x0E0000 6336#define GRCBASE_CDU 0x101000 6337#define GRCBASE_DMAE 0x102000 6338#define GRCBASE_PXP 0x103000 6339#define GRCBASE_CFC 0x104000 6340#define GRCBASE_HC 0x108000 6341#define GRCBASE_PXP2 0x120000 6342#define GRCBASE_PBF 0x140000 6343#define GRCBASE_UMAC0 0x160000 6344#define GRCBASE_UMAC1 0x160400 6345#define GRCBASE_XPB 0x161000 6346#define GRCBASE_MSTAT0 0x162000 6347#define GRCBASE_MSTAT1 0x162800 6348#define GRCBASE_XMAC0 0x163000 6349#define GRCBASE_XMAC1 0x163800 6350#define GRCBASE_TIMERS 0x164000 6351#define GRCBASE_XSDM 0x166000 6352#define GRCBASE_QM 0x168000 6353#define GRCBASE_DQ 0x170000 6354#define GRCBASE_TSEM 0x180000 6355#define GRCBASE_CSEM 0x200000 6356#define GRCBASE_XSEM 0x280000 6357#define GRCBASE_USEM 0x300000 6358#define GRCBASE_MISC_AEU GRCBASE_MISC 6359 6360 6361/* offset of configuration space in the pci core register */ 6362#define PCICFG_OFFSET 0x2000 6363#define PCICFG_VENDOR_ID_OFFSET 0x00 6364#define PCICFG_DEVICE_ID_OFFSET 0x02 6365#define PCICFG_COMMAND_OFFSET 0x04 6366#define PCICFG_COMMAND_IO_SPACE (1<<0) 6367#define PCICFG_COMMAND_MEM_SPACE (1<<1) 6368#define PCICFG_COMMAND_BUS_MASTER (1<<2) 6369#define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 6370#define PCICFG_COMMAND_MWI_CYCLES (1<<4) 6371#define PCICFG_COMMAND_VGA_SNOOP (1<<5) 6372#define PCICFG_COMMAND_PERR_ENA (1<<6) 6373#define PCICFG_COMMAND_STEPPING (1<<7) 6374#define PCICFG_COMMAND_SERR_ENA (1<<8) 6375#define PCICFG_COMMAND_FAST_B2B (1<<9) 6376#define PCICFG_COMMAND_INT_DISABLE (1<<10) 6377#define PCICFG_COMMAND_RESERVED (0x1f<<11) 6378#define PCICFG_STATUS_OFFSET 0x06 6379#define PCICFG_REVISION_ID_OFFSET 0x08 6380#define PCICFG_REVESION_ID_MASK 0xff 6381#define PCICFG_REVESION_ID_ERROR_VAL 0xff 6382#define PCICFG_CACHE_LINE_SIZE 0x0c 6383#define PCICFG_LATENCY_TIMER 0x0d 6384#define PCICFG_BAR_1_LOW 0x10 6385#define PCICFG_BAR_1_HIGH 0x14 6386#define PCICFG_BAR_2_LOW 0x18 6387#define PCICFG_BAR_2_HIGH 0x1c 6388#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 6389#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 6390#define PCICFG_INT_LINE 0x3c 6391#define PCICFG_INT_PIN 0x3d 6392#define PCICFG_PM_CAPABILITY 0x48 6393#define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 6394#define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 6395#define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 6396#define PCICFG_PM_CAPABILITY_DSI (1<<21) 6397#define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 6398#define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 6399#define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 6400#define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 6401#define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 6402#define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 6403#define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 6404#define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 6405#define PCICFG_PM_CSR_OFFSET 0x4c 6406#define PCICFG_PM_CSR_STATE (0x3<<0) 6407#define PCICFG_PM_CSR_PME_ENABLE (1<<8) 6408#define PCICFG_PM_CSR_PME_STATUS (1<<15) 6409#define PCICFG_MSI_CAP_ID_OFFSET 0x58 6410#define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 6411#define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 6412#define PCICFG_MSI_CONTROL_MENA (0x7<<20) 6413#define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 6414#define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 6415#define PCICFG_GRC_ADDRESS 0x78 6416#define PCICFG_GRC_DATA 0x80 6417#define PCICFG_ME_REGISTER 0x98 6418#define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 6419#define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 6420#define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 6421#define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 6422#define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 6423 6424#define PCICFG_DEVICE_CONTROL 0xb4 6425#define PCICFG_DEVICE_STATUS 0xb6 6426#define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 6427#define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 6428#define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 6429#define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 6430#define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 6431#define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 6432#define PCICFG_LINK_CONTROL 0xbc 6433 6434 6435#define BAR_USTRORM_INTMEM 0x400000 6436#define BAR_CSTRORM_INTMEM 0x410000 6437#define BAR_XSTRORM_INTMEM 0x420000 6438#define BAR_TSTRORM_INTMEM 0x430000 6439 6440/* for accessing the IGU in case of status block ACK */ 6441#define BAR_IGU_INTMEM 0x440000 6442 6443#define BAR_DOORBELL_OFFSET 0x800000 6444 6445#define BAR_ME_REGISTER 0x450000 6446 6447/* config_2 offset */ 6448#define GRC_CONFIG_2_SIZE_REG 0x408 6449#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 6450#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 6451#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 6452#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 6453#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 6454#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 6455#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 6456#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 6457#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 6458#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 6459#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 6460#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 6461#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 6462#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 6463#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 6464#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 6465#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 6466#define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 6467#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 6468#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 6469#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 6470#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 6471#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 6472#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 6473#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 6474#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 6475#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 6476#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 6477#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 6478#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 6479#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 6480#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 6481#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 6482#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 6483#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 6484#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 6485#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 6486#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 6487#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 6488#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 6489 6490/* config_3 offset */ 6491#define GRC_CONFIG_3_SIZE_REG 0x40c 6492#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 6493#define PCI_CONFIG_3_FORCE_PME (1L<<24) 6494#define PCI_CONFIG_3_PME_STATUS (1L<<25) 6495#define PCI_CONFIG_3_PME_ENABLE (1L<<26) 6496#define PCI_CONFIG_3_PM_STATE (0x3L<<27) 6497#define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 6498#define PCI_CONFIG_3_PCI_POWER (1L<<31) 6499 6500#define GRC_BAR2_CONFIG 0x4e0 6501#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 6502#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 6503#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 6504#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 6505#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 6506#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 6507#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 6508#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 6509#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 6510#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 6511#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 6512#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 6513#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 6514#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 6515#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 6516#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 6517#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 6518#define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 6519 6520#define PCI_PM_DATA_A 0x410 6521#define PCI_PM_DATA_B 0x414 6522#define PCI_ID_VAL1 0x434 6523#define PCI_ID_VAL2 0x438 6524#define PCI_ID_VAL3 0x43c 6525 6526#define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 6527#define GRC_CONFIG_REG_PF_INIT_VF 0x624 6528#define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xf 6529/* First VF_NUM for PF is encoded in this register. 6530 * The number of VFs assigned to a PF is assumed to be a multiple of 8. 6531 * Software should program these bits based on Total Number of VFs \ 6532 * programmed for each PF. 6533 * Since registers from 0x000-0x7ff are split across functions, each PF will 6534 * have the same location for the same 4 bits 6535 */ 6536 6537#define PXPCS_TL_CONTROL_5 0x814 6538#define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 6539#define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 6540#define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 6541#define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 6542#define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 6543#define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 6544#define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 6545#define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 6546#define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 6547#define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 6548#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 6549#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 6550#define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 6551#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 6552#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 6553#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 6554#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 6555#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 6556#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 6557#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 6558#define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 6559#define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 6560#define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 6561#define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 6562#define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 6563#define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 6564#define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 6565#define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 6566#define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 6567#define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 6568 6569 6570#define PXPCS_TL_FUNC345_STAT 0x854 6571#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 6572#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4\ 6573 (1 << 28) /* Unsupported Request Error Status in function4, if \ 6574 set, generate pcie_err_attn output when this error is seen. WC */ 6575#define PXPCS_TL_FUNC345_STAT_ERR_ECRC4\ 6576 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 6577 generate pcie_err_attn output when this error is seen.. WC */ 6578#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4\ 6579 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 6580 generate pcie_err_attn output when this error is seen.. WC */ 6581#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4\ 6582 (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 6583 set, generate pcie_err_attn output when this error is seen.. WC \ 6584 */ 6585#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4\ 6586 (1 << 24) /* Unexpected Completion Status Status in function 4, \ 6587 if set, generate pcie_err_attn output when this error is seen. WC \ 6588 */ 6589#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4\ 6590 (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 6591 pcie_err_attn output when this error is seen. WC */ 6592#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4\ 6593 (1 << 22) /* Completer Timeout Status Status in function 4, if \ 6594 set, generate pcie_err_attn output when this error is seen. WC */ 6595#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4\ 6596 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6597 function 4, if set, generate pcie_err_attn output when this error \ 6598 is seen. WC */ 6599#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4\ 6600 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 6601 generate pcie_err_attn output when this error is seen.. WC */ 6602#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 6603#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3\ 6604 (1 << 18) /* Unsupported Request Error Status in function3, if \ 6605 set, generate pcie_err_attn output when this error is seen. WC */ 6606#define PXPCS_TL_FUNC345_STAT_ERR_ECRC3\ 6607 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 6608 generate pcie_err_attn output when this error is seen.. WC */ 6609#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3\ 6610 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 6611 generate pcie_err_attn output when this error is seen.. WC */ 6612#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3\ 6613 (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 6614 set, generate pcie_err_attn output when this error is seen.. WC \ 6615 */ 6616#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3\ 6617 (1 << 14) /* Unexpected Completion Status Status in function 3, \ 6618 if set, generate pcie_err_attn output when this error is seen. WC \ 6619 */ 6620#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3\ 6621 (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 6622 pcie_err_attn output when this error is seen. WC */ 6623#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3\ 6624 (1 << 12) /* Completer Timeout Status Status in function 3, if \ 6625 set, generate pcie_err_attn output when this error is seen. WC */ 6626#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3\ 6627 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6628 function 3, if set, generate pcie_err_attn output when this error \ 6629 is seen. WC */ 6630#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3\ 6631 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 6632 generate pcie_err_attn output when this error is seen.. WC */ 6633#define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 6634#define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2\ 6635 (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 6636 set, generate pcie_err_attn output when this error is seen. WC */ 6637#define PXPCS_TL_FUNC345_STAT_ERR_ECRC2\ 6638 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 6639 generate pcie_err_attn output when this error is seen.. WC */ 6640#define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2\ 6641 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 6642 generate pcie_err_attn output when this error is seen.. WC */ 6643#define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2\ 6644 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 6645 set, generate pcie_err_attn output when this error is seen.. WC \ 6646 */ 6647#define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2\ 6648 (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 6649 if set, generate pcie_err_attn output when this error is seen. WC \ 6650 */ 6651#define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2\ 6652 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 6653 pcie_err_attn output when this error is seen. WC */ 6654#define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2\ 6655 (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 6656 set, generate pcie_err_attn output when this error is seen. WC */ 6657#define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2\ 6658 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6659 Function 2, if set, generate pcie_err_attn output when this error \ 6660 is seen. WC */ 6661#define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2\ 6662 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 6663 generate pcie_err_attn output when this error is seen.. WC */ 6664 6665 6666#define PXPCS_TL_FUNC678_STAT 0x85C 6667#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 6668#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7\ 6669 (1 << 28) /* Unsupported Request Error Status in function7, if \ 6670 set, generate pcie_err_attn output when this error is seen. WC */ 6671#define PXPCS_TL_FUNC678_STAT_ERR_ECRC7\ 6672 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 6673 generate pcie_err_attn output when this error is seen.. WC */ 6674#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7\ 6675 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 6676 generate pcie_err_attn output when this error is seen.. WC */ 6677#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7\ 6678 (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 6679 set, generate pcie_err_attn output when this error is seen.. WC \ 6680 */ 6681#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7\ 6682 (1 << 24) /* Unexpected Completion Status Status in function 7, \ 6683 if set, generate pcie_err_attn output when this error is seen. WC \ 6684 */ 6685#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7\ 6686 (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 6687 pcie_err_attn output when this error is seen. WC */ 6688#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7\ 6689 (1 << 22) /* Completer Timeout Status Status in function 7, if \ 6690 set, generate pcie_err_attn output when this error is seen. WC */ 6691#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7\ 6692 (1 << 21) /* Flow Control Protocol Error Status Status in \ 6693 function 7, if set, generate pcie_err_attn output when this error \ 6694 is seen. WC */ 6695#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7\ 6696 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 6697 generate pcie_err_attn output when this error is seen.. WC */ 6698#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 6699#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6\ 6700 (1 << 18) /* Unsupported Request Error Status in function6, if \ 6701 set, generate pcie_err_attn output when this error is seen. WC */ 6702#define PXPCS_TL_FUNC678_STAT_ERR_ECRC6\ 6703 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 6704 generate pcie_err_attn output when this error is seen.. WC */ 6705#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6\ 6706 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 6707 generate pcie_err_attn output when this error is seen.. WC */ 6708#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6\ 6709 (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 6710 set, generate pcie_err_attn output when this error is seen.. WC \ 6711 */ 6712#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6\ 6713 (1 << 14) /* Unexpected Completion Status Status in function 6, \ 6714 if set, generate pcie_err_attn output when this error is seen. WC \ 6715 */ 6716#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6\ 6717 (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 6718 pcie_err_attn output when this error is seen. WC */ 6719#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6\ 6720 (1 << 12) /* Completer Timeout Status Status in function 6, if \ 6721 set, generate pcie_err_attn output when this error is seen. WC */ 6722#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6\ 6723 (1 << 11) /* Flow Control Protocol Error Status Status in \ 6724 function 6, if set, generate pcie_err_attn output when this error \ 6725 is seen. WC */ 6726#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6\ 6727 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 6728 generate pcie_err_attn output when this error is seen.. WC */ 6729#define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 6730#define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5\ 6731 (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 6732 set, generate pcie_err_attn output when this error is seen. WC */ 6733#define PXPCS_TL_FUNC678_STAT_ERR_ECRC5\ 6734 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 6735 generate pcie_err_attn output when this error is seen.. WC */ 6736#define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5\ 6737 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 6738 generate pcie_err_attn output when this error is seen.. WC */ 6739#define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5\ 6740 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 6741 set, generate pcie_err_attn output when this error is seen.. WC \ 6742 */ 6743#define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5\ 6744 (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 6745 if set, generate pcie_err_attn output when this error is seen. WC \ 6746 */ 6747#define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5\ 6748 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 6749 pcie_err_attn output when this error is seen. WC */ 6750#define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5\ 6751 (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 6752 set, generate pcie_err_attn output when this error is seen. WC */ 6753#define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5\ 6754 (1 << 1) /* Flow Control Protocol Error Status Status for \ 6755 Function 5, if set, generate pcie_err_attn output when this error \ 6756 is seen. WC */ 6757#define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5\ 6758 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 6759 generate pcie_err_attn output when this error is seen.. WC */ 6760 6761 6762#define BAR_USTRORM_INTMEM 0x400000 6763#define BAR_CSTRORM_INTMEM 0x410000 6764#define BAR_XSTRORM_INTMEM 0x420000 6765#define BAR_TSTRORM_INTMEM 0x430000 6766 6767/* for accessing the IGU in case of status block ACK */ 6768#define BAR_IGU_INTMEM 0x440000 6769 6770#define BAR_DOORBELL_OFFSET 0x800000 6771 6772#define BAR_ME_REGISTER 0x450000 6773#define ME_REG_PF_NUM_SHIFT 0 6774#define ME_REG_PF_NUM\ 6775 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 6776#define ME_REG_VF_VALID (1<<8) 6777#define ME_REG_VF_NUM_SHIFT 9 6778#define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 6779#define ME_REG_VF_ERR (0x1<<3) 6780#define ME_REG_ABS_PF_NUM_SHIFT 16 6781#define ME_REG_ABS_PF_NUM\ 6782 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 6783 6784 6785#define PXP_VF_ADDR_IGU_START 0 6786#define PXP_VF_ADDR_IGU_SIZE 0x3000 6787#define PXP_VF_ADDR_IGU_END\ 6788 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1) 6789 6790#define PXP_VF_ADDR_USDM_QUEUES_START 0x3000 6791#define PXP_VF_ADDR_USDM_QUEUES_SIZE\ 6792 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 6793#define PXP_VF_ADDR_USDM_QUEUES_END\ 6794 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1) 6795 6796#define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600 6797#define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 6798#define PXP_VF_ADDR_CSDM_GLOBAL_END\ 6799 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1) 6800 6801#define PXP_VF_ADDR_DB_START 0x7c00 6802#define PXP_VF_ADDR_DB_SIZE 0x200 6803#define PXP_VF_ADDR_DB_END\ 6804 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1) 6805 6806#define MDIO_REG_BANK_CL73_IEEEB0 0x0 6807#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 6808#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 6809#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 6810#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 6811 6812#define MDIO_REG_BANK_CL73_IEEEB1 0x10 6813#define MDIO_CL73_IEEEB1_AN_ADV1 0x00 6814#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 6815#define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 6816#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 6817#define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 6818#define MDIO_CL73_IEEEB1_AN_ADV2 0x01 6819#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 6820#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 6821#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 6822#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 6823#define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 6824#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 6825#define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 6826#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 6827#define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 6828#define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 6829 6830#define MDIO_REG_BANK_RX0 0x80b0 6831#define MDIO_RX0_RX_STATUS 0x10 6832#define MDIO_RX0_RX_STATUS_SIGDET 0x8000 6833#define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 6834#define MDIO_RX0_RX_EQ_BOOST 0x1c 6835#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6836#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 6837 6838#define MDIO_REG_BANK_RX1 0x80c0 6839#define MDIO_RX1_RX_EQ_BOOST 0x1c 6840#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6841#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 6842 6843#define MDIO_REG_BANK_RX2 0x80d0 6844#define MDIO_RX2_RX_EQ_BOOST 0x1c 6845#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6846#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 6847 6848#define MDIO_REG_BANK_RX3 0x80e0 6849#define MDIO_RX3_RX_EQ_BOOST 0x1c 6850#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6851#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 6852 6853#define MDIO_REG_BANK_RX_ALL 0x80f0 6854#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 6855#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 6856#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 6857 6858#define MDIO_REG_BANK_TX0 0x8060 6859#define MDIO_TX0_TX_DRIVER 0x17 6860#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6861#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6862#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6863#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6864#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6865#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6866#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6867#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6868#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6869 6870#define MDIO_REG_BANK_TX1 0x8070 6871#define MDIO_TX1_TX_DRIVER 0x17 6872#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6873#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6874#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6875#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6876#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6877#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6878#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6879#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6880#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6881 6882#define MDIO_REG_BANK_TX2 0x8080 6883#define MDIO_TX2_TX_DRIVER 0x17 6884#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6885#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6886#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6887#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6888#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6889#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6890#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6891#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6892#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6893 6894#define MDIO_REG_BANK_TX3 0x8090 6895#define MDIO_TX3_TX_DRIVER 0x17 6896#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 6897#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 6898#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 6899#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 6900#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 6901#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 6902#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 6903#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 6904#define MDIO_TX0_TX_DRIVER_ICBUF1T 1 6905 6906#define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 6907#define MDIO_BLOCK0_XGXS_CONTROL 0x10 6908 6909#define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 6910#define MDIO_BLOCK1_LANE_CTRL0 0x15 6911#define MDIO_BLOCK1_LANE_CTRL1 0x16 6912#define MDIO_BLOCK1_LANE_CTRL2 0x17 6913#define MDIO_BLOCK1_LANE_PRBS 0x19 6914 6915#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 6916#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 6917#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 6918#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 6919#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 6920#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 6921#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 6922#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 6923#define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 6924#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 6925 6926#define MDIO_REG_BANK_GP_STATUS 0x8120 6927#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 6928#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 6929#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 6930#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 6931#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 6932#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 6933#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 6934#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 6935#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 6936#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 6937#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 6938#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 6939#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 6940#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 6941#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 6942#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 6943#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 6944#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 6945#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 6946#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 6947#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 6948#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 6949#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 6950#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 6951#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 6952#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 6953#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 6954#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 6955#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 6956#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 6957 6958 6959#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 6960#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 6961#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 6962#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 6963#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 6964#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 6965#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 6966 6967#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 6968#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 6969#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 6970#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 6971#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 6972#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 6973#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 6974#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 6975#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 6976#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 6977#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 6978#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 6979#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 6980#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 6981#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 6982#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 6983#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 6984#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 6985#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 6986#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 6987#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 6988#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 6989#define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 6990#define MDIO_SERDES_DIGITAL_MISC1 0x18 6991#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 6992#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 6993#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 6994#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 6995#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 6996#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 6997#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 6998#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 6999#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 7000#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 7001#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 7002#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 7003#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 7004#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 7005#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 7006#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 7007#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 7008#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 7009 7010#define MDIO_REG_BANK_OVER_1G 0x8320 7011#define MDIO_OVER_1G_DIGCTL_3_4 0x14 7012#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 7013#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 7014#define MDIO_OVER_1G_UP1 0x19 7015#define MDIO_OVER_1G_UP1_2_5G 0x0001 7016#define MDIO_OVER_1G_UP1_5G 0x0002 7017#define MDIO_OVER_1G_UP1_6G 0x0004 7018#define MDIO_OVER_1G_UP1_10G 0x0010 7019#define MDIO_OVER_1G_UP1_10GH 0x0008 7020#define MDIO_OVER_1G_UP1_12G 0x0020 7021#define MDIO_OVER_1G_UP1_12_5G 0x0040 7022#define MDIO_OVER_1G_UP1_13G 0x0080 7023#define MDIO_OVER_1G_UP1_15G 0x0100 7024#define MDIO_OVER_1G_UP1_16G 0x0200 7025#define MDIO_OVER_1G_UP2 0x1A 7026#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 7027#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 7028#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 7029#define MDIO_OVER_1G_UP3 0x1B 7030#define MDIO_OVER_1G_UP3_HIGIG2 0x0001 7031#define MDIO_OVER_1G_LP_UP1 0x1C 7032#define MDIO_OVER_1G_LP_UP2 0x1D 7033#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 7034#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 7035#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 7036#define MDIO_OVER_1G_LP_UP3 0x1E 7037 7038#define MDIO_REG_BANK_REMOTE_PHY 0x8330 7039#define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 7040#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 7041#define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 7042 7043#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 7044#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 7045#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 7046#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 7047 7048#define MDIO_REG_BANK_CL73_USERB0 0x8370 7049#define MDIO_CL73_USERB0_CL73_UCTRL 0x10 7050#define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 7051#define MDIO_CL73_USERB0_CL73_USTAT1 0x11 7052#define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 7053#define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 7054#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 7055#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 7056#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 7057#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 7058#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 7059#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 7060 7061#define MDIO_REG_BANK_AER_BLOCK 0xFFD0 7062#define MDIO_AER_BLOCK_AER_REG 0x1E 7063 7064#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 7065#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 7066#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 7067#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 7068#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 7069#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 7070#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 7071#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 7072#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 7073#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 7074#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 7075#define MDIO_COMBO_IEEE0_MII_STATUS 0x11 7076#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 7077#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 7078#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 7079#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 7080#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 7081#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 7082#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 7083#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 7084#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 7085#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 7086#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 7087#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 7088#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 7089#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 7090#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 7091#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 7092#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 7093#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 7094#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 7095/*WhenthelinkpartnerisinSGMIImode(bit0=1),then 7096bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. 7097Theotherbitsarereservedandshouldbezero*/ 7098#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 7099 7100 7101#define MDIO_PMA_DEVAD 0x1 7102/*ieee*/ 7103#define MDIO_PMA_REG_CTRL 0x0 7104#define MDIO_PMA_REG_STATUS 0x1 7105#define MDIO_PMA_REG_10G_CTRL2 0x7 7106#define MDIO_PMA_REG_TX_DISABLE 0x0009 7107#define MDIO_PMA_REG_RX_SD 0xa 7108/*bcm*/ 7109#define MDIO_PMA_REG_BCM_CTRL 0x0096 7110#define MDIO_PMA_REG_FEC_CTRL 0x00ab 7111#define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 7112#define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 7113#define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 7114#define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 7115#define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 7116#define MDIO_PMA_REG_MISC_CTRL 0xca0a 7117#define MDIO_PMA_REG_GEN_CTRL 0xca10 7118#define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 7119#define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 7120#define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 7121#define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 7122#define MDIO_PMA_REG_ROM_VER1 0xca19 7123#define MDIO_PMA_REG_ROM_VER2 0xca1a 7124#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 7125#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 7126#define MDIO_PMA_REG_PLL_CTRL 0xca1e 7127#define MDIO_PMA_REG_MISC_CTRL0 0xca23 7128#define MDIO_PMA_REG_LRM_MODE 0xca3f 7129#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 7130#define MDIO_PMA_REG_MISC_CTRL1 0xca85 7131 7132#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 7133#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 7134#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 7135#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 7136#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 7137#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 7138#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 7139#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 7140#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 7141#define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 7142#define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 7143#define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 7144 7145#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 7146#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 7147#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 7148#define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 7149#define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 7150#define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 7151#define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 7152#define MDIO_PMA_REG_8727_PCS_GP 0xc842 7153#define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 7154 7155#define MDIO_AN_REG_8727_MISC_CTRL 0x8309 7156 7157#define MDIO_PMA_REG_8073_CHIP_REV 0xc801 7158#define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 7159#define MDIO_PMA_REG_8073_XAUI_WA 0xc841 7160#define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 7161 7162#define MDIO_PMA_REG_7101_RESET 0xc000 7163#define MDIO_PMA_REG_7107_LED_CNTL 0xc007 7164#define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 7165#define MDIO_PMA_REG_7101_VER1 0xc026 7166#define MDIO_PMA_REG_7101_VER2 0xc027 7167 7168#define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 7169#define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 7170#define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 7171#define MDIO_PMA_REG_8481_LED3_MASK 0xa832 7172#define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 7173#define MDIO_PMA_REG_8481_LED5_MASK 0xa838 7174#define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 7175#define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 7176#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 7177#define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 7178 7179 7180#define MDIO_WIS_DEVAD 0x2 7181/*bcm*/ 7182#define MDIO_WIS_REG_LASI_CNTL 0x9002 7183#define MDIO_WIS_REG_LASI_STATUS 0x9005 7184 7185#define MDIO_PCS_DEVAD 0x3 7186#define MDIO_PCS_REG_STATUS 0x0020 7187#define MDIO_PCS_REG_LASI_STATUS 0x9005 7188#define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 7189#define MDIO_PCS_REG_7101_SPI_MUX 0xD008 7190#define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 7191#define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 7192#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 7193#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 7194#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 7195#define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 7196#define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 7197 7198 7199#define MDIO_XS_DEVAD 0x4 7200#define MDIO_XS_PLL_SEQUENCER 0x8000 7201#define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 7202 7203#define MDIO_XS_8706_REG_BANK_RX0 0x80bc 7204#define MDIO_XS_8706_REG_BANK_RX1 0x80cc 7205#define MDIO_XS_8706_REG_BANK_RX2 0x80dc 7206#define MDIO_XS_8706_REG_BANK_RX3 0x80ec 7207#define MDIO_XS_8706_REG_BANK_RXA 0x80fc 7208 7209#define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 7210 7211#define MDIO_AN_DEVAD 0x7 7212/*ieee*/ 7213#define MDIO_AN_REG_CTRL 0x0000 7214#define MDIO_AN_REG_STATUS 0x0001 7215#define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 7216#define MDIO_AN_REG_ADV_PAUSE 0x0010 7217#define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 7218#define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 7219#define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 7220#define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 7221#define MDIO_AN_REG_ADV 0x0011 7222#define MDIO_AN_REG_ADV2 0x0012 7223#define MDIO_AN_REG_LP_AUTO_NEG 0x0013 7224#define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 7225#define MDIO_AN_REG_MASTER_STATUS 0x0021 7226#define MDIO_AN_REG_EEE_ADV 0x003c 7227#define MDIO_AN_REG_LP_EEE_ADV 0x003d 7228/*bcm*/ 7229#define MDIO_AN_REG_LINK_STATUS 0x8304 7230#define MDIO_AN_REG_CL37_CL73 0x8370 7231#define MDIO_AN_REG_CL37_AN 0xffe0 7232#define MDIO_AN_REG_CL37_FC_LD 0xffe4 7233#define MDIO_AN_REG_CL37_FC_LP 0xffe5 7234#define MDIO_AN_REG_1000T_STATUS 0xffea 7235 7236#define MDIO_AN_REG_8073_2_5G 0x8329 7237#define MDIO_AN_REG_8073_BAM 0x8350 7238 7239#define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 7240#define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 7241#define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 7242#define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 7243#define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 7244#define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 7245#define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 7246#define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 7247#define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 7248#define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 7249#define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 7250#define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 7251#define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 7252 7253/* BCM84823 only */ 7254#define MDIO_CTL_DEVAD 0x1e 7255#define MDIO_CTL_REG_84823_MEDIA 0x401a 7256#define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 7257 /* These pins configure the BCM84823 interface to MAC after reset. */ 7258#define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 7259#define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 7260 /* These pins configure the BCM84823 interface to Line after reset. */ 7261#define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 7262#define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 7263#define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 7264 /* When this pin is active high during reset, 10GBASE-T core is power 7265 * down, When it is active low the 10GBASE-T is power up 7266 */ 7267#define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 7268#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 7269#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 7270#define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 7271#define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 7272#define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 7273#define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 7274#define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b 7275#define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f 7276#define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 7277#define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec 7278#define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 7279 7280/* BCM84833 only */ 7281#define MDIO_84833_TOP_CFG_FW_REV 0x400f 7282#define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 7283#define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 7284#define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 7285#define MDIO_84833_SUPER_ISOLATE 0x8000 7286/* These are mailbox register set used by 84833. */ 7287#define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 7288#define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 7289#define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 7290#define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 7291#define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 7292#define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 7293#define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 7294#define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 7295#define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a 7296#define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b 7297#define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c 7298#define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 7299#define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 7300#define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 7301#define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 7302#define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 7303#define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 7304#define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 7305 7306/* Mailbox command set used by 84833. */ 7307#define PHY84833_CMD_SET_PAIR_SWAP 0x8001 7308#define PHY84833_CMD_GET_EEE_MODE 0x8008 7309#define PHY84833_CMD_SET_EEE_MODE 0x8009 7310/* Mailbox status set used by 84833. */ 7311#define PHY84833_STATUS_CMD_RECEIVED 0x0001 7312#define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 7313#define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 7314#define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 7315#define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 7316#define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 7317#define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 7318#define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 7319#define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 7320 7321 7322/* Warpcore clause 45 addressing */ 7323#define MDIO_WC_DEVAD 0x3 7324#define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 7325#define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 7326#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 7327#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 7328#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 7329#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 7330#define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 7331#define MDIO_WC_REG_PCS_STATUS2 0x0021 7332#define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 7333#define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 7334#define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 7335#define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 7336#define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 7337#define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 7338#define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 7339#define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 7340#define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 7341#define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 7342#define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 7343#define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 7344#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01 7345#define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e 7346#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 7347#define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 7348#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 7349#define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 7350#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 7351#define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 7352#define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 7353#define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 7354#define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 7355#define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 7356#define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 7357#define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 7358#define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 7359#define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 7360#define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 7361#define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa 7362#define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 7363#define MDIO_WC_REG_XGXS_STATUS3 0x8129 7364#define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 7365#define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 7366#define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 7367#define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 7368#define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 7369#define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 7370#define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 7371#define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 7372#define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 7373#define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 7374#define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 7375#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 7376#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 7377#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 7378#define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 7379#define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 7380#define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 7381#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 7382#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 7383#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 7384#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 7385#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 7386#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 7387#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 7388#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 7389#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 7390#define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 7391#define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 7392#define MDIO_WC_REG_DSC_SMC 0x8213 7393#define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 7394#define MDIO_WC_REG_TX_FIR_TAP 0x82e2 7395#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 7396#define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 7397#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 7398#define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 7399#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 7400#define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 7401#define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 7402#define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 7403#define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 7404#define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 7405#define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 7406#define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 7407#define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 7408#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 7409#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 7410#define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 7411#define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 7412#define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 7413#define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 7414#define MDIO_WC_REG_DIGITAL3_UP1 0x8329 7415#define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c 7416#define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 7417#define MDIO_WC_REG_DIGITAL4_MISC5 0x833e 7418#define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 7419#define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 7420#define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d 7421#define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 7422#define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 7423#define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 7424#define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 7425#define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 7426#define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 7427#define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 7428#define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 7429#define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b 7430#define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 7431#define MDIO_WC_REG_TX66_CONTROL 0x83b0 7432#define MDIO_WC_REG_RX66_CONTROL 0x83c0 7433#define MDIO_WC_REG_RX66_SCW0 0x83c2 7434#define MDIO_WC_REG_RX66_SCW1 0x83c3 7435#define MDIO_WC_REG_RX66_SCW2 0x83c4 7436#define MDIO_WC_REG_RX66_SCW3 0x83c5 7437#define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 7438#define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 7439#define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 7440#define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 7441#define MDIO_WC_REG_FX100_CTRL1 0x8400 7442#define MDIO_WC_REG_FX100_CTRL3 0x8402 7443#define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 7444#define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 7445#define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 7446#define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 7447#define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a 7448#define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b 7449#define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 7450#define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 7451#define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 7452#define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 7453#define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 7454#define MDIO_WC_REG_MICROBLK_CMD 0xffc2 7455#define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 7456#define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 7457 7458#define MDIO_WC_REG_AERBLK_AER 0xffde 7459#define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 7460#define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 7461 7462#define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 7463#define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 7464#define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 7465 7466#define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 7467 7468#define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 7469 7470/* 54618se */ 7471#define MDIO_REG_GPHY_PHYID_LSB 0x3 7472#define MDIO_REG_GPHY_ID_54618SE 0x5cd5 7473#define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 7474#define MDIO_REG_GPHY_CL45_DATA_REG 0xe 7475#define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 7476#define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 7477#define MDIO_REG_GPHY_EXP_ACCESS 0x17 7478#define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 7479#define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 7480#define MDIO_REG_GPHY_AUX_STATUS 0x19 7481#define MDIO_REG_INTR_STATUS 0x1a 7482#define MDIO_REG_INTR_MASK 0x1b 7483#define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 7484#define MDIO_REG_GPHY_SHADOW 0x1c 7485#define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) 7486#define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 7487#define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 7488#define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 7489#define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 7490 7491#define IGU_FUNC_BASE 0x0400 7492 7493#define IGU_ADDR_MSIX 0x0000 7494#define IGU_ADDR_INT_ACK 0x0200 7495#define IGU_ADDR_PROD_UPD 0x0201 7496#define IGU_ADDR_ATTN_BITS_UPD 0x0202 7497#define IGU_ADDR_ATTN_BITS_SET 0x0203 7498#define IGU_ADDR_ATTN_BITS_CLR 0x0204 7499#define IGU_ADDR_COALESCE_NOW 0x0205 7500#define IGU_ADDR_SIMD_MASK 0x0206 7501#define IGU_ADDR_SIMD_NOMASK 0x0207 7502#define IGU_ADDR_MSI_CTL 0x0210 7503#define IGU_ADDR_MSI_ADDR_LO 0x0211 7504#define IGU_ADDR_MSI_ADDR_HI 0x0212 7505#define IGU_ADDR_MSI_DATA 0x0213 7506 7507#define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 7508#define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 7509#define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 7510#define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 7511 7512#define COMMAND_REG_INT_ACK 0x0 7513#define COMMAND_REG_PROD_UPD 0x4 7514#define COMMAND_REG_ATTN_BITS_UPD 0x8 7515#define COMMAND_REG_ATTN_BITS_SET 0xc 7516#define COMMAND_REG_ATTN_BITS_CLR 0x10 7517#define COMMAND_REG_COALESCE_NOW 0x14 7518#define COMMAND_REG_SIMD_MASK 0x18 7519#define COMMAND_REG_SIMD_NOMASK 0x1c 7520 7521 7522#define IGU_MEM_BASE 0x0000 7523 7524#define IGU_MEM_MSIX_BASE 0x0000 7525#define IGU_MEM_MSIX_UPPER 0x007f 7526#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 7527 7528#define IGU_MEM_PBA_MSIX_BASE 0x0200 7529#define IGU_MEM_PBA_MSIX_UPPER 0x0200 7530 7531#define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 7532#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 7533 7534#define IGU_CMD_INT_ACK_BASE 0x0400 7535#define IGU_CMD_INT_ACK_UPPER\ 7536 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7537#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 7538 7539#define IGU_CMD_E2_PROD_UPD_BASE 0x0500 7540#define IGU_CMD_E2_PROD_UPD_UPPER\ 7541 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1) 7542#define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 7543 7544#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 7545#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 7546#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 7547 7548#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 7549#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 7550#define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 7551#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 7552 7553#define IGU_REG_RESERVED_UPPER 0x05ff 7554/* Fields of IGU PF CONFIGURATION REGISTER */ 7555#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7556#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7557#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 7558#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 7559#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7560#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 7561 7562/* Fields of IGU VF CONFIGURATION REGISTER */ 7563#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 7564#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 7565#define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 7566#define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 7567#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 7568 7569 7570#define IGU_BC_DSB_NUM_SEGS 5 7571#define IGU_BC_NDSB_NUM_SEGS 2 7572#define IGU_NORM_DSB_NUM_SEGS 2 7573#define IGU_NORM_NDSB_NUM_SEGS 1 7574#define IGU_BC_BASE_DSB_PROD 128 7575#define IGU_NORM_BASE_DSB_PROD 136 7576 7577 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 7578 [5:2] = 0; [1:0] = PF number) */ 7579#define IGU_FID_ENCODE_IS_PF (0x1<<6) 7580#define IGU_FID_ENCODE_IS_PF_SHIFT 6 7581#define IGU_FID_VF_NUM_MASK (0x3f) 7582#define IGU_FID_PF_NUM_MASK (0x7) 7583 7584#define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 7585#define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 7586#define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 7587#define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 7588#define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 7589 7590 7591#define CDU_REGION_NUMBER_XCM_AG 2 7592#define CDU_REGION_NUMBER_UCM_AG 4 7593 7594 7595/* String-to-compress [31:8] = CID (all 24 bits) 7596 * String-to-compress [7:4] = Region 7597 * String-to-compress [3:0] = Type 7598 */ 7599#define CDU_VALID_DATA(_cid, _region, _type)\ 7600 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 7601#define CDU_CRC8(_cid, _region, _type)\ 7602 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 7603#define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type)\ 7604 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 7605#define CDU_RSRVD_VALUE_TYPE_B(_crc, _type)\ 7606 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 7607#define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 7608 7609/****************************************************************************** 7610 * Description: 7611 * Calculates crc 8 on a word value: polynomial 0-1-2-8 7612 * Code was translated from Verilog. 7613 * Return: 7614 *****************************************************************************/ 7615static inline u8 calc_crc8(u32 data, u8 crc) 7616{ 7617 u8 D[32]; 7618 u8 NewCRC[8]; 7619 u8 C[8]; 7620 u8 crc_res; 7621 u8 i; 7622 7623 /* split the data into 31 bits */ 7624 for (i = 0; i < 32; i++) { 7625 D[i] = (u8)(data & 1); 7626 data = data >> 1; 7627 } 7628 7629 /* split the crc into 8 bits */ 7630 for (i = 0; i < 8; i++) { 7631 C[i] = crc & 1; 7632 crc = crc >> 1; 7633 } 7634 7635 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ 7636 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ 7637 C[6] ^ C[7]; 7638 NewCRC[1] = D[30] ^ D[29] ^ D[28] ^ D[24] ^ D[23] ^ D[22] ^ D[21] ^ 7639 D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ 7640 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ 7641 C[6]; 7642 NewCRC[2] = D[29] ^ D[28] ^ D[25] ^ D[24] ^ D[22] ^ D[17] ^ D[15] ^ 7643 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ 7644 C[0] ^ C[1] ^ C[4] ^ C[5]; 7645 NewCRC[3] = D[30] ^ D[29] ^ D[26] ^ D[25] ^ D[23] ^ D[18] ^ D[16] ^ 7646 D[14] ^ D[13] ^ D[11] ^ D[9] ^ D[7] ^ D[3] ^ D[2] ^ D[1] ^ 7647 C[1] ^ C[2] ^ C[5] ^ C[6]; 7648 NewCRC[4] = D[31] ^ D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[19] ^ D[17] ^ 7649 D[15] ^ D[14] ^ D[12] ^ D[10] ^ D[8] ^ D[4] ^ D[3] ^ D[2] ^ 7650 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; 7651 NewCRC[5] = D[31] ^ D[28] ^ D[27] ^ D[25] ^ D[20] ^ D[18] ^ D[16] ^ 7652 D[15] ^ D[13] ^ D[11] ^ D[9] ^ D[5] ^ D[4] ^ D[3] ^ C[1] ^ 7653 C[3] ^ C[4] ^ C[7]; 7654 NewCRC[6] = D[29] ^ D[28] ^ D[26] ^ D[21] ^ D[19] ^ D[17] ^ D[16] ^ 7655 D[14] ^ D[12] ^ D[10] ^ D[6] ^ D[5] ^ D[4] ^ C[2] ^ C[4] ^ 7656 C[5]; 7657 NewCRC[7] = D[30] ^ D[29] ^ D[27] ^ D[22] ^ D[20] ^ D[18] ^ D[17] ^ 7658 D[15] ^ D[13] ^ D[11] ^ D[7] ^ D[6] ^ D[5] ^ C[3] ^ C[5] ^ 7659 C[6]; 7660 7661 crc_res = 0; 7662 for (i = 0; i < 8; i++) 7663 crc_res |= (NewCRC[i] << i); 7664 7665 return crc_res; 7666} 7667 7668 7669#endif /* BNX2X_REG_H */ 7670