1/* bnx2x_mfw_req.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2012-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 */ 9 10#ifndef BNX2X_MFW_REQ_H 11#define BNX2X_MFW_REQ_H 12 13#define PORT_0 0 14#define PORT_1 1 15#define PORT_MAX 2 16#define NVM_PATH_MAX 2 17 18/* FCoE capabilities required from the driver */ 19struct fcoe_capabilities { 20 u32 capability1; 21 /* Maximum number of I/Os per connection */ 22 #define FCOE_IOS_PER_CONNECTION_MASK 0x0000ffff 23 #define FCOE_IOS_PER_CONNECTION_SHIFT 0 24 /* Maximum number of Logins per port */ 25 #define FCOE_LOGINS_PER_PORT_MASK 0xffff0000 26 #define FCOE_LOGINS_PER_PORT_SHIFT 16 27 28 u32 capability2; 29 /* Maximum number of exchanges */ 30 #define FCOE_NUMBER_OF_EXCHANGES_MASK 0x0000ffff 31 #define FCOE_NUMBER_OF_EXCHANGES_SHIFT 0 32 /* Maximum NPIV WWN per port */ 33 #define FCOE_NPIV_WWN_PER_PORT_MASK 0xffff0000 34 #define FCOE_NPIV_WWN_PER_PORT_SHIFT 16 35 36 u32 capability3; 37 /* Maximum number of targets supported */ 38 #define FCOE_TARGETS_SUPPORTED_MASK 0x0000ffff 39 #define FCOE_TARGETS_SUPPORTED_SHIFT 0 40 /* Maximum number of outstanding commands across all connections */ 41 #define FCOE_OUTSTANDING_COMMANDS_MASK 0xffff0000 42 #define FCOE_OUTSTANDING_COMMANDS_SHIFT 16 43 44 u32 capability4; 45 #define FCOE_CAPABILITY4_STATEFUL 0x00000001 46 #define FCOE_CAPABILITY4_STATELESS 0x00000002 47 #define FCOE_CAPABILITY4_CAPABILITIES_REPORTED_VALID 0x00000004 48}; 49 50struct glob_ncsi_oem_data { 51 u32 driver_version; 52 u32 unused[3]; 53 struct fcoe_capabilities fcoe_features[NVM_PATH_MAX][PORT_MAX]; 54}; 55 56/* current drv_info version */ 57#define DRV_INFO_CUR_VER 2 58 59/* drv_info op codes supported */ 60enum drv_info_opcode { 61 ETH_STATS_OPCODE, 62 FCOE_STATS_OPCODE, 63 ISCSI_STATS_OPCODE 64}; 65 66#define ETH_STAT_INFO_VERSION_LEN 12 67/* Per PCI Function Ethernet Statistics required from the driver */ 68struct eth_stats_info { 69 /* Function's Driver Version. padded to 12 */ 70 u8 version[ETH_STAT_INFO_VERSION_LEN]; 71 /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */ 72 u8 mac_local[8]; 73 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 74 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */ 75 u32 mtu_size; /* MTU Size. Note : Negotiated MTU */ 76 u32 feature_flags; /* Feature_Flags. */ 77#define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01 78#define FEATURE_ETH_LSO_MASK 0x02 79#define FEATURE_ETH_BOOTMODE_MASK 0x1C 80#define FEATURE_ETH_BOOTMODE_SHIFT 2 81#define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2) 82#define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2) 83#define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2) 84#define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2) 85#define FEATURE_ETH_TOE_MASK 0x20 86 u32 lso_max_size; /* LSO MaxOffloadSize. */ 87 u32 lso_min_seg_cnt; /* LSO MinSegmentCount. */ 88 /* Num Offloaded Connections TCP_IPv4. */ 89 u32 ipv4_ofld_cnt; 90 /* Num Offloaded Connections TCP_IPv6. */ 91 u32 ipv6_ofld_cnt; 92 u32 promiscuous_mode; /* Promiscuous Mode. non-zero true */ 93 u32 txq_size; /* TX Descriptors Queue Size */ 94 u32 rxq_size; /* RX Descriptors Queue Size */ 95 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */ 96 u32 txq_avg_depth; 97 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */ 98 u32 rxq_avg_depth; 99 /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/ 100 u32 iov_offload; 101 /* Number of NetQueue/VMQ Config'd. */ 102 u32 netq_cnt; 103 u32 vf_cnt; /* Num VF assigned to this PF. */ 104}; 105 106/* Per PCI Function FCOE Statistics required from the driver */ 107struct fcoe_stats_info { 108 u8 version[12]; /* Function's Driver Version. */ 109 u8 mac_local[8]; /* Locally Admin Addr. */ 110 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 111 u8 mac_add2[8]; /* Additional Programmed MAC Addr 2. */ 112 /* QoS Priority (per 802.1p). 0-7255 */ 113 u32 qos_priority; 114 u32 txq_size; /* FCoE TX Descriptors Queue Size. */ 115 u32 rxq_size; /* FCoE RX Descriptors Queue Size. */ 116 /* FCoE TX Descriptor Queue Avg Depth. */ 117 u32 txq_avg_depth; 118 /* FCoE RX Descriptors Queue Avg Depth. */ 119 u32 rxq_avg_depth; 120 u32 rx_frames_lo; /* FCoE RX Frames received. */ 121 u32 rx_frames_hi; /* FCoE RX Frames received. */ 122 u32 rx_bytes_lo; /* FCoE RX Bytes received. */ 123 u32 rx_bytes_hi; /* FCoE RX Bytes received. */ 124 u32 tx_frames_lo; /* FCoE TX Frames sent. */ 125 u32 tx_frames_hi; /* FCoE TX Frames sent. */ 126 u32 tx_bytes_lo; /* FCoE TX Bytes sent. */ 127 u32 tx_bytes_hi; /* FCoE TX Bytes sent. */ 128}; 129 130/* Per PCI Function iSCSI Statistics required from the driver*/ 131struct iscsi_stats_info { 132 u8 version[12]; /* Function's Driver Version. */ 133 u8 mac_local[8]; /* Locally Admin iSCSI MAC Addr. */ 134 u8 mac_add1[8]; /* Additional Programmed MAC Addr 1. */ 135 /* QoS Priority (per 802.1p). 0-7255 */ 136 u32 qos_priority; 137 u8 initiator_name[64]; /* iSCSI Boot Initiator Node name. */ 138 u8 ww_port_name[64]; /* iSCSI World wide port name */ 139 u8 boot_target_name[64];/* iSCSI Boot Target Name. */ 140 u8 boot_target_ip[16]; /* iSCSI Boot Target IP. */ 141 u32 boot_target_portal; /* iSCSI Boot Target Portal. */ 142 u8 boot_init_ip[16]; /* iSCSI Boot Initiator IP Address. */ 143 u32 max_frame_size; /* Max Frame Size. bytes */ 144 u32 txq_size; /* PDU TX Descriptors Queue Size. */ 145 u32 rxq_size; /* PDU RX Descriptors Queue Size. */ 146 u32 txq_avg_depth; /* PDU TX Descriptor Queue Avg Depth. */ 147 u32 rxq_avg_depth; /* PDU RX Descriptors Queue Avg Depth. */ 148 u32 rx_pdus_lo; /* iSCSI PDUs received. */ 149 u32 rx_pdus_hi; /* iSCSI PDUs received. */ 150 u32 rx_bytes_lo; /* iSCSI RX Bytes received. */ 151 u32 rx_bytes_hi; /* iSCSI RX Bytes received. */ 152 u32 tx_pdus_lo; /* iSCSI PDUs sent. */ 153 u32 tx_pdus_hi; /* iSCSI PDUs sent. */ 154 u32 tx_bytes_lo; /* iSCSI PDU TX Bytes sent. */ 155 u32 tx_bytes_hi; /* iSCSI PDU TX Bytes sent. */ 156 u32 pcp_prior_map_tbl; /* C-PCP to S-PCP Priority MapTable. 157 * 9 nibbles, the position of each nibble 158 * represents the C-PCP value, the value 159 * of the nibble = S-PCP value. 160 */ 161}; 162 163union drv_info_to_mcp { 164 struct eth_stats_info ether_stat; 165 struct fcoe_stats_info fcoe_stat; 166 struct iscsi_stats_info iscsi_stat; 167}; 168#endif /* BNX2X_MFW_REQ_H */ 169