1/* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * 12 * Your platform definition file should specify something like: 13 * 14 * static struct at91_can_data ek_can_data = { 15 * transceiver_switch = sam9263ek_transceiver_switch, 16 * }; 17 * 18 * at91_add_device_can(&ek_can_data); 19 * 20 */ 21 22#include <linux/clk.h> 23#include <linux/errno.h> 24#include <linux/if_arp.h> 25#include <linux/interrupt.h> 26#include <linux/kernel.h> 27#include <linux/module.h> 28#include <linux/netdevice.h> 29#include <linux/of.h> 30#include <linux/platform_device.h> 31#include <linux/rtnetlink.h> 32#include <linux/skbuff.h> 33#include <linux/spinlock.h> 34#include <linux/string.h> 35#include <linux/types.h> 36#include <linux/platform_data/atmel.h> 37 38#include <linux/can/dev.h> 39#include <linux/can/error.h> 40#include <linux/can/led.h> 41 42#define AT91_MB_MASK(i) ((1 << (i)) - 1) 43 44/* Common registers */ 45enum at91_reg { 46 AT91_MR = 0x000, 47 AT91_IER = 0x004, 48 AT91_IDR = 0x008, 49 AT91_IMR = 0x00C, 50 AT91_SR = 0x010, 51 AT91_BR = 0x014, 52 AT91_TIM = 0x018, 53 AT91_TIMESTP = 0x01C, 54 AT91_ECR = 0x020, 55 AT91_TCR = 0x024, 56 AT91_ACR = 0x028, 57}; 58 59/* Mailbox registers (0 <= i <= 15) */ 60#define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 61#define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 62#define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 63#define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 64#define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 65#define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 66#define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 67#define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 68 69/* Register bits */ 70#define AT91_MR_CANEN BIT(0) 71#define AT91_MR_LPM BIT(1) 72#define AT91_MR_ABM BIT(2) 73#define AT91_MR_OVL BIT(3) 74#define AT91_MR_TEOF BIT(4) 75#define AT91_MR_TTM BIT(5) 76#define AT91_MR_TIMFRZ BIT(6) 77#define AT91_MR_DRPT BIT(7) 78 79#define AT91_SR_RBSY BIT(29) 80 81#define AT91_MMR_PRIO_SHIFT (16) 82 83#define AT91_MID_MIDE BIT(29) 84 85#define AT91_MSR_MRTR BIT(20) 86#define AT91_MSR_MABT BIT(22) 87#define AT91_MSR_MRDY BIT(23) 88#define AT91_MSR_MMI BIT(24) 89 90#define AT91_MCR_MRTR BIT(20) 91#define AT91_MCR_MTCR BIT(23) 92 93/* Mailbox Modes */ 94enum at91_mb_mode { 95 AT91_MB_MODE_DISABLED = 0, 96 AT91_MB_MODE_RX = 1, 97 AT91_MB_MODE_RX_OVRWR = 2, 98 AT91_MB_MODE_TX = 3, 99 AT91_MB_MODE_CONSUMER = 4, 100 AT91_MB_MODE_PRODUCER = 5, 101}; 102 103/* Interrupt mask bits */ 104#define AT91_IRQ_ERRA (1 << 16) 105#define AT91_IRQ_WARN (1 << 17) 106#define AT91_IRQ_ERRP (1 << 18) 107#define AT91_IRQ_BOFF (1 << 19) 108#define AT91_IRQ_SLEEP (1 << 20) 109#define AT91_IRQ_WAKEUP (1 << 21) 110#define AT91_IRQ_TOVF (1 << 22) 111#define AT91_IRQ_TSTP (1 << 23) 112#define AT91_IRQ_CERR (1 << 24) 113#define AT91_IRQ_SERR (1 << 25) 114#define AT91_IRQ_AERR (1 << 26) 115#define AT91_IRQ_FERR (1 << 27) 116#define AT91_IRQ_BERR (1 << 28) 117 118#define AT91_IRQ_ERR_ALL (0x1fff0000) 119#define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 120 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 121#define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 122 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 123 124#define AT91_IRQ_ALL (0x1fffffff) 125 126enum at91_devtype { 127 AT91_DEVTYPE_SAM9263, 128 AT91_DEVTYPE_SAM9X5, 129}; 130 131struct at91_devtype_data { 132 unsigned int rx_first; 133 unsigned int rx_split; 134 unsigned int rx_last; 135 unsigned int tx_shift; 136 enum at91_devtype type; 137}; 138 139struct at91_priv { 140 struct can_priv can; /* must be the first member! */ 141 struct napi_struct napi; 142 143 void __iomem *reg_base; 144 145 u32 reg_sr; 146 unsigned int tx_next; 147 unsigned int tx_echo; 148 unsigned int rx_next; 149 struct at91_devtype_data devtype_data; 150 151 struct clk *clk; 152 struct at91_can_data *pdata; 153 154 canid_t mb0_id; 155}; 156 157static const struct at91_devtype_data at91_at91sam9263_data = { 158 .rx_first = 1, 159 .rx_split = 8, 160 .rx_last = 11, 161 .tx_shift = 2, 162 .type = AT91_DEVTYPE_SAM9263, 163}; 164 165static const struct at91_devtype_data at91_at91sam9x5_data = { 166 .rx_first = 0, 167 .rx_split = 4, 168 .rx_last = 5, 169 .tx_shift = 1, 170 .type = AT91_DEVTYPE_SAM9X5, 171}; 172 173static const struct can_bittiming_const at91_bittiming_const = { 174 .name = KBUILD_MODNAME, 175 .tseg1_min = 4, 176 .tseg1_max = 16, 177 .tseg2_min = 2, 178 .tseg2_max = 8, 179 .sjw_max = 4, 180 .brp_min = 2, 181 .brp_max = 128, 182 .brp_inc = 1, 183}; 184 185#define AT91_IS(_model) \ 186static inline int at91_is_sam##_model(const struct at91_priv *priv) \ 187{ \ 188 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ 189} 190 191AT91_IS(9263); 192AT91_IS(9X5); 193 194static inline unsigned int get_mb_rx_first(const struct at91_priv *priv) 195{ 196 return priv->devtype_data.rx_first; 197} 198 199static inline unsigned int get_mb_rx_last(const struct at91_priv *priv) 200{ 201 return priv->devtype_data.rx_last; 202} 203 204static inline unsigned int get_mb_rx_split(const struct at91_priv *priv) 205{ 206 return priv->devtype_data.rx_split; 207} 208 209static inline unsigned int get_mb_rx_num(const struct at91_priv *priv) 210{ 211 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1; 212} 213 214static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 215{ 216 return get_mb_rx_split(priv) - 1; 217} 218 219static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 220{ 221 return AT91_MB_MASK(get_mb_rx_split(priv)) & 222 ~AT91_MB_MASK(get_mb_rx_first(priv)); 223} 224 225static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv) 226{ 227 return priv->devtype_data.tx_shift; 228} 229 230static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 231{ 232 return 1 << get_mb_tx_shift(priv); 233} 234 235static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 236{ 237 return get_mb_rx_last(priv) + 1; 238} 239 240static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 241{ 242 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 243} 244 245static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 246{ 247 return get_mb_tx_shift(priv); 248} 249 250static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 251{ 252 return 0xf << get_mb_tx_shift(priv); 253} 254 255static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 256{ 257 return AT91_MB_MASK(get_mb_tx_shift(priv)); 258} 259 260static inline unsigned int get_next_mask(const struct at91_priv *priv) 261{ 262 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 263} 264 265static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 266{ 267 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) & 268 ~AT91_MB_MASK(get_mb_rx_first(priv)); 269} 270 271static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 272{ 273 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 274 ~AT91_MB_MASK(get_mb_tx_first(priv)); 275} 276 277static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 278{ 279 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 280} 281 282static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 283{ 284 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 285} 286 287static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 288{ 289 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 290} 291 292static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 293{ 294 return readl_relaxed(priv->reg_base + reg); 295} 296 297static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 298 u32 value) 299{ 300 writel_relaxed(value, priv->reg_base + reg); 301} 302 303static inline void set_mb_mode_prio(const struct at91_priv *priv, 304 unsigned int mb, enum at91_mb_mode mode, int prio) 305{ 306 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 307} 308 309static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 310 enum at91_mb_mode mode) 311{ 312 set_mb_mode_prio(priv, mb, mode, 0); 313} 314 315static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 316{ 317 u32 reg_mid; 318 319 if (can_id & CAN_EFF_FLAG) 320 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 321 else 322 reg_mid = (can_id & CAN_SFF_MASK) << 18; 323 324 return reg_mid; 325} 326 327/* 328 * Swtich transceiver on or off 329 */ 330static void at91_transceiver_switch(const struct at91_priv *priv, int on) 331{ 332 if (priv->pdata && priv->pdata->transceiver_switch) 333 priv->pdata->transceiver_switch(on); 334} 335 336static void at91_setup_mailboxes(struct net_device *dev) 337{ 338 struct at91_priv *priv = netdev_priv(dev); 339 unsigned int i; 340 u32 reg_mid; 341 342 /* 343 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 344 * mailbox is disabled. The next 11 mailboxes are used as a 345 * reception FIFO. The last mailbox is configured with 346 * overwrite option. The overwrite flag indicates a FIFO 347 * overflow. 348 */ 349 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 350 for (i = 0; i < get_mb_rx_first(priv); i++) { 351 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 352 at91_write(priv, AT91_MID(i), reg_mid); 353 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 354 } 355 356 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++) 357 set_mb_mode(priv, i, AT91_MB_MODE_RX); 358 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR); 359 360 /* reset acceptance mask and id register */ 361 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) { 362 at91_write(priv, AT91_MAM(i), 0x0); 363 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 364 } 365 366 /* The last 4 mailboxes are used for transmitting. */ 367 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 368 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 369 370 /* Reset tx and rx helper pointers */ 371 priv->tx_next = priv->tx_echo = 0; 372 priv->rx_next = get_mb_rx_first(priv); 373} 374 375static int at91_set_bittiming(struct net_device *dev) 376{ 377 const struct at91_priv *priv = netdev_priv(dev); 378 const struct can_bittiming *bt = &priv->can.bittiming; 379 u32 reg_br; 380 381 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 382 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 383 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 384 ((bt->phase_seg2 - 1) << 0); 385 386 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 387 388 at91_write(priv, AT91_BR, reg_br); 389 390 return 0; 391} 392 393static int at91_get_berr_counter(const struct net_device *dev, 394 struct can_berr_counter *bec) 395{ 396 const struct at91_priv *priv = netdev_priv(dev); 397 u32 reg_ecr = at91_read(priv, AT91_ECR); 398 399 bec->rxerr = reg_ecr & 0xff; 400 bec->txerr = reg_ecr >> 16; 401 402 return 0; 403} 404 405static void at91_chip_start(struct net_device *dev) 406{ 407 struct at91_priv *priv = netdev_priv(dev); 408 u32 reg_mr, reg_ier; 409 410 /* disable interrupts */ 411 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 412 413 /* disable chip */ 414 reg_mr = at91_read(priv, AT91_MR); 415 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 416 417 at91_set_bittiming(dev); 418 at91_setup_mailboxes(dev); 419 at91_transceiver_switch(priv, 1); 420 421 /* enable chip */ 422 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 423 reg_mr = AT91_MR_CANEN | AT91_MR_ABM; 424 else 425 reg_mr = AT91_MR_CANEN; 426 at91_write(priv, AT91_MR, reg_mr); 427 428 priv->can.state = CAN_STATE_ERROR_ACTIVE; 429 430 /* Enable interrupts */ 431 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 432 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 433 at91_write(priv, AT91_IER, reg_ier); 434} 435 436static void at91_chip_stop(struct net_device *dev, enum can_state state) 437{ 438 struct at91_priv *priv = netdev_priv(dev); 439 u32 reg_mr; 440 441 /* disable interrupts */ 442 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 443 444 reg_mr = at91_read(priv, AT91_MR); 445 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 446 447 at91_transceiver_switch(priv, 0); 448 priv->can.state = state; 449} 450 451/* 452 * theory of operation: 453 * 454 * According to the datasheet priority 0 is the highest priority, 15 455 * is the lowest. If two mailboxes have the same priority level the 456 * message of the mailbox with the lowest number is sent first. 457 * 458 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 459 * the next mailbox with prio 0, and so on, until all mailboxes are 460 * used. Then we start from the beginning with mailbox 461 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 462 * prio 1. When we reach the last mailbox with prio 15, we have to 463 * stop sending, waiting for all messages to be delivered, then start 464 * again with mailbox AT91_MB_TX_FIRST prio 0. 465 * 466 * We use the priv->tx_next as counter for the next transmission 467 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 468 * encode the mailbox number, the upper 4 bits the mailbox priority: 469 * 470 * priv->tx_next = (prio << get_next_prio_shift(priv)) | 471 * (mb - get_mb_tx_first(priv)); 472 * 473 */ 474static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 475{ 476 struct at91_priv *priv = netdev_priv(dev); 477 struct net_device_stats *stats = &dev->stats; 478 struct can_frame *cf = (struct can_frame *)skb->data; 479 unsigned int mb, prio; 480 u32 reg_mid, reg_mcr; 481 482 if (can_dropped_invalid_skb(dev, skb)) 483 return NETDEV_TX_OK; 484 485 mb = get_tx_next_mb(priv); 486 prio = get_tx_next_prio(priv); 487 488 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 489 netif_stop_queue(dev); 490 491 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 492 return NETDEV_TX_BUSY; 493 } 494 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 495 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 496 (cf->can_dlc << 16) | AT91_MCR_MTCR; 497 498 /* disable MB while writing ID (see datasheet) */ 499 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 500 at91_write(priv, AT91_MID(mb), reg_mid); 501 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 502 503 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 504 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 505 506 /* This triggers transmission */ 507 at91_write(priv, AT91_MCR(mb), reg_mcr); 508 509 stats->tx_bytes += cf->can_dlc; 510 511 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 512 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv)); 513 514 /* 515 * we have to stop the queue and deliver all messages in case 516 * of a prio+mb counter wrap around. This is the case if 517 * tx_next buffer prio and mailbox equals 0. 518 * 519 * also stop the queue if next buffer is still in use 520 * (== not ready) 521 */ 522 priv->tx_next++; 523 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 524 AT91_MSR_MRDY) || 525 (priv->tx_next & get_next_mask(priv)) == 0) 526 netif_stop_queue(dev); 527 528 /* Enable interrupt for this mailbox */ 529 at91_write(priv, AT91_IER, 1 << mb); 530 531 return NETDEV_TX_OK; 532} 533 534/** 535 * at91_activate_rx_low - activate lower rx mailboxes 536 * @priv: a91 context 537 * 538 * Reenables the lower mailboxes for reception of new CAN messages 539 */ 540static inline void at91_activate_rx_low(const struct at91_priv *priv) 541{ 542 u32 mask = get_mb_rx_low_mask(priv); 543 at91_write(priv, AT91_TCR, mask); 544} 545 546/** 547 * at91_activate_rx_mb - reactive single rx mailbox 548 * @priv: a91 context 549 * @mb: mailbox to reactivate 550 * 551 * Reenables given mailbox for reception of new CAN messages 552 */ 553static inline void at91_activate_rx_mb(const struct at91_priv *priv, 554 unsigned int mb) 555{ 556 u32 mask = 1 << mb; 557 at91_write(priv, AT91_TCR, mask); 558} 559 560/** 561 * at91_rx_overflow_err - send error frame due to rx overflow 562 * @dev: net device 563 */ 564static void at91_rx_overflow_err(struct net_device *dev) 565{ 566 struct net_device_stats *stats = &dev->stats; 567 struct sk_buff *skb; 568 struct can_frame *cf; 569 570 netdev_dbg(dev, "RX buffer overflow\n"); 571 stats->rx_over_errors++; 572 stats->rx_errors++; 573 574 skb = alloc_can_err_skb(dev, &cf); 575 if (unlikely(!skb)) 576 return; 577 578 cf->can_id |= CAN_ERR_CRTL; 579 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 580 netif_receive_skb(skb); 581 582 stats->rx_packets++; 583 stats->rx_bytes += cf->can_dlc; 584} 585 586/** 587 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 588 * @dev: net device 589 * @mb: mailbox number to read from 590 * @cf: can frame where to store message 591 * 592 * Reads a CAN message from the given mailbox and stores data into 593 * given can frame. "mb" and "cf" must be valid. 594 */ 595static void at91_read_mb(struct net_device *dev, unsigned int mb, 596 struct can_frame *cf) 597{ 598 const struct at91_priv *priv = netdev_priv(dev); 599 u32 reg_msr, reg_mid; 600 601 reg_mid = at91_read(priv, AT91_MID(mb)); 602 if (reg_mid & AT91_MID_MIDE) 603 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 604 else 605 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 606 607 reg_msr = at91_read(priv, AT91_MSR(mb)); 608 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 609 610 if (reg_msr & AT91_MSR_MRTR) 611 cf->can_id |= CAN_RTR_FLAG; 612 else { 613 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 614 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 615 } 616 617 /* allow RX of extended frames */ 618 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 619 620 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI)) 621 at91_rx_overflow_err(dev); 622} 623 624/** 625 * at91_read_msg - read CAN message from mailbox 626 * @dev: net device 627 * @mb: mail box to read from 628 * 629 * Reads a CAN message from given mailbox, and put into linux network 630 * RX queue, does all housekeeping chores (stats, ...) 631 */ 632static void at91_read_msg(struct net_device *dev, unsigned int mb) 633{ 634 struct net_device_stats *stats = &dev->stats; 635 struct can_frame *cf; 636 struct sk_buff *skb; 637 638 skb = alloc_can_skb(dev, &cf); 639 if (unlikely(!skb)) { 640 stats->rx_dropped++; 641 return; 642 } 643 644 at91_read_mb(dev, mb, cf); 645 netif_receive_skb(skb); 646 647 stats->rx_packets++; 648 stats->rx_bytes += cf->can_dlc; 649 650 can_led_event(dev, CAN_LED_EVENT_RX); 651} 652 653/** 654 * at91_poll_rx - read multiple CAN messages from mailboxes 655 * @dev: net device 656 * @quota: max number of pkgs we're allowed to receive 657 * 658 * Theory of Operation: 659 * 660 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last()) 661 * on the chip are reserved for RX. We split them into 2 groups. The 662 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last(). 663 * 664 * Like it or not, but the chip always saves a received CAN message 665 * into the first free mailbox it finds (starting with the 666 * lowest). This makes it very difficult to read the messages in the 667 * right order from the chip. This is how we work around that problem: 668 * 669 * The first message goes into mb nr. 1 and issues an interrupt. All 670 * rx ints are disabled in the interrupt handler and a napi poll is 671 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 672 * receive another message). 673 * 674 * lower mbxs upper 675 * ____^______ __^__ 676 * / \ / \ 677 * +-+-+-+-+-+-+-+-++-+-+-+-+ 678 * | |x|x|x|x|x|x|x|| | | | | 679 * +-+-+-+-+-+-+-+-++-+-+-+-+ 680 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 681 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 682 * ^ 683 * | 684 * \ 685 * unused, due to chip bug 686 * 687 * The variable priv->rx_next points to the next mailbox to read a 688 * message from. As long we're in the lower mailboxes we just read the 689 * mailbox but not reenable it. 690 * 691 * With completion of the last of the lower mailboxes, we reenable the 692 * whole first group, but continue to look for filled mailboxes in the 693 * upper mailboxes. Imagine the second group like overflow mailboxes, 694 * which takes CAN messages if the lower goup is full. While in the 695 * upper group we reenable the mailbox right after reading it. Giving 696 * the chip more room to store messages. 697 * 698 * After finishing we look again in the lower group if we've still 699 * quota. 700 * 701 */ 702static int at91_poll_rx(struct net_device *dev, int quota) 703{ 704 struct at91_priv *priv = netdev_priv(dev); 705 u32 reg_sr = at91_read(priv, AT91_SR); 706 const unsigned long *addr = (unsigned long *)®_sr; 707 unsigned int mb; 708 int received = 0; 709 710 if (priv->rx_next > get_mb_rx_low_last(priv) && 711 reg_sr & get_mb_rx_low_mask(priv)) 712 netdev_info(dev, 713 "order of incoming frames cannot be guaranteed\n"); 714 715 again: 716 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 717 mb < get_mb_tx_first(priv) && quota > 0; 718 reg_sr = at91_read(priv, AT91_SR), 719 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 720 at91_read_msg(dev, mb); 721 722 /* reactivate mailboxes */ 723 if (mb == get_mb_rx_low_last(priv)) 724 /* all lower mailboxed, if just finished it */ 725 at91_activate_rx_low(priv); 726 else if (mb > get_mb_rx_low_last(priv)) 727 /* only the mailbox we read */ 728 at91_activate_rx_mb(priv, mb); 729 730 received++; 731 quota--; 732 } 733 734 /* upper group completed, look again in lower */ 735 if (priv->rx_next > get_mb_rx_low_last(priv) && 736 quota > 0 && mb > get_mb_rx_last(priv)) { 737 priv->rx_next = get_mb_rx_first(priv); 738 goto again; 739 } 740 741 return received; 742} 743 744static void at91_poll_err_frame(struct net_device *dev, 745 struct can_frame *cf, u32 reg_sr) 746{ 747 struct at91_priv *priv = netdev_priv(dev); 748 749 /* CRC error */ 750 if (reg_sr & AT91_IRQ_CERR) { 751 netdev_dbg(dev, "CERR irq\n"); 752 dev->stats.rx_errors++; 753 priv->can.can_stats.bus_error++; 754 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 755 } 756 757 /* Stuffing Error */ 758 if (reg_sr & AT91_IRQ_SERR) { 759 netdev_dbg(dev, "SERR irq\n"); 760 dev->stats.rx_errors++; 761 priv->can.can_stats.bus_error++; 762 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 763 cf->data[2] |= CAN_ERR_PROT_STUFF; 764 } 765 766 /* Acknowledgement Error */ 767 if (reg_sr & AT91_IRQ_AERR) { 768 netdev_dbg(dev, "AERR irq\n"); 769 dev->stats.tx_errors++; 770 cf->can_id |= CAN_ERR_ACK; 771 } 772 773 /* Form error */ 774 if (reg_sr & AT91_IRQ_FERR) { 775 netdev_dbg(dev, "FERR irq\n"); 776 dev->stats.rx_errors++; 777 priv->can.can_stats.bus_error++; 778 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 779 cf->data[2] |= CAN_ERR_PROT_FORM; 780 } 781 782 /* Bit Error */ 783 if (reg_sr & AT91_IRQ_BERR) { 784 netdev_dbg(dev, "BERR irq\n"); 785 dev->stats.tx_errors++; 786 priv->can.can_stats.bus_error++; 787 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 788 cf->data[2] |= CAN_ERR_PROT_BIT; 789 } 790} 791 792static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 793{ 794 struct sk_buff *skb; 795 struct can_frame *cf; 796 797 if (quota == 0) 798 return 0; 799 800 skb = alloc_can_err_skb(dev, &cf); 801 if (unlikely(!skb)) 802 return 0; 803 804 at91_poll_err_frame(dev, cf, reg_sr); 805 netif_receive_skb(skb); 806 807 dev->stats.rx_packets++; 808 dev->stats.rx_bytes += cf->can_dlc; 809 810 return 1; 811} 812 813static int at91_poll(struct napi_struct *napi, int quota) 814{ 815 struct net_device *dev = napi->dev; 816 const struct at91_priv *priv = netdev_priv(dev); 817 u32 reg_sr = at91_read(priv, AT91_SR); 818 int work_done = 0; 819 820 if (reg_sr & get_irq_mb_rx(priv)) 821 work_done += at91_poll_rx(dev, quota - work_done); 822 823 /* 824 * The error bits are clear on read, 825 * so use saved value from irq handler. 826 */ 827 reg_sr |= priv->reg_sr; 828 if (reg_sr & AT91_IRQ_ERR_FRAME) 829 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 830 831 if (work_done < quota) { 832 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 833 u32 reg_ier = AT91_IRQ_ERR_FRAME; 834 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 835 836 napi_complete(napi); 837 at91_write(priv, AT91_IER, reg_ier); 838 } 839 840 return work_done; 841} 842 843/* 844 * theory of operation: 845 * 846 * priv->tx_echo holds the number of the oldest can_frame put for 847 * transmission into the hardware, but not yet ACKed by the CAN tx 848 * complete IRQ. 849 * 850 * We iterate from priv->tx_echo to priv->tx_next and check if the 851 * packet has been transmitted, echo it back to the CAN framework. If 852 * we discover a not yet transmitted package, stop looking for more. 853 * 854 */ 855static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 856{ 857 struct at91_priv *priv = netdev_priv(dev); 858 u32 reg_msr; 859 unsigned int mb; 860 861 /* masking of reg_sr not needed, already done by at91_irq */ 862 863 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 864 mb = get_tx_echo_mb(priv); 865 866 /* no event in mailbox? */ 867 if (!(reg_sr & (1 << mb))) 868 break; 869 870 /* Disable irq for this TX mailbox */ 871 at91_write(priv, AT91_IDR, 1 << mb); 872 873 /* 874 * only echo if mailbox signals us a transfer 875 * complete (MSR_MRDY). Otherwise it's a tansfer 876 * abort. "can_bus_off()" takes care about the skbs 877 * parked in the echo queue. 878 */ 879 reg_msr = at91_read(priv, AT91_MSR(mb)); 880 if (likely(reg_msr & AT91_MSR_MRDY && 881 ~reg_msr & AT91_MSR_MABT)) { 882 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 883 can_get_echo_skb(dev, mb - get_mb_tx_first(priv)); 884 dev->stats.tx_packets++; 885 can_led_event(dev, CAN_LED_EVENT_TX); 886 } 887 } 888 889 /* 890 * restart queue if we don't have a wrap around but restart if 891 * we get a TX int for the last can frame directly before a 892 * wrap around. 893 */ 894 if ((priv->tx_next & get_next_mask(priv)) != 0 || 895 (priv->tx_echo & get_next_mask(priv)) == 0) 896 netif_wake_queue(dev); 897} 898 899static void at91_irq_err_state(struct net_device *dev, 900 struct can_frame *cf, enum can_state new_state) 901{ 902 struct at91_priv *priv = netdev_priv(dev); 903 u32 reg_idr = 0, reg_ier = 0; 904 struct can_berr_counter bec; 905 906 at91_get_berr_counter(dev, &bec); 907 908 switch (priv->can.state) { 909 case CAN_STATE_ERROR_ACTIVE: 910 /* 911 * from: ERROR_ACTIVE 912 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 913 * => : there was a warning int 914 */ 915 if (new_state >= CAN_STATE_ERROR_WARNING && 916 new_state <= CAN_STATE_BUS_OFF) { 917 netdev_dbg(dev, "Error Warning IRQ\n"); 918 priv->can.can_stats.error_warning++; 919 920 cf->can_id |= CAN_ERR_CRTL; 921 cf->data[1] = (bec.txerr > bec.rxerr) ? 922 CAN_ERR_CRTL_TX_WARNING : 923 CAN_ERR_CRTL_RX_WARNING; 924 } 925 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 926 /* 927 * from: ERROR_ACTIVE, ERROR_WARNING 928 * to : ERROR_PASSIVE, BUS_OFF 929 * => : error passive int 930 */ 931 if (new_state >= CAN_STATE_ERROR_PASSIVE && 932 new_state <= CAN_STATE_BUS_OFF) { 933 netdev_dbg(dev, "Error Passive IRQ\n"); 934 priv->can.can_stats.error_passive++; 935 936 cf->can_id |= CAN_ERR_CRTL; 937 cf->data[1] = (bec.txerr > bec.rxerr) ? 938 CAN_ERR_CRTL_TX_PASSIVE : 939 CAN_ERR_CRTL_RX_PASSIVE; 940 } 941 break; 942 case CAN_STATE_BUS_OFF: 943 /* 944 * from: BUS_OFF 945 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 946 */ 947 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 948 cf->can_id |= CAN_ERR_RESTARTED; 949 950 netdev_dbg(dev, "restarted\n"); 951 priv->can.can_stats.restarts++; 952 953 netif_carrier_on(dev); 954 netif_wake_queue(dev); 955 } 956 break; 957 default: 958 break; 959 } 960 961 962 /* process state changes depending on the new state */ 963 switch (new_state) { 964 case CAN_STATE_ERROR_ACTIVE: 965 /* 966 * actually we want to enable AT91_IRQ_WARN here, but 967 * it screws up the system under certain 968 * circumstances. so just enable AT91_IRQ_ERRP, thus 969 * the "fallthrough" 970 */ 971 netdev_dbg(dev, "Error Active\n"); 972 cf->can_id |= CAN_ERR_PROT; 973 cf->data[2] = CAN_ERR_PROT_ACTIVE; 974 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 975 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 976 reg_ier = AT91_IRQ_ERRP; 977 break; 978 case CAN_STATE_ERROR_PASSIVE: 979 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 980 reg_ier = AT91_IRQ_BOFF; 981 break; 982 case CAN_STATE_BUS_OFF: 983 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 984 AT91_IRQ_WARN | AT91_IRQ_BOFF; 985 reg_ier = 0; 986 987 cf->can_id |= CAN_ERR_BUSOFF; 988 989 netdev_dbg(dev, "bus-off\n"); 990 netif_carrier_off(dev); 991 priv->can.can_stats.bus_off++; 992 993 /* turn off chip, if restart is disabled */ 994 if (!priv->can.restart_ms) { 995 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 996 return; 997 } 998 break; 999 default: 1000 break; 1001 } 1002 1003 at91_write(priv, AT91_IDR, reg_idr); 1004 at91_write(priv, AT91_IER, reg_ier); 1005} 1006 1007static int at91_get_state_by_bec(const struct net_device *dev, 1008 enum can_state *state) 1009{ 1010 struct can_berr_counter bec; 1011 int err; 1012 1013 err = at91_get_berr_counter(dev, &bec); 1014 if (err) 1015 return err; 1016 1017 if (bec.txerr < 96 && bec.rxerr < 96) 1018 *state = CAN_STATE_ERROR_ACTIVE; 1019 else if (bec.txerr < 128 && bec.rxerr < 128) 1020 *state = CAN_STATE_ERROR_WARNING; 1021 else if (bec.txerr < 256 && bec.rxerr < 256) 1022 *state = CAN_STATE_ERROR_PASSIVE; 1023 else 1024 *state = CAN_STATE_BUS_OFF; 1025 1026 return 0; 1027} 1028 1029 1030static void at91_irq_err(struct net_device *dev) 1031{ 1032 struct at91_priv *priv = netdev_priv(dev); 1033 struct sk_buff *skb; 1034 struct can_frame *cf; 1035 enum can_state new_state; 1036 u32 reg_sr; 1037 int err; 1038 1039 if (at91_is_sam9263(priv)) { 1040 reg_sr = at91_read(priv, AT91_SR); 1041 1042 /* we need to look at the unmasked reg_sr */ 1043 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 1044 new_state = CAN_STATE_BUS_OFF; 1045 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 1046 new_state = CAN_STATE_ERROR_PASSIVE; 1047 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 1048 new_state = CAN_STATE_ERROR_WARNING; 1049 else if (likely(reg_sr & AT91_IRQ_ERRA)) 1050 new_state = CAN_STATE_ERROR_ACTIVE; 1051 else { 1052 netdev_err(dev, "BUG! hardware in undefined state\n"); 1053 return; 1054 } 1055 } else { 1056 err = at91_get_state_by_bec(dev, &new_state); 1057 if (err) 1058 return; 1059 } 1060 1061 /* state hasn't changed */ 1062 if (likely(new_state == priv->can.state)) 1063 return; 1064 1065 skb = alloc_can_err_skb(dev, &cf); 1066 if (unlikely(!skb)) 1067 return; 1068 1069 at91_irq_err_state(dev, cf, new_state); 1070 netif_rx(skb); 1071 1072 dev->stats.rx_packets++; 1073 dev->stats.rx_bytes += cf->can_dlc; 1074 1075 priv->can.state = new_state; 1076} 1077 1078/* 1079 * interrupt handler 1080 */ 1081static irqreturn_t at91_irq(int irq, void *dev_id) 1082{ 1083 struct net_device *dev = dev_id; 1084 struct at91_priv *priv = netdev_priv(dev); 1085 irqreturn_t handled = IRQ_NONE; 1086 u32 reg_sr, reg_imr; 1087 1088 reg_sr = at91_read(priv, AT91_SR); 1089 reg_imr = at91_read(priv, AT91_IMR); 1090 1091 /* Ignore masked interrupts */ 1092 reg_sr &= reg_imr; 1093 if (!reg_sr) 1094 goto exit; 1095 1096 handled = IRQ_HANDLED; 1097 1098 /* Receive or error interrupt? -> napi */ 1099 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1100 /* 1101 * The error bits are clear on read, 1102 * save for later use. 1103 */ 1104 priv->reg_sr = reg_sr; 1105 at91_write(priv, AT91_IDR, 1106 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1107 napi_schedule(&priv->napi); 1108 } 1109 1110 /* Transmission complete interrupt */ 1111 if (reg_sr & get_irq_mb_tx(priv)) 1112 at91_irq_tx(dev, reg_sr); 1113 1114 at91_irq_err(dev); 1115 1116 exit: 1117 return handled; 1118} 1119 1120static int at91_open(struct net_device *dev) 1121{ 1122 struct at91_priv *priv = netdev_priv(dev); 1123 int err; 1124 1125 err = clk_prepare_enable(priv->clk); 1126 if (err) 1127 return err; 1128 1129 /* check or determine and set bittime */ 1130 err = open_candev(dev); 1131 if (err) 1132 goto out; 1133 1134 /* register interrupt handler */ 1135 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1136 dev->name, dev)) { 1137 err = -EAGAIN; 1138 goto out_close; 1139 } 1140 1141 can_led_event(dev, CAN_LED_EVENT_OPEN); 1142 1143 /* start chip and queuing */ 1144 at91_chip_start(dev); 1145 napi_enable(&priv->napi); 1146 netif_start_queue(dev); 1147 1148 return 0; 1149 1150 out_close: 1151 close_candev(dev); 1152 out: 1153 clk_disable_unprepare(priv->clk); 1154 1155 return err; 1156} 1157 1158/* 1159 * stop CAN bus activity 1160 */ 1161static int at91_close(struct net_device *dev) 1162{ 1163 struct at91_priv *priv = netdev_priv(dev); 1164 1165 netif_stop_queue(dev); 1166 napi_disable(&priv->napi); 1167 at91_chip_stop(dev, CAN_STATE_STOPPED); 1168 1169 free_irq(dev->irq, dev); 1170 clk_disable_unprepare(priv->clk); 1171 1172 close_candev(dev); 1173 1174 can_led_event(dev, CAN_LED_EVENT_STOP); 1175 1176 return 0; 1177} 1178 1179static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1180{ 1181 switch (mode) { 1182 case CAN_MODE_START: 1183 at91_chip_start(dev); 1184 netif_wake_queue(dev); 1185 break; 1186 1187 default: 1188 return -EOPNOTSUPP; 1189 } 1190 1191 return 0; 1192} 1193 1194static const struct net_device_ops at91_netdev_ops = { 1195 .ndo_open = at91_open, 1196 .ndo_stop = at91_close, 1197 .ndo_start_xmit = at91_start_xmit, 1198 .ndo_change_mtu = can_change_mtu, 1199}; 1200 1201static ssize_t at91_sysfs_show_mb0_id(struct device *dev, 1202 struct device_attribute *attr, char *buf) 1203{ 1204 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1205 1206 if (priv->mb0_id & CAN_EFF_FLAG) 1207 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); 1208 else 1209 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); 1210} 1211 1212static ssize_t at91_sysfs_set_mb0_id(struct device *dev, 1213 struct device_attribute *attr, const char *buf, size_t count) 1214{ 1215 struct net_device *ndev = to_net_dev(dev); 1216 struct at91_priv *priv = netdev_priv(ndev); 1217 unsigned long can_id; 1218 ssize_t ret; 1219 int err; 1220 1221 rtnl_lock(); 1222 1223 if (ndev->flags & IFF_UP) { 1224 ret = -EBUSY; 1225 goto out; 1226 } 1227 1228 err = kstrtoul(buf, 0, &can_id); 1229 if (err) { 1230 ret = err; 1231 goto out; 1232 } 1233 1234 if (can_id & CAN_EFF_FLAG) 1235 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1236 else 1237 can_id &= CAN_SFF_MASK; 1238 1239 priv->mb0_id = can_id; 1240 ret = count; 1241 1242 out: 1243 rtnl_unlock(); 1244 return ret; 1245} 1246 1247static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, 1248 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); 1249 1250static struct attribute *at91_sysfs_attrs[] = { 1251 &dev_attr_mb0_id.attr, 1252 NULL, 1253}; 1254 1255static struct attribute_group at91_sysfs_attr_group = { 1256 .attrs = at91_sysfs_attrs, 1257}; 1258 1259#if defined(CONFIG_OF) 1260static const struct of_device_id at91_can_dt_ids[] = { 1261 { 1262 .compatible = "atmel,at91sam9x5-can", 1263 .data = &at91_at91sam9x5_data, 1264 }, { 1265 .compatible = "atmel,at91sam9263-can", 1266 .data = &at91_at91sam9263_data, 1267 }, { 1268 /* sentinel */ 1269 } 1270}; 1271MODULE_DEVICE_TABLE(of, at91_can_dt_ids); 1272#endif 1273 1274static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev) 1275{ 1276 if (pdev->dev.of_node) { 1277 const struct of_device_id *match; 1278 1279 match = of_match_node(at91_can_dt_ids, pdev->dev.of_node); 1280 if (!match) { 1281 dev_err(&pdev->dev, "no matching node found in dtb\n"); 1282 return NULL; 1283 } 1284 return (const struct at91_devtype_data *)match->data; 1285 } 1286 return (const struct at91_devtype_data *) 1287 platform_get_device_id(pdev)->driver_data; 1288} 1289 1290static int at91_can_probe(struct platform_device *pdev) 1291{ 1292 const struct at91_devtype_data *devtype_data; 1293 struct net_device *dev; 1294 struct at91_priv *priv; 1295 struct resource *res; 1296 struct clk *clk; 1297 void __iomem *addr; 1298 int err, irq; 1299 1300 devtype_data = at91_can_get_driver_data(pdev); 1301 if (!devtype_data) { 1302 dev_err(&pdev->dev, "no driver data\n"); 1303 err = -ENODEV; 1304 goto exit; 1305 } 1306 1307 clk = clk_get(&pdev->dev, "can_clk"); 1308 if (IS_ERR(clk)) { 1309 dev_err(&pdev->dev, "no clock defined\n"); 1310 err = -ENODEV; 1311 goto exit; 1312 } 1313 1314 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1315 irq = platform_get_irq(pdev, 0); 1316 if (!res || irq <= 0) { 1317 err = -ENODEV; 1318 goto exit_put; 1319 } 1320 1321 if (!request_mem_region(res->start, 1322 resource_size(res), 1323 pdev->name)) { 1324 err = -EBUSY; 1325 goto exit_put; 1326 } 1327 1328 addr = ioremap_nocache(res->start, resource_size(res)); 1329 if (!addr) { 1330 err = -ENOMEM; 1331 goto exit_release; 1332 } 1333 1334 dev = alloc_candev(sizeof(struct at91_priv), 1335 1 << devtype_data->tx_shift); 1336 if (!dev) { 1337 err = -ENOMEM; 1338 goto exit_iounmap; 1339 } 1340 1341 dev->netdev_ops = &at91_netdev_ops; 1342 dev->irq = irq; 1343 dev->flags |= IFF_ECHO; 1344 1345 priv = netdev_priv(dev); 1346 priv->can.clock.freq = clk_get_rate(clk); 1347 priv->can.bittiming_const = &at91_bittiming_const; 1348 priv->can.do_set_mode = at91_set_mode; 1349 priv->can.do_get_berr_counter = at91_get_berr_counter; 1350 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | 1351 CAN_CTRLMODE_LISTENONLY; 1352 priv->reg_base = addr; 1353 priv->devtype_data = *devtype_data; 1354 priv->clk = clk; 1355 priv->pdata = dev_get_platdata(&pdev->dev); 1356 priv->mb0_id = 0x7ff; 1357 1358 netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv)); 1359 1360 if (at91_is_sam9263(priv)) 1361 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1362 1363 platform_set_drvdata(pdev, dev); 1364 SET_NETDEV_DEV(dev, &pdev->dev); 1365 1366 err = register_candev(dev); 1367 if (err) { 1368 dev_err(&pdev->dev, "registering netdev failed\n"); 1369 goto exit_free; 1370 } 1371 1372 devm_can_led_init(dev); 1373 1374 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1375 priv->reg_base, dev->irq); 1376 1377 return 0; 1378 1379 exit_free: 1380 free_candev(dev); 1381 exit_iounmap: 1382 iounmap(addr); 1383 exit_release: 1384 release_mem_region(res->start, resource_size(res)); 1385 exit_put: 1386 clk_put(clk); 1387 exit: 1388 return err; 1389} 1390 1391static int at91_can_remove(struct platform_device *pdev) 1392{ 1393 struct net_device *dev = platform_get_drvdata(pdev); 1394 struct at91_priv *priv = netdev_priv(dev); 1395 struct resource *res; 1396 1397 unregister_netdev(dev); 1398 1399 iounmap(priv->reg_base); 1400 1401 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1402 release_mem_region(res->start, resource_size(res)); 1403 1404 clk_put(priv->clk); 1405 1406 free_candev(dev); 1407 1408 return 0; 1409} 1410 1411static const struct platform_device_id at91_can_id_table[] = { 1412 { 1413 .name = "at91sam9x5_can", 1414 .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data, 1415 }, { 1416 .name = "at91_can", 1417 .driver_data = (kernel_ulong_t)&at91_at91sam9263_data, 1418 }, { 1419 /* sentinel */ 1420 } 1421}; 1422MODULE_DEVICE_TABLE(platform, at91_can_id_table); 1423 1424static struct platform_driver at91_can_driver = { 1425 .probe = at91_can_probe, 1426 .remove = at91_can_remove, 1427 .driver = { 1428 .name = KBUILD_MODNAME, 1429 .of_match_table = of_match_ptr(at91_can_dt_ids), 1430 }, 1431 .id_table = at91_can_id_table, 1432}; 1433 1434module_platform_driver(at91_can_driver); 1435 1436MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1437MODULE_LICENSE("GPL v2"); 1438MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1439