1/* 2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com> 3 * 4 * Derived from: 5 * https://github.com/yuq/sunxi-nfc-mtd 6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com> 7 * 8 * https://github.com/hno/Allwinner-Info 9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström> 10 * 11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com> 12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 */ 24 25#include <linux/dma-mapping.h> 26#include <linux/slab.h> 27#include <linux/module.h> 28#include <linux/moduleparam.h> 29#include <linux/platform_device.h> 30#include <linux/of.h> 31#include <linux/of_device.h> 32#include <linux/of_gpio.h> 33#include <linux/of_mtd.h> 34#include <linux/mtd/mtd.h> 35#include <linux/mtd/nand.h> 36#include <linux/mtd/partitions.h> 37#include <linux/clk.h> 38#include <linux/delay.h> 39#include <linux/dmaengine.h> 40#include <linux/gpio.h> 41#include <linux/interrupt.h> 42#include <linux/io.h> 43 44#define NFC_REG_CTL 0x0000 45#define NFC_REG_ST 0x0004 46#define NFC_REG_INT 0x0008 47#define NFC_REG_TIMING_CTL 0x000C 48#define NFC_REG_TIMING_CFG 0x0010 49#define NFC_REG_ADDR_LOW 0x0014 50#define NFC_REG_ADDR_HIGH 0x0018 51#define NFC_REG_SECTOR_NUM 0x001C 52#define NFC_REG_CNT 0x0020 53#define NFC_REG_CMD 0x0024 54#define NFC_REG_RCMD_SET 0x0028 55#define NFC_REG_WCMD_SET 0x002C 56#define NFC_REG_IO_DATA 0x0030 57#define NFC_REG_ECC_CTL 0x0034 58#define NFC_REG_ECC_ST 0x0038 59#define NFC_REG_DEBUG 0x003C 60#define NFC_REG_ECC_CNT0 0x0040 61#define NFC_REG_ECC_CNT1 0x0044 62#define NFC_REG_ECC_CNT2 0x0048 63#define NFC_REG_ECC_CNT3 0x004c 64#define NFC_REG_USER_DATA_BASE 0x0050 65#define NFC_REG_SPARE_AREA 0x00A0 66#define NFC_RAM0_BASE 0x0400 67#define NFC_RAM1_BASE 0x0800 68 69/* define bit use in NFC_CTL */ 70#define NFC_EN BIT(0) 71#define NFC_RESET BIT(1) 72#define NFC_BUS_WIDYH BIT(2) 73#define NFC_RB_SEL BIT(3) 74#define NFC_CE_SEL GENMASK(26, 24) 75#define NFC_CE_CTL BIT(6) 76#define NFC_CE_CTL1 BIT(7) 77#define NFC_PAGE_SIZE GENMASK(11, 8) 78#define NFC_SAM BIT(12) 79#define NFC_RAM_METHOD BIT(14) 80#define NFC_DEBUG_CTL BIT(31) 81 82/* define bit use in NFC_ST */ 83#define NFC_RB_B2R BIT(0) 84#define NFC_CMD_INT_FLAG BIT(1) 85#define NFC_DMA_INT_FLAG BIT(2) 86#define NFC_CMD_FIFO_STATUS BIT(3) 87#define NFC_STA BIT(4) 88#define NFC_NATCH_INT_FLAG BIT(5) 89#define NFC_RB_STATE0 BIT(8) 90#define NFC_RB_STATE1 BIT(9) 91#define NFC_RB_STATE2 BIT(10) 92#define NFC_RB_STATE3 BIT(11) 93 94/* define bit use in NFC_INT */ 95#define NFC_B2R_INT_ENABLE BIT(0) 96#define NFC_CMD_INT_ENABLE BIT(1) 97#define NFC_DMA_INT_ENABLE BIT(2) 98#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \ 99 NFC_CMD_INT_ENABLE | \ 100 NFC_DMA_INT_ENABLE) 101 102/* define bit use in NFC_CMD */ 103#define NFC_CMD_LOW_BYTE GENMASK(7, 0) 104#define NFC_CMD_HIGH_BYTE GENMASK(15, 8) 105#define NFC_ADR_NUM GENMASK(18, 16) 106#define NFC_SEND_ADR BIT(19) 107#define NFC_ACCESS_DIR BIT(20) 108#define NFC_DATA_TRANS BIT(21) 109#define NFC_SEND_CMD1 BIT(22) 110#define NFC_WAIT_FLAG BIT(23) 111#define NFC_SEND_CMD2 BIT(24) 112#define NFC_SEQ BIT(25) 113#define NFC_DATA_SWAP_METHOD BIT(26) 114#define NFC_ROW_AUTO_INC BIT(27) 115#define NFC_SEND_CMD3 BIT(28) 116#define NFC_SEND_CMD4 BIT(29) 117#define NFC_CMD_TYPE GENMASK(31, 30) 118 119/* define bit use in NFC_RCMD_SET */ 120#define NFC_READ_CMD GENMASK(7, 0) 121#define NFC_RANDOM_READ_CMD0 GENMASK(15, 8) 122#define NFC_RANDOM_READ_CMD1 GENMASK(23, 16) 123 124/* define bit use in NFC_WCMD_SET */ 125#define NFC_PROGRAM_CMD GENMASK(7, 0) 126#define NFC_RANDOM_WRITE_CMD GENMASK(15, 8) 127#define NFC_READ_CMD0 GENMASK(23, 16) 128#define NFC_READ_CMD1 GENMASK(31, 24) 129 130/* define bit use in NFC_ECC_CTL */ 131#define NFC_ECC_EN BIT(0) 132#define NFC_ECC_PIPELINE BIT(3) 133#define NFC_ECC_EXCEPTION BIT(4) 134#define NFC_ECC_BLOCK_SIZE BIT(5) 135#define NFC_RANDOM_EN BIT(9) 136#define NFC_RANDOM_DIRECTION BIT(10) 137#define NFC_ECC_MODE_SHIFT 12 138#define NFC_ECC_MODE GENMASK(15, 12) 139#define NFC_RANDOM_SEED GENMASK(30, 16) 140 141/* NFC_USER_DATA helper macros */ 142#define NFC_BUF_TO_USER_DATA(buf) ((buf)[0] | ((buf)[1] << 8) | \ 143 ((buf)[2] << 16) | ((buf)[3] << 24)) 144 145#define NFC_DEFAULT_TIMEOUT_MS 1000 146 147#define NFC_SRAM_SIZE 1024 148 149#define NFC_MAX_CS 7 150 151/* 152 * Ready/Busy detection type: describes the Ready/Busy detection modes 153 * 154 * @RB_NONE: no external detection available, rely on STATUS command 155 * and software timeouts 156 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy 157 * pin of the NAND flash chip must be connected to one of the 158 * native NAND R/B pins (those which can be muxed to the NAND 159 * Controller) 160 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy 161 * pin of the NAND flash chip must be connected to a GPIO capable 162 * pin. 163 */ 164enum sunxi_nand_rb_type { 165 RB_NONE, 166 RB_NATIVE, 167 RB_GPIO, 168}; 169 170/* 171 * Ready/Busy structure: stores information related to Ready/Busy detection 172 * 173 * @type: the Ready/Busy detection mode 174 * @info: information related to the R/B detection mode. Either a gpio 175 * id or a native R/B id (those supported by the NAND controller). 176 */ 177struct sunxi_nand_rb { 178 enum sunxi_nand_rb_type type; 179 union { 180 int gpio; 181 int nativeid; 182 } info; 183}; 184 185/* 186 * Chip Select structure: stores information related to NAND Chip Select 187 * 188 * @cs: the NAND CS id used to communicate with a NAND Chip 189 * @rb: the Ready/Busy description 190 */ 191struct sunxi_nand_chip_sel { 192 u8 cs; 193 struct sunxi_nand_rb rb; 194}; 195 196/* 197 * sunxi HW ECC infos: stores information related to HW ECC support 198 * 199 * @mode: the sunxi ECC mode field deduced from ECC requirements 200 * @layout: the OOB layout depending on the ECC requirements and the 201 * selected ECC mode 202 */ 203struct sunxi_nand_hw_ecc { 204 int mode; 205 struct nand_ecclayout layout; 206}; 207 208/* 209 * NAND chip structure: stores NAND chip device related information 210 * 211 * @node: used to store NAND chips into a list 212 * @nand: base NAND chip structure 213 * @mtd: base MTD structure 214 * @clk_rate: clk_rate required for this NAND chip 215 * @selected: current active CS 216 * @nsels: number of CS lines required by the NAND chip 217 * @sels: array of CS lines descriptions 218 */ 219struct sunxi_nand_chip { 220 struct list_head node; 221 struct nand_chip nand; 222 struct mtd_info mtd; 223 unsigned long clk_rate; 224 int selected; 225 int nsels; 226 struct sunxi_nand_chip_sel sels[0]; 227}; 228 229static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) 230{ 231 return container_of(nand, struct sunxi_nand_chip, nand); 232} 233 234/* 235 * NAND Controller structure: stores sunxi NAND controller information 236 * 237 * @controller: base controller structure 238 * @dev: parent device (used to print error messages) 239 * @regs: NAND controller registers 240 * @ahb_clk: NAND Controller AHB clock 241 * @mod_clk: NAND Controller mod clock 242 * @assigned_cs: bitmask describing already assigned CS lines 243 * @clk_rate: NAND controller current clock rate 244 * @chips: a list containing all the NAND chips attached to 245 * this NAND controller 246 * @complete: a completion object used to wait for NAND 247 * controller events 248 */ 249struct sunxi_nfc { 250 struct nand_hw_control controller; 251 struct device *dev; 252 void __iomem *regs; 253 struct clk *ahb_clk; 254 struct clk *mod_clk; 255 unsigned long assigned_cs; 256 unsigned long clk_rate; 257 struct list_head chips; 258 struct completion complete; 259}; 260 261static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl) 262{ 263 return container_of(ctrl, struct sunxi_nfc, controller); 264} 265 266static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id) 267{ 268 struct sunxi_nfc *nfc = dev_id; 269 u32 st = readl(nfc->regs + NFC_REG_ST); 270 u32 ien = readl(nfc->regs + NFC_REG_INT); 271 272 if (!(ien & st)) 273 return IRQ_NONE; 274 275 if ((ien & st) == ien) 276 complete(&nfc->complete); 277 278 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST); 279 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT); 280 281 return IRQ_HANDLED; 282} 283 284static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags, 285 unsigned int timeout_ms) 286{ 287 init_completion(&nfc->complete); 288 289 writel(flags, nfc->regs + NFC_REG_INT); 290 291 if (!timeout_ms) 292 timeout_ms = NFC_DEFAULT_TIMEOUT_MS; 293 294 if (!wait_for_completion_timeout(&nfc->complete, 295 msecs_to_jiffies(timeout_ms))) { 296 dev_err(nfc->dev, "wait interrupt timedout\n"); 297 return -ETIMEDOUT; 298 } 299 300 return 0; 301} 302 303static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc) 304{ 305 unsigned long timeout = jiffies + 306 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS); 307 308 do { 309 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS)) 310 return 0; 311 } while (time_before(jiffies, timeout)); 312 313 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n"); 314 return -ETIMEDOUT; 315} 316 317static int sunxi_nfc_rst(struct sunxi_nfc *nfc) 318{ 319 unsigned long timeout = jiffies + 320 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS); 321 322 writel(0, nfc->regs + NFC_REG_ECC_CTL); 323 writel(NFC_RESET, nfc->regs + NFC_REG_CTL); 324 325 do { 326 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET)) 327 return 0; 328 } while (time_before(jiffies, timeout)); 329 330 dev_err(nfc->dev, "wait for NAND controller reset timedout\n"); 331 return -ETIMEDOUT; 332} 333 334static int sunxi_nfc_dev_ready(struct mtd_info *mtd) 335{ 336 struct nand_chip *nand = mtd->priv; 337 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 338 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 339 struct sunxi_nand_rb *rb; 340 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20); 341 int ret; 342 343 if (sunxi_nand->selected < 0) 344 return 0; 345 346 rb = &sunxi_nand->sels[sunxi_nand->selected].rb; 347 348 switch (rb->type) { 349 case RB_NATIVE: 350 ret = !!(readl(nfc->regs + NFC_REG_ST) & 351 (NFC_RB_STATE0 << rb->info.nativeid)); 352 if (ret) 353 break; 354 355 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo); 356 ret = !!(readl(nfc->regs + NFC_REG_ST) & 357 (NFC_RB_STATE0 << rb->info.nativeid)); 358 break; 359 case RB_GPIO: 360 ret = gpio_get_value(rb->info.gpio); 361 break; 362 case RB_NONE: 363 default: 364 ret = 0; 365 dev_err(nfc->dev, "cannot check R/B NAND status!\n"); 366 break; 367 } 368 369 return ret; 370} 371 372static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip) 373{ 374 struct nand_chip *nand = mtd->priv; 375 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 376 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 377 struct sunxi_nand_chip_sel *sel; 378 u32 ctl; 379 380 if (chip > 0 && chip >= sunxi_nand->nsels) 381 return; 382 383 if (chip == sunxi_nand->selected) 384 return; 385 386 ctl = readl(nfc->regs + NFC_REG_CTL) & 387 ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN); 388 389 if (chip >= 0) { 390 sel = &sunxi_nand->sels[chip]; 391 392 ctl |= (sel->cs << 24) | NFC_EN | 393 (((nand->page_shift - 10) & 0xf) << 8); 394 if (sel->rb.type == RB_NONE) { 395 nand->dev_ready = NULL; 396 } else { 397 nand->dev_ready = sunxi_nfc_dev_ready; 398 if (sel->rb.type == RB_NATIVE) 399 ctl |= (sel->rb.info.nativeid << 3); 400 } 401 402 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA); 403 404 if (nfc->clk_rate != sunxi_nand->clk_rate) { 405 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate); 406 nfc->clk_rate = sunxi_nand->clk_rate; 407 } 408 } 409 410 writel(ctl, nfc->regs + NFC_REG_CTL); 411 412 sunxi_nand->selected = chip; 413} 414 415static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 416{ 417 struct nand_chip *nand = mtd->priv; 418 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 419 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 420 int ret; 421 int cnt; 422 int offs = 0; 423 u32 tmp; 424 425 while (len > offs) { 426 cnt = min(len - offs, NFC_SRAM_SIZE); 427 428 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 429 if (ret) 430 break; 431 432 writel(cnt, nfc->regs + NFC_REG_CNT); 433 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; 434 writel(tmp, nfc->regs + NFC_REG_CMD); 435 436 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); 437 if (ret) 438 break; 439 440 if (buf) 441 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE, 442 cnt); 443 offs += cnt; 444 } 445} 446 447static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, 448 int len) 449{ 450 struct nand_chip *nand = mtd->priv; 451 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 452 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 453 int ret; 454 int cnt; 455 int offs = 0; 456 u32 tmp; 457 458 while (len > offs) { 459 cnt = min(len - offs, NFC_SRAM_SIZE); 460 461 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 462 if (ret) 463 break; 464 465 writel(cnt, nfc->regs + NFC_REG_CNT); 466 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt); 467 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | 468 NFC_ACCESS_DIR; 469 writel(tmp, nfc->regs + NFC_REG_CMD); 470 471 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); 472 if (ret) 473 break; 474 475 offs += cnt; 476 } 477} 478 479static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd) 480{ 481 uint8_t ret; 482 483 sunxi_nfc_read_buf(mtd, &ret, 1); 484 485 return ret; 486} 487 488static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, 489 unsigned int ctrl) 490{ 491 struct nand_chip *nand = mtd->priv; 492 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 493 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 494 int ret; 495 u32 tmp; 496 497 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 498 if (ret) 499 return; 500 501 if (ctrl & NAND_CTRL_CHANGE) { 502 tmp = readl(nfc->regs + NFC_REG_CTL); 503 if (ctrl & NAND_NCE) 504 tmp |= NFC_CE_CTL; 505 else 506 tmp &= ~NFC_CE_CTL; 507 writel(tmp, nfc->regs + NFC_REG_CTL); 508 } 509 510 if (dat == NAND_CMD_NONE) 511 return; 512 513 if (ctrl & NAND_CLE) { 514 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD); 515 } else { 516 writel(dat, nfc->regs + NFC_REG_ADDR_LOW); 517 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD); 518 } 519 520 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); 521} 522 523static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd, 524 struct nand_chip *chip, uint8_t *buf, 525 int oob_required, int page) 526{ 527 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); 528 struct nand_ecc_ctrl *ecc = &chip->ecc; 529 struct nand_ecclayout *layout = ecc->layout; 530 struct sunxi_nand_hw_ecc *data = ecc->priv; 531 unsigned int max_bitflips = 0; 532 int offset; 533 int ret; 534 u32 tmp; 535 int i; 536 int cnt; 537 538 tmp = readl(nfc->regs + NFC_REG_ECC_CTL); 539 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); 540 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | 541 NFC_ECC_EXCEPTION; 542 543 writel(tmp, nfc->regs + NFC_REG_ECC_CTL); 544 545 for (i = 0; i < ecc->steps; i++) { 546 if (i) 547 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1); 548 549 offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4; 550 551 chip->read_buf(mtd, NULL, ecc->size); 552 553 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); 554 555 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 556 if (ret) 557 return ret; 558 559 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30); 560 writel(tmp, nfc->regs + NFC_REG_CMD); 561 562 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); 563 if (ret) 564 return ret; 565 566 memcpy_fromio(buf + (i * ecc->size), 567 nfc->regs + NFC_RAM0_BASE, ecc->size); 568 569 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) { 570 mtd->ecc_stats.failed++; 571 } else { 572 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff; 573 mtd->ecc_stats.corrected += tmp; 574 max_bitflips = max_t(unsigned int, max_bitflips, tmp); 575 } 576 577 if (oob_required) { 578 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); 579 580 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 581 if (ret) 582 return ret; 583 584 offset -= mtd->writesize; 585 chip->read_buf(mtd, chip->oob_poi + offset, 586 ecc->bytes + 4); 587 } 588 } 589 590 if (oob_required) { 591 cnt = ecc->layout->oobfree[ecc->steps].length; 592 if (cnt > 0) { 593 offset = mtd->writesize + 594 ecc->layout->oobfree[ecc->steps].offset; 595 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); 596 offset -= mtd->writesize; 597 chip->read_buf(mtd, chip->oob_poi + offset, cnt); 598 } 599 } 600 601 tmp = readl(nfc->regs + NFC_REG_ECC_CTL); 602 tmp &= ~NFC_ECC_EN; 603 604 writel(tmp, nfc->regs + NFC_REG_ECC_CTL); 605 606 return max_bitflips; 607} 608 609static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd, 610 struct nand_chip *chip, 611 const uint8_t *buf, int oob_required) 612{ 613 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); 614 struct nand_ecc_ctrl *ecc = &chip->ecc; 615 struct nand_ecclayout *layout = ecc->layout; 616 struct sunxi_nand_hw_ecc *data = ecc->priv; 617 int offset; 618 int ret; 619 u32 tmp; 620 int i; 621 int cnt; 622 623 tmp = readl(nfc->regs + NFC_REG_ECC_CTL); 624 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); 625 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | 626 NFC_ECC_EXCEPTION; 627 628 writel(tmp, nfc->regs + NFC_REG_ECC_CTL); 629 630 for (i = 0; i < ecc->steps; i++) { 631 if (i) 632 chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1); 633 634 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size); 635 636 offset = layout->eccpos[i * ecc->bytes] - 4 + mtd->writesize; 637 638 /* Fill OOB data in */ 639 writel(NFC_BUF_TO_USER_DATA(chip->oob_poi + 640 layout->oobfree[i].offset), 641 nfc->regs + NFC_REG_USER_DATA_BASE); 642 643 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1); 644 645 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); 646 if (ret) 647 return ret; 648 649 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR | 650 (1 << 30); 651 writel(tmp, nfc->regs + NFC_REG_CMD); 652 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); 653 if (ret) 654 return ret; 655 } 656 657 if (oob_required) { 658 cnt = ecc->layout->oobfree[i].length; 659 if (cnt > 0) { 660 offset = mtd->writesize + 661 ecc->layout->oobfree[i].offset; 662 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1); 663 offset -= mtd->writesize; 664 chip->write_buf(mtd, chip->oob_poi + offset, cnt); 665 } 666 } 667 668 tmp = readl(nfc->regs + NFC_REG_ECC_CTL); 669 tmp &= ~NFC_ECC_EN; 670 671 writel(tmp, nfc->regs + NFC_REG_ECC_CTL); 672 673 return 0; 674} 675 676static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd, 677 struct nand_chip *chip, 678 uint8_t *buf, int oob_required, 679 int page) 680{ 681 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); 682 struct nand_ecc_ctrl *ecc = &chip->ecc; 683 struct sunxi_nand_hw_ecc *data = ecc->priv; 684 unsigned int max_bitflips = 0; 685 uint8_t *oob = chip->oob_poi; 686 int offset = 0; 687 int ret; 688 int cnt; 689 u32 tmp; 690 int i; 691 692 tmp = readl(nfc->regs + NFC_REG_ECC_CTL); 693 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); 694 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | 695 NFC_ECC_EXCEPTION; 696 697 writel(tmp, nfc->regs + NFC_REG_ECC_CTL); 698 699 for (i = 0; i < ecc->steps; i++) { 700 chip->read_buf(mtd, NULL, ecc->size); 701 702 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30); 703 writel(tmp, nfc->regs + NFC_REG_CMD); 704 705 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); 706 if (ret) 707 return ret; 708 709 memcpy_fromio(buf, nfc->regs + NFC_RAM0_BASE, ecc->size); 710 buf += ecc->size; 711 offset += ecc->size; 712 713 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) { 714 mtd->ecc_stats.failed++; 715 } else { 716 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff; 717 mtd->ecc_stats.corrected += tmp; 718 max_bitflips = max_t(unsigned int, max_bitflips, tmp); 719 } 720 721 if (oob_required) { 722 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); 723 chip->read_buf(mtd, oob, ecc->bytes + ecc->prepad); 724 oob += ecc->bytes + ecc->prepad; 725 } 726 727 offset += ecc->bytes + ecc->prepad; 728 } 729 730 if (oob_required) { 731 cnt = mtd->oobsize - (oob - chip->oob_poi); 732 if (cnt > 0) { 733 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1); 734 chip->read_buf(mtd, oob, cnt); 735 } 736 } 737 738 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN, 739 nfc->regs + NFC_REG_ECC_CTL); 740 741 return max_bitflips; 742} 743 744static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd, 745 struct nand_chip *chip, 746 const uint8_t *buf, 747 int oob_required) 748{ 749 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller); 750 struct nand_ecc_ctrl *ecc = &chip->ecc; 751 struct sunxi_nand_hw_ecc *data = ecc->priv; 752 uint8_t *oob = chip->oob_poi; 753 int offset = 0; 754 int ret; 755 int cnt; 756 u32 tmp; 757 int i; 758 759 tmp = readl(nfc->regs + NFC_REG_ECC_CTL); 760 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE); 761 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) | 762 NFC_ECC_EXCEPTION; 763 764 writel(tmp, nfc->regs + NFC_REG_ECC_CTL); 765 766 for (i = 0; i < ecc->steps; i++) { 767 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size); 768 offset += ecc->size; 769 770 /* Fill OOB data in */ 771 writel(NFC_BUF_TO_USER_DATA(oob), 772 nfc->regs + NFC_REG_USER_DATA_BASE); 773 774 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR | 775 (1 << 30); 776 writel(tmp, nfc->regs + NFC_REG_CMD); 777 778 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); 779 if (ret) 780 return ret; 781 782 offset += ecc->bytes + ecc->prepad; 783 oob += ecc->bytes + ecc->prepad; 784 } 785 786 if (oob_required) { 787 cnt = mtd->oobsize - (oob - chip->oob_poi); 788 if (cnt > 0) { 789 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1); 790 chip->write_buf(mtd, oob, cnt); 791 } 792 } 793 794 tmp = readl(nfc->regs + NFC_REG_ECC_CTL); 795 tmp &= ~NFC_ECC_EN; 796 797 writel(tmp, nfc->regs + NFC_REG_ECC_CTL); 798 799 return 0; 800} 801 802static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, 803 const struct nand_sdr_timings *timings) 804{ 805 u32 min_clk_period = 0; 806 807 /* T1 <=> tCLS */ 808 if (timings->tCLS_min > min_clk_period) 809 min_clk_period = timings->tCLS_min; 810 811 /* T2 <=> tCLH */ 812 if (timings->tCLH_min > min_clk_period) 813 min_clk_period = timings->tCLH_min; 814 815 /* T3 <=> tCS */ 816 if (timings->tCS_min > min_clk_period) 817 min_clk_period = timings->tCS_min; 818 819 /* T4 <=> tCH */ 820 if (timings->tCH_min > min_clk_period) 821 min_clk_period = timings->tCH_min; 822 823 /* T5 <=> tWP */ 824 if (timings->tWP_min > min_clk_period) 825 min_clk_period = timings->tWP_min; 826 827 /* T6 <=> tWH */ 828 if (timings->tWH_min > min_clk_period) 829 min_clk_period = timings->tWH_min; 830 831 /* T7 <=> tALS */ 832 if (timings->tALS_min > min_clk_period) 833 min_clk_period = timings->tALS_min; 834 835 /* T8 <=> tDS */ 836 if (timings->tDS_min > min_clk_period) 837 min_clk_period = timings->tDS_min; 838 839 /* T9 <=> tDH */ 840 if (timings->tDH_min > min_clk_period) 841 min_clk_period = timings->tDH_min; 842 843 /* T10 <=> tRR */ 844 if (timings->tRR_min > (min_clk_period * 3)) 845 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3); 846 847 /* T11 <=> tALH */ 848 if (timings->tALH_min > min_clk_period) 849 min_clk_period = timings->tALH_min; 850 851 /* T12 <=> tRP */ 852 if (timings->tRP_min > min_clk_period) 853 min_clk_period = timings->tRP_min; 854 855 /* T13 <=> tREH */ 856 if (timings->tREH_min > min_clk_period) 857 min_clk_period = timings->tREH_min; 858 859 /* T14 <=> tRC */ 860 if (timings->tRC_min > (min_clk_period * 2)) 861 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2); 862 863 /* T15 <=> tWC */ 864 if (timings->tWC_min > (min_clk_period * 2)) 865 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); 866 867 868 /* Convert min_clk_period from picoseconds to nanoseconds */ 869 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); 870 871 /* 872 * Convert min_clk_period into a clk frequency, then get the 873 * appropriate rate for the NAND controller IP given this formula 874 * (specified in the datasheet): 875 * nand clk_rate = 2 * min_clk_rate 876 */ 877 chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period; 878 879 /* TODO: configure T16-T19 */ 880 881 return 0; 882} 883 884static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip, 885 struct device_node *np) 886{ 887 const struct nand_sdr_timings *timings; 888 int ret; 889 int mode; 890 891 mode = onfi_get_async_timing_mode(&chip->nand); 892 if (mode == ONFI_TIMING_MODE_UNKNOWN) { 893 mode = chip->nand.onfi_timing_mode_default; 894 } else { 895 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {}; 896 897 mode = fls(mode) - 1; 898 if (mode < 0) 899 mode = 0; 900 901 feature[0] = mode; 902 ret = chip->nand.onfi_set_features(&chip->mtd, &chip->nand, 903 ONFI_FEATURE_ADDR_TIMING_MODE, 904 feature); 905 if (ret) 906 return ret; 907 } 908 909 timings = onfi_async_timing_mode_to_sdr_timings(mode); 910 if (IS_ERR(timings)) 911 return PTR_ERR(timings); 912 913 return sunxi_nand_chip_set_timings(chip, timings); 914} 915 916static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd, 917 struct nand_ecc_ctrl *ecc, 918 struct device_node *np) 919{ 920 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; 921 struct nand_chip *nand = mtd->priv; 922 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); 923 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); 924 struct sunxi_nand_hw_ecc *data; 925 struct nand_ecclayout *layout; 926 int nsectors; 927 int ret; 928 int i; 929 930 data = kzalloc(sizeof(*data), GFP_KERNEL); 931 if (!data) 932 return -ENOMEM; 933 934 /* Add ECC info retrieval from DT */ 935 for (i = 0; i < ARRAY_SIZE(strengths); i++) { 936 if (ecc->strength <= strengths[i]) 937 break; 938 } 939 940 if (i >= ARRAY_SIZE(strengths)) { 941 dev_err(nfc->dev, "unsupported strength\n"); 942 ret = -ENOTSUPP; 943 goto err; 944 } 945 946 data->mode = i; 947 948 /* HW ECC always request ECC bytes for 1024 bytes blocks */ 949 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8); 950 951 /* HW ECC always work with even numbers of ECC bytes */ 952 ecc->bytes = ALIGN(ecc->bytes, 2); 953 954 layout = &data->layout; 955 nsectors = mtd->writesize / ecc->size; 956 957 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) { 958 ret = -EINVAL; 959 goto err; 960 } 961 962 layout->eccbytes = (ecc->bytes * nsectors); 963 964 ecc->layout = layout; 965 ecc->priv = data; 966 967 return 0; 968 969err: 970 kfree(data); 971 972 return ret; 973} 974 975static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc) 976{ 977 kfree(ecc->priv); 978} 979 980static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, 981 struct nand_ecc_ctrl *ecc, 982 struct device_node *np) 983{ 984 struct nand_ecclayout *layout; 985 int nsectors; 986 int i, j; 987 int ret; 988 989 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np); 990 if (ret) 991 return ret; 992 993 ecc->read_page = sunxi_nfc_hw_ecc_read_page; 994 ecc->write_page = sunxi_nfc_hw_ecc_write_page; 995 layout = ecc->layout; 996 nsectors = mtd->writesize / ecc->size; 997 998 for (i = 0; i < nsectors; i++) { 999 if (i) { 1000 layout->oobfree[i].offset = 1001 layout->oobfree[i - 1].offset + 1002 layout->oobfree[i - 1].length + 1003 ecc->bytes; 1004 layout->oobfree[i].length = 4; 1005 } else { 1006 /* 1007 * The first 2 bytes are used for BB markers, hence we 1008 * only have 2 bytes available in the first user data 1009 * section. 1010 */ 1011 layout->oobfree[i].length = 2; 1012 layout->oobfree[i].offset = 2; 1013 } 1014 1015 for (j = 0; j < ecc->bytes; j++) 1016 layout->eccpos[(ecc->bytes * i) + j] = 1017 layout->oobfree[i].offset + 1018 layout->oobfree[i].length + j; 1019 } 1020 1021 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) { 1022 layout->oobfree[nsectors].offset = 1023 layout->oobfree[nsectors - 1].offset + 1024 layout->oobfree[nsectors - 1].length + 1025 ecc->bytes; 1026 layout->oobfree[nsectors].length = mtd->oobsize - 1027 ((ecc->bytes + 4) * nsectors); 1028 } 1029 1030 return 0; 1031} 1032 1033static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd, 1034 struct nand_ecc_ctrl *ecc, 1035 struct device_node *np) 1036{ 1037 struct nand_ecclayout *layout; 1038 int nsectors; 1039 int i; 1040 int ret; 1041 1042 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np); 1043 if (ret) 1044 return ret; 1045 1046 ecc->prepad = 4; 1047 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page; 1048 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page; 1049 1050 layout = ecc->layout; 1051 nsectors = mtd->writesize / ecc->size; 1052 1053 for (i = 0; i < (ecc->bytes * nsectors); i++) 1054 layout->eccpos[i] = i; 1055 1056 layout->oobfree[0].length = mtd->oobsize - i; 1057 layout->oobfree[0].offset = i; 1058 1059 return 0; 1060} 1061 1062static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc) 1063{ 1064 switch (ecc->mode) { 1065 case NAND_ECC_HW: 1066 case NAND_ECC_HW_SYNDROME: 1067 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc); 1068 break; 1069 case NAND_ECC_NONE: 1070 kfree(ecc->layout); 1071 default: 1072 break; 1073 } 1074} 1075 1076static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc, 1077 struct device_node *np) 1078{ 1079 struct nand_chip *nand = mtd->priv; 1080 int strength; 1081 int blk_size; 1082 int ret; 1083 1084 blk_size = of_get_nand_ecc_step_size(np); 1085 strength = of_get_nand_ecc_strength(np); 1086 if (blk_size > 0 && strength > 0) { 1087 ecc->size = blk_size; 1088 ecc->strength = strength; 1089 } else { 1090 ecc->size = nand->ecc_step_ds; 1091 ecc->strength = nand->ecc_strength_ds; 1092 } 1093 1094 if (!ecc->size || !ecc->strength) 1095 return -EINVAL; 1096 1097 ecc->mode = NAND_ECC_HW; 1098 1099 ret = of_get_nand_ecc_mode(np); 1100 if (ret >= 0) 1101 ecc->mode = ret; 1102 1103 switch (ecc->mode) { 1104 case NAND_ECC_SOFT_BCH: 1105 break; 1106 case NAND_ECC_HW: 1107 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np); 1108 if (ret) 1109 return ret; 1110 break; 1111 case NAND_ECC_HW_SYNDROME: 1112 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np); 1113 if (ret) 1114 return ret; 1115 break; 1116 case NAND_ECC_NONE: 1117 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL); 1118 if (!ecc->layout) 1119 return -ENOMEM; 1120 ecc->layout->oobfree[0].length = mtd->oobsize; 1121 case NAND_ECC_SOFT: 1122 break; 1123 default: 1124 return -EINVAL; 1125 } 1126 1127 return 0; 1128} 1129 1130static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc, 1131 struct device_node *np) 1132{ 1133 const struct nand_sdr_timings *timings; 1134 struct sunxi_nand_chip *chip; 1135 struct mtd_part_parser_data ppdata; 1136 struct mtd_info *mtd; 1137 struct nand_chip *nand; 1138 int nsels; 1139 int ret; 1140 int i; 1141 u32 tmp; 1142 1143 if (!of_get_property(np, "reg", &nsels)) 1144 return -EINVAL; 1145 1146 nsels /= sizeof(u32); 1147 if (!nsels) { 1148 dev_err(dev, "invalid reg property size\n"); 1149 return -EINVAL; 1150 } 1151 1152 chip = devm_kzalloc(dev, 1153 sizeof(*chip) + 1154 (nsels * sizeof(struct sunxi_nand_chip_sel)), 1155 GFP_KERNEL); 1156 if (!chip) { 1157 dev_err(dev, "could not allocate chip\n"); 1158 return -ENOMEM; 1159 } 1160 1161 chip->nsels = nsels; 1162 chip->selected = -1; 1163 1164 for (i = 0; i < nsels; i++) { 1165 ret = of_property_read_u32_index(np, "reg", i, &tmp); 1166 if (ret) { 1167 dev_err(dev, "could not retrieve reg property: %d\n", 1168 ret); 1169 return ret; 1170 } 1171 1172 if (tmp > NFC_MAX_CS) { 1173 dev_err(dev, 1174 "invalid reg value: %u (max CS = 7)\n", 1175 tmp); 1176 return -EINVAL; 1177 } 1178 1179 if (test_and_set_bit(tmp, &nfc->assigned_cs)) { 1180 dev_err(dev, "CS %d already assigned\n", tmp); 1181 return -EINVAL; 1182 } 1183 1184 chip->sels[i].cs = tmp; 1185 1186 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) && 1187 tmp < 2) { 1188 chip->sels[i].rb.type = RB_NATIVE; 1189 chip->sels[i].rb.info.nativeid = tmp; 1190 } else { 1191 ret = of_get_named_gpio(np, "rb-gpios", i); 1192 if (ret >= 0) { 1193 tmp = ret; 1194 chip->sels[i].rb.type = RB_GPIO; 1195 chip->sels[i].rb.info.gpio = tmp; 1196 ret = devm_gpio_request(dev, tmp, "nand-rb"); 1197 if (ret) 1198 return ret; 1199 1200 ret = gpio_direction_input(tmp); 1201 if (ret) 1202 return ret; 1203 } else { 1204 chip->sels[i].rb.type = RB_NONE; 1205 } 1206 } 1207 } 1208 1209 timings = onfi_async_timing_mode_to_sdr_timings(0); 1210 if (IS_ERR(timings)) { 1211 ret = PTR_ERR(timings); 1212 dev_err(dev, 1213 "could not retrieve timings for ONFI mode 0: %d\n", 1214 ret); 1215 return ret; 1216 } 1217 1218 ret = sunxi_nand_chip_set_timings(chip, timings); 1219 if (ret) { 1220 dev_err(dev, "could not configure chip timings: %d\n", ret); 1221 return ret; 1222 } 1223 1224 nand = &chip->nand; 1225 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */ 1226 nand->chip_delay = 200; 1227 nand->controller = &nfc->controller; 1228 nand->select_chip = sunxi_nfc_select_chip; 1229 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl; 1230 nand->read_buf = sunxi_nfc_read_buf; 1231 nand->write_buf = sunxi_nfc_write_buf; 1232 nand->read_byte = sunxi_nfc_read_byte; 1233 1234 if (of_get_nand_on_flash_bbt(np)) 1235 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 1236 1237 mtd = &chip->mtd; 1238 mtd->dev.parent = dev; 1239 mtd->priv = nand; 1240 mtd->owner = THIS_MODULE; 1241 1242 ret = nand_scan_ident(mtd, nsels, NULL); 1243 if (ret) 1244 return ret; 1245 1246 ret = sunxi_nand_chip_init_timings(chip, np); 1247 if (ret) { 1248 dev_err(dev, "could not configure chip timings: %d\n", ret); 1249 return ret; 1250 } 1251 1252 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np); 1253 if (ret) { 1254 dev_err(dev, "ECC init failed: %d\n", ret); 1255 return ret; 1256 } 1257 1258 ret = nand_scan_tail(mtd); 1259 if (ret) { 1260 dev_err(dev, "nand_scan_tail failed: %d\n", ret); 1261 return ret; 1262 } 1263 1264 ppdata.of_node = np; 1265 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); 1266 if (ret) { 1267 dev_err(dev, "failed to register mtd device: %d\n", ret); 1268 nand_release(mtd); 1269 return ret; 1270 } 1271 1272 list_add_tail(&chip->node, &nfc->chips); 1273 1274 return 0; 1275} 1276 1277static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc) 1278{ 1279 struct device_node *np = dev->of_node; 1280 struct device_node *nand_np; 1281 int nchips = of_get_child_count(np); 1282 int ret; 1283 1284 if (nchips > 8) { 1285 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips); 1286 return -EINVAL; 1287 } 1288 1289 for_each_child_of_node(np, nand_np) { 1290 ret = sunxi_nand_chip_init(dev, nfc, nand_np); 1291 if (ret) 1292 return ret; 1293 } 1294 1295 return 0; 1296} 1297 1298static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc) 1299{ 1300 struct sunxi_nand_chip *chip; 1301 1302 while (!list_empty(&nfc->chips)) { 1303 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip, 1304 node); 1305 nand_release(&chip->mtd); 1306 sunxi_nand_ecc_cleanup(&chip->nand.ecc); 1307 list_del(&chip->node); 1308 } 1309} 1310 1311static int sunxi_nfc_probe(struct platform_device *pdev) 1312{ 1313 struct device *dev = &pdev->dev; 1314 struct resource *r; 1315 struct sunxi_nfc *nfc; 1316 int irq; 1317 int ret; 1318 1319 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL); 1320 if (!nfc) 1321 return -ENOMEM; 1322 1323 nfc->dev = dev; 1324 spin_lock_init(&nfc->controller.lock); 1325 init_waitqueue_head(&nfc->controller.wq); 1326 INIT_LIST_HEAD(&nfc->chips); 1327 1328 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1329 nfc->regs = devm_ioremap_resource(dev, r); 1330 if (IS_ERR(nfc->regs)) 1331 return PTR_ERR(nfc->regs); 1332 1333 irq = platform_get_irq(pdev, 0); 1334 if (irq < 0) { 1335 dev_err(dev, "failed to retrieve irq\n"); 1336 return irq; 1337 } 1338 1339 nfc->ahb_clk = devm_clk_get(dev, "ahb"); 1340 if (IS_ERR(nfc->ahb_clk)) { 1341 dev_err(dev, "failed to retrieve ahb clk\n"); 1342 return PTR_ERR(nfc->ahb_clk); 1343 } 1344 1345 ret = clk_prepare_enable(nfc->ahb_clk); 1346 if (ret) 1347 return ret; 1348 1349 nfc->mod_clk = devm_clk_get(dev, "mod"); 1350 if (IS_ERR(nfc->mod_clk)) { 1351 dev_err(dev, "failed to retrieve mod clk\n"); 1352 ret = PTR_ERR(nfc->mod_clk); 1353 goto out_ahb_clk_unprepare; 1354 } 1355 1356 ret = clk_prepare_enable(nfc->mod_clk); 1357 if (ret) 1358 goto out_ahb_clk_unprepare; 1359 1360 ret = sunxi_nfc_rst(nfc); 1361 if (ret) 1362 goto out_mod_clk_unprepare; 1363 1364 writel(0, nfc->regs + NFC_REG_INT); 1365 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt, 1366 0, "sunxi-nand", nfc); 1367 if (ret) 1368 goto out_mod_clk_unprepare; 1369 1370 platform_set_drvdata(pdev, nfc); 1371 1372 /* 1373 * TODO: replace these magic values with proper flags as soon as we 1374 * know what they are encoding. 1375 */ 1376 writel(0x100, nfc->regs + NFC_REG_TIMING_CTL); 1377 writel(0x7ff, nfc->regs + NFC_REG_TIMING_CFG); 1378 1379 ret = sunxi_nand_chips_init(dev, nfc); 1380 if (ret) { 1381 dev_err(dev, "failed to init nand chips\n"); 1382 goto out_mod_clk_unprepare; 1383 } 1384 1385 return 0; 1386 1387out_mod_clk_unprepare: 1388 clk_disable_unprepare(nfc->mod_clk); 1389out_ahb_clk_unprepare: 1390 clk_disable_unprepare(nfc->ahb_clk); 1391 1392 return ret; 1393} 1394 1395static int sunxi_nfc_remove(struct platform_device *pdev) 1396{ 1397 struct sunxi_nfc *nfc = platform_get_drvdata(pdev); 1398 1399 sunxi_nand_chips_cleanup(nfc); 1400 1401 return 0; 1402} 1403 1404static const struct of_device_id sunxi_nfc_ids[] = { 1405 { .compatible = "allwinner,sun4i-a10-nand" }, 1406 { /* sentinel */ } 1407}; 1408MODULE_DEVICE_TABLE(of, sunxi_nfc_ids); 1409 1410static struct platform_driver sunxi_nfc_driver = { 1411 .driver = { 1412 .name = "sunxi_nand", 1413 .of_match_table = sunxi_nfc_ids, 1414 }, 1415 .probe = sunxi_nfc_probe, 1416 .remove = sunxi_nfc_remove, 1417}; 1418module_platform_driver(sunxi_nfc_driver); 1419 1420MODULE_LICENSE("GPL v2"); 1421MODULE_AUTHOR("Boris BREZILLON"); 1422MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver"); 1423MODULE_ALIAS("platform:sunxi_nand"); 1424