1/*
2 * Copyright (C) 2010 Marvell International Ltd.
3 *		Zhangfei Gao <zhangfei.gao@marvell.com>
4 *		Kevin Wang <dwang4@marvell.com>
5 *		Mingwei Wang <mwwang@marvell.com>
6 *		Philip Rakity <prakity@marvell.com>
7 *		Mark Brown <markb@marvell.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16 * GNU General Public License for more details.
17 *
18 */
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/gpio.h>
25#include <linux/mmc/card.h>
26#include <linux/mmc/host.h>
27#include <linux/mmc/slot-gpio.h>
28#include <linux/platform_data/pxa_sdhci.h>
29#include <linux/slab.h>
30#include <linux/delay.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_gpio.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/mbus.h>
38
39#include "sdhci.h"
40#include "sdhci-pltfm.h"
41
42#define PXAV3_RPM_DELAY_MS     50
43
44#define SD_CLOCK_BURST_SIZE_SETUP		0x10A
45#define SDCLK_SEL	0x100
46#define SDCLK_DELAY_SHIFT	9
47#define SDCLK_DELAY_MASK	0x1f
48
49#define SD_CFG_FIFO_PARAM       0x100
50#define SDCFG_GEN_PAD_CLK_ON	(1<<6)
51#define SDCFG_GEN_PAD_CLK_CNT_MASK	0xFF
52#define SDCFG_GEN_PAD_CLK_CNT_SHIFT	24
53
54#define SD_SPI_MODE          0x108
55#define SD_CE_ATA_1          0x10C
56
57#define SD_CE_ATA_2          0x10E
58#define SDCE_MISC_INT		(1<<2)
59#define SDCE_MISC_INT_EN	(1<<1)
60
61struct sdhci_pxa {
62	struct clk *clk_core;
63	struct clk *clk_io;
64	u8	power_mode;
65	void __iomem *sdio3_conf_reg;
66};
67
68/*
69 * These registers are relative to the second register region, for the
70 * MBus bridge.
71 */
72#define SDHCI_WINDOW_CTRL(i)	(0x80 + ((i) << 3))
73#define SDHCI_WINDOW_BASE(i)	(0x84 + ((i) << 3))
74#define SDHCI_MAX_WIN_NUM	8
75
76/*
77 * Fields below belong to SDIO3 Configuration Register (third register
78 * region for the Armada 38x flavor)
79 */
80
81#define SDIO3_CONF_CLK_INV	BIT(0)
82#define SDIO3_CONF_SD_FB_CLK	BIT(2)
83
84static int mv_conf_mbus_windows(struct platform_device *pdev,
85				const struct mbus_dram_target_info *dram)
86{
87	int i;
88	void __iomem *regs;
89	struct resource *res;
90
91	if (!dram) {
92		dev_err(&pdev->dev, "no mbus dram info\n");
93		return -EINVAL;
94	}
95
96	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
97	if (!res) {
98		dev_err(&pdev->dev, "cannot get mbus registers\n");
99		return -EINVAL;
100	}
101
102	regs = ioremap(res->start, resource_size(res));
103	if (!regs) {
104		dev_err(&pdev->dev, "cannot map mbus registers\n");
105		return -ENOMEM;
106	}
107
108	for (i = 0; i < SDHCI_MAX_WIN_NUM; i++) {
109		writel(0, regs + SDHCI_WINDOW_CTRL(i));
110		writel(0, regs + SDHCI_WINDOW_BASE(i));
111	}
112
113	for (i = 0; i < dram->num_cs; i++) {
114		const struct mbus_dram_window *cs = dram->cs + i;
115
116		/* Write size, attributes and target id to control register */
117		writel(((cs->size - 1) & 0xffff0000) |
118			(cs->mbus_attr << 8) |
119			(dram->mbus_dram_target_id << 4) | 1,
120			regs + SDHCI_WINDOW_CTRL(i));
121		/* Write base address to base register */
122		writel(cs->base, regs + SDHCI_WINDOW_BASE(i));
123	}
124
125	iounmap(regs);
126
127	return 0;
128}
129
130static int armada_38x_quirks(struct platform_device *pdev,
131			     struct sdhci_host *host)
132{
133	struct device_node *np = pdev->dev.of_node;
134	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
135	struct sdhci_pxa *pxa = pltfm_host->priv;
136	struct resource *res;
137
138	host->quirks |= SDHCI_QUIRK_MISSING_CAPS;
139
140	host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
141	host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
142
143	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
144					   "conf-sdio3");
145	if (res) {
146		pxa->sdio3_conf_reg = devm_ioremap_resource(&pdev->dev, res);
147		if (IS_ERR(pxa->sdio3_conf_reg))
148			return PTR_ERR(pxa->sdio3_conf_reg);
149	} else {
150		/*
151		 * According to erratum 'FE-2946959' both SDR50 and DDR50
152		 * modes require specific clock adjustments in SDIO3
153		 * Configuration register, if the adjustment is not done,
154		 * remove them from the capabilities.
155		 */
156		host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50);
157
158		dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider updating your dtb\n");
159	}
160
161	/*
162	 * According to erratum 'ERR-7878951' Armada 38x SDHCI
163	 * controller has different capabilities than the ones shown
164	 * in its registers
165	 */
166	if (of_property_read_bool(np, "no-1-8-v")) {
167		host->caps &= ~SDHCI_CAN_VDD_180;
168		host->mmc->caps &= ~MMC_CAP_1_8V_DDR;
169	} else {
170		host->caps &= ~SDHCI_CAN_VDD_330;
171	}
172	host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_USE_SDR50_TUNING);
173
174	return 0;
175}
176
177static void pxav3_reset(struct sdhci_host *host, u8 mask)
178{
179	struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc));
180	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
181
182	sdhci_reset(host, mask);
183
184	if (mask == SDHCI_RESET_ALL) {
185		/*
186		 * tune timing of read data/command when crc error happen
187		 * no performance impact
188		 */
189		if (pdata && 0 != pdata->clk_delay_cycles) {
190			u16 tmp;
191
192			tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
193			tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK)
194				<< SDCLK_DELAY_SHIFT;
195			tmp |= SDCLK_SEL;
196			writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP);
197		}
198	}
199}
200
201#define MAX_WAIT_COUNT 5
202static void pxav3_gen_init_74_clocks(struct sdhci_host *host, u8 power_mode)
203{
204	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
205	struct sdhci_pxa *pxa = pltfm_host->priv;
206	u16 tmp;
207	int count;
208
209	if (pxa->power_mode == MMC_POWER_UP
210			&& power_mode == MMC_POWER_ON) {
211
212		dev_dbg(mmc_dev(host->mmc),
213				"%s: slot->power_mode = %d,"
214				"ios->power_mode = %d\n",
215				__func__,
216				pxa->power_mode,
217				power_mode);
218
219		/* set we want notice of when 74 clocks are sent */
220		tmp = readw(host->ioaddr + SD_CE_ATA_2);
221		tmp |= SDCE_MISC_INT_EN;
222		writew(tmp, host->ioaddr + SD_CE_ATA_2);
223
224		/* start sending the 74 clocks */
225		tmp = readw(host->ioaddr + SD_CFG_FIFO_PARAM);
226		tmp |= SDCFG_GEN_PAD_CLK_ON;
227		writew(tmp, host->ioaddr + SD_CFG_FIFO_PARAM);
228
229		/* slowest speed is about 100KHz or 10usec per clock */
230		udelay(740);
231		count = 0;
232
233		while (count++ < MAX_WAIT_COUNT) {
234			if ((readw(host->ioaddr + SD_CE_ATA_2)
235						& SDCE_MISC_INT) == 0)
236				break;
237			udelay(10);
238		}
239
240		if (count == MAX_WAIT_COUNT)
241			dev_warn(mmc_dev(host->mmc), "74 clock interrupt not cleared\n");
242
243		/* clear the interrupt bit if posted */
244		tmp = readw(host->ioaddr + SD_CE_ATA_2);
245		tmp |= SDCE_MISC_INT;
246		writew(tmp, host->ioaddr + SD_CE_ATA_2);
247	}
248	pxa->power_mode = power_mode;
249}
250
251static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
252{
253	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
254	struct sdhci_pxa *pxa = pltfm_host->priv;
255	u16 ctrl_2;
256
257	/*
258	 * Set V18_EN -- UHS modes do not work without this.
259	 * does not change signaling voltage
260	 */
261	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
262
263	/* Select Bus Speed Mode for host */
264	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
265	switch (uhs) {
266	case MMC_TIMING_UHS_SDR12:
267		ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
268		break;
269	case MMC_TIMING_UHS_SDR25:
270		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
271		break;
272	case MMC_TIMING_UHS_SDR50:
273		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
274		break;
275	case MMC_TIMING_UHS_SDR104:
276		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
277		break;
278	case MMC_TIMING_MMC_DDR52:
279	case MMC_TIMING_UHS_DDR50:
280		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
281		break;
282	}
283
284	/*
285	 * Update SDIO3 Configuration register according to erratum
286	 * FE-2946959
287	 */
288	if (pxa->sdio3_conf_reg) {
289		u8 reg_val  = readb(pxa->sdio3_conf_reg);
290
291		if (uhs == MMC_TIMING_UHS_SDR50 ||
292		    uhs == MMC_TIMING_UHS_DDR50) {
293			reg_val &= ~SDIO3_CONF_CLK_INV;
294			reg_val |= SDIO3_CONF_SD_FB_CLK;
295		} else {
296			reg_val |= SDIO3_CONF_CLK_INV;
297			reg_val &= ~SDIO3_CONF_SD_FB_CLK;
298		}
299		writeb(reg_val, pxa->sdio3_conf_reg);
300	}
301
302	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
303	dev_dbg(mmc_dev(host->mmc),
304		"%s uhs = %d, ctrl_2 = %04X\n",
305		__func__, uhs, ctrl_2);
306}
307
308static const struct sdhci_ops pxav3_sdhci_ops = {
309	.set_clock = sdhci_set_clock,
310	.platform_send_init_74_clocks = pxav3_gen_init_74_clocks,
311	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
312	.set_bus_width = sdhci_set_bus_width,
313	.reset = pxav3_reset,
314	.set_uhs_signaling = pxav3_set_uhs_signaling,
315};
316
317static struct sdhci_pltfm_data sdhci_pxav3_pdata = {
318	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
319		| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
320		| SDHCI_QUIRK_32BIT_ADMA_SIZE
321		| SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
322	.ops = &pxav3_sdhci_ops,
323};
324
325#ifdef CONFIG_OF
326static const struct of_device_id sdhci_pxav3_of_match[] = {
327	{
328		.compatible = "mrvl,pxav3-mmc",
329	},
330	{
331		.compatible = "marvell,armada-380-sdhci",
332	},
333	{},
334};
335MODULE_DEVICE_TABLE(of, sdhci_pxav3_of_match);
336
337static struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
338{
339	struct sdhci_pxa_platdata *pdata;
340	struct device_node *np = dev->of_node;
341	u32 clk_delay_cycles;
342
343	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
344	if (!pdata)
345		return NULL;
346
347	if (!of_property_read_u32(np, "mrvl,clk-delay-cycles",
348				  &clk_delay_cycles))
349		pdata->clk_delay_cycles = clk_delay_cycles;
350
351	return pdata;
352}
353#else
354static inline struct sdhci_pxa_platdata *pxav3_get_mmc_pdata(struct device *dev)
355{
356	return NULL;
357}
358#endif
359
360static int sdhci_pxav3_probe(struct platform_device *pdev)
361{
362	struct sdhci_pltfm_host *pltfm_host;
363	struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data;
364	struct device *dev = &pdev->dev;
365	struct device_node *np = pdev->dev.of_node;
366	struct sdhci_host *host = NULL;
367	struct sdhci_pxa *pxa = NULL;
368	const struct of_device_id *match;
369	int ret;
370
371	pxa = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_pxa), GFP_KERNEL);
372	if (!pxa)
373		return -ENOMEM;
374
375	host = sdhci_pltfm_init(pdev, &sdhci_pxav3_pdata, 0);
376	if (IS_ERR(host))
377		return PTR_ERR(host);
378
379	pltfm_host = sdhci_priv(host);
380	pltfm_host->priv = pxa;
381
382	pxa->clk_io = devm_clk_get(dev, "io");
383	if (IS_ERR(pxa->clk_io))
384		pxa->clk_io = devm_clk_get(dev, NULL);
385	if (IS_ERR(pxa->clk_io)) {
386		dev_err(dev, "failed to get io clock\n");
387		ret = PTR_ERR(pxa->clk_io);
388		goto err_clk_get;
389	}
390	pltfm_host->clk = pxa->clk_io;
391	clk_prepare_enable(pxa->clk_io);
392
393	pxa->clk_core = devm_clk_get(dev, "core");
394	if (!IS_ERR(pxa->clk_core))
395		clk_prepare_enable(pxa->clk_core);
396
397	/* enable 1/8V DDR capable */
398	host->mmc->caps |= MMC_CAP_1_8V_DDR;
399
400	if (of_device_is_compatible(np, "marvell,armada-380-sdhci")) {
401		ret = armada_38x_quirks(pdev, host);
402		if (ret < 0)
403			goto err_clk_get;
404		ret = mv_conf_mbus_windows(pdev, mv_mbus_dram_info());
405		if (ret < 0)
406			goto err_mbus_win;
407	}
408
409	match = of_match_device(of_match_ptr(sdhci_pxav3_of_match), &pdev->dev);
410	if (match) {
411		ret = mmc_of_parse(host->mmc);
412		if (ret)
413			goto err_of_parse;
414		sdhci_get_of_property(pdev);
415		pdata = pxav3_get_mmc_pdata(dev);
416		pdev->dev.platform_data = pdata;
417	} else if (pdata) {
418		/* on-chip device */
419		if (pdata->flags & PXA_FLAG_CARD_PERMANENT)
420			host->mmc->caps |= MMC_CAP_NONREMOVABLE;
421
422		/* If slot design supports 8 bit data, indicate this to MMC. */
423		if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
424			host->mmc->caps |= MMC_CAP_8_BIT_DATA;
425
426		if (pdata->quirks)
427			host->quirks |= pdata->quirks;
428		if (pdata->quirks2)
429			host->quirks2 |= pdata->quirks2;
430		if (pdata->host_caps)
431			host->mmc->caps |= pdata->host_caps;
432		if (pdata->host_caps2)
433			host->mmc->caps2 |= pdata->host_caps2;
434		if (pdata->pm_caps)
435			host->mmc->pm_caps |= pdata->pm_caps;
436
437		if (gpio_is_valid(pdata->ext_cd_gpio)) {
438			ret = mmc_gpio_request_cd(host->mmc, pdata->ext_cd_gpio,
439						  0);
440			if (ret) {
441				dev_err(mmc_dev(host->mmc),
442					"failed to allocate card detect gpio\n");
443				goto err_cd_req;
444			}
445		}
446	}
447
448	pm_runtime_get_noresume(&pdev->dev);
449	pm_runtime_set_active(&pdev->dev);
450	pm_runtime_set_autosuspend_delay(&pdev->dev, PXAV3_RPM_DELAY_MS);
451	pm_runtime_use_autosuspend(&pdev->dev);
452	pm_runtime_enable(&pdev->dev);
453	pm_suspend_ignore_children(&pdev->dev, 1);
454
455	ret = sdhci_add_host(host);
456	if (ret) {
457		dev_err(&pdev->dev, "failed to add host\n");
458		goto err_add_host;
459	}
460
461	platform_set_drvdata(pdev, host);
462
463	if (host->mmc->pm_caps & MMC_PM_KEEP_POWER) {
464		device_init_wakeup(&pdev->dev, 1);
465		host->mmc->pm_flags |= MMC_PM_WAKE_SDIO_IRQ;
466	} else {
467		device_init_wakeup(&pdev->dev, 0);
468	}
469
470	pm_runtime_put_autosuspend(&pdev->dev);
471
472	return 0;
473
474err_add_host:
475	pm_runtime_disable(&pdev->dev);
476	pm_runtime_put_noidle(&pdev->dev);
477err_of_parse:
478err_cd_req:
479err_mbus_win:
480	clk_disable_unprepare(pxa->clk_io);
481	clk_disable_unprepare(pxa->clk_core);
482err_clk_get:
483	sdhci_pltfm_free(pdev);
484	return ret;
485}
486
487static int sdhci_pxav3_remove(struct platform_device *pdev)
488{
489	struct sdhci_host *host = platform_get_drvdata(pdev);
490	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
491	struct sdhci_pxa *pxa = pltfm_host->priv;
492
493	pm_runtime_get_sync(&pdev->dev);
494	pm_runtime_disable(&pdev->dev);
495	pm_runtime_put_noidle(&pdev->dev);
496
497	sdhci_remove_host(host, 1);
498
499	clk_disable_unprepare(pxa->clk_io);
500	clk_disable_unprepare(pxa->clk_core);
501
502	sdhci_pltfm_free(pdev);
503
504	return 0;
505}
506
507#ifdef CONFIG_PM_SLEEP
508static int sdhci_pxav3_suspend(struct device *dev)
509{
510	int ret;
511	struct sdhci_host *host = dev_get_drvdata(dev);
512
513	pm_runtime_get_sync(dev);
514	ret = sdhci_suspend_host(host);
515	pm_runtime_mark_last_busy(dev);
516	pm_runtime_put_autosuspend(dev);
517
518	return ret;
519}
520
521static int sdhci_pxav3_resume(struct device *dev)
522{
523	int ret;
524	struct sdhci_host *host = dev_get_drvdata(dev);
525
526	pm_runtime_get_sync(dev);
527	ret = sdhci_resume_host(host);
528	pm_runtime_mark_last_busy(dev);
529	pm_runtime_put_autosuspend(dev);
530
531	return ret;
532}
533#endif
534
535#ifdef CONFIG_PM
536static int sdhci_pxav3_runtime_suspend(struct device *dev)
537{
538	struct sdhci_host *host = dev_get_drvdata(dev);
539	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
540	struct sdhci_pxa *pxa = pltfm_host->priv;
541	int ret;
542
543	ret = sdhci_runtime_suspend_host(host);
544	if (ret)
545		return ret;
546
547	clk_disable_unprepare(pxa->clk_io);
548	if (!IS_ERR(pxa->clk_core))
549		clk_disable_unprepare(pxa->clk_core);
550
551	return 0;
552}
553
554static int sdhci_pxav3_runtime_resume(struct device *dev)
555{
556	struct sdhci_host *host = dev_get_drvdata(dev);
557	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
558	struct sdhci_pxa *pxa = pltfm_host->priv;
559
560	clk_prepare_enable(pxa->clk_io);
561	if (!IS_ERR(pxa->clk_core))
562		clk_prepare_enable(pxa->clk_core);
563
564	return sdhci_runtime_resume_host(host);
565}
566#endif
567
568#ifdef CONFIG_PM
569static const struct dev_pm_ops sdhci_pxav3_pmops = {
570	SET_SYSTEM_SLEEP_PM_OPS(sdhci_pxav3_suspend, sdhci_pxav3_resume)
571	SET_RUNTIME_PM_OPS(sdhci_pxav3_runtime_suspend,
572		sdhci_pxav3_runtime_resume, NULL)
573};
574
575#define SDHCI_PXAV3_PMOPS (&sdhci_pxav3_pmops)
576
577#else
578#define SDHCI_PXAV3_PMOPS NULL
579#endif
580
581static struct platform_driver sdhci_pxav3_driver = {
582	.driver		= {
583		.name	= "sdhci-pxav3",
584#ifdef CONFIG_OF
585		.of_match_table = sdhci_pxav3_of_match,
586#endif
587		.pm	= SDHCI_PXAV3_PMOPS,
588	},
589	.probe		= sdhci_pxav3_probe,
590	.remove		= sdhci_pxav3_remove,
591};
592
593module_platform_driver(sdhci_pxav3_driver);
594
595MODULE_DESCRIPTION("SDHCI driver for pxav3");
596MODULE_AUTHOR("Marvell International Ltd.");
597MODULE_LICENSE("GPL v2");
598
599