1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * Roger Tseng <rogerable@realtek.com>
21 */
22
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/mfd/rtsx_pci.h>
26
27 #include "rtsx_pcr.h"
28
rts5227_fill_driving(struct rtsx_pcr * pcr,u8 voltage)29 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
30 {
31 u8 driving_3v3[4][3] = {
32 {0x13, 0x13, 0x13},
33 {0x96, 0x96, 0x96},
34 {0x7F, 0x7F, 0x7F},
35 {0x96, 0x96, 0x96},
36 };
37 u8 driving_1v8[4][3] = {
38 {0x99, 0x99, 0x99},
39 {0xAA, 0xAA, 0xAA},
40 {0xFE, 0xFE, 0xFE},
41 {0xB3, 0xB3, 0xB3},
42 };
43 u8 (*driving)[3], drive_sel;
44
45 if (voltage == OUTPUT_3V3) {
46 driving = driving_3v3;
47 drive_sel = pcr->sd30_drive_sel_3v3;
48 } else {
49 driving = driving_1v8;
50 drive_sel = pcr->sd30_drive_sel_1v8;
51 }
52
53 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
54 0xFF, driving[drive_sel][0]);
55 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
56 0xFF, driving[drive_sel][1]);
57 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
58 0xFF, driving[drive_sel][2]);
59 }
60
rts5227_fetch_vendor_settings(struct rtsx_pcr * pcr)61 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
62 {
63 u32 reg;
64
65 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
66 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
67
68 if (!rtsx_vendor_setting_valid(reg))
69 return;
70
71 pcr->aspm_en = rtsx_reg_to_aspm(reg);
72 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
73 pcr->card_drive_sel &= 0x3F;
74 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
75
76 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®);
77 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
78 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
79 if (rtsx_reg_check_reverse_socket(reg))
80 pcr->flags |= PCR_REVERSE_SOCKET;
81 }
82
rts5227_force_power_down(struct rtsx_pcr * pcr,u8 pm_state)83 static void rts5227_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
84 {
85 /* Set relink_time to 0 */
86 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0);
87 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0);
88 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0);
89
90 if (pm_state == HOST_ENTER_S3)
91 rtsx_pci_write_register(pcr, PM_CTRL3, 0x10, 0x10);
92
93 rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03);
94 }
95
rts5227_extra_init_hw(struct rtsx_pcr * pcr)96 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
97 {
98 u16 cap;
99
100 rtsx_pci_init_cmd(pcr);
101
102 /* Configure GPIO as output */
103 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
104 /* Reset ASPM state to default value */
105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
106 /* Switch LDO3318 source from DV33 to card_3v3 */
107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
109 /* LED shine disabled, set initial shine cycle period */
110 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
111 /* Configure LTR */
112 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
113 if (cap & PCI_EXP_DEVCTL2_LTR_EN)
114 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
115 /* Configure OBFF */
116 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
117 /* Configure driving */
118 rts5227_fill_driving(pcr, OUTPUT_3V3);
119 /* Configure force_clock_req */
120 if (pcr->flags & PCR_REVERSE_SOCKET)
121 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0xB8);
122 else
123 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB8, 0x88);
124 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x10, 0x00);
125
126 return rtsx_pci_send_cmd(pcr, 100);
127 }
128
rts5227_optimize_phy(struct rtsx_pcr * pcr)129 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
130 {
131 int err;
132
133 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
134 if (err < 0)
135 return err;
136
137 /* Optimize RX sensitivity */
138 return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
139 }
140
rts5227_turn_on_led(struct rtsx_pcr * pcr)141 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
142 {
143 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
144 }
145
rts5227_turn_off_led(struct rtsx_pcr * pcr)146 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
147 {
148 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
149 }
150
rts5227_enable_auto_blink(struct rtsx_pcr * pcr)151 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
152 {
153 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
154 }
155
rts5227_disable_auto_blink(struct rtsx_pcr * pcr)156 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
157 {
158 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
159 }
160
rts5227_card_power_on(struct rtsx_pcr * pcr,int card)161 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
162 {
163 int err;
164
165 rtsx_pci_init_cmd(pcr);
166 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
167 SD_POWER_MASK, SD_PARTIAL_POWER_ON);
168 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
169 LDO3318_PWR_MASK, 0x02);
170 err = rtsx_pci_send_cmd(pcr, 100);
171 if (err < 0)
172 return err;
173
174 /* To avoid too large in-rush current */
175 udelay(150);
176
177 rtsx_pci_init_cmd(pcr);
178 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
179 SD_POWER_MASK, SD_POWER_ON);
180 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
181 LDO3318_PWR_MASK, 0x06);
182 err = rtsx_pci_send_cmd(pcr, 100);
183 if (err < 0)
184 return err;
185
186 return 0;
187 }
188
rts5227_card_power_off(struct rtsx_pcr * pcr,int card)189 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
190 {
191 rtsx_pci_init_cmd(pcr);
192 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
193 SD_POWER_MASK | PMOS_STRG_MASK,
194 SD_POWER_OFF | PMOS_STRG_400mA);
195 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
196 LDO3318_PWR_MASK, 0X00);
197 return rtsx_pci_send_cmd(pcr, 100);
198 }
199
rts5227_switch_output_voltage(struct rtsx_pcr * pcr,u8 voltage)200 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
201 {
202 int err;
203
204 if (voltage == OUTPUT_3V3) {
205 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
206 if (err < 0)
207 return err;
208 } else if (voltage == OUTPUT_1V8) {
209 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
210 if (err < 0)
211 return err;
212 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
213 if (err < 0)
214 return err;
215 } else {
216 return -EINVAL;
217 }
218
219 /* set pad drive */
220 rtsx_pci_init_cmd(pcr);
221 rts5227_fill_driving(pcr, voltage);
222 return rtsx_pci_send_cmd(pcr, 100);
223 }
224
225 static const struct pcr_ops rts5227_pcr_ops = {
226 .fetch_vendor_settings = rts5227_fetch_vendor_settings,
227 .extra_init_hw = rts5227_extra_init_hw,
228 .optimize_phy = rts5227_optimize_phy,
229 .turn_on_led = rts5227_turn_on_led,
230 .turn_off_led = rts5227_turn_off_led,
231 .enable_auto_blink = rts5227_enable_auto_blink,
232 .disable_auto_blink = rts5227_disable_auto_blink,
233 .card_power_on = rts5227_card_power_on,
234 .card_power_off = rts5227_card_power_off,
235 .switch_output_voltage = rts5227_switch_output_voltage,
236 .cd_deglitch = NULL,
237 .conv_clk_and_div_n = NULL,
238 .force_power_down = rts5227_force_power_down,
239 };
240
241 /* SD Pull Control Enable:
242 * SD_DAT[3:0] ==> pull up
243 * SD_CD ==> pull up
244 * SD_WP ==> pull up
245 * SD_CMD ==> pull up
246 * SD_CLK ==> pull down
247 */
248 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
249 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
250 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
251 0,
252 };
253
254 /* SD Pull Control Disable:
255 * SD_DAT[3:0] ==> pull down
256 * SD_CD ==> pull up
257 * SD_WP ==> pull down
258 * SD_CMD ==> pull down
259 * SD_CLK ==> pull down
260 */
261 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
262 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
263 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
264 0,
265 };
266
267 /* MS Pull Control Enable:
268 * MS CD ==> pull up
269 * others ==> pull down
270 */
271 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
272 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
273 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
274 0,
275 };
276
277 /* MS Pull Control Disable:
278 * MS CD ==> pull up
279 * others ==> pull down
280 */
281 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
282 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
283 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
284 0,
285 };
286
rts5227_init_params(struct rtsx_pcr * pcr)287 void rts5227_init_params(struct rtsx_pcr *pcr)
288 {
289 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
290 pcr->num_slots = 2;
291 pcr->ops = &rts5227_pcr_ops;
292
293 pcr->flags = 0;
294 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
295 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
296 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
297 pcr->aspm_en = ASPM_L1_EN;
298 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
299 pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
300
301 pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
302 pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
303 pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
304 pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
305 }
306