1/*
2 * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/clk.h>
10#include <linux/interrupt.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/slab.h>
16
17#include "mc.h"
18
19#define MC_INTSTATUS 0x000
20#define  MC_INT_DECERR_MTS (1 << 16)
21#define  MC_INT_SECERR_SEC (1 << 13)
22#define  MC_INT_DECERR_VPR (1 << 12)
23#define  MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
24#define  MC_INT_INVALID_SMMU_PAGE (1 << 10)
25#define  MC_INT_ARBITRATION_EMEM (1 << 9)
26#define  MC_INT_SECURITY_VIOLATION (1 << 8)
27#define  MC_INT_DECERR_EMEM (1 << 6)
28
29#define MC_INTMASK 0x004
30
31#define MC_ERR_STATUS 0x08
32#define  MC_ERR_STATUS_TYPE_SHIFT 28
33#define  MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
34#define  MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
35#define  MC_ERR_STATUS_READABLE (1 << 27)
36#define  MC_ERR_STATUS_WRITABLE (1 << 26)
37#define  MC_ERR_STATUS_NONSECURE (1 << 25)
38#define  MC_ERR_STATUS_ADR_HI_SHIFT 20
39#define  MC_ERR_STATUS_ADR_HI_MASK 0x3
40#define  MC_ERR_STATUS_SECURITY (1 << 17)
41#define  MC_ERR_STATUS_RW (1 << 16)
42#define  MC_ERR_STATUS_CLIENT_MASK 0x7f
43
44#define MC_ERR_ADR 0x0c
45
46#define MC_EMEM_ARB_CFG 0x90
47#define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)	(((x) & 0x1ff) << 0)
48#define  MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK	0x1ff
49#define MC_EMEM_ARB_MISC0 0xd8
50
51static const struct of_device_id tegra_mc_of_match[] = {
52#ifdef CONFIG_ARCH_TEGRA_3x_SOC
53	{ .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
54#endif
55#ifdef CONFIG_ARCH_TEGRA_114_SOC
56	{ .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
57#endif
58#ifdef CONFIG_ARCH_TEGRA_124_SOC
59	{ .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
60#endif
61	{ }
62};
63MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
64
65static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
66{
67	unsigned long long tick;
68	unsigned int i;
69	u32 value;
70
71	/* compute the number of MC clock cycles per tick */
72	tick = mc->tick * clk_get_rate(mc->clk);
73	do_div(tick, NSEC_PER_SEC);
74
75	value = readl(mc->regs + MC_EMEM_ARB_CFG);
76	value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
77	value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
78	writel(value, mc->regs + MC_EMEM_ARB_CFG);
79
80	/* write latency allowance defaults */
81	for (i = 0; i < mc->soc->num_clients; i++) {
82		const struct tegra_mc_la *la = &mc->soc->clients[i].la;
83		u32 value;
84
85		value = readl(mc->regs + la->reg);
86		value &= ~(la->mask << la->shift);
87		value |= (la->def & la->mask) << la->shift;
88		writel(value, mc->regs + la->reg);
89	}
90
91	return 0;
92}
93
94static const char *const status_names[32] = {
95	[ 1] = "External interrupt",
96	[ 6] = "EMEM address decode error",
97	[ 8] = "Security violation",
98	[ 9] = "EMEM arbitration error",
99	[10] = "Page fault",
100	[11] = "Invalid APB ASID update",
101	[12] = "VPR violation",
102	[13] = "Secure carveout violation",
103	[16] = "MTS carveout violation",
104};
105
106static const char *const error_names[8] = {
107	[2] = "EMEM decode error",
108	[3] = "TrustZone violation",
109	[4] = "Carveout violation",
110	[6] = "SMMU translation error",
111};
112
113static irqreturn_t tegra_mc_irq(int irq, void *data)
114{
115	struct tegra_mc *mc = data;
116	unsigned long status, mask;
117	unsigned int bit;
118
119	/* mask all interrupts to avoid flooding */
120	status = mc_readl(mc, MC_INTSTATUS);
121	mask = mc_readl(mc, MC_INTMASK);
122
123	for_each_set_bit(bit, &status, 32) {
124		const char *error = status_names[bit] ?: "unknown";
125		const char *client = "unknown", *desc;
126		const char *direction, *secure;
127		phys_addr_t addr = 0;
128		unsigned int i;
129		char perm[7];
130		u8 id, type;
131		u32 value;
132
133		value = mc_readl(mc, MC_ERR_STATUS);
134
135#ifdef CONFIG_PHYS_ADDR_T_64BIT
136		if (mc->soc->num_address_bits > 32) {
137			addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
138				MC_ERR_STATUS_ADR_HI_MASK);
139			addr <<= 32;
140		}
141#endif
142
143		if (value & MC_ERR_STATUS_RW)
144			direction = "write";
145		else
146			direction = "read";
147
148		if (value & MC_ERR_STATUS_SECURITY)
149			secure = "secure ";
150		else
151			secure = "";
152
153		id = value & MC_ERR_STATUS_CLIENT_MASK;
154
155		for (i = 0; i < mc->soc->num_clients; i++) {
156			if (mc->soc->clients[i].id == id) {
157				client = mc->soc->clients[i].name;
158				break;
159			}
160		}
161
162		type = (value & MC_ERR_STATUS_TYPE_MASK) >>
163		       MC_ERR_STATUS_TYPE_SHIFT;
164		desc = error_names[type];
165
166		switch (value & MC_ERR_STATUS_TYPE_MASK) {
167		case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
168			perm[0] = ' ';
169			perm[1] = '[';
170
171			if (value & MC_ERR_STATUS_READABLE)
172				perm[2] = 'R';
173			else
174				perm[2] = '-';
175
176			if (value & MC_ERR_STATUS_WRITABLE)
177				perm[3] = 'W';
178			else
179				perm[3] = '-';
180
181			if (value & MC_ERR_STATUS_NONSECURE)
182				perm[4] = '-';
183			else
184				perm[4] = 'S';
185
186			perm[5] = ']';
187			perm[6] = '\0';
188			break;
189
190		default:
191			perm[0] = '\0';
192			break;
193		}
194
195		value = mc_readl(mc, MC_ERR_ADR);
196		addr |= value;
197
198		dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
199				    client, secure, direction, &addr, error,
200				    desc, perm);
201	}
202
203	/* clear interrupts */
204	mc_writel(mc, status, MC_INTSTATUS);
205
206	return IRQ_HANDLED;
207}
208
209static int tegra_mc_probe(struct platform_device *pdev)
210{
211	const struct of_device_id *match;
212	struct resource *res;
213	struct tegra_mc *mc;
214	u32 value;
215	int err;
216
217	match = of_match_node(tegra_mc_of_match, pdev->dev.of_node);
218	if (!match)
219		return -ENODEV;
220
221	mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
222	if (!mc)
223		return -ENOMEM;
224
225	platform_set_drvdata(pdev, mc);
226	mc->soc = match->data;
227	mc->dev = &pdev->dev;
228
229	/* length of MC tick in nanoseconds */
230	mc->tick = 30;
231
232	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
233	mc->regs = devm_ioremap_resource(&pdev->dev, res);
234	if (IS_ERR(mc->regs))
235		return PTR_ERR(mc->regs);
236
237	mc->clk = devm_clk_get(&pdev->dev, "mc");
238	if (IS_ERR(mc->clk)) {
239		dev_err(&pdev->dev, "failed to get MC clock: %ld\n",
240			PTR_ERR(mc->clk));
241		return PTR_ERR(mc->clk);
242	}
243
244	err = tegra_mc_setup_latency_allowance(mc);
245	if (err < 0) {
246		dev_err(&pdev->dev, "failed to setup latency allowance: %d\n",
247			err);
248		return err;
249	}
250
251	if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
252		mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
253		if (IS_ERR(mc->smmu)) {
254			dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
255				PTR_ERR(mc->smmu));
256			return PTR_ERR(mc->smmu);
257		}
258	}
259
260	mc->irq = platform_get_irq(pdev, 0);
261	if (mc->irq < 0) {
262		dev_err(&pdev->dev, "interrupt not specified\n");
263		return mc->irq;
264	}
265
266	err = devm_request_irq(&pdev->dev, mc->irq, tegra_mc_irq, IRQF_SHARED,
267			       dev_name(&pdev->dev), mc);
268	if (err < 0) {
269		dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
270			err);
271		return err;
272	}
273
274	value = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
275		MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
276		MC_INT_ARBITRATION_EMEM | MC_INT_SECURITY_VIOLATION |
277		MC_INT_DECERR_EMEM;
278	mc_writel(mc, value, MC_INTMASK);
279
280	return 0;
281}
282
283static struct platform_driver tegra_mc_driver = {
284	.driver = {
285		.name = "tegra-mc",
286		.of_match_table = tegra_mc_of_match,
287		.suppress_bind_attrs = true,
288	},
289	.prevent_deferred_probe = true,
290	.probe = tegra_mc_probe,
291};
292
293static int tegra_mc_init(void)
294{
295	return platform_driver_register(&tegra_mc_driver);
296}
297arch_initcall(tegra_mc_init);
298
299MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
300MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
301MODULE_LICENSE("GPL v2");
302