1/* 2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver 3 * 4 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 5 * 6 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com> 7 * Younghwan Joo <yhwan.joo@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__ 14 15#include <linux/device.h> 16#include <linux/debugfs.h> 17#include <linux/delay.h> 18#include <linux/dma-contiguous.h> 19#include <linux/errno.h> 20#include <linux/firmware.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/module.h> 24#include <linux/i2c.h> 25#include <linux/of_irq.h> 26#include <linux/of_address.h> 27#include <linux/of_graph.h> 28#include <linux/of_platform.h> 29#include <linux/platform_device.h> 30#include <linux/pm_runtime.h> 31#include <linux/slab.h> 32#include <linux/types.h> 33#include <linux/videodev2.h> 34#include <media/videobuf2-dma-contig.h> 35 36#include "media-dev.h" 37#include "fimc-is.h" 38#include "fimc-is-command.h" 39#include "fimc-is-errno.h" 40#include "fimc-is-i2c.h" 41#include "fimc-is-param.h" 42#include "fimc-is-regs.h" 43 44 45static char *fimc_is_clocks[ISS_CLKS_MAX] = { 46 [ISS_CLK_PPMUISPX] = "ppmuispx", 47 [ISS_CLK_PPMUISPMX] = "ppmuispmx", 48 [ISS_CLK_LITE0] = "lite0", 49 [ISS_CLK_LITE1] = "lite1", 50 [ISS_CLK_MPLL] = "mpll", 51 [ISS_CLK_ISP] = "isp", 52 [ISS_CLK_DRC] = "drc", 53 [ISS_CLK_FD] = "fd", 54 [ISS_CLK_MCUISP] = "mcuisp", 55 [ISS_CLK_UART] = "uart", 56 [ISS_CLK_ISP_DIV0] = "ispdiv0", 57 [ISS_CLK_ISP_DIV1] = "ispdiv1", 58 [ISS_CLK_MCUISP_DIV0] = "mcuispdiv0", 59 [ISS_CLK_MCUISP_DIV1] = "mcuispdiv1", 60 [ISS_CLK_ACLK200] = "aclk200", 61 [ISS_CLK_ACLK200_DIV] = "div_aclk200", 62 [ISS_CLK_ACLK400MCUISP] = "aclk400mcuisp", 63 [ISS_CLK_ACLK400MCUISP_DIV] = "div_aclk400mcuisp", 64}; 65 66static void fimc_is_put_clocks(struct fimc_is *is) 67{ 68 int i; 69 70 for (i = 0; i < ISS_CLKS_MAX; i++) { 71 if (IS_ERR(is->clocks[i])) 72 continue; 73 clk_put(is->clocks[i]); 74 is->clocks[i] = ERR_PTR(-EINVAL); 75 } 76} 77 78static int fimc_is_get_clocks(struct fimc_is *is) 79{ 80 int i, ret; 81 82 for (i = 0; i < ISS_CLKS_MAX; i++) 83 is->clocks[i] = ERR_PTR(-EINVAL); 84 85 for (i = 0; i < ISS_CLKS_MAX; i++) { 86 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]); 87 if (IS_ERR(is->clocks[i])) { 88 ret = PTR_ERR(is->clocks[i]); 89 goto err; 90 } 91 } 92 93 return 0; 94err: 95 fimc_is_put_clocks(is); 96 dev_err(&is->pdev->dev, "failed to get clock: %s\n", 97 fimc_is_clocks[i]); 98 return ret; 99} 100 101static int fimc_is_setup_clocks(struct fimc_is *is) 102{ 103 int ret; 104 105 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200], 106 is->clocks[ISS_CLK_ACLK200_DIV]); 107 if (ret < 0) 108 return ret; 109 110 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP], 111 is->clocks[ISS_CLK_ACLK400MCUISP_DIV]); 112 if (ret < 0) 113 return ret; 114 115 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY); 116 if (ret < 0) 117 return ret; 118 119 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY); 120 if (ret < 0) 121 return ret; 122 123 ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0], 124 ATCLK_MCUISP_FREQUENCY); 125 if (ret < 0) 126 return ret; 127 128 return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1], 129 ATCLK_MCUISP_FREQUENCY); 130} 131 132static int fimc_is_enable_clocks(struct fimc_is *is) 133{ 134 int i, ret; 135 136 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) { 137 if (IS_ERR(is->clocks[i])) 138 continue; 139 ret = clk_prepare_enable(is->clocks[i]); 140 if (ret < 0) { 141 dev_err(&is->pdev->dev, "clock %s enable failed\n", 142 fimc_is_clocks[i]); 143 for (--i; i >= 0; i--) 144 clk_disable(is->clocks[i]); 145 return ret; 146 } 147 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]); 148 } 149 return 0; 150} 151 152static void fimc_is_disable_clocks(struct fimc_is *is) 153{ 154 int i; 155 156 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) { 157 if (!IS_ERR(is->clocks[i])) { 158 clk_disable_unprepare(is->clocks[i]); 159 pr_debug("disabled clock: %s\n", fimc_is_clocks[i]); 160 } 161 } 162} 163 164static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index, 165 struct device_node *node) 166{ 167 struct fimc_is_sensor *sensor = &is->sensor[index]; 168 u32 tmp = 0; 169 int ret; 170 171 sensor->drvdata = fimc_is_sensor_get_drvdata(node); 172 if (!sensor->drvdata) { 173 dev_err(&is->pdev->dev, "no driver data found for: %s\n", 174 node->full_name); 175 return -EINVAL; 176 } 177 178 node = of_graph_get_next_endpoint(node, NULL); 179 if (!node) 180 return -ENXIO; 181 182 node = of_graph_get_remote_port(node); 183 if (!node) 184 return -ENXIO; 185 186 /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */ 187 ret = of_property_read_u32(node, "reg", &tmp); 188 if (ret < 0) { 189 dev_err(&is->pdev->dev, "reg property not found at: %s\n", 190 node->full_name); 191 return ret; 192 } 193 194 sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0; 195 return 0; 196} 197 198static int fimc_is_register_subdevs(struct fimc_is *is) 199{ 200 struct device_node *i2c_bus, *child; 201 int ret, index = 0; 202 203 ret = fimc_isp_subdev_create(&is->isp); 204 if (ret < 0) 205 return ret; 206 207 /* Initialize memory allocator context for the ISP DMA. */ 208 is->isp.alloc_ctx = is->alloc_ctx; 209 210 for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) { 211 for_each_available_child_of_node(i2c_bus, child) { 212 ret = fimc_is_parse_sensor_config(is, index, child); 213 214 if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) { 215 of_node_put(child); 216 return ret; 217 } 218 index++; 219 } 220 } 221 return 0; 222} 223 224static int fimc_is_unregister_subdevs(struct fimc_is *is) 225{ 226 fimc_isp_subdev_destroy(&is->isp); 227 return 0; 228} 229 230static int fimc_is_load_setfile(struct fimc_is *is, char *file_name) 231{ 232 const struct firmware *fw; 233 void *buf; 234 int ret; 235 236 ret = request_firmware(&fw, file_name, &is->pdev->dev); 237 if (ret < 0) { 238 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret); 239 return ret; 240 } 241 buf = is->memory.vaddr + is->setfile.base; 242 memcpy(buf, fw->data, fw->size); 243 fimc_is_mem_barrier(); 244 is->setfile.size = fw->size; 245 246 pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf); 247 248 memcpy(is->fw.setfile_info, 249 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN, 250 FIMC_IS_SETFILE_INFO_LEN - 1); 251 252 is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0'; 253 is->setfile.state = 1; 254 255 pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n", 256 is->setfile.base, fw->size); 257 258 release_firmware(fw); 259 return ret; 260} 261 262int fimc_is_cpu_set_power(struct fimc_is *is, int on) 263{ 264 unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT; 265 266 if (on) { 267 /* Disable watchdog */ 268 mcuctl_write(0, is, REG_WDT_ISP); 269 270 /* Cortex-A5 start address setting */ 271 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR); 272 273 /* Enable and start Cortex-A5 */ 274 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION); 275 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION); 276 } else { 277 /* A5 power off */ 278 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION); 279 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION); 280 281 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) { 282 if (timeout == 0) 283 return -ETIME; 284 timeout--; 285 udelay(1); 286 } 287 } 288 289 return 0; 290} 291 292/* Wait until @bit of @is->state is set to @state in the interrupt handler. */ 293int fimc_is_wait_event(struct fimc_is *is, unsigned long bit, 294 unsigned int state, unsigned int timeout) 295{ 296 297 int ret = wait_event_timeout(is->irq_queue, 298 !state ^ test_bit(bit, &is->state), 299 timeout); 300 if (ret == 0) { 301 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__); 302 return -ETIME; 303 } 304 return 0; 305} 306 307int fimc_is_start_firmware(struct fimc_is *is) 308{ 309 struct device *dev = &is->pdev->dev; 310 int ret; 311 312 if (is->fw.f_w == NULL) { 313 dev_err(dev, "firmware is not loaded\n"); 314 return -EINVAL; 315 } 316 317 memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size); 318 wmb(); 319 320 ret = fimc_is_cpu_set_power(is, 1); 321 if (ret < 0) 322 return ret; 323 324 ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1, 325 msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT)); 326 if (ret < 0) 327 dev_err(dev, "FIMC-IS CPU power on failed\n"); 328 329 return ret; 330} 331 332/* Allocate working memory for the FIMC-IS CPU. */ 333static int fimc_is_alloc_cpu_memory(struct fimc_is *is) 334{ 335 struct device *dev = &is->pdev->dev; 336 337 is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE, 338 &is->memory.paddr, GFP_KERNEL); 339 if (is->memory.vaddr == NULL) 340 return -ENOMEM; 341 342 is->memory.size = FIMC_IS_CPU_MEM_SIZE; 343 memset(is->memory.vaddr, 0, is->memory.size); 344 345 dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr); 346 347 if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) { 348 dev_err(dev, "invalid firmware memory alignment: %#x\n", 349 (u32)is->memory.paddr); 350 dma_free_coherent(dev, is->memory.size, is->memory.vaddr, 351 is->memory.paddr); 352 return -EIO; 353 } 354 355 is->is_p_region = (struct is_region *)(is->memory.vaddr + 356 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE); 357 358 is->is_dma_p_region = is->memory.paddr + 359 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE; 360 361 is->is_shared_region = (struct is_share_region *)(is->memory.vaddr + 362 FIMC_IS_SHARED_REGION_OFFSET); 363 return 0; 364} 365 366static void fimc_is_free_cpu_memory(struct fimc_is *is) 367{ 368 struct device *dev = &is->pdev->dev; 369 370 if (is->memory.vaddr == NULL) 371 return; 372 373 dma_free_coherent(dev, is->memory.size, is->memory.vaddr, 374 is->memory.paddr); 375} 376 377static void fimc_is_load_firmware(const struct firmware *fw, void *context) 378{ 379 struct fimc_is *is = context; 380 struct device *dev = &is->pdev->dev; 381 void *buf; 382 int ret; 383 384 if (fw == NULL) { 385 dev_err(dev, "firmware request failed\n"); 386 return; 387 } 388 mutex_lock(&is->lock); 389 390 if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) { 391 dev_err(dev, "wrong firmware size: %zu\n", fw->size); 392 goto done; 393 } 394 395 is->fw.size = fw->size; 396 397 ret = fimc_is_alloc_cpu_memory(is); 398 if (ret < 0) { 399 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n"); 400 goto done; 401 } 402 403 memcpy(is->memory.vaddr, fw->data, fw->size); 404 wmb(); 405 406 /* Read firmware description. */ 407 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN); 408 memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN); 409 is->fw.info[FIMC_IS_FW_INFO_LEN] = 0; 410 411 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN); 412 memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN); 413 is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0; 414 415 is->fw.state = 1; 416 417 dev_info(dev, "loaded firmware: %s, rev. %s\n", 418 is->fw.info, is->fw.version); 419 dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr); 420 421 is->is_shared_region->chip_id = 0xe4412; 422 is->is_shared_region->chip_rev_no = 1; 423 424 fimc_is_mem_barrier(); 425 426 /* 427 * FIXME: The firmware is not being released for now, as it is 428 * needed around for copying to the IS working memory every 429 * time before the Cortex-A5 is restarted. 430 */ 431 release_firmware(is->fw.f_w); 432 is->fw.f_w = fw; 433done: 434 mutex_unlock(&is->lock); 435} 436 437static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name) 438{ 439 return request_firmware_nowait(THIS_MODULE, 440 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev, 441 GFP_KERNEL, is, fimc_is_load_firmware); 442} 443 444/* General IS interrupt handler */ 445static void fimc_is_general_irq_handler(struct fimc_is *is) 446{ 447 is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10)); 448 449 switch (is->i2h_cmd.cmd) { 450 case IHC_GET_SENSOR_NUM: 451 fimc_is_hw_get_params(is, 1); 452 fimc_is_hw_wait_intmsr0_intmsd0(is); 453 fimc_is_hw_set_sensor_num(is); 454 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]); 455 break; 456 case IHC_SET_FACE_MARK: 457 case IHC_FRAME_DONE: 458 fimc_is_hw_get_params(is, 2); 459 break; 460 case IHC_SET_SHOT_MARK: 461 case IHC_AA_DONE: 462 case IH_REPLY_DONE: 463 fimc_is_hw_get_params(is, 3); 464 break; 465 case IH_REPLY_NOT_DONE: 466 fimc_is_hw_get_params(is, 4); 467 break; 468 case IHC_NOT_READY: 469 break; 470 default: 471 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd); 472 } 473 474 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL); 475 476 switch (is->i2h_cmd.cmd) { 477 case IHC_GET_SENSOR_NUM: 478 fimc_is_hw_set_intgr0_gd0(is); 479 set_bit(IS_ST_A5_PWR_ON, &is->state); 480 break; 481 482 case IHC_SET_SHOT_MARK: 483 break; 484 485 case IHC_SET_FACE_MARK: 486 is->fd_header.count = is->i2h_cmd.args[0]; 487 is->fd_header.index = is->i2h_cmd.args[1]; 488 is->fd_header.offset = 0; 489 break; 490 491 case IHC_FRAME_DONE: 492 break; 493 494 case IHC_AA_DONE: 495 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0], 496 is->i2h_cmd.args[1], is->i2h_cmd.args[2]); 497 break; 498 499 case IH_REPLY_DONE: 500 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]); 501 502 switch (is->i2h_cmd.args[0]) { 503 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO: 504 /* Get CAC margin */ 505 set_bit(IS_ST_CHANGE_MODE, &is->state); 506 is->isp.cac_margin_x = is->i2h_cmd.args[1]; 507 is->isp.cac_margin_y = is->i2h_cmd.args[2]; 508 pr_debug("CAC margin (x,y): (%d,%d)\n", 509 is->isp.cac_margin_x, is->isp.cac_margin_y); 510 break; 511 512 case HIC_STREAM_ON: 513 clear_bit(IS_ST_STREAM_OFF, &is->state); 514 set_bit(IS_ST_STREAM_ON, &is->state); 515 break; 516 517 case HIC_STREAM_OFF: 518 clear_bit(IS_ST_STREAM_ON, &is->state); 519 set_bit(IS_ST_STREAM_OFF, &is->state); 520 break; 521 522 case HIC_SET_PARAMETER: 523 is->config[is->config_index].p_region_index[0] = 0; 524 is->config[is->config_index].p_region_index[1] = 0; 525 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); 526 pr_debug("HIC_SET_PARAMETER\n"); 527 break; 528 529 case HIC_GET_PARAMETER: 530 break; 531 532 case HIC_SET_TUNE: 533 break; 534 535 case HIC_GET_STATUS: 536 break; 537 538 case HIC_OPEN_SENSOR: 539 set_bit(IS_ST_OPEN_SENSOR, &is->state); 540 pr_debug("data lanes: %d, settle line: %d\n", 541 is->i2h_cmd.args[2], is->i2h_cmd.args[1]); 542 break; 543 544 case HIC_CLOSE_SENSOR: 545 clear_bit(IS_ST_OPEN_SENSOR, &is->state); 546 is->sensor_index = 0; 547 break; 548 549 case HIC_MSG_TEST: 550 pr_debug("config MSG level completed\n"); 551 break; 552 553 case HIC_POWER_DOWN: 554 clear_bit(IS_ST_PWR_SUBIP_ON, &is->state); 555 break; 556 557 case HIC_GET_SET_FILE_ADDR: 558 is->setfile.base = is->i2h_cmd.args[1]; 559 set_bit(IS_ST_SETFILE_LOADED, &is->state); 560 break; 561 562 case HIC_LOAD_SET_FILE: 563 set_bit(IS_ST_SETFILE_LOADED, &is->state); 564 break; 565 } 566 break; 567 568 case IH_REPLY_NOT_DONE: 569 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0], 570 is->i2h_cmd.args[1], 571 fimc_is_strerr(is->i2h_cmd.args[1])); 572 573 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG) 574 pr_err("IS_ERROR_TIME_OUT\n"); 575 576 switch (is->i2h_cmd.args[1]) { 577 case IS_ERROR_SET_PARAMETER: 578 fimc_is_mem_barrier(); 579 } 580 581 switch (is->i2h_cmd.args[0]) { 582 case HIC_SET_PARAMETER: 583 is->config[is->config_index].p_region_index[0] = 0; 584 is->config[is->config_index].p_region_index[1] = 0; 585 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); 586 break; 587 } 588 break; 589 590 case IHC_NOT_READY: 591 pr_err("IS control sequence error: Not Ready\n"); 592 break; 593 } 594 595 wake_up(&is->irq_queue); 596} 597 598static irqreturn_t fimc_is_irq_handler(int irq, void *priv) 599{ 600 struct fimc_is *is = priv; 601 unsigned long flags; 602 u32 status; 603 604 spin_lock_irqsave(&is->slock, flags); 605 status = mcuctl_read(is, MCUCTL_REG_INTSR1); 606 607 if (status & (1UL << FIMC_IS_INT_GENERAL)) 608 fimc_is_general_irq_handler(is); 609 610 if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP)) 611 fimc_isp_irq_handler(is); 612 613 spin_unlock_irqrestore(&is->slock, flags); 614 return IRQ_HANDLED; 615} 616 617static int fimc_is_hw_open_sensor(struct fimc_is *is, 618 struct fimc_is_sensor *sensor) 619{ 620 struct sensor_open_extended *soe = (void *)&is->is_p_region->shared; 621 622 fimc_is_hw_wait_intmsr0_intmsd0(is); 623 624 soe->self_calibration_mode = 1; 625 soe->actuator_type = 0; 626 soe->mipi_lane_num = 0; 627 soe->mclk = 0; 628 soe->mipi_speed = 0; 629 soe->fast_open_sensor = 0; 630 soe->i2c_sclk = 88000000; 631 632 fimc_is_mem_barrier(); 633 634 mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0)); 635 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 636 mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2)); 637 mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3)); 638 mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4)); 639 640 fimc_is_hw_set_intgr0_gd0(is); 641 642 return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1, 643 sensor->drvdata->open_timeout); 644} 645 646 647int fimc_is_hw_initialize(struct fimc_is *is) 648{ 649 const int config_ids[] = { 650 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO, 651 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO 652 }; 653 struct device *dev = &is->pdev->dev; 654 u32 prev_id; 655 int i, ret; 656 657 /* Sensor initialization. Only one sensor is currently supported. */ 658 ret = fimc_is_hw_open_sensor(is, &is->sensor[0]); 659 if (ret < 0) 660 return ret; 661 662 /* Get the setfile address. */ 663 fimc_is_hw_get_setfile_addr(is); 664 665 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1, 666 FIMC_IS_CONFIG_TIMEOUT); 667 if (ret < 0) { 668 dev_err(dev, "get setfile address timed out\n"); 669 return ret; 670 } 671 pr_debug("setfile.base: %#x\n", is->setfile.base); 672 673 /* Load the setfile. */ 674 fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3); 675 clear_bit(IS_ST_SETFILE_LOADED, &is->state); 676 fimc_is_hw_load_setfile(is); 677 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1, 678 FIMC_IS_CONFIG_TIMEOUT); 679 if (ret < 0) { 680 dev_err(dev, "loading setfile timed out\n"); 681 return ret; 682 } 683 684 pr_debug("setfile: base: %#x, size: %d\n", 685 is->setfile.base, is->setfile.size); 686 pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info); 687 688 /* Check magic number. */ 689 if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] != 690 FIMC_IS_MAGIC_NUMBER) { 691 dev_err(dev, "magic number error!\n"); 692 return -EIO; 693 } 694 695 pr_debug("shared region: %pad, parameter region: %pad\n", 696 &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET, 697 &is->is_dma_p_region); 698 699 is->setfile.sub_index = 0; 700 701 /* Stream off. */ 702 fimc_is_hw_stream_off(is); 703 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1, 704 FIMC_IS_CONFIG_TIMEOUT); 705 if (ret < 0) { 706 dev_err(dev, "stream off timeout\n"); 707 return ret; 708 } 709 710 /* Preserve previous mode. */ 711 prev_id = is->config_index; 712 713 /* Set initial parameter values. */ 714 for (i = 0; i < ARRAY_SIZE(config_ids); i++) { 715 is->config_index = config_ids[i]; 716 fimc_is_set_initial_params(is); 717 ret = fimc_is_itf_s_param(is, true); 718 if (ret < 0) { 719 is->config_index = prev_id; 720 return ret; 721 } 722 } 723 is->config_index = prev_id; 724 725 set_bit(IS_ST_INIT_DONE, &is->state); 726 dev_info(dev, "initialization sequence completed (%d)\n", 727 is->config_index); 728 return 0; 729} 730 731static int fimc_is_log_show(struct seq_file *s, void *data) 732{ 733 struct fimc_is *is = s->private; 734 const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET; 735 736 if (is->memory.vaddr == NULL) { 737 dev_err(&is->pdev->dev, "firmware memory is not initialized\n"); 738 return -EIO; 739 } 740 741 seq_printf(s, "%s\n", buf); 742 return 0; 743} 744 745static int fimc_is_debugfs_open(struct inode *inode, struct file *file) 746{ 747 return single_open(file, fimc_is_log_show, inode->i_private); 748} 749 750static const struct file_operations fimc_is_debugfs_fops = { 751 .open = fimc_is_debugfs_open, 752 .read = seq_read, 753 .llseek = seq_lseek, 754 .release = single_release, 755}; 756 757static void fimc_is_debugfs_remove(struct fimc_is *is) 758{ 759 debugfs_remove_recursive(is->debugfs_entry); 760 is->debugfs_entry = NULL; 761} 762 763static int fimc_is_debugfs_create(struct fimc_is *is) 764{ 765 struct dentry *dentry; 766 767 is->debugfs_entry = debugfs_create_dir("fimc_is", NULL); 768 769 dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry, 770 is, &fimc_is_debugfs_fops); 771 if (!dentry) 772 fimc_is_debugfs_remove(is); 773 774 return is->debugfs_entry == NULL ? -EIO : 0; 775} 776 777static int fimc_is_runtime_resume(struct device *dev); 778static int fimc_is_runtime_suspend(struct device *dev); 779 780static int fimc_is_probe(struct platform_device *pdev) 781{ 782 struct device *dev = &pdev->dev; 783 struct fimc_is *is; 784 struct resource res; 785 struct device_node *node; 786 int ret; 787 788 is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL); 789 if (!is) 790 return -ENOMEM; 791 792 is->pdev = pdev; 793 is->isp.pdev = pdev; 794 795 init_waitqueue_head(&is->irq_queue); 796 spin_lock_init(&is->slock); 797 mutex_init(&is->lock); 798 799 ret = of_address_to_resource(dev->of_node, 0, &res); 800 if (ret < 0) 801 return ret; 802 803 is->regs = devm_ioremap_resource(dev, &res); 804 if (IS_ERR(is->regs)) 805 return PTR_ERR(is->regs); 806 807 node = of_get_child_by_name(dev->of_node, "pmu"); 808 if (!node) 809 return -ENODEV; 810 811 is->pmu_regs = of_iomap(node, 0); 812 if (!is->pmu_regs) 813 return -ENOMEM; 814 815 is->irq = irq_of_parse_and_map(dev->of_node, 0); 816 if (!is->irq) { 817 dev_err(dev, "no irq found\n"); 818 return -EINVAL; 819 } 820 821 ret = fimc_is_get_clocks(is); 822 if (ret < 0) 823 return ret; 824 825 platform_set_drvdata(pdev, is); 826 827 ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is); 828 if (ret < 0) { 829 dev_err(dev, "irq request failed\n"); 830 goto err_clk; 831 } 832 pm_runtime_enable(dev); 833 834 if (!pm_runtime_enabled(dev)) { 835 ret = fimc_is_runtime_resume(dev); 836 if (ret < 0) 837 goto err_irq; 838 } 839 840 ret = pm_runtime_get_sync(dev); 841 if (ret < 0) 842 goto err_pm; 843 844 is->alloc_ctx = vb2_dma_contig_init_ctx(dev); 845 if (IS_ERR(is->alloc_ctx)) { 846 ret = PTR_ERR(is->alloc_ctx); 847 goto err_pm; 848 } 849 /* 850 * Register FIMC-IS V4L2 subdevs to this driver. The video nodes 851 * will be created within the subdev's registered() callback. 852 */ 853 ret = fimc_is_register_subdevs(is); 854 if (ret < 0) 855 goto err_vb; 856 857 ret = fimc_is_debugfs_create(is); 858 if (ret < 0) 859 goto err_sd; 860 861 ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME); 862 if (ret < 0) 863 goto err_dfs; 864 865 pm_runtime_put_sync(dev); 866 867 dev_dbg(dev, "FIMC-IS registered successfully\n"); 868 return 0; 869 870err_dfs: 871 fimc_is_debugfs_remove(is); 872err_sd: 873 fimc_is_unregister_subdevs(is); 874err_vb: 875 vb2_dma_contig_cleanup_ctx(is->alloc_ctx); 876err_pm: 877 if (!pm_runtime_enabled(dev)) 878 fimc_is_runtime_suspend(dev); 879err_irq: 880 free_irq(is->irq, is); 881err_clk: 882 fimc_is_put_clocks(is); 883 return ret; 884} 885 886static int fimc_is_runtime_resume(struct device *dev) 887{ 888 struct fimc_is *is = dev_get_drvdata(dev); 889 int ret; 890 891 ret = fimc_is_setup_clocks(is); 892 if (ret) 893 return ret; 894 895 return fimc_is_enable_clocks(is); 896} 897 898static int fimc_is_runtime_suspend(struct device *dev) 899{ 900 struct fimc_is *is = dev_get_drvdata(dev); 901 902 fimc_is_disable_clocks(is); 903 return 0; 904} 905 906#ifdef CONFIG_PM_SLEEP 907static int fimc_is_resume(struct device *dev) 908{ 909 /* TODO: */ 910 return 0; 911} 912 913static int fimc_is_suspend(struct device *dev) 914{ 915 struct fimc_is *is = dev_get_drvdata(dev); 916 917 /* TODO: */ 918 if (test_bit(IS_ST_A5_PWR_ON, &is->state)) 919 return -EBUSY; 920 921 return 0; 922} 923#endif /* CONFIG_PM_SLEEP */ 924 925static int fimc_is_remove(struct platform_device *pdev) 926{ 927 struct device *dev = &pdev->dev; 928 struct fimc_is *is = dev_get_drvdata(dev); 929 930 pm_runtime_disable(dev); 931 pm_runtime_set_suspended(dev); 932 if (!pm_runtime_status_suspended(dev)) 933 fimc_is_runtime_suspend(dev); 934 free_irq(is->irq, is); 935 fimc_is_unregister_subdevs(is); 936 vb2_dma_contig_cleanup_ctx(is->alloc_ctx); 937 fimc_is_put_clocks(is); 938 fimc_is_debugfs_remove(is); 939 release_firmware(is->fw.f_w); 940 fimc_is_free_cpu_memory(is); 941 942 return 0; 943} 944 945static const struct of_device_id fimc_is_of_match[] = { 946 { .compatible = "samsung,exynos4212-fimc-is" }, 947 { /* sentinel */ }, 948}; 949MODULE_DEVICE_TABLE(of, fimc_is_of_match); 950 951static const struct dev_pm_ops fimc_is_pm_ops = { 952 SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume) 953 SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume, 954 NULL) 955}; 956 957static struct platform_driver fimc_is_driver = { 958 .probe = fimc_is_probe, 959 .remove = fimc_is_remove, 960 .driver = { 961 .of_match_table = fimc_is_of_match, 962 .name = FIMC_IS_DRV_NAME, 963 .pm = &fimc_is_pm_ops, 964 } 965}; 966 967static int fimc_is_module_init(void) 968{ 969 int ret; 970 971 ret = fimc_is_register_i2c_driver(); 972 if (ret < 0) 973 return ret; 974 975 ret = platform_driver_register(&fimc_is_driver); 976 977 if (ret < 0) 978 fimc_is_unregister_i2c_driver(); 979 980 return ret; 981} 982 983static void fimc_is_module_exit(void) 984{ 985 fimc_is_unregister_i2c_driver(); 986 platform_driver_unregister(&fimc_is_driver); 987} 988 989module_init(fimc_is_module_init); 990module_exit(fimc_is_module_exit); 991 992MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME); 993MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>"); 994MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>"); 995MODULE_LICENSE("GPL v2"); 996