1/* 2 * OmniVision OV96xx Camera Driver 3 * 4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> 5 * 6 * Based on ov772x camera driver: 7 * 8 * Copyright (C) 2008 Renesas Solutions Corp. 9 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 10 * 11 * Based on ov7670 and soc_camera_platform driver, 12 * 13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 14 * Copyright (C) 2008 Magnus Damm 15 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> 16 * 17 * This program is free software; you can redistribute it and/or modify 18 * it under the terms of the GNU General Public License version 2 as 19 * published by the Free Software Foundation. 20 */ 21 22#include <linux/init.h> 23#include <linux/module.h> 24#include <linux/i2c.h> 25#include <linux/slab.h> 26#include <linux/delay.h> 27#include <linux/v4l2-mediabus.h> 28#include <linux/videodev2.h> 29 30#include <media/soc_camera.h> 31#include <media/v4l2-clk.h> 32#include <media/v4l2-common.h> 33#include <media/v4l2-ctrls.h> 34 35#include "ov9640.h" 36 37#define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev) 38 39/* default register setup */ 40static const struct ov9640_reg ov9640_regs_dflt[] = { 41 { OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP }, 42 { OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS | 43 OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN }, 44 { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) }, 45 { OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD }, 46 { OV9640_TSLB, OV9640_TSLB_YUYV_UYVY }, 47 { OV9640_COM16, OV9640_COM16_RB_AVG }, 48 49 /* Gamma curve P */ 50 { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 }, 51 { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 }, 52 { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 }, 53 { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 }, 54 55 /* Gamma curve T */ 56 { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 }, 57 { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 }, 58 { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e }, 59 { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 }, 60}; 61 62/* Configurations 63 * NOTE: for YUV, alter the following registers: 64 * COM12 |= OV9640_COM12_YUV_AVG 65 * 66 * for RGB, alter the following registers: 67 * COM7 |= OV9640_COM7_RGB 68 * COM13 |= OV9640_COM13_RGB_AVG 69 * COM15 |= proper RGB color encoding mode 70 */ 71static const struct ov9640_reg ov9640_regs_qqcif[] = { 72 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) }, 73 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP }, 74 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, 75 { OV9640_COM7, OV9640_COM7_QCIF }, 76 { OV9640_COM12, OV9640_COM12_RSVD }, 77 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, 78 { OV9640_COM15, OV9640_COM15_OR_10F0 }, 79}; 80 81static const struct ov9640_reg ov9640_regs_qqvga[] = { 82 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) }, 83 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP }, 84 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, 85 { OV9640_COM7, OV9640_COM7_QVGA }, 86 { OV9640_COM12, OV9640_COM12_RSVD }, 87 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, 88 { OV9640_COM15, OV9640_COM15_OR_10F0 }, 89}; 90 91static const struct ov9640_reg ov9640_regs_qcif[] = { 92 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) }, 93 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, 94 { OV9640_COM7, OV9640_COM7_QCIF }, 95 { OV9640_COM12, OV9640_COM12_RSVD }, 96 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, 97 { OV9640_COM15, OV9640_COM15_OR_10F0 }, 98}; 99 100static const struct ov9640_reg ov9640_regs_qvga[] = { 101 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) }, 102 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, 103 { OV9640_COM7, OV9640_COM7_QVGA }, 104 { OV9640_COM12, OV9640_COM12_RSVD }, 105 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, 106 { OV9640_COM15, OV9640_COM15_OR_10F0 }, 107}; 108 109static const struct ov9640_reg ov9640_regs_cif[] = { 110 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) }, 111 { OV9640_COM3, OV9640_COM3_VP }, 112 { OV9640_COM7, OV9640_COM7_CIF }, 113 { OV9640_COM12, OV9640_COM12_RSVD }, 114 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, 115 { OV9640_COM15, OV9640_COM15_OR_10F0 }, 116}; 117 118static const struct ov9640_reg ov9640_regs_vga[] = { 119 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) }, 120 { OV9640_COM3, OV9640_COM3_VP }, 121 { OV9640_COM7, OV9640_COM7_VGA }, 122 { OV9640_COM12, OV9640_COM12_RSVD }, 123 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, 124 { OV9640_COM15, OV9640_COM15_OR_10F0 }, 125}; 126 127static const struct ov9640_reg ov9640_regs_sxga[] = { 128 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) }, 129 { OV9640_COM3, OV9640_COM3_VP }, 130 { OV9640_COM7, 0 }, 131 { OV9640_COM12, OV9640_COM12_RSVD }, 132 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, 133 { OV9640_COM15, OV9640_COM15_OR_10F0 }, 134}; 135 136static const struct ov9640_reg ov9640_regs_yuv[] = { 137 { OV9640_MTX1, 0x58 }, 138 { OV9640_MTX2, 0x48 }, 139 { OV9640_MTX3, 0x10 }, 140 { OV9640_MTX4, 0x28 }, 141 { OV9640_MTX5, 0x48 }, 142 { OV9640_MTX6, 0x70 }, 143 { OV9640_MTX7, 0x40 }, 144 { OV9640_MTX8, 0x40 }, 145 { OV9640_MTX9, 0x40 }, 146 { OV9640_MTXS, 0x0f }, 147}; 148 149static const struct ov9640_reg ov9640_regs_rgb[] = { 150 { OV9640_MTX1, 0x71 }, 151 { OV9640_MTX2, 0x3e }, 152 { OV9640_MTX3, 0x0c }, 153 { OV9640_MTX4, 0x33 }, 154 { OV9640_MTX5, 0x72 }, 155 { OV9640_MTX6, 0x00 }, 156 { OV9640_MTX7, 0x2b }, 157 { OV9640_MTX8, 0x66 }, 158 { OV9640_MTX9, 0xd2 }, 159 { OV9640_MTXS, 0x65 }, 160}; 161 162static u32 ov9640_codes[] = { 163 MEDIA_BUS_FMT_UYVY8_2X8, 164 MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, 165 MEDIA_BUS_FMT_RGB565_2X8_LE, 166}; 167 168/* read a register */ 169static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val) 170{ 171 int ret; 172 u8 data = reg; 173 struct i2c_msg msg = { 174 .addr = client->addr, 175 .flags = 0, 176 .len = 1, 177 .buf = &data, 178 }; 179 180 ret = i2c_transfer(client->adapter, &msg, 1); 181 if (ret < 0) 182 goto err; 183 184 msg.flags = I2C_M_RD; 185 ret = i2c_transfer(client->adapter, &msg, 1); 186 if (ret < 0) 187 goto err; 188 189 *val = data; 190 return 0; 191 192err: 193 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); 194 return ret; 195} 196 197/* write a register */ 198static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val) 199{ 200 int ret; 201 u8 _val; 202 unsigned char data[2] = { reg, val }; 203 struct i2c_msg msg = { 204 .addr = client->addr, 205 .flags = 0, 206 .len = 2, 207 .buf = data, 208 }; 209 210 ret = i2c_transfer(client->adapter, &msg, 1); 211 if (ret < 0) { 212 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); 213 return ret; 214 } 215 216 /* we have to read the register back ... no idea why, maybe HW bug */ 217 ret = ov9640_reg_read(client, reg, &_val); 218 if (ret) 219 dev_err(&client->dev, 220 "Failed reading back register 0x%02x!\n", reg); 221 222 return 0; 223} 224 225 226/* Read a register, alter its bits, write it back */ 227static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset) 228{ 229 u8 val; 230 int ret; 231 232 ret = ov9640_reg_read(client, reg, &val); 233 if (ret) { 234 dev_err(&client->dev, 235 "[Read]-Modify-Write of register %02x failed!\n", reg); 236 return val; 237 } 238 239 val |= set; 240 val &= ~unset; 241 242 ret = ov9640_reg_write(client, reg, val); 243 if (ret) 244 dev_err(&client->dev, 245 "Read-Modify-[Write] of register %02x failed!\n", reg); 246 247 return ret; 248} 249 250/* Soft reset the camera. This has nothing to do with the RESET pin! */ 251static int ov9640_reset(struct i2c_client *client) 252{ 253 int ret; 254 255 ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET); 256 if (ret) 257 dev_err(&client->dev, 258 "An error occurred while entering soft reset!\n"); 259 260 return ret; 261} 262 263/* Start/Stop streaming from the device */ 264static int ov9640_s_stream(struct v4l2_subdev *sd, int enable) 265{ 266 return 0; 267} 268 269/* Set status of additional camera capabilities */ 270static int ov9640_s_ctrl(struct v4l2_ctrl *ctrl) 271{ 272 struct ov9640_priv *priv = container_of(ctrl->handler, struct ov9640_priv, hdl); 273 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); 274 275 switch (ctrl->id) { 276 case V4L2_CID_VFLIP: 277 if (ctrl->val) 278 return ov9640_reg_rmw(client, OV9640_MVFP, 279 OV9640_MVFP_V, 0); 280 return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_V); 281 case V4L2_CID_HFLIP: 282 if (ctrl->val) 283 return ov9640_reg_rmw(client, OV9640_MVFP, 284 OV9640_MVFP_H, 0); 285 return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_H); 286 } 287 return -EINVAL; 288} 289 290#ifdef CONFIG_VIDEO_ADV_DEBUG 291static int ov9640_get_register(struct v4l2_subdev *sd, 292 struct v4l2_dbg_register *reg) 293{ 294 struct i2c_client *client = v4l2_get_subdevdata(sd); 295 int ret; 296 u8 val; 297 298 if (reg->reg & ~0xff) 299 return -EINVAL; 300 301 reg->size = 1; 302 303 ret = ov9640_reg_read(client, reg->reg, &val); 304 if (ret) 305 return ret; 306 307 reg->val = (__u64)val; 308 309 return 0; 310} 311 312static int ov9640_set_register(struct v4l2_subdev *sd, 313 const struct v4l2_dbg_register *reg) 314{ 315 struct i2c_client *client = v4l2_get_subdevdata(sd); 316 317 if (reg->reg & ~0xff || reg->val & ~0xff) 318 return -EINVAL; 319 320 return ov9640_reg_write(client, reg->reg, reg->val); 321} 322#endif 323 324static int ov9640_s_power(struct v4l2_subdev *sd, int on) 325{ 326 struct i2c_client *client = v4l2_get_subdevdata(sd); 327 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 328 struct ov9640_priv *priv = to_ov9640_sensor(sd); 329 330 return soc_camera_set_power(&client->dev, ssdd, priv->clk, on); 331} 332 333/* select nearest higher resolution for capture */ 334static void ov9640_res_roundup(u32 *width, u32 *height) 335{ 336 int i; 337 enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA }; 338 int res_x[] = { 88, 160, 176, 320, 352, 640, 1280 }; 339 int res_y[] = { 72, 120, 144, 240, 288, 480, 960 }; 340 341 for (i = 0; i < ARRAY_SIZE(res_x); i++) { 342 if (res_x[i] >= *width && res_y[i] >= *height) { 343 *width = res_x[i]; 344 *height = res_y[i]; 345 return; 346 } 347 } 348 349 *width = res_x[SXGA]; 350 *height = res_y[SXGA]; 351} 352 353/* Prepare necessary register changes depending on color encoding */ 354static void ov9640_alter_regs(u32 code, 355 struct ov9640_reg_alt *alt) 356{ 357 switch (code) { 358 default: 359 case MEDIA_BUS_FMT_UYVY8_2X8: 360 alt->com12 = OV9640_COM12_YUV_AVG; 361 alt->com13 = OV9640_COM13_Y_DELAY_EN | 362 OV9640_COM13_YUV_DLY(0x01); 363 break; 364 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 365 alt->com7 = OV9640_COM7_RGB; 366 alt->com13 = OV9640_COM13_RGB_AVG; 367 alt->com15 = OV9640_COM15_RGB_555; 368 break; 369 case MEDIA_BUS_FMT_RGB565_2X8_LE: 370 alt->com7 = OV9640_COM7_RGB; 371 alt->com13 = OV9640_COM13_RGB_AVG; 372 alt->com15 = OV9640_COM15_RGB_565; 373 break; 374 } 375} 376 377/* Setup registers according to resolution and color encoding */ 378static int ov9640_write_regs(struct i2c_client *client, u32 width, 379 u32 code, struct ov9640_reg_alt *alts) 380{ 381 const struct ov9640_reg *ov9640_regs, *matrix_regs; 382 int ov9640_regs_len, matrix_regs_len; 383 int i, ret; 384 u8 val; 385 386 /* select register configuration for given resolution */ 387 switch (width) { 388 case W_QQCIF: 389 ov9640_regs = ov9640_regs_qqcif; 390 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif); 391 break; 392 case W_QQVGA: 393 ov9640_regs = ov9640_regs_qqvga; 394 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga); 395 break; 396 case W_QCIF: 397 ov9640_regs = ov9640_regs_qcif; 398 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif); 399 break; 400 case W_QVGA: 401 ov9640_regs = ov9640_regs_qvga; 402 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga); 403 break; 404 case W_CIF: 405 ov9640_regs = ov9640_regs_cif; 406 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif); 407 break; 408 case W_VGA: 409 ov9640_regs = ov9640_regs_vga; 410 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga); 411 break; 412 case W_SXGA: 413 ov9640_regs = ov9640_regs_sxga; 414 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga); 415 break; 416 default: 417 dev_err(&client->dev, "Failed to select resolution!\n"); 418 return -EINVAL; 419 } 420 421 /* select color matrix configuration for given color encoding */ 422 if (code == MEDIA_BUS_FMT_UYVY8_2X8) { 423 matrix_regs = ov9640_regs_yuv; 424 matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv); 425 } else { 426 matrix_regs = ov9640_regs_rgb; 427 matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb); 428 } 429 430 /* write register settings into the module */ 431 for (i = 0; i < ov9640_regs_len; i++) { 432 val = ov9640_regs[i].val; 433 434 switch (ov9640_regs[i].reg) { 435 case OV9640_COM7: 436 val |= alts->com7; 437 break; 438 case OV9640_COM12: 439 val |= alts->com12; 440 break; 441 case OV9640_COM13: 442 val |= alts->com13; 443 break; 444 case OV9640_COM15: 445 val |= alts->com15; 446 break; 447 } 448 449 ret = ov9640_reg_write(client, ov9640_regs[i].reg, val); 450 if (ret) 451 return ret; 452 } 453 454 /* write color matrix configuration into the module */ 455 for (i = 0; i < matrix_regs_len; i++) { 456 ret = ov9640_reg_write(client, matrix_regs[i].reg, 457 matrix_regs[i].val); 458 if (ret) 459 return ret; 460 } 461 462 return 0; 463} 464 465/* program default register values */ 466static int ov9640_prog_dflt(struct i2c_client *client) 467{ 468 int i, ret; 469 470 for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) { 471 ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg, 472 ov9640_regs_dflt[i].val); 473 if (ret) 474 return ret; 475 } 476 477 /* wait for the changes to actually happen, 140ms are not enough yet */ 478 mdelay(150); 479 480 return 0; 481} 482 483/* set the format we will capture in */ 484static int ov9640_s_fmt(struct v4l2_subdev *sd, 485 struct v4l2_mbus_framefmt *mf) 486{ 487 struct i2c_client *client = v4l2_get_subdevdata(sd); 488 struct ov9640_reg_alt alts = {0}; 489 enum v4l2_colorspace cspace; 490 u32 code = mf->code; 491 int ret; 492 493 ov9640_res_roundup(&mf->width, &mf->height); 494 ov9640_alter_regs(mf->code, &alts); 495 496 ov9640_reset(client); 497 498 ret = ov9640_prog_dflt(client); 499 if (ret) 500 return ret; 501 502 switch (code) { 503 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 504 case MEDIA_BUS_FMT_RGB565_2X8_LE: 505 cspace = V4L2_COLORSPACE_SRGB; 506 break; 507 default: 508 code = MEDIA_BUS_FMT_UYVY8_2X8; 509 case MEDIA_BUS_FMT_UYVY8_2X8: 510 cspace = V4L2_COLORSPACE_JPEG; 511 } 512 513 ret = ov9640_write_regs(client, mf->width, code, &alts); 514 if (!ret) { 515 mf->code = code; 516 mf->colorspace = cspace; 517 } 518 519 return ret; 520} 521 522static int ov9640_try_fmt(struct v4l2_subdev *sd, 523 struct v4l2_mbus_framefmt *mf) 524{ 525 ov9640_res_roundup(&mf->width, &mf->height); 526 527 mf->field = V4L2_FIELD_NONE; 528 529 switch (mf->code) { 530 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: 531 case MEDIA_BUS_FMT_RGB565_2X8_LE: 532 mf->colorspace = V4L2_COLORSPACE_SRGB; 533 break; 534 default: 535 mf->code = MEDIA_BUS_FMT_UYVY8_2X8; 536 case MEDIA_BUS_FMT_UYVY8_2X8: 537 mf->colorspace = V4L2_COLORSPACE_JPEG; 538 } 539 540 return 0; 541} 542 543static int ov9640_enum_fmt(struct v4l2_subdev *sd, unsigned int index, 544 u32 *code) 545{ 546 if (index >= ARRAY_SIZE(ov9640_codes)) 547 return -EINVAL; 548 549 *code = ov9640_codes[index]; 550 return 0; 551} 552 553static int ov9640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) 554{ 555 a->c.left = 0; 556 a->c.top = 0; 557 a->c.width = W_SXGA; 558 a->c.height = H_SXGA; 559 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 560 561 return 0; 562} 563 564static int ov9640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) 565{ 566 a->bounds.left = 0; 567 a->bounds.top = 0; 568 a->bounds.width = W_SXGA; 569 a->bounds.height = H_SXGA; 570 a->defrect = a->bounds; 571 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 572 a->pixelaspect.numerator = 1; 573 a->pixelaspect.denominator = 1; 574 575 return 0; 576} 577 578static int ov9640_video_probe(struct i2c_client *client) 579{ 580 struct v4l2_subdev *sd = i2c_get_clientdata(client); 581 struct ov9640_priv *priv = to_ov9640_sensor(sd); 582 u8 pid, ver, midh, midl; 583 const char *devname; 584 int ret; 585 586 ret = ov9640_s_power(&priv->subdev, 1); 587 if (ret < 0) 588 return ret; 589 590 /* 591 * check and show product ID and manufacturer ID 592 */ 593 594 ret = ov9640_reg_read(client, OV9640_PID, &pid); 595 if (!ret) 596 ret = ov9640_reg_read(client, OV9640_VER, &ver); 597 if (!ret) 598 ret = ov9640_reg_read(client, OV9640_MIDH, &midh); 599 if (!ret) 600 ret = ov9640_reg_read(client, OV9640_MIDL, &midl); 601 if (ret) 602 goto done; 603 604 switch (VERSION(pid, ver)) { 605 case OV9640_V2: 606 devname = "ov9640"; 607 priv->revision = 2; 608 break; 609 case OV9640_V3: 610 devname = "ov9640"; 611 priv->revision = 3; 612 break; 613 default: 614 dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver); 615 ret = -ENODEV; 616 goto done; 617 } 618 619 dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", 620 devname, pid, ver, midh, midl); 621 622 ret = v4l2_ctrl_handler_setup(&priv->hdl); 623 624done: 625 ov9640_s_power(&priv->subdev, 0); 626 return ret; 627} 628 629static const struct v4l2_ctrl_ops ov9640_ctrl_ops = { 630 .s_ctrl = ov9640_s_ctrl, 631}; 632 633static struct v4l2_subdev_core_ops ov9640_core_ops = { 634#ifdef CONFIG_VIDEO_ADV_DEBUG 635 .g_register = ov9640_get_register, 636 .s_register = ov9640_set_register, 637#endif 638 .s_power = ov9640_s_power, 639}; 640 641/* Request bus settings on camera side */ 642static int ov9640_g_mbus_config(struct v4l2_subdev *sd, 643 struct v4l2_mbus_config *cfg) 644{ 645 struct i2c_client *client = v4l2_get_subdevdata(sd); 646 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 647 648 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | 649 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | 650 V4L2_MBUS_DATA_ACTIVE_HIGH; 651 cfg->type = V4L2_MBUS_PARALLEL; 652 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); 653 654 return 0; 655} 656 657static struct v4l2_subdev_video_ops ov9640_video_ops = { 658 .s_stream = ov9640_s_stream, 659 .s_mbus_fmt = ov9640_s_fmt, 660 .try_mbus_fmt = ov9640_try_fmt, 661 .enum_mbus_fmt = ov9640_enum_fmt, 662 .cropcap = ov9640_cropcap, 663 .g_crop = ov9640_g_crop, 664 .g_mbus_config = ov9640_g_mbus_config, 665}; 666 667static struct v4l2_subdev_ops ov9640_subdev_ops = { 668 .core = &ov9640_core_ops, 669 .video = &ov9640_video_ops, 670}; 671 672/* 673 * i2c_driver function 674 */ 675static int ov9640_probe(struct i2c_client *client, 676 const struct i2c_device_id *did) 677{ 678 struct ov9640_priv *priv; 679 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); 680 int ret; 681 682 if (!ssdd) { 683 dev_err(&client->dev, "Missing platform_data for driver\n"); 684 return -EINVAL; 685 } 686 687 priv = devm_kzalloc(&client->dev, sizeof(struct ov9640_priv), GFP_KERNEL); 688 if (!priv) { 689 dev_err(&client->dev, 690 "Failed to allocate memory for private data!\n"); 691 return -ENOMEM; 692 } 693 694 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops); 695 696 v4l2_ctrl_handler_init(&priv->hdl, 2); 697 v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops, 698 V4L2_CID_VFLIP, 0, 1, 1, 0); 699 v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops, 700 V4L2_CID_HFLIP, 0, 1, 1, 0); 701 priv->subdev.ctrl_handler = &priv->hdl; 702 if (priv->hdl.error) 703 return priv->hdl.error; 704 705 priv->clk = v4l2_clk_get(&client->dev, "mclk"); 706 if (IS_ERR(priv->clk)) { 707 ret = PTR_ERR(priv->clk); 708 goto eclkget; 709 } 710 711 ret = ov9640_video_probe(client); 712 if (ret) { 713 v4l2_clk_put(priv->clk); 714eclkget: 715 v4l2_ctrl_handler_free(&priv->hdl); 716 } 717 718 return ret; 719} 720 721static int ov9640_remove(struct i2c_client *client) 722{ 723 struct v4l2_subdev *sd = i2c_get_clientdata(client); 724 struct ov9640_priv *priv = to_ov9640_sensor(sd); 725 726 v4l2_clk_put(priv->clk); 727 v4l2_device_unregister_subdev(&priv->subdev); 728 v4l2_ctrl_handler_free(&priv->hdl); 729 return 0; 730} 731 732static const struct i2c_device_id ov9640_id[] = { 733 { "ov9640", 0 }, 734 { } 735}; 736MODULE_DEVICE_TABLE(i2c, ov9640_id); 737 738static struct i2c_driver ov9640_i2c_driver = { 739 .driver = { 740 .name = "ov9640", 741 }, 742 .probe = ov9640_probe, 743 .remove = ov9640_remove, 744 .id_table = ov9640_id, 745}; 746 747module_i2c_driver(ov9640_i2c_driver); 748 749MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx"); 750MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>"); 751MODULE_LICENSE("GPL v2"); 752