1/* 2 * stv0900_reg.h 3 * 4 * Driver for ST STV0900 satellite demodulator IC. 5 * 6 * Copyright (C) ST Microelectronics. 7 * Copyright (C) 2009 NetUP Inc. 8 * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 24 */ 25 26#ifndef STV0900_REG_H 27#define STV0900_REG_H 28 29extern s32 shiftx(s32 x, int demod, s32 shift); 30 31#define REGx(x) shiftx(x, demod, 0x200) 32#define FLDx(x) shiftx(x, demod, 0x2000000) 33 34/*MID*/ 35#define R0900_MID 0xf100 36#define F0900_MCHIP_IDENT 0xf10000f0 37#define F0900_MRELEASE 0xf100000f 38 39/*DACR1*/ 40#define R0900_DACR1 0xf113 41#define F0900_DAC_MODE 0xf11300e0 42#define F0900_DAC_VALUE1 0xf113000f 43 44/*DACR2*/ 45#define R0900_DACR2 0xf114 46#define F0900_DAC_VALUE0 0xf11400ff 47 48/*OUTCFG*/ 49#define R0900_OUTCFG 0xf11c 50#define F0900_OUTSERRS1_HZ 0xf11c0040 51#define F0900_OUTSERRS2_HZ 0xf11c0020 52#define F0900_OUTSERRS3_HZ 0xf11c0010 53#define F0900_OUTPARRS3_HZ 0xf11c0008 54 55/*IRQSTATUS3*/ 56#define R0900_IRQSTATUS3 0xf120 57#define F0900_SPLL_LOCK 0xf1200020 58#define F0900_SSTREAM_LCK_3 0xf1200010 59#define F0900_SSTREAM_LCK_2 0xf1200008 60#define F0900_SSTREAM_LCK_1 0xf1200004 61#define F0900_SDVBS1_PRF_2 0xf1200002 62#define F0900_SDVBS1_PRF_1 0xf1200001 63 64/*IRQSTATUS2*/ 65#define R0900_IRQSTATUS2 0xf121 66#define F0900_SSPY_ENDSIM_3 0xf1210080 67#define F0900_SSPY_ENDSIM_2 0xf1210040 68#define F0900_SSPY_ENDSIM_1 0xf1210020 69#define F0900_SPKTDEL_ERROR_2 0xf1210010 70#define F0900_SPKTDEL_LOCKB_2 0xf1210008 71#define F0900_SPKTDEL_LOCK_2 0xf1210004 72#define F0900_SPKTDEL_ERROR_1 0xf1210002 73#define F0900_SPKTDEL_LOCKB_1 0xf1210001 74 75/*IRQSTATUS1*/ 76#define R0900_IRQSTATUS1 0xf122 77#define F0900_SPKTDEL_LOCK_1 0xf1220080 78#define F0900_SDEMOD_LOCKB_2 0xf1220004 79#define F0900_SDEMOD_LOCK_2 0xf1220002 80#define F0900_SDEMOD_IRQ_2 0xf1220001 81 82/*IRQSTATUS0*/ 83#define R0900_IRQSTATUS0 0xf123 84#define F0900_SDEMOD_LOCKB_1 0xf1230080 85#define F0900_SDEMOD_LOCK_1 0xf1230040 86#define F0900_SDEMOD_IRQ_1 0xf1230020 87#define F0900_SBCH_ERRFLAG 0xf1230010 88#define F0900_SDISEQC2RX_IRQ 0xf1230008 89#define F0900_SDISEQC2TX_IRQ 0xf1230004 90#define F0900_SDISEQC1RX_IRQ 0xf1230002 91#define F0900_SDISEQC1TX_IRQ 0xf1230001 92 93/*IRQMASK3*/ 94#define R0900_IRQMASK3 0xf124 95#define F0900_MPLL_LOCK 0xf1240020 96#define F0900_MSTREAM_LCK_3 0xf1240010 97#define F0900_MSTREAM_LCK_2 0xf1240008 98#define F0900_MSTREAM_LCK_1 0xf1240004 99#define F0900_MDVBS1_PRF_2 0xf1240002 100#define F0900_MDVBS1_PRF_1 0xf1240001 101 102/*IRQMASK2*/ 103#define R0900_IRQMASK2 0xf125 104#define F0900_MSPY_ENDSIM_3 0xf1250080 105#define F0900_MSPY_ENDSIM_2 0xf1250040 106#define F0900_MSPY_ENDSIM_1 0xf1250020 107#define F0900_MPKTDEL_ERROR_2 0xf1250010 108#define F0900_MPKTDEL_LOCKB_2 0xf1250008 109#define F0900_MPKTDEL_LOCK_2 0xf1250004 110#define F0900_MPKTDEL_ERROR_1 0xf1250002 111#define F0900_MPKTDEL_LOCKB_1 0xf1250001 112 113/*IRQMASK1*/ 114#define R0900_IRQMASK1 0xf126 115#define F0900_MPKTDEL_LOCK_1 0xf1260080 116#define F0900_MEXTPINB2 0xf1260040 117#define F0900_MEXTPIN2 0xf1260020 118#define F0900_MEXTPINB1 0xf1260010 119#define F0900_MEXTPIN1 0xf1260008 120#define F0900_MDEMOD_LOCKB_2 0xf1260004 121#define F0900_MDEMOD_LOCK_2 0xf1260002 122#define F0900_MDEMOD_IRQ_2 0xf1260001 123 124/*IRQMASK0*/ 125#define R0900_IRQMASK0 0xf127 126#define F0900_MDEMOD_LOCKB_1 0xf1270080 127#define F0900_MDEMOD_LOCK_1 0xf1270040 128#define F0900_MDEMOD_IRQ_1 0xf1270020 129#define F0900_MBCH_ERRFLAG 0xf1270010 130#define F0900_MDISEQC2RX_IRQ 0xf1270008 131#define F0900_MDISEQC2TX_IRQ 0xf1270004 132#define F0900_MDISEQC1RX_IRQ 0xf1270002 133#define F0900_MDISEQC1TX_IRQ 0xf1270001 134 135/*I2CCFG*/ 136#define R0900_I2CCFG 0xf129 137#define F0900_I2C_FASTMODE 0xf1290008 138#define F0900_I2CADDR_INC 0xf1290003 139 140/*P1_I2CRPT*/ 141#define R0900_P1_I2CRPT 0xf12a 142#define I2CRPT shiftx(R0900_P1_I2CRPT, demod, -1) 143#define F0900_P1_I2CT_ON 0xf12a0080 144#define I2CT_ON shiftx(F0900_P1_I2CT_ON, demod, -0x10000) 145#define F0900_P1_ENARPT_LEVEL 0xf12a0070 146#define F0900_P1_SCLT_DELAY 0xf12a0008 147#define F0900_P1_STOP_ENABLE 0xf12a0004 148#define F0900_P1_STOP_SDAT2SDA 0xf12a0002 149 150/*P2_I2CRPT*/ 151#define R0900_P2_I2CRPT 0xf12b 152#define F0900_P2_I2CT_ON 0xf12b0080 153#define F0900_P2_ENARPT_LEVEL 0xf12b0070 154#define F0900_P2_SCLT_DELAY 0xf12b0008 155#define F0900_P2_STOP_ENABLE 0xf12b0004 156#define F0900_P2_STOP_SDAT2SDA 0xf12b0002 157 158/*IOPVALUE6*/ 159#define R0900_IOPVALUE6 0xf138 160#define F0900_VSCL 0xf1380004 161#define F0900_VSDA 0xf1380002 162#define F0900_VDATA3_0 0xf1380001 163 164/*IOPVALUE5*/ 165#define R0900_IOPVALUE5 0xf139 166#define F0900_VDATA3_1 0xf1390080 167#define F0900_VDATA3_2 0xf1390040 168#define F0900_VDATA3_3 0xf1390020 169#define F0900_VDATA3_4 0xf1390010 170#define F0900_VDATA3_5 0xf1390008 171#define F0900_VDATA3_6 0xf1390004 172#define F0900_VDATA3_7 0xf1390002 173#define F0900_VCLKOUT3 0xf1390001 174 175/*IOPVALUE4*/ 176#define R0900_IOPVALUE4 0xf13a 177#define F0900_VSTROUT3 0xf13a0080 178#define F0900_VDPN3 0xf13a0040 179#define F0900_VERROR3 0xf13a0020 180#define F0900_VDATA2_7 0xf13a0010 181#define F0900_VCLKOUT2 0xf13a0008 182#define F0900_VSTROUT2 0xf13a0004 183#define F0900_VDPN2 0xf13a0002 184#define F0900_VERROR2 0xf13a0001 185 186/*IOPVALUE3*/ 187#define R0900_IOPVALUE3 0xf13b 188#define F0900_VDATA1_7 0xf13b0080 189#define F0900_VCLKOUT1 0xf13b0040 190#define F0900_VSTROUT1 0xf13b0020 191#define F0900_VDPN1 0xf13b0010 192#define F0900_VERROR1 0xf13b0008 193#define F0900_VCLKOUT27 0xf13b0004 194#define F0900_VDISEQCOUT2 0xf13b0002 195#define F0900_VSCLT2 0xf13b0001 196 197/*IOPVALUE2*/ 198#define R0900_IOPVALUE2 0xf13c 199#define F0900_VSDAT2 0xf13c0080 200#define F0900_VAGCRF2 0xf13c0040 201#define F0900_VDISEQCOUT1 0xf13c0020 202#define F0900_VSCLT1 0xf13c0010 203#define F0900_VSDAT1 0xf13c0008 204#define F0900_VAGCRF1 0xf13c0004 205#define F0900_VDIRCLK 0xf13c0002 206#define F0900_VSTDBY 0xf13c0001 207 208/*IOPVALUE1*/ 209#define R0900_IOPVALUE1 0xf13d 210#define F0900_VCS1 0xf13d0080 211#define F0900_VCS0 0xf13d0040 212#define F0900_VGPIO13 0xf13d0020 213#define F0900_VGPIO12 0xf13d0010 214#define F0900_VGPIO11 0xf13d0008 215#define F0900_VGPIO10 0xf13d0004 216#define F0900_VGPIO9 0xf13d0002 217#define F0900_VGPIO8 0xf13d0001 218 219/*IOPVALUE0*/ 220#define R0900_IOPVALUE0 0xf13e 221#define F0900_VGPIO7 0xf13e0080 222#define F0900_VGPIO6 0xf13e0040 223#define F0900_VGPIO5 0xf13e0020 224#define F0900_VGPIO4 0xf13e0010 225#define F0900_VGPIO3 0xf13e0008 226#define F0900_VGPIO2 0xf13e0004 227#define F0900_VGPIO1 0xf13e0002 228#define F0900_VCLKI2 0xf13e0001 229 230/*CLKI2CFG*/ 231#define R0900_CLKI2CFG 0xf140 232#define F0900_CLKI2_OPD 0xf1400080 233#define F0900_CLKI2_CONFIG 0xf140007e 234#define F0900_CLKI2_XOR 0xf1400001 235 236/*GPIO1CFG*/ 237#define R0900_GPIO1CFG 0xf141 238#define F0900_GPIO1_OPD 0xf1410080 239#define F0900_GPIO1_CONFIG 0xf141007e 240#define F0900_GPIO1_XOR 0xf1410001 241 242/*GPIO2CFG*/ 243#define R0900_GPIO2CFG 0xf142 244#define F0900_GPIO2_OPD 0xf1420080 245#define F0900_GPIO2_CONFIG 0xf142007e 246#define F0900_GPIO2_XOR 0xf1420001 247 248/*GPIO3CFG*/ 249#define R0900_GPIO3CFG 0xf143 250#define F0900_GPIO3_OPD 0xf1430080 251#define F0900_GPIO3_CONFIG 0xf143007e 252#define F0900_GPIO3_XOR 0xf1430001 253 254/*GPIO4CFG*/ 255#define R0900_GPIO4CFG 0xf144 256#define F0900_GPIO4_OPD 0xf1440080 257#define F0900_GPIO4_CONFIG 0xf144007e 258#define F0900_GPIO4_XOR 0xf1440001 259 260/*GPIO5CFG*/ 261#define R0900_GPIO5CFG 0xf145 262#define F0900_GPIO5_OPD 0xf1450080 263#define F0900_GPIO5_CONFIG 0xf145007e 264#define F0900_GPIO5_XOR 0xf1450001 265 266/*GPIO6CFG*/ 267#define R0900_GPIO6CFG 0xf146 268#define F0900_GPIO6_OPD 0xf1460080 269#define F0900_GPIO6_CONFIG 0xf146007e 270#define F0900_GPIO6_XOR 0xf1460001 271 272/*GPIO7CFG*/ 273#define R0900_GPIO7CFG 0xf147 274#define F0900_GPIO7_OPD 0xf1470080 275#define F0900_GPIO7_CONFIG 0xf147007e 276#define F0900_GPIO7_XOR 0xf1470001 277 278/*GPIO8CFG*/ 279#define R0900_GPIO8CFG 0xf148 280#define F0900_GPIO8_OPD 0xf1480080 281#define F0900_GPIO8_CONFIG 0xf148007e 282#define F0900_GPIO8_XOR 0xf1480001 283 284/*GPIO9CFG*/ 285#define R0900_GPIO9CFG 0xf149 286#define F0900_GPIO9_OPD 0xf1490080 287#define F0900_GPIO9_CONFIG 0xf149007e 288#define F0900_GPIO9_XOR 0xf1490001 289 290/*GPIO10CFG*/ 291#define R0900_GPIO10CFG 0xf14a 292#define F0900_GPIO10_OPD 0xf14a0080 293#define F0900_GPIO10_CONFIG 0xf14a007e 294#define F0900_GPIO10_XOR 0xf14a0001 295 296/*GPIO11CFG*/ 297#define R0900_GPIO11CFG 0xf14b 298#define F0900_GPIO11_OPD 0xf14b0080 299#define F0900_GPIO11_CONFIG 0xf14b007e 300#define F0900_GPIO11_XOR 0xf14b0001 301 302/*GPIO12CFG*/ 303#define R0900_GPIO12CFG 0xf14c 304#define F0900_GPIO12_OPD 0xf14c0080 305#define F0900_GPIO12_CONFIG 0xf14c007e 306#define F0900_GPIO12_XOR 0xf14c0001 307 308/*GPIO13CFG*/ 309#define R0900_GPIO13CFG 0xf14d 310#define F0900_GPIO13_OPD 0xf14d0080 311#define F0900_GPIO13_CONFIG 0xf14d007e 312#define F0900_GPIO13_XOR 0xf14d0001 313 314/*CS0CFG*/ 315#define R0900_CS0CFG 0xf14e 316#define F0900_CS0_OPD 0xf14e0080 317#define F0900_CS0_CONFIG 0xf14e007e 318#define F0900_CS0_XOR 0xf14e0001 319 320/*CS1CFG*/ 321#define R0900_CS1CFG 0xf14f 322#define F0900_CS1_OPD 0xf14f0080 323#define F0900_CS1_CONFIG 0xf14f007e 324#define F0900_CS1_XOR 0xf14f0001 325 326/*STDBYCFG*/ 327#define R0900_STDBYCFG 0xf150 328#define F0900_STDBY_OPD 0xf1500080 329#define F0900_STDBY_CONFIG 0xf150007e 330#define F0900_STBDY_XOR 0xf1500001 331 332/*DIRCLKCFG*/ 333#define R0900_DIRCLKCFG 0xf151 334#define F0900_DIRCLK_OPD 0xf1510080 335#define F0900_DIRCLK_CONFIG 0xf151007e 336#define F0900_DIRCLK_XOR 0xf1510001 337 338/*AGCRF1CFG*/ 339#define R0900_AGCRF1CFG 0xf152 340#define F0900_AGCRF1_OPD 0xf1520080 341#define F0900_AGCRF1_CONFIG 0xf152007e 342#define F0900_AGCRF1_XOR 0xf1520001 343 344/*SDAT1CFG*/ 345#define R0900_SDAT1CFG 0xf153 346#define F0900_SDAT1_OPD 0xf1530080 347#define F0900_SDAT1_CONFIG 0xf153007e 348#define F0900_SDAT1_XOR 0xf1530001 349 350/*SCLT1CFG*/ 351#define R0900_SCLT1CFG 0xf154 352#define F0900_SCLT1_OPD 0xf1540080 353#define F0900_SCLT1_CONFIG 0xf154007e 354#define F0900_SCLT1_XOR 0xf1540001 355 356/*DISEQCO1CFG*/ 357#define R0900_DISEQCO1CFG 0xf155 358#define F0900_DISEQCO1_OPD 0xf1550080 359#define F0900_DISEQCO1_CONFIG 0xf155007e 360#define F0900_DISEQC1_XOR 0xf1550001 361 362/*AGCRF2CFG*/ 363#define R0900_AGCRF2CFG 0xf156 364#define F0900_AGCRF2_OPD 0xf1560080 365#define F0900_AGCRF2_CONFIG 0xf156007e 366#define F0900_AGCRF2_XOR 0xf1560001 367 368/*SDAT2CFG*/ 369#define R0900_SDAT2CFG 0xf157 370#define F0900_SDAT2_OPD 0xf1570080 371#define F0900_SDAT2_CONFIG 0xf157007e 372#define F0900_SDAT2_XOR 0xf1570001 373 374/*SCLT2CFG*/ 375#define R0900_SCLT2CFG 0xf158 376#define F0900_SCLT2_OPD 0xf1580080 377#define F0900_SCLT2_CONFIG 0xf158007e 378#define F0900_SCLT2_XOR 0xf1580001 379 380/*DISEQCO2CFG*/ 381#define R0900_DISEQCO2CFG 0xf159 382#define F0900_DISEQCO2_OPD 0xf1590080 383#define F0900_DISEQCO2_CONFIG 0xf159007e 384#define F0900_DISEQC2_XOR 0xf1590001 385 386/*CLKOUT27CFG*/ 387#define R0900_CLKOUT27CFG 0xf15a 388#define F0900_CLKOUT27_OPD 0xf15a0080 389#define F0900_CLKOUT27_CONFIG 0xf15a007e 390#define F0900_CLKOUT27_XOR 0xf15a0001 391 392/*ERROR1CFG*/ 393#define R0900_ERROR1CFG 0xf15b 394#define F0900_ERROR1_OPD 0xf15b0080 395#define F0900_ERROR1_CONFIG 0xf15b007e 396#define F0900_ERROR1_XOR 0xf15b0001 397 398/*DPN1CFG*/ 399#define R0900_DPN1CFG 0xf15c 400#define F0900_DPN1_OPD 0xf15c0080 401#define F0900_DPN1_CONFIG 0xf15c007e 402#define F0900_DPN1_XOR 0xf15c0001 403 404/*STROUT1CFG*/ 405#define R0900_STROUT1CFG 0xf15d 406#define F0900_STROUT1_OPD 0xf15d0080 407#define F0900_STROUT1_CONFIG 0xf15d007e 408#define F0900_STROUT1_XOR 0xf15d0001 409 410/*CLKOUT1CFG*/ 411#define R0900_CLKOUT1CFG 0xf15e 412#define F0900_CLKOUT1_OPD 0xf15e0080 413#define F0900_CLKOUT1_CONFIG 0xf15e007e 414#define F0900_CLKOUT1_XOR 0xf15e0001 415 416/*DATA71CFG*/ 417#define R0900_DATA71CFG 0xf15f 418#define F0900_DATA71_OPD 0xf15f0080 419#define F0900_DATA71_CONFIG 0xf15f007e 420#define F0900_DATA71_XOR 0xf15f0001 421 422/*ERROR2CFG*/ 423#define R0900_ERROR2CFG 0xf160 424#define F0900_ERROR2_OPD 0xf1600080 425#define F0900_ERROR2_CONFIG 0xf160007e 426#define F0900_ERROR2_XOR 0xf1600001 427 428/*DPN2CFG*/ 429#define R0900_DPN2CFG 0xf161 430#define F0900_DPN2_OPD 0xf1610080 431#define F0900_DPN2_CONFIG 0xf161007e 432#define F0900_DPN2_XOR 0xf1610001 433 434/*STROUT2CFG*/ 435#define R0900_STROUT2CFG 0xf162 436#define F0900_STROUT2_OPD 0xf1620080 437#define F0900_STROUT2_CONFIG 0xf162007e 438#define F0900_STROUT2_XOR 0xf1620001 439 440/*CLKOUT2CFG*/ 441#define R0900_CLKOUT2CFG 0xf163 442#define F0900_CLKOUT2_OPD 0xf1630080 443#define F0900_CLKOUT2_CONFIG 0xf163007e 444#define F0900_CLKOUT2_XOR 0xf1630001 445 446/*DATA72CFG*/ 447#define R0900_DATA72CFG 0xf164 448#define F0900_DATA72_OPD 0xf1640080 449#define F0900_DATA72_CONFIG 0xf164007e 450#define F0900_DATA72_XOR 0xf1640001 451 452/*ERROR3CFG*/ 453#define R0900_ERROR3CFG 0xf165 454#define F0900_ERROR3_OPD 0xf1650080 455#define F0900_ERROR3_CONFIG 0xf165007e 456#define F0900_ERROR3_XOR 0xf1650001 457 458/*DPN3CFG*/ 459#define R0900_DPN3CFG 0xf166 460#define F0900_DPN3_OPD 0xf1660080 461#define F0900_DPN3_CONFIG 0xf166007e 462#define F0900_DPN3_XOR 0xf1660001 463 464/*STROUT3CFG*/ 465#define R0900_STROUT3CFG 0xf167 466#define F0900_STROUT3_OPD 0xf1670080 467#define F0900_STROUT3_CONFIG 0xf167007e 468#define F0900_STROUT3_XOR 0xf1670001 469 470/*CLKOUT3CFG*/ 471#define R0900_CLKOUT3CFG 0xf168 472#define F0900_CLKOUT3_OPD 0xf1680080 473#define F0900_CLKOUT3_CONFIG 0xf168007e 474#define F0900_CLKOUT3_XOR 0xf1680001 475 476/*DATA73CFG*/ 477#define R0900_DATA73CFG 0xf169 478#define F0900_DATA73_OPD 0xf1690080 479#define F0900_DATA73_CONFIG 0xf169007e 480#define F0900_DATA73_XOR 0xf1690001 481 482/*STRSTATUS1*/ 483#define R0900_STRSTATUS1 0xf16a 484#define F0900_STRSTATUS_SEL2 0xf16a00f0 485#define F0900_STRSTATUS_SEL1 0xf16a000f 486 487/*STRSTATUS2*/ 488#define R0900_STRSTATUS2 0xf16b 489#define F0900_STRSTATUS_SEL4 0xf16b00f0 490#define F0900_STRSTATUS_SEL3 0xf16b000f 491 492/*STRSTATUS3*/ 493#define R0900_STRSTATUS3 0xf16c 494#define F0900_STRSTATUS_SEL6 0xf16c00f0 495#define F0900_STRSTATUS_SEL5 0xf16c000f 496 497/*FSKTFC2*/ 498#define R0900_FSKTFC2 0xf170 499#define F0900_FSKT_KMOD 0xf17000fc 500#define F0900_FSKT_CAR2 0xf1700003 501 502/*FSKTFC1*/ 503#define R0900_FSKTFC1 0xf171 504#define F0900_FSKT_CAR1 0xf17100ff 505 506/*FSKTFC0*/ 507#define R0900_FSKTFC0 0xf172 508#define F0900_FSKT_CAR0 0xf17200ff 509 510/*FSKTDELTAF1*/ 511#define R0900_FSKTDELTAF1 0xf173 512#define F0900_FSKT_DELTAF1 0xf173000f 513 514/*FSKTDELTAF0*/ 515#define R0900_FSKTDELTAF0 0xf174 516#define F0900_FSKT_DELTAF0 0xf17400ff 517 518/*FSKTCTRL*/ 519#define R0900_FSKTCTRL 0xf175 520#define F0900_FSKT_EN_SGN 0xf1750040 521#define F0900_FSKT_MOD_SGN 0xf1750020 522#define F0900_FSKT_MOD_EN 0xf175001c 523#define F0900_FSKT_DACMODE 0xf1750003 524 525/*FSKRFC2*/ 526#define R0900_FSKRFC2 0xf176 527#define F0900_FSKR_DETSGN 0xf1760040 528#define F0900_FSKR_OUTSGN 0xf1760020 529#define F0900_FSKR_KAGC 0xf176001c 530#define F0900_FSKR_CAR2 0xf1760003 531 532/*FSKRFC1*/ 533#define R0900_FSKRFC1 0xf177 534#define F0900_FSKR_CAR1 0xf17700ff 535 536/*FSKRFC0*/ 537#define R0900_FSKRFC0 0xf178 538#define F0900_FSKR_CAR0 0xf17800ff 539 540/*FSKRK1*/ 541#define R0900_FSKRK1 0xf179 542#define F0900_FSKR_K1_EXP 0xf17900e0 543#define F0900_FSKR_K1_MANT 0xf179001f 544 545/*FSKRK2*/ 546#define R0900_FSKRK2 0xf17a 547#define F0900_FSKR_K2_EXP 0xf17a00e0 548#define F0900_FSKR_K2_MANT 0xf17a001f 549 550/*FSKRAGCR*/ 551#define R0900_FSKRAGCR 0xf17b 552#define F0900_FSKR_OUTCTL 0xf17b00c0 553#define F0900_FSKR_AGC_REF 0xf17b003f 554 555/*FSKRAGC*/ 556#define R0900_FSKRAGC 0xf17c 557#define F0900_FSKR_AGC_ACCU 0xf17c00ff 558 559/*FSKRALPHA*/ 560#define R0900_FSKRALPHA 0xf17d 561#define F0900_FSKR_ALPHA_EXP 0xf17d001c 562#define F0900_FSKR_ALPHA_M 0xf17d0003 563 564/*FSKRPLTH1*/ 565#define R0900_FSKRPLTH1 0xf17e 566#define F0900_FSKR_BETA 0xf17e00f0 567#define F0900_FSKR_PLL_TRESH1 0xf17e000f 568 569/*FSKRPLTH0*/ 570#define R0900_FSKRPLTH0 0xf17f 571#define F0900_FSKR_PLL_TRESH0 0xf17f00ff 572 573/*FSKRDF1*/ 574#define R0900_FSKRDF1 0xf180 575#define F0900_FSKR_OUT 0xf1800080 576#define F0900_FSKR_DELTAF1 0xf180001f 577 578/*FSKRDF0*/ 579#define R0900_FSKRDF0 0xf181 580#define F0900_FSKR_DELTAF0 0xf18100ff 581 582/*FSKRSTEPP*/ 583#define R0900_FSKRSTEPP 0xf182 584#define F0900_FSKR_STEP_PLUS 0xf18200ff 585 586/*FSKRSTEPM*/ 587#define R0900_FSKRSTEPM 0xf183 588#define F0900_FSKR_STEP_MINUS 0xf18300ff 589 590/*FSKRDET1*/ 591#define R0900_FSKRDET1 0xf184 592#define F0900_FSKR_DETECT 0xf1840080 593#define F0900_FSKR_CARDET_ACCU1 0xf184000f 594 595/*FSKRDET0*/ 596#define R0900_FSKRDET0 0xf185 597#define F0900_FSKR_CARDET_ACCU0 0xf18500ff 598 599/*FSKRDTH1*/ 600#define R0900_FSKRDTH1 0xf186 601#define F0900_FSKR_CARLOSS_THRESH1 0xf18600f0 602#define F0900_FSKR_CARDET_THRESH1 0xf186000f 603 604/*FSKRDTH0*/ 605#define R0900_FSKRDTH0 0xf187 606#define F0900_FSKR_CARDET_THRESH0 0xf18700ff 607 608/*FSKRLOSS*/ 609#define R0900_FSKRLOSS 0xf188 610#define F0900_FSKR_CARLOSS_THRESH0 0xf18800ff 611 612/*P2_DISTXCTL*/ 613#define R0900_P2_DISTXCTL 0xf190 614#define F0900_P2_TIM_OFF 0xf1900080 615#define F0900_P2_DISEQC_RESET 0xf1900040 616#define F0900_P2_TIM_CMD 0xf1900030 617#define F0900_P2_DIS_PRECHARGE 0xf1900008 618#define F0900_P2_DISTX_MODE 0xf1900007 619 620/*P2_DISRXCTL*/ 621#define R0900_P2_DISRXCTL 0xf191 622#define F0900_P2_RECEIVER_ON 0xf1910080 623#define F0900_P2_IGNO_SHORT22K 0xf1910040 624#define F0900_P2_ONECHIP_TRX 0xf1910020 625#define F0900_P2_EXT_ENVELOP 0xf1910010 626#define F0900_P2_PIN_SELECT0 0xf191000c 627#define F0900_P2_IRQ_RXEND 0xf1910002 628#define F0900_P2_IRQ_4NBYTES 0xf1910001 629 630/*P2_DISRX_ST0*/ 631#define R0900_P2_DISRX_ST0 0xf194 632#define F0900_P2_RX_END 0xf1940080 633#define F0900_P2_RX_ACTIVE 0xf1940040 634#define F0900_P2_SHORT_22KHZ 0xf1940020 635#define F0900_P2_CONT_TONE 0xf1940010 636#define F0900_P2_FIFO_4BREADY 0xf1940008 637#define F0900_P2_FIFO_EMPTY 0xf1940004 638#define F0900_P2_ABORT_DISRX 0xf1940001 639 640/*P2_DISRX_ST1*/ 641#define R0900_P2_DISRX_ST1 0xf195 642#define F0900_P2_RX_FAIL 0xf1950080 643#define F0900_P2_FIFO_PARITYFAIL 0xf1950040 644#define F0900_P2_RX_NONBYTE 0xf1950020 645#define F0900_P2_FIFO_OVERFLOW 0xf1950010 646#define F0900_P2_FIFO_BYTENBR 0xf195000f 647 648/*P2_DISRXDATA*/ 649#define R0900_P2_DISRXDATA 0xf196 650#define F0900_P2_DISRX_DATA 0xf19600ff 651 652/*P2_DISTXDATA*/ 653#define R0900_P2_DISTXDATA 0xf197 654#define F0900_P2_DISEQC_FIFO 0xf19700ff 655 656/*P2_DISTXSTATUS*/ 657#define R0900_P2_DISTXSTATUS 0xf198 658#define F0900_P2_TX_FAIL 0xf1980080 659#define F0900_P2_FIFO_FULL 0xf1980040 660#define F0900_P2_TX_IDLE 0xf1980020 661#define F0900_P2_GAP_BURST 0xf1980010 662#define F0900_P2_TXFIFO_BYTES 0xf198000f 663 664/*P2_F22TX*/ 665#define R0900_P2_F22TX 0xf199 666#define F0900_P2_F22_REG 0xf19900ff 667 668/*P2_F22RX*/ 669#define R0900_P2_F22RX 0xf19a 670#define F0900_P2_F22RX_REG 0xf19a00ff 671 672/*P2_ACRPRESC*/ 673#define R0900_P2_ACRPRESC 0xf19c 674#define F0900_P2_ACR_PRESC 0xf19c0007 675 676/*P2_ACRDIV*/ 677#define R0900_P2_ACRDIV 0xf19d 678#define F0900_P2_ACR_DIV 0xf19d00ff 679 680/*P1_DISTXCTL*/ 681#define R0900_P1_DISTXCTL 0xf1a0 682#define DISTXCTL shiftx(R0900_P1_DISTXCTL, demod, 0x10) 683#define F0900_P1_TIM_OFF 0xf1a00080 684#define F0900_P1_DISEQC_RESET 0xf1a00040 685#define DISEQC_RESET shiftx(F0900_P1_DISEQC_RESET, demod, 0x100000) 686#define F0900_P1_TIM_CMD 0xf1a00030 687#define F0900_P1_DIS_PRECHARGE 0xf1a00008 688#define DIS_PRECHARGE shiftx(F0900_P1_DIS_PRECHARGE, demod, 0x100000) 689#define F0900_P1_DISTX_MODE 0xf1a00007 690#define DISTX_MODE shiftx(F0900_P1_DISTX_MODE, demod, 0x100000) 691 692/*P1_DISRXCTL*/ 693#define R0900_P1_DISRXCTL 0xf1a1 694#define DISRXCTL shiftx(R0900_P1_DISRXCTL, demod, 0x10) 695#define F0900_P1_RECEIVER_ON 0xf1a10080 696#define F0900_P1_IGNO_SHORT22K 0xf1a10040 697#define F0900_P1_ONECHIP_TRX 0xf1a10020 698#define F0900_P1_EXT_ENVELOP 0xf1a10010 699#define F0900_P1_PIN_SELECT0 0xf1a1000c 700#define F0900_P1_IRQ_RXEND 0xf1a10002 701#define F0900_P1_IRQ_4NBYTES 0xf1a10001 702 703/*P1_DISRX_ST0*/ 704#define R0900_P1_DISRX_ST0 0xf1a4 705#define DISRX_ST0 shiftx(R0900_P1_DISRX_ST0, demod, 0x10) 706#define F0900_P1_RX_END 0xf1a40080 707#define RX_END shiftx(F0900_P1_RX_END, demod, 0x100000) 708#define F0900_P1_RX_ACTIVE 0xf1a40040 709#define F0900_P1_SHORT_22KHZ 0xf1a40020 710#define F0900_P1_CONT_TONE 0xf1a40010 711#define F0900_P1_FIFO_4BREADY 0xf1a40008 712#define F0900_P1_FIFO_EMPTY 0xf1a40004 713#define F0900_P1_ABORT_DISRX 0xf1a40001 714 715/*P1_DISRX_ST1*/ 716#define R0900_P1_DISRX_ST1 0xf1a5 717#define DISRX_ST1 shiftx(R0900_P1_DISRX_ST1, demod, 0x10) 718#define F0900_P1_RX_FAIL 0xf1a50080 719#define F0900_P1_FIFO_PARITYFAIL 0xf1a50040 720#define F0900_P1_RX_NONBYTE 0xf1a50020 721#define F0900_P1_FIFO_OVERFLOW 0xf1a50010 722#define F0900_P1_FIFO_BYTENBR 0xf1a5000f 723#define FIFO_BYTENBR shiftx(F0900_P1_FIFO_BYTENBR, demod, 0x100000) 724 725/*P1_DISRXDATA*/ 726#define R0900_P1_DISRXDATA 0xf1a6 727#define DISRXDATA shiftx(R0900_P1_DISRXDATA, demod, 0x10) 728#define F0900_P1_DISRX_DATA 0xf1a600ff 729 730/*P1_DISTXDATA*/ 731#define R0900_P1_DISTXDATA 0xf1a7 732#define DISTXDATA shiftx(R0900_P1_DISTXDATA, demod, 0x10) 733#define F0900_P1_DISEQC_FIFO 0xf1a700ff 734 735/*P1_DISTXSTATUS*/ 736#define R0900_P1_DISTXSTATUS 0xf1a8 737#define F0900_P1_TX_FAIL 0xf1a80080 738#define F0900_P1_FIFO_FULL 0xf1a80040 739#define FIFO_FULL shiftx(F0900_P1_FIFO_FULL, demod, 0x100000) 740#define F0900_P1_TX_IDLE 0xf1a80020 741#define TX_IDLE shiftx(F0900_P1_TX_IDLE, demod, 0x100000) 742#define F0900_P1_GAP_BURST 0xf1a80010 743#define F0900_P1_TXFIFO_BYTES 0xf1a8000f 744 745/*P1_F22TX*/ 746#define R0900_P1_F22TX 0xf1a9 747#define F22TX shiftx(R0900_P1_F22TX, demod, 0x10) 748#define F0900_P1_F22_REG 0xf1a900ff 749 750/*P1_F22RX*/ 751#define R0900_P1_F22RX 0xf1aa 752#define F22RX shiftx(R0900_P1_F22RX, demod, 0x10) 753#define F0900_P1_F22RX_REG 0xf1aa00ff 754 755/*P1_ACRPRESC*/ 756#define R0900_P1_ACRPRESC 0xf1ac 757#define ACRPRESC shiftx(R0900_P1_ACRPRESC, demod, 0x10) 758#define F0900_P1_ACR_PRESC 0xf1ac0007 759 760/*P1_ACRDIV*/ 761#define R0900_P1_ACRDIV 0xf1ad 762#define ACRDIV shiftx(R0900_P1_ACRDIV, demod, 0x10) 763#define F0900_P1_ACR_DIV 0xf1ad00ff 764 765/*NCOARSE*/ 766#define R0900_NCOARSE 0xf1b3 767#define F0900_M_DIV 0xf1b300ff 768 769/*SYNTCTRL*/ 770#define R0900_SYNTCTRL 0xf1b6 771#define F0900_STANDBY 0xf1b60080 772#define F0900_BYPASSPLLCORE 0xf1b60040 773#define F0900_SELX1RATIO 0xf1b60020 774#define F0900_STOP_PLL 0xf1b60008 775#define F0900_BYPASSPLLFSK 0xf1b60004 776#define F0900_SELOSCI 0xf1b60002 777#define F0900_BYPASSPLLADC 0xf1b60001 778 779/*FILTCTRL*/ 780#define R0900_FILTCTRL 0xf1b7 781#define F0900_INV_CLK135 0xf1b70080 782#define F0900_SEL_FSKCKDIV 0xf1b70004 783#define F0900_INV_CLKFSK 0xf1b70002 784#define F0900_BYPASS_APPLI 0xf1b70001 785 786/*PLLSTAT*/ 787#define R0900_PLLSTAT 0xf1b8 788#define F0900_PLLLOCK 0xf1b80001 789 790/*STOPCLK1*/ 791#define R0900_STOPCLK1 0xf1c2 792#define F0900_STOP_CLKPKDT2 0xf1c20040 793#define F0900_STOP_CLKPKDT1 0xf1c20020 794#define F0900_STOP_CLKFEC 0xf1c20010 795#define F0900_STOP_CLKADCI2 0xf1c20008 796#define F0900_INV_CLKADCI2 0xf1c20004 797#define F0900_STOP_CLKADCI1 0xf1c20002 798#define F0900_INV_CLKADCI1 0xf1c20001 799 800/*STOPCLK2*/ 801#define R0900_STOPCLK2 0xf1c3 802#define F0900_STOP_CLKSAMP2 0xf1c30010 803#define F0900_STOP_CLKSAMP1 0xf1c30008 804#define F0900_STOP_CLKVIT2 0xf1c30004 805#define F0900_STOP_CLKVIT1 0xf1c30002 806#define STOP_CLKVIT shiftx(F0900_STOP_CLKVIT1, demod, -2) 807#define F0900_STOP_CLKTS 0xf1c30001 808 809/*TSTTNR0*/ 810#define R0900_TSTTNR0 0xf1df 811#define F0900_SEL_FSK 0xf1df0080 812#define F0900_FSK_PON 0xf1df0004 813 814/*TSTTNR1*/ 815#define R0900_TSTTNR1 0xf1e0 816#define F0900_ADC1_PON 0xf1e00002 817#define F0900_ADC1_INMODE 0xf1e00001 818 819/*TSTTNR2*/ 820#define R0900_TSTTNR2 0xf1e1 821#define F0900_DISEQC1_PON 0xf1e10020 822 823/*TSTTNR3*/ 824#define R0900_TSTTNR3 0xf1e2 825#define F0900_ADC2_PON 0xf1e20002 826#define F0900_ADC2_INMODE 0xf1e20001 827 828/*TSTTNR4*/ 829#define R0900_TSTTNR4 0xf1e3 830#define F0900_DISEQC2_PON 0xf1e30020 831 832/*P2_IQCONST*/ 833#define R0900_P2_IQCONST 0xf200 834#define F0900_P2_CONSTEL_SELECT 0xf2000060 835#define F0900_P2_IQSYMB_SEL 0xf200001f 836 837/*P2_NOSCFG*/ 838#define R0900_P2_NOSCFG 0xf201 839#define F0900_P2_DUMMYPL_NOSDATA 0xf2010020 840#define F0900_P2_NOSPLH_BETA 0xf2010018 841#define F0900_P2_NOSDATA_BETA 0xf2010007 842 843/*P2_ISYMB*/ 844#define R0900_P2_ISYMB 0xf202 845#define F0900_P2_I_SYMBOL 0xf20201ff 846 847/*P2_QSYMB*/ 848#define R0900_P2_QSYMB 0xf203 849#define F0900_P2_Q_SYMBOL 0xf20301ff 850 851/*P2_AGC1CFG*/ 852#define R0900_P2_AGC1CFG 0xf204 853#define F0900_P2_DC_FROZEN 0xf2040080 854#define F0900_P2_DC_CORRECT 0xf2040040 855#define F0900_P2_AMM_FROZEN 0xf2040020 856#define F0900_P2_AMM_CORRECT 0xf2040010 857#define F0900_P2_QUAD_FROZEN 0xf2040008 858#define F0900_P2_QUAD_CORRECT 0xf2040004 859 860/*P2_AGC1CN*/ 861#define R0900_P2_AGC1CN 0xf206 862#define F0900_P2_AGC1_LOCKED 0xf2060080 863#define F0900_P2_AGC1_MINPOWER 0xf2060010 864#define F0900_P2_AGCOUT_FAST 0xf2060008 865#define F0900_P2_AGCIQ_BETA 0xf2060007 866 867/*P2_AGC1REF*/ 868#define R0900_P2_AGC1REF 0xf207 869#define F0900_P2_AGCIQ_REF 0xf20700ff 870 871/*P2_IDCCOMP*/ 872#define R0900_P2_IDCCOMP 0xf208 873#define F0900_P2_IAVERAGE_ADJ 0xf20801ff 874 875/*P2_QDCCOMP*/ 876#define R0900_P2_QDCCOMP 0xf209 877#define F0900_P2_QAVERAGE_ADJ 0xf20901ff 878 879/*P2_POWERI*/ 880#define R0900_P2_POWERI 0xf20a 881#define F0900_P2_POWER_I 0xf20a00ff 882 883/*P2_POWERQ*/ 884#define R0900_P2_POWERQ 0xf20b 885#define F0900_P2_POWER_Q 0xf20b00ff 886 887/*P2_AGC1AMM*/ 888#define R0900_P2_AGC1AMM 0xf20c 889#define F0900_P2_AMM_VALUE 0xf20c00ff 890 891/*P2_AGC1QUAD*/ 892#define R0900_P2_AGC1QUAD 0xf20d 893#define F0900_P2_QUAD_VALUE 0xf20d01ff 894 895/*P2_AGCIQIN1*/ 896#define R0900_P2_AGCIQIN1 0xf20e 897#define F0900_P2_AGCIQ_VALUE1 0xf20e00ff 898 899/*P2_AGCIQIN0*/ 900#define R0900_P2_AGCIQIN0 0xf20f 901#define F0900_P2_AGCIQ_VALUE0 0xf20f00ff 902 903/*P2_DEMOD*/ 904#define R0900_P2_DEMOD 0xf210 905#define F0900_P2_MANUALS2_ROLLOFF 0xf2100080 906#define F0900_P2_SPECINV_CONTROL 0xf2100030 907#define F0900_P2_FORCE_ENASAMP 0xf2100008 908#define F0900_P2_MANUALSX_ROLLOFF 0xf2100004 909#define F0900_P2_ROLLOFF_CONTROL 0xf2100003 910 911/*P2_DMDMODCOD*/ 912#define R0900_P2_DMDMODCOD 0xf211 913#define F0900_P2_MANUAL_MODCOD 0xf2110080 914#define F0900_P2_DEMOD_MODCOD 0xf211007c 915#define F0900_P2_DEMOD_TYPE 0xf2110003 916 917/*P2_DSTATUS*/ 918#define R0900_P2_DSTATUS 0xf212 919#define F0900_P2_CAR_LOCK 0xf2120080 920#define F0900_P2_TMGLOCK_QUALITY 0xf2120060 921#define F0900_P2_LOCK_DEFINITIF 0xf2120008 922#define F0900_P2_OVADC_DETECT 0xf2120001 923 924/*P2_DSTATUS2*/ 925#define R0900_P2_DSTATUS2 0xf213 926#define F0900_P2_DEMOD_DELOCK 0xf2130080 927#define F0900_P2_AGC1_NOSIGNALACK 0xf2130008 928#define F0900_P2_AGC2_OVERFLOW 0xf2130004 929#define F0900_P2_CFR_OVERFLOW 0xf2130002 930#define F0900_P2_GAMMA_OVERUNDER 0xf2130001 931 932/*P2_DMDCFGMD*/ 933#define R0900_P2_DMDCFGMD 0xf214 934#define F0900_P2_DVBS2_ENABLE 0xf2140080 935#define F0900_P2_DVBS1_ENABLE 0xf2140040 936#define F0900_P2_SCAN_ENABLE 0xf2140010 937#define F0900_P2_CFR_AUTOSCAN 0xf2140008 938#define F0900_P2_TUN_RNG 0xf2140003 939 940/*P2_DMDCFG2*/ 941#define R0900_P2_DMDCFG2 0xf215 942#define F0900_P2_S1S2_SEQUENTIAL 0xf2150040 943#define F0900_P2_INFINITE_RELOCK 0xf2150010 944 945/*P2_DMDISTATE*/ 946#define R0900_P2_DMDISTATE 0xf216 947#define F0900_P2_I2C_DEMOD_MODE 0xf216001f 948 949/*P2_DMDT0M*/ 950#define R0900_P2_DMDT0M 0xf217 951#define F0900_P2_DMDT0_MIN 0xf21700ff 952 953/*P2_DMDSTATE*/ 954#define R0900_P2_DMDSTATE 0xf21b 955#define F0900_P2_HEADER_MODE 0xf21b0060 956 957/*P2_DMDFLYW*/ 958#define R0900_P2_DMDFLYW 0xf21c 959#define F0900_P2_I2C_IRQVAL 0xf21c00f0 960#define F0900_P2_FLYWHEEL_CPT 0xf21c000f 961 962/*P2_DSTATUS3*/ 963#define R0900_P2_DSTATUS3 0xf21d 964#define F0900_P2_DEMOD_CFGMODE 0xf21d0060 965 966/*P2_DMDCFG3*/ 967#define R0900_P2_DMDCFG3 0xf21e 968#define F0900_P2_NOSTOP_FIFOFULL 0xf21e0008 969 970/*P2_DMDCFG4*/ 971#define R0900_P2_DMDCFG4 0xf21f 972#define F0900_P2_TUNER_NRELAUNCH 0xf21f0008 973 974/*P2_CORRELMANT*/ 975#define R0900_P2_CORRELMANT 0xf220 976#define F0900_P2_CORREL_MANT 0xf22000ff 977 978/*P2_CORRELABS*/ 979#define R0900_P2_CORRELABS 0xf221 980#define F0900_P2_CORREL_ABS 0xf22100ff 981 982/*P2_CORRELEXP*/ 983#define R0900_P2_CORRELEXP 0xf222 984#define F0900_P2_CORREL_ABSEXP 0xf22200f0 985#define F0900_P2_CORREL_EXP 0xf222000f 986 987/*P2_PLHMODCOD*/ 988#define R0900_P2_PLHMODCOD 0xf224 989#define F0900_P2_SPECINV_DEMOD 0xf2240080 990#define F0900_P2_PLH_MODCOD 0xf224007c 991#define F0900_P2_PLH_TYPE 0xf2240003 992 993/*P2_DMDREG*/ 994#define R0900_P2_DMDREG 0xf225 995#define F0900_P2_DECIM_PLFRAMES 0xf2250001 996 997/*P2_AGC2O*/ 998#define R0900_P2_AGC2O 0xf22c 999#define F0900_P2_AGC2_COEF 0xf22c0007 1000 1001/*P2_AGC2REF*/ 1002#define R0900_P2_AGC2REF 0xf22d 1003#define F0900_P2_AGC2_REF 0xf22d00ff 1004 1005/*P2_AGC1ADJ*/ 1006#define R0900_P2_AGC1ADJ 0xf22e 1007#define F0900_P2_AGC1_ADJUSTED 0xf22e007f 1008 1009/*P2_AGC2I1*/ 1010#define R0900_P2_AGC2I1 0xf236 1011#define F0900_P2_AGC2_INTEGRATOR1 0xf23600ff 1012 1013/*P2_AGC2I0*/ 1014#define R0900_P2_AGC2I0 0xf237 1015#define F0900_P2_AGC2_INTEGRATOR0 0xf23700ff 1016 1017/*P2_CARCFG*/ 1018#define R0900_P2_CARCFG 0xf238 1019#define F0900_P2_CFRUPLOW_AUTO 0xf2380080 1020#define F0900_P2_CFRUPLOW_TEST 0xf2380040 1021#define F0900_P2_ROTAON 0xf2380004 1022#define F0900_P2_PH_DET_ALGO 0xf2380003 1023 1024/*P2_ACLC*/ 1025#define R0900_P2_ACLC 0xf239 1026#define F0900_P2_CAR_ALPHA_MANT 0xf2390030 1027#define F0900_P2_CAR_ALPHA_EXP 0xf239000f 1028 1029/*P2_BCLC*/ 1030#define R0900_P2_BCLC 0xf23a 1031#define F0900_P2_CAR_BETA_MANT 0xf23a0030 1032#define F0900_P2_CAR_BETA_EXP 0xf23a000f 1033 1034/*P2_CARFREQ*/ 1035#define R0900_P2_CARFREQ 0xf23d 1036#define F0900_P2_KC_COARSE_EXP 0xf23d00f0 1037#define F0900_P2_BETA_FREQ 0xf23d000f 1038 1039/*P2_CARHDR*/ 1040#define R0900_P2_CARHDR 0xf23e 1041#define F0900_P2_K_FREQ_HDR 0xf23e00ff 1042 1043/*P2_LDT*/ 1044#define R0900_P2_LDT 0xf23f 1045#define F0900_P2_CARLOCK_THRES 0xf23f01ff 1046 1047/*P2_LDT2*/ 1048#define R0900_P2_LDT2 0xf240 1049#define F0900_P2_CARLOCK_THRES2 0xf24001ff 1050 1051/*P2_CFRICFG*/ 1052#define R0900_P2_CFRICFG 0xf241 1053#define F0900_P2_NEG_CFRSTEP 0xf2410001 1054 1055/*P2_CFRUP1*/ 1056#define R0900_P2_CFRUP1 0xf242 1057#define F0900_P2_CFR_UP1 0xf24201ff 1058 1059/*P2_CFRUP0*/ 1060#define R0900_P2_CFRUP0 0xf243 1061#define F0900_P2_CFR_UP0 0xf24300ff 1062 1063/*P2_CFRLOW1*/ 1064#define R0900_P2_CFRLOW1 0xf246 1065#define F0900_P2_CFR_LOW1 0xf24601ff 1066 1067/*P2_CFRLOW0*/ 1068#define R0900_P2_CFRLOW0 0xf247 1069#define F0900_P2_CFR_LOW0 0xf24700ff 1070 1071/*P2_CFRINIT1*/ 1072#define R0900_P2_CFRINIT1 0xf248 1073#define F0900_P2_CFR_INIT1 0xf24801ff 1074 1075/*P2_CFRINIT0*/ 1076#define R0900_P2_CFRINIT0 0xf249 1077#define F0900_P2_CFR_INIT0 0xf24900ff 1078 1079/*P2_CFRINC1*/ 1080#define R0900_P2_CFRINC1 0xf24a 1081#define F0900_P2_MANUAL_CFRINC 0xf24a0080 1082#define F0900_P2_CFR_INC1 0xf24a003f 1083 1084/*P2_CFRINC0*/ 1085#define R0900_P2_CFRINC0 0xf24b 1086#define F0900_P2_CFR_INC0 0xf24b00f8 1087 1088/*P2_CFR2*/ 1089#define R0900_P2_CFR2 0xf24c 1090#define F0900_P2_CAR_FREQ2 0xf24c01ff 1091 1092/*P2_CFR1*/ 1093#define R0900_P2_CFR1 0xf24d 1094#define F0900_P2_CAR_FREQ1 0xf24d00ff 1095 1096/*P2_CFR0*/ 1097#define R0900_P2_CFR0 0xf24e 1098#define F0900_P2_CAR_FREQ0 0xf24e00ff 1099 1100/*P2_LDI*/ 1101#define R0900_P2_LDI 0xf24f 1102#define F0900_P2_LOCK_DET_INTEGR 0xf24f01ff 1103 1104/*P2_TMGCFG*/ 1105#define R0900_P2_TMGCFG 0xf250 1106#define F0900_P2_TMGLOCK_BETA 0xf25000c0 1107#define F0900_P2_DO_TIMING_CORR 0xf2500010 1108#define F0900_P2_TMG_MINFREQ 0xf2500003 1109 1110/*P2_RTC*/ 1111#define R0900_P2_RTC 0xf251 1112#define F0900_P2_TMGALPHA_EXP 0xf25100f0 1113#define F0900_P2_TMGBETA_EXP 0xf251000f 1114 1115/*P2_RTCS2*/ 1116#define R0900_P2_RTCS2 0xf252 1117#define F0900_P2_TMGALPHAS2_EXP 0xf25200f0 1118#define F0900_P2_TMGBETAS2_EXP 0xf252000f 1119 1120/*P2_TMGTHRISE*/ 1121#define R0900_P2_TMGTHRISE 0xf253 1122#define F0900_P2_TMGLOCK_THRISE 0xf25300ff 1123 1124/*P2_TMGTHFALL*/ 1125#define R0900_P2_TMGTHFALL 0xf254 1126#define F0900_P2_TMGLOCK_THFALL 0xf25400ff 1127 1128/*P2_SFRUPRATIO*/ 1129#define R0900_P2_SFRUPRATIO 0xf255 1130#define F0900_P2_SFR_UPRATIO 0xf25500ff 1131 1132/*P2_SFRLOWRATIO*/ 1133#define R0900_P2_SFRLOWRATIO 0xf256 1134#define F0900_P2_SFR_LOWRATIO 0xf25600ff 1135 1136/*P2_KREFTMG*/ 1137#define R0900_P2_KREFTMG 0xf258 1138#define F0900_P2_KREF_TMG 0xf25800ff 1139 1140/*P2_SFRSTEP*/ 1141#define R0900_P2_SFRSTEP 0xf259 1142#define F0900_P2_SFR_SCANSTEP 0xf25900f0 1143#define F0900_P2_SFR_CENTERSTEP 0xf259000f 1144 1145/*P2_TMGCFG2*/ 1146#define R0900_P2_TMGCFG2 0xf25a 1147#define F0900_P2_SFRRATIO_FINE 0xf25a0001 1148 1149/*P2_KREFTMG2*/ 1150#define R0900_P2_KREFTMG2 0xf25b 1151#define F0900_P2_KREF_TMG2 0xf25b00ff 1152 1153/*P2_SFRINIT1*/ 1154#define R0900_P2_SFRINIT1 0xf25e 1155#define F0900_P2_SFR_INIT1 0xf25e007f 1156 1157/*P2_SFRINIT0*/ 1158#define R0900_P2_SFRINIT0 0xf25f 1159#define F0900_P2_SFR_INIT0 0xf25f00ff 1160 1161/*P2_SFRUP1*/ 1162#define R0900_P2_SFRUP1 0xf260 1163#define F0900_P2_AUTO_GUP 0xf2600080 1164#define F0900_P2_SYMB_FREQ_UP1 0xf260007f 1165 1166/*P2_SFRUP0*/ 1167#define R0900_P2_SFRUP0 0xf261 1168#define F0900_P2_SYMB_FREQ_UP0 0xf26100ff 1169 1170/*P2_SFRLOW1*/ 1171#define R0900_P2_SFRLOW1 0xf262 1172#define F0900_P2_AUTO_GLOW 0xf2620080 1173#define F0900_P2_SYMB_FREQ_LOW1 0xf262007f 1174 1175/*P2_SFRLOW0*/ 1176#define R0900_P2_SFRLOW0 0xf263 1177#define F0900_P2_SYMB_FREQ_LOW0 0xf26300ff 1178 1179/*P2_SFR3*/ 1180#define R0900_P2_SFR3 0xf264 1181#define F0900_P2_SYMB_FREQ3 0xf26400ff 1182 1183/*P2_SFR2*/ 1184#define R0900_P2_SFR2 0xf265 1185#define F0900_P2_SYMB_FREQ2 0xf26500ff 1186 1187/*P2_SFR1*/ 1188#define R0900_P2_SFR1 0xf266 1189#define F0900_P2_SYMB_FREQ1 0xf26600ff 1190 1191/*P2_SFR0*/ 1192#define R0900_P2_SFR0 0xf267 1193#define F0900_P2_SYMB_FREQ0 0xf26700ff 1194 1195/*P2_TMGREG2*/ 1196#define R0900_P2_TMGREG2 0xf268 1197#define F0900_P2_TMGREG2 0xf26800ff 1198 1199/*P2_TMGREG1*/ 1200#define R0900_P2_TMGREG1 0xf269 1201#define F0900_P2_TMGREG1 0xf26900ff 1202 1203/*P2_TMGREG0*/ 1204#define R0900_P2_TMGREG0 0xf26a 1205#define F0900_P2_TMGREG0 0xf26a00ff 1206 1207/*P2_TMGLOCK1*/ 1208#define R0900_P2_TMGLOCK1 0xf26b 1209#define F0900_P2_TMGLOCK_LEVEL1 0xf26b01ff 1210 1211/*P2_TMGLOCK0*/ 1212#define R0900_P2_TMGLOCK0 0xf26c 1213#define F0900_P2_TMGLOCK_LEVEL0 0xf26c00ff 1214 1215/*P2_TMGOBS*/ 1216#define R0900_P2_TMGOBS 0xf26d 1217#define F0900_P2_ROLLOFF_STATUS 0xf26d00c0 1218 1219/*P2_EQUALCFG*/ 1220#define R0900_P2_EQUALCFG 0xf26f 1221#define F0900_P2_EQUAL_ON 0xf26f0040 1222#define F0900_P2_MU_EQUALDFE 0xf26f0007 1223 1224/*P2_EQUAI1*/ 1225#define R0900_P2_EQUAI1 0xf270 1226#define F0900_P2_EQUA_ACCI1 0xf27001ff 1227 1228/*P2_EQUAQ1*/ 1229#define R0900_P2_EQUAQ1 0xf271 1230#define F0900_P2_EQUA_ACCQ1 0xf27101ff 1231 1232/*P2_EQUAI2*/ 1233#define R0900_P2_EQUAI2 0xf272 1234#define F0900_P2_EQUA_ACCI2 0xf27201ff 1235 1236/*P2_EQUAQ2*/ 1237#define R0900_P2_EQUAQ2 0xf273 1238#define F0900_P2_EQUA_ACCQ2 0xf27301ff 1239 1240/*P2_EQUAI3*/ 1241#define R0900_P2_EQUAI3 0xf274 1242#define F0900_P2_EQUA_ACCI3 0xf27401ff 1243 1244/*P2_EQUAQ3*/ 1245#define R0900_P2_EQUAQ3 0xf275 1246#define F0900_P2_EQUA_ACCQ3 0xf27501ff 1247 1248/*P2_EQUAI4*/ 1249#define R0900_P2_EQUAI4 0xf276 1250#define F0900_P2_EQUA_ACCI4 0xf27601ff 1251 1252/*P2_EQUAQ4*/ 1253#define R0900_P2_EQUAQ4 0xf277 1254#define F0900_P2_EQUA_ACCQ4 0xf27701ff 1255 1256/*P2_EQUAI5*/ 1257#define R0900_P2_EQUAI5 0xf278 1258#define F0900_P2_EQUA_ACCI5 0xf27801ff 1259 1260/*P2_EQUAQ5*/ 1261#define R0900_P2_EQUAQ5 0xf279 1262#define F0900_P2_EQUA_ACCQ5 0xf27901ff 1263 1264/*P2_EQUAI6*/ 1265#define R0900_P2_EQUAI6 0xf27a 1266#define F0900_P2_EQUA_ACCI6 0xf27a01ff 1267 1268/*P2_EQUAQ6*/ 1269#define R0900_P2_EQUAQ6 0xf27b 1270#define F0900_P2_EQUA_ACCQ6 0xf27b01ff 1271 1272/*P2_EQUAI7*/ 1273#define R0900_P2_EQUAI7 0xf27c 1274#define F0900_P2_EQUA_ACCI7 0xf27c01ff 1275 1276/*P2_EQUAQ7*/ 1277#define R0900_P2_EQUAQ7 0xf27d 1278#define F0900_P2_EQUA_ACCQ7 0xf27d01ff 1279 1280/*P2_EQUAI8*/ 1281#define R0900_P2_EQUAI8 0xf27e 1282#define F0900_P2_EQUA_ACCI8 0xf27e01ff 1283 1284/*P2_EQUAQ8*/ 1285#define R0900_P2_EQUAQ8 0xf27f 1286#define F0900_P2_EQUA_ACCQ8 0xf27f01ff 1287 1288/*P2_NNOSDATAT1*/ 1289#define R0900_P2_NNOSDATAT1 0xf280 1290#define F0900_P2_NOSDATAT_NORMED1 0xf28000ff 1291 1292/*P2_NNOSDATAT0*/ 1293#define R0900_P2_NNOSDATAT0 0xf281 1294#define F0900_P2_NOSDATAT_NORMED0 0xf28100ff 1295 1296/*P2_NNOSDATA1*/ 1297#define R0900_P2_NNOSDATA1 0xf282 1298#define F0900_P2_NOSDATA_NORMED1 0xf28200ff 1299 1300/*P2_NNOSDATA0*/ 1301#define R0900_P2_NNOSDATA0 0xf283 1302#define F0900_P2_NOSDATA_NORMED0 0xf28300ff 1303 1304/*P2_NNOSPLHT1*/ 1305#define R0900_P2_NNOSPLHT1 0xf284 1306#define F0900_P2_NOSPLHT_NORMED1 0xf28400ff 1307 1308/*P2_NNOSPLHT0*/ 1309#define R0900_P2_NNOSPLHT0 0xf285 1310#define F0900_P2_NOSPLHT_NORMED0 0xf28500ff 1311 1312/*P2_NNOSPLH1*/ 1313#define R0900_P2_NNOSPLH1 0xf286 1314#define F0900_P2_NOSPLH_NORMED1 0xf28600ff 1315 1316/*P2_NNOSPLH0*/ 1317#define R0900_P2_NNOSPLH0 0xf287 1318#define F0900_P2_NOSPLH_NORMED0 0xf28700ff 1319 1320/*P2_NOSDATAT1*/ 1321#define R0900_P2_NOSDATAT1 0xf288 1322#define F0900_P2_NOSDATAT_UNNORMED1 0xf28800ff 1323 1324/*P2_NOSDATAT0*/ 1325#define R0900_P2_NOSDATAT0 0xf289 1326#define F0900_P2_NOSDATAT_UNNORMED0 0xf28900ff 1327 1328/*P2_NOSDATA1*/ 1329#define R0900_P2_NOSDATA1 0xf28a 1330#define F0900_P2_NOSDATA_UNNORMED1 0xf28a00ff 1331 1332/*P2_NOSDATA0*/ 1333#define R0900_P2_NOSDATA0 0xf28b 1334#define F0900_P2_NOSDATA_UNNORMED0 0xf28b00ff 1335 1336/*P2_NOSPLHT1*/ 1337#define R0900_P2_NOSPLHT1 0xf28c 1338#define F0900_P2_NOSPLHT_UNNORMED1 0xf28c00ff 1339 1340/*P2_NOSPLHT0*/ 1341#define R0900_P2_NOSPLHT0 0xf28d 1342#define F0900_P2_NOSPLHT_UNNORMED0 0xf28d00ff 1343 1344/*P2_NOSPLH1*/ 1345#define R0900_P2_NOSPLH1 0xf28e 1346#define F0900_P2_NOSPLH_UNNORMED1 0xf28e00ff 1347 1348/*P2_NOSPLH0*/ 1349#define R0900_P2_NOSPLH0 0xf28f 1350#define F0900_P2_NOSPLH_UNNORMED0 0xf28f00ff 1351 1352/*P2_CAR2CFG*/ 1353#define R0900_P2_CAR2CFG 0xf290 1354#define F0900_P2_CARRIER3_DISABLE 0xf2900040 1355#define F0900_P2_ROTA2ON 0xf2900004 1356#define F0900_P2_PH_DET_ALGO2 0xf2900003 1357 1358/*P2_CFR2CFR1*/ 1359#define R0900_P2_CFR2CFR1 0xf291 1360#define F0900_P2_CFR2TOCFR1_DVBS1 0xf29100c0 1361#define F0900_P2_EN_S2CAR2CENTER 0xf2910020 1362#define F0900_P2_DIS_BCHERRCFR2 0xf2910010 1363#define F0900_P2_CFR2TOCFR1_BETA 0xf2910007 1364 1365/*P2_CFR22*/ 1366#define R0900_P2_CFR22 0xf293 1367#define F0900_P2_CAR2_FREQ2 0xf29301ff 1368 1369/*P2_CFR21*/ 1370#define R0900_P2_CFR21 0xf294 1371#define F0900_P2_CAR2_FREQ1 0xf29400ff 1372 1373/*P2_CFR20*/ 1374#define R0900_P2_CFR20 0xf295 1375#define F0900_P2_CAR2_FREQ0 0xf29500ff 1376 1377/*P2_ACLC2S2Q*/ 1378#define R0900_P2_ACLC2S2Q 0xf297 1379#define F0900_P2_ENAB_SPSKSYMB 0xf2970080 1380#define F0900_P2_CAR2S2_Q_ALPH_M 0xf2970030 1381#define F0900_P2_CAR2S2_Q_ALPH_E 0xf297000f 1382 1383/*P2_ACLC2S28*/ 1384#define R0900_P2_ACLC2S28 0xf298 1385#define F0900_P2_OLDI3Q_MODE 0xf2980080 1386#define F0900_P2_CAR2S2_8_ALPH_M 0xf2980030 1387#define F0900_P2_CAR2S2_8_ALPH_E 0xf298000f 1388 1389/*P2_ACLC2S216A*/ 1390#define R0900_P2_ACLC2S216A 0xf299 1391#define F0900_P2_DIS_C3STOPA2 0xf2990080 1392#define F0900_P2_CAR2S2_16ADERAT 0xf2990040 1393#define F0900_P2_CAR2S2_16A_ALPH_M 0xf2990030 1394#define F0900_P2_CAR2S2_16A_ALPH_E 0xf299000f 1395 1396/*P2_ACLC2S232A*/ 1397#define R0900_P2_ACLC2S232A 0xf29a 1398#define F0900_P2_CAR2S2_32ADERAT 0xf29a0040 1399#define F0900_P2_CAR2S2_32A_ALPH_M 0xf29a0030 1400#define F0900_P2_CAR2S2_32A_ALPH_E 0xf29a000f 1401 1402/*P2_BCLC2S2Q*/ 1403#define R0900_P2_BCLC2S2Q 0xf29c 1404#define F0900_P2_CAR2S2_Q_BETA_M 0xf29c0030 1405#define F0900_P2_CAR2S2_Q_BETA_E 0xf29c000f 1406 1407/*P2_BCLC2S28*/ 1408#define R0900_P2_BCLC2S28 0xf29d 1409#define F0900_P2_CAR2S2_8_BETA_M 0xf29d0030 1410#define F0900_P2_CAR2S2_8_BETA_E 0xf29d000f 1411 1412/*P2_BCLC2S216A*/ 1413#define R0900_P2_BCLC2S216A 0xf29e 1414 1415/*P2_BCLC2S232A*/ 1416#define R0900_P2_BCLC2S232A 0xf29f 1417 1418/*P2_PLROOT2*/ 1419#define R0900_P2_PLROOT2 0xf2ac 1420#define F0900_P2_PLSCRAMB_MODE 0xf2ac000c 1421#define F0900_P2_PLSCRAMB_ROOT2 0xf2ac0003 1422 1423/*P2_PLROOT1*/ 1424#define R0900_P2_PLROOT1 0xf2ad 1425#define F0900_P2_PLSCRAMB_ROOT1 0xf2ad00ff 1426 1427/*P2_PLROOT0*/ 1428#define R0900_P2_PLROOT0 0xf2ae 1429#define F0900_P2_PLSCRAMB_ROOT0 0xf2ae00ff 1430 1431/*P2_MODCODLST0*/ 1432#define R0900_P2_MODCODLST0 0xf2b0 1433 1434/*P2_MODCODLST1*/ 1435#define R0900_P2_MODCODLST1 0xf2b1 1436#define F0900_P2_DIS_MODCOD29 0xf2b100f0 1437#define F0900_P2_DIS_32PSK_9_10 0xf2b1000f 1438 1439/*P2_MODCODLST2*/ 1440#define R0900_P2_MODCODLST2 0xf2b2 1441#define F0900_P2_DIS_32PSK_8_9 0xf2b200f0 1442#define F0900_P2_DIS_32PSK_5_6 0xf2b2000f 1443 1444/*P2_MODCODLST3*/ 1445#define R0900_P2_MODCODLST3 0xf2b3 1446#define F0900_P2_DIS_32PSK_4_5 0xf2b300f0 1447#define F0900_P2_DIS_32PSK_3_4 0xf2b3000f 1448 1449/*P2_MODCODLST4*/ 1450#define R0900_P2_MODCODLST4 0xf2b4 1451#define F0900_P2_DIS_16PSK_9_10 0xf2b400f0 1452#define F0900_P2_DIS_16PSK_8_9 0xf2b4000f 1453 1454/*P2_MODCODLST5*/ 1455#define R0900_P2_MODCODLST5 0xf2b5 1456#define F0900_P2_DIS_16PSK_5_6 0xf2b500f0 1457#define F0900_P2_DIS_16PSK_4_5 0xf2b5000f 1458 1459/*P2_MODCODLST6*/ 1460#define R0900_P2_MODCODLST6 0xf2b6 1461#define F0900_P2_DIS_16PSK_3_4 0xf2b600f0 1462#define F0900_P2_DIS_16PSK_2_3 0xf2b6000f 1463 1464/*P2_MODCODLST7*/ 1465#define R0900_P2_MODCODLST7 0xf2b7 1466#define F0900_P2_DIS_8P_9_10 0xf2b700f0 1467#define F0900_P2_DIS_8P_8_9 0xf2b7000f 1468 1469/*P2_MODCODLST8*/ 1470#define R0900_P2_MODCODLST8 0xf2b8 1471#define F0900_P2_DIS_8P_5_6 0xf2b800f0 1472#define F0900_P2_DIS_8P_3_4 0xf2b8000f 1473 1474/*P2_MODCODLST9*/ 1475#define R0900_P2_MODCODLST9 0xf2b9 1476#define F0900_P2_DIS_8P_2_3 0xf2b900f0 1477#define F0900_P2_DIS_8P_3_5 0xf2b9000f 1478 1479/*P2_MODCODLSTA*/ 1480#define R0900_P2_MODCODLSTA 0xf2ba 1481#define F0900_P2_DIS_QP_9_10 0xf2ba00f0 1482#define F0900_P2_DIS_QP_8_9 0xf2ba000f 1483 1484/*P2_MODCODLSTB*/ 1485#define R0900_P2_MODCODLSTB 0xf2bb 1486#define F0900_P2_DIS_QP_5_6 0xf2bb00f0 1487#define F0900_P2_DIS_QP_4_5 0xf2bb000f 1488 1489/*P2_MODCODLSTC*/ 1490#define R0900_P2_MODCODLSTC 0xf2bc 1491#define F0900_P2_DIS_QP_3_4 0xf2bc00f0 1492#define F0900_P2_DIS_QP_2_3 0xf2bc000f 1493 1494/*P2_MODCODLSTD*/ 1495#define R0900_P2_MODCODLSTD 0xf2bd 1496#define F0900_P2_DIS_QP_3_5 0xf2bd00f0 1497#define F0900_P2_DIS_QP_1_2 0xf2bd000f 1498 1499/*P2_MODCODLSTE*/ 1500#define R0900_P2_MODCODLSTE 0xf2be 1501#define F0900_P2_DIS_QP_2_5 0xf2be00f0 1502#define F0900_P2_DIS_QP_1_3 0xf2be000f 1503 1504/*P2_MODCODLSTF*/ 1505#define R0900_P2_MODCODLSTF 0xf2bf 1506#define F0900_P2_DIS_QP_1_4 0xf2bf00f0 1507 1508/*P2_GAUSSR0*/ 1509#define R0900_P2_GAUSSR0 0xf2c0 1510#define F0900_P2_EN_CCIMODE 0xf2c00080 1511#define F0900_P2_R0_GAUSSIEN 0xf2c0007f 1512 1513/*P2_CCIR0*/ 1514#define R0900_P2_CCIR0 0xf2c1 1515#define F0900_P2_CCIDETECT_PLHONLY 0xf2c10080 1516#define F0900_P2_R0_CCI 0xf2c1007f 1517 1518/*P2_CCIQUANT*/ 1519#define R0900_P2_CCIQUANT 0xf2c2 1520#define F0900_P2_CCI_BETA 0xf2c200e0 1521#define F0900_P2_CCI_QUANT 0xf2c2001f 1522 1523/*P2_CCITHRES*/ 1524#define R0900_P2_CCITHRES 0xf2c3 1525#define F0900_P2_CCI_THRESHOLD 0xf2c300ff 1526 1527/*P2_CCIACC*/ 1528#define R0900_P2_CCIACC 0xf2c4 1529#define F0900_P2_CCI_VALUE 0xf2c400ff 1530 1531/*P2_DMDRESCFG*/ 1532#define R0900_P2_DMDRESCFG 0xf2c6 1533#define F0900_P2_DMDRES_RESET 0xf2c60080 1534#define F0900_P2_DMDRES_STRALL 0xf2c60008 1535#define F0900_P2_DMDRES_NEWONLY 0xf2c60004 1536#define F0900_P2_DMDRES_NOSTORE 0xf2c60002 1537 1538/*P2_DMDRESADR*/ 1539#define R0900_P2_DMDRESADR 0xf2c7 1540#define F0900_P2_DMDRES_VALIDCFR 0xf2c70040 1541#define F0900_P2_DMDRES_MEMFULL 0xf2c70030 1542#define F0900_P2_DMDRES_RESNBR 0xf2c7000f 1543 1544/*P2_DMDRESDATA7*/ 1545#define R0900_P2_DMDRESDATA7 0xf2c8 1546#define F0900_P2_DMDRES_DATA7 0xf2c800ff 1547 1548/*P2_DMDRESDATA6*/ 1549#define R0900_P2_DMDRESDATA6 0xf2c9 1550#define F0900_P2_DMDRES_DATA6 0xf2c900ff 1551 1552/*P2_DMDRESDATA5*/ 1553#define R0900_P2_DMDRESDATA5 0xf2ca 1554#define F0900_P2_DMDRES_DATA5 0xf2ca00ff 1555 1556/*P2_DMDRESDATA4*/ 1557#define R0900_P2_DMDRESDATA4 0xf2cb 1558#define F0900_P2_DMDRES_DATA4 0xf2cb00ff 1559 1560/*P2_DMDRESDATA3*/ 1561#define R0900_P2_DMDRESDATA3 0xf2cc 1562#define F0900_P2_DMDRES_DATA3 0xf2cc00ff 1563 1564/*P2_DMDRESDATA2*/ 1565#define R0900_P2_DMDRESDATA2 0xf2cd 1566#define F0900_P2_DMDRES_DATA2 0xf2cd00ff 1567 1568/*P2_DMDRESDATA1*/ 1569#define R0900_P2_DMDRESDATA1 0xf2ce 1570#define F0900_P2_DMDRES_DATA1 0xf2ce00ff 1571 1572/*P2_DMDRESDATA0*/ 1573#define R0900_P2_DMDRESDATA0 0xf2cf 1574#define F0900_P2_DMDRES_DATA0 0xf2cf00ff 1575 1576/*P2_FFEI1*/ 1577#define R0900_P2_FFEI1 0xf2d0 1578#define F0900_P2_FFE_ACCI1 0xf2d001ff 1579 1580/*P2_FFEQ1*/ 1581#define R0900_P2_FFEQ1 0xf2d1 1582#define F0900_P2_FFE_ACCQ1 0xf2d101ff 1583 1584/*P2_FFEI2*/ 1585#define R0900_P2_FFEI2 0xf2d2 1586#define F0900_P2_FFE_ACCI2 0xf2d201ff 1587 1588/*P2_FFEQ2*/ 1589#define R0900_P2_FFEQ2 0xf2d3 1590#define F0900_P2_FFE_ACCQ2 0xf2d301ff 1591 1592/*P2_FFEI3*/ 1593#define R0900_P2_FFEI3 0xf2d4 1594#define F0900_P2_FFE_ACCI3 0xf2d401ff 1595 1596/*P2_FFEQ3*/ 1597#define R0900_P2_FFEQ3 0xf2d5 1598#define F0900_P2_FFE_ACCQ3 0xf2d501ff 1599 1600/*P2_FFEI4*/ 1601#define R0900_P2_FFEI4 0xf2d6 1602#define F0900_P2_FFE_ACCI4 0xf2d601ff 1603 1604/*P2_FFEQ4*/ 1605#define R0900_P2_FFEQ4 0xf2d7 1606#define F0900_P2_FFE_ACCQ4 0xf2d701ff 1607 1608/*P2_FFECFG*/ 1609#define R0900_P2_FFECFG 0xf2d8 1610#define F0900_P2_EQUALFFE_ON 0xf2d80040 1611#define F0900_P2_MU_EQUALFFE 0xf2d80007 1612 1613/*P2_TNRCFG*/ 1614#define R0900_P2_TNRCFG 0xf2e0 1615#define F0900_P2_TUN_ACKFAIL 0xf2e00080 1616#define F0900_P2_TUN_TYPE 0xf2e00070 1617#define F0900_P2_TUN_SECSTOP 0xf2e00008 1618#define F0900_P2_TUN_VCOSRCH 0xf2e00004 1619#define F0900_P2_TUN_MADDRESS 0xf2e00003 1620 1621/*P2_TNRCFG2*/ 1622#define R0900_P2_TNRCFG2 0xf2e1 1623#define F0900_P2_TUN_IQSWAP 0xf2e10080 1624#define F0900_P2_DIS_BWCALC 0xf2e10004 1625#define F0900_P2_SHORT_WAITSTATES 0xf2e10002 1626 1627/*P2_TNRXTAL*/ 1628#define R0900_P2_TNRXTAL 0xf2e4 1629#define F0900_P2_TUN_XTALFREQ 0xf2e4001f 1630 1631/*P2_TNRSTEPS*/ 1632#define R0900_P2_TNRSTEPS 0xf2e7 1633#define F0900_P2_TUNER_BW0P125 0xf2e70080 1634#define F0900_P2_BWINC_OFFSET 0xf2e70170 1635#define F0900_P2_SOFTSTEP_RNG 0xf2e70008 1636#define F0900_P2_TUN_BWOFFSET 0xf2e70007 1637 1638/*P2_TNRGAIN*/ 1639#define R0900_P2_TNRGAIN 0xf2e8 1640#define F0900_P2_TUN_KDIVEN 0xf2e800c0 1641#define F0900_P2_STB6X00_OCK 0xf2e80030 1642#define F0900_P2_TUN_GAIN 0xf2e8000f 1643 1644/*P2_TNRRF1*/ 1645#define R0900_P2_TNRRF1 0xf2e9 1646#define F0900_P2_TUN_RFFREQ2 0xf2e900ff 1647 1648/*P2_TNRRF0*/ 1649#define R0900_P2_TNRRF0 0xf2ea 1650#define F0900_P2_TUN_RFFREQ1 0xf2ea00ff 1651 1652/*P2_TNRBW*/ 1653#define R0900_P2_TNRBW 0xf2eb 1654#define F0900_P2_TUN_RFFREQ0 0xf2eb00c0 1655#define F0900_P2_TUN_BW 0xf2eb003f 1656 1657/*P2_TNRADJ*/ 1658#define R0900_P2_TNRADJ 0xf2ec 1659#define F0900_P2_STB61X0_CALTIME 0xf2ec0040 1660 1661/*P2_TNRCTL2*/ 1662#define R0900_P2_TNRCTL2 0xf2ed 1663#define F0900_P2_STB61X0_RCCKOFF 0xf2ed0080 1664#define F0900_P2_STB61X0_ICP_SDOFF 0xf2ed0040 1665#define F0900_P2_STB61X0_DCLOOPOFF 0xf2ed0020 1666#define F0900_P2_STB61X0_REFOUTSEL 0xf2ed0010 1667#define F0900_P2_STB61X0_CALOFF 0xf2ed0008 1668#define F0900_P2_STB6XX0_LPT_BEN 0xf2ed0004 1669#define F0900_P2_STB6XX0_RX_OSCP 0xf2ed0002 1670#define F0900_P2_STB6XX0_SYN 0xf2ed0001 1671 1672/*P2_TNRCFG3*/ 1673#define R0900_P2_TNRCFG3 0xf2ee 1674#define F0900_P2_TUN_PLLFREQ 0xf2ee001c 1675#define F0900_P2_TUN_I2CFREQ_MODE 0xf2ee0003 1676 1677/*P2_TNRLAUNCH*/ 1678#define R0900_P2_TNRLAUNCH 0xf2f0 1679 1680/*P2_TNRLD*/ 1681#define R0900_P2_TNRLD 0xf2f0 1682#define F0900_P2_TUNLD_VCOING 0xf2f00080 1683#define F0900_P2_TUN_REG1FAIL 0xf2f00040 1684#define F0900_P2_TUN_REG2FAIL 0xf2f00020 1685#define F0900_P2_TUN_REG3FAIL 0xf2f00010 1686#define F0900_P2_TUN_REG4FAIL 0xf2f00008 1687#define F0900_P2_TUN_REG5FAIL 0xf2f00004 1688#define F0900_P2_TUN_BWING 0xf2f00002 1689#define F0900_P2_TUN_LOCKED 0xf2f00001 1690 1691/*P2_TNROBSL*/ 1692#define R0900_P2_TNROBSL 0xf2f6 1693#define F0900_P2_TUN_I2CABORTED 0xf2f60080 1694#define F0900_P2_TUN_LPEN 0xf2f60040 1695#define F0900_P2_TUN_FCCK 0xf2f60020 1696#define F0900_P2_TUN_I2CLOCKED 0xf2f60010 1697#define F0900_P2_TUN_PROGDONE 0xf2f6000c 1698#define F0900_P2_TUN_RFRESTE1 0xf2f60003 1699 1700/*P2_TNRRESTE*/ 1701#define R0900_P2_TNRRESTE 0xf2f7 1702#define F0900_P2_TUN_RFRESTE0 0xf2f700ff 1703 1704/*P2_SMAPCOEF7*/ 1705#define R0900_P2_SMAPCOEF7 0xf300 1706#define F0900_P2_DIS_QSCALE 0xf3000080 1707#define F0900_P2_SMAPCOEF_Q_LLR12 0xf300017f 1708 1709/*P2_SMAPCOEF6*/ 1710#define R0900_P2_SMAPCOEF6 0xf301 1711#define F0900_P2_ADJ_8PSKLLR1 0xf3010004 1712#define F0900_P2_OLD_8PSKLLR1 0xf3010002 1713#define F0900_P2_DIS_AB8PSK 0xf3010001 1714 1715/*P2_SMAPCOEF5*/ 1716#define R0900_P2_SMAPCOEF5 0xf302 1717#define F0900_P2_DIS_8SCALE 0xf3020080 1718#define F0900_P2_SMAPCOEF_8P_LLR23 0xf302017f 1719 1720/*P2_NCO2MAX1*/ 1721#define R0900_P2_NCO2MAX1 0xf314 1722#define F0900_P2_TETA2_MAXVABS1 0xf31400ff 1723 1724/*P2_NCO2MAX0*/ 1725#define R0900_P2_NCO2MAX0 0xf315 1726#define F0900_P2_TETA2_MAXVABS0 0xf31500ff 1727 1728/*P2_NCO2FR1*/ 1729#define R0900_P2_NCO2FR1 0xf316 1730#define F0900_P2_NCO2FINAL_ANGLE1 0xf31600ff 1731 1732/*P2_NCO2FR0*/ 1733#define R0900_P2_NCO2FR0 0xf317 1734#define F0900_P2_NCO2FINAL_ANGLE0 0xf31700ff 1735 1736/*P2_CFR2AVRGE1*/ 1737#define R0900_P2_CFR2AVRGE1 0xf318 1738#define F0900_P2_I2C_CFR2AVERAGE1 0xf31800ff 1739 1740/*P2_CFR2AVRGE0*/ 1741#define R0900_P2_CFR2AVRGE0 0xf319 1742#define F0900_P2_I2C_CFR2AVERAGE0 0xf31900ff 1743 1744/*P2_DMDPLHSTAT*/ 1745#define R0900_P2_DMDPLHSTAT 0xf320 1746#define F0900_P2_PLH_STATISTIC 0xf32000ff 1747 1748/*P2_LOCKTIME3*/ 1749#define R0900_P2_LOCKTIME3 0xf322 1750#define F0900_P2_DEMOD_LOCKTIME3 0xf32200ff 1751 1752/*P2_LOCKTIME2*/ 1753#define R0900_P2_LOCKTIME2 0xf323 1754#define F0900_P2_DEMOD_LOCKTIME2 0xf32300ff 1755 1756/*P2_LOCKTIME1*/ 1757#define R0900_P2_LOCKTIME1 0xf324 1758#define F0900_P2_DEMOD_LOCKTIME1 0xf32400ff 1759 1760/*P2_LOCKTIME0*/ 1761#define R0900_P2_LOCKTIME0 0xf325 1762#define F0900_P2_DEMOD_LOCKTIME0 0xf32500ff 1763 1764/*P2_VITSCALE*/ 1765#define R0900_P2_VITSCALE 0xf332 1766#define F0900_P2_NVTH_NOSRANGE 0xf3320080 1767#define F0900_P2_VERROR_MAXMODE 0xf3320040 1768#define F0900_P2_NSLOWSN_LOCKED 0xf3320008 1769#define F0900_P2_DIS_RSFLOCK 0xf3320002 1770 1771/*P2_FECM*/ 1772#define R0900_P2_FECM 0xf333 1773#define F0900_P2_DSS_DVB 0xf3330080 1774#define F0900_P2_DSS_SRCH 0xf3330010 1775#define F0900_P2_SYNCVIT 0xf3330002 1776#define F0900_P2_IQINV 0xf3330001 1777 1778/*P2_VTH12*/ 1779#define R0900_P2_VTH12 0xf334 1780#define F0900_P2_VTH12 0xf33400ff 1781 1782/*P2_VTH23*/ 1783#define R0900_P2_VTH23 0xf335 1784#define F0900_P2_VTH23 0xf33500ff 1785 1786/*P2_VTH34*/ 1787#define R0900_P2_VTH34 0xf336 1788#define F0900_P2_VTH34 0xf33600ff 1789 1790/*P2_VTH56*/ 1791#define R0900_P2_VTH56 0xf337 1792#define F0900_P2_VTH56 0xf33700ff 1793 1794/*P2_VTH67*/ 1795#define R0900_P2_VTH67 0xf338 1796#define F0900_P2_VTH67 0xf33800ff 1797 1798/*P2_VTH78*/ 1799#define R0900_P2_VTH78 0xf339 1800#define F0900_P2_VTH78 0xf33900ff 1801 1802/*P2_VITCURPUN*/ 1803#define R0900_P2_VITCURPUN 0xf33a 1804#define F0900_P2_VIT_CURPUN 0xf33a001f 1805 1806/*P2_VERROR*/ 1807#define R0900_P2_VERROR 0xf33b 1808#define F0900_P2_REGERR_VIT 0xf33b00ff 1809 1810/*P2_PRVIT*/ 1811#define R0900_P2_PRVIT 0xf33c 1812#define F0900_P2_DIS_VTHLOCK 0xf33c0040 1813#define F0900_P2_E7_8VIT 0xf33c0020 1814#define F0900_P2_E6_7VIT 0xf33c0010 1815#define F0900_P2_E5_6VIT 0xf33c0008 1816#define F0900_P2_E3_4VIT 0xf33c0004 1817#define F0900_P2_E2_3VIT 0xf33c0002 1818#define F0900_P2_E1_2VIT 0xf33c0001 1819 1820/*P2_VAVSRVIT*/ 1821#define R0900_P2_VAVSRVIT 0xf33d 1822#define F0900_P2_AMVIT 0xf33d0080 1823#define F0900_P2_FROZENVIT 0xf33d0040 1824#define F0900_P2_SNVIT 0xf33d0030 1825#define F0900_P2_TOVVIT 0xf33d000c 1826#define F0900_P2_HYPVIT 0xf33d0003 1827 1828/*P2_VSTATUSVIT*/ 1829#define R0900_P2_VSTATUSVIT 0xf33e 1830#define F0900_P2_PRFVIT 0xf33e0010 1831#define F0900_P2_LOCKEDVIT 0xf33e0008 1832 1833/*P2_VTHINUSE*/ 1834#define R0900_P2_VTHINUSE 0xf33f 1835#define F0900_P2_VIT_INUSE 0xf33f00ff 1836 1837/*P2_KDIV12*/ 1838#define R0900_P2_KDIV12 0xf340 1839#define F0900_P2_K_DIVIDER_12 0xf340007f 1840 1841/*P2_KDIV23*/ 1842#define R0900_P2_KDIV23 0xf341 1843#define F0900_P2_K_DIVIDER_23 0xf341007f 1844 1845/*P2_KDIV34*/ 1846#define R0900_P2_KDIV34 0xf342 1847#define F0900_P2_K_DIVIDER_34 0xf342007f 1848 1849/*P2_KDIV56*/ 1850#define R0900_P2_KDIV56 0xf343 1851#define F0900_P2_K_DIVIDER_56 0xf343007f 1852 1853/*P2_KDIV67*/ 1854#define R0900_P2_KDIV67 0xf344 1855#define F0900_P2_K_DIVIDER_67 0xf344007f 1856 1857/*P2_KDIV78*/ 1858#define R0900_P2_KDIV78 0xf345 1859#define F0900_P2_K_DIVIDER_78 0xf345007f 1860 1861/*P2_PDELCTRL1*/ 1862#define R0900_P2_PDELCTRL1 0xf350 1863#define F0900_P2_INV_MISMASK 0xf3500080 1864#define F0900_P2_FILTER_EN 0xf3500020 1865#define F0900_P2_EN_MIS00 0xf3500002 1866#define F0900_P2_ALGOSWRST 0xf3500001 1867 1868/*P2_PDELCTRL2*/ 1869#define R0900_P2_PDELCTRL2 0xf351 1870#define F0900_P2_RESET_UPKO_COUNT 0xf3510040 1871#define F0900_P2_FRAME_MODE 0xf3510002 1872#define F0900_P2_NOBCHERRFLG_USE 0xf3510001 1873 1874/*P2_HYSTTHRESH*/ 1875#define R0900_P2_HYSTTHRESH 0xf354 1876#define F0900_P2_UNLCK_THRESH 0xf35400f0 1877#define F0900_P2_DELIN_LCK_THRESH 0xf354000f 1878 1879/*P2_ISIENTRY*/ 1880#define R0900_P2_ISIENTRY 0xf35e 1881#define F0900_P2_ISI_ENTRY 0xf35e00ff 1882 1883/*P2_ISIBITENA*/ 1884#define R0900_P2_ISIBITENA 0xf35f 1885#define F0900_P2_ISI_BIT_EN 0xf35f00ff 1886 1887/*P2_MATSTR1*/ 1888#define R0900_P2_MATSTR1 0xf360 1889#define F0900_P2_MATYPE_CURRENT1 0xf36000ff 1890 1891/*P2_MATSTR0*/ 1892#define R0900_P2_MATSTR0 0xf361 1893#define F0900_P2_MATYPE_CURRENT0 0xf36100ff 1894 1895/*P2_UPLSTR1*/ 1896#define R0900_P2_UPLSTR1 0xf362 1897#define F0900_P2_UPL_CURRENT1 0xf36200ff 1898 1899/*P2_UPLSTR0*/ 1900#define R0900_P2_UPLSTR0 0xf363 1901#define F0900_P2_UPL_CURRENT0 0xf36300ff 1902 1903/*P2_DFLSTR1*/ 1904#define R0900_P2_DFLSTR1 0xf364 1905#define F0900_P2_DFL_CURRENT1 0xf36400ff 1906 1907/*P2_DFLSTR0*/ 1908#define R0900_P2_DFLSTR0 0xf365 1909#define F0900_P2_DFL_CURRENT0 0xf36500ff 1910 1911/*P2_SYNCSTR*/ 1912#define R0900_P2_SYNCSTR 0xf366 1913#define F0900_P2_SYNC_CURRENT 0xf36600ff 1914 1915/*P2_SYNCDSTR1*/ 1916#define R0900_P2_SYNCDSTR1 0xf367 1917#define F0900_P2_SYNCD_CURRENT1 0xf36700ff 1918 1919/*P2_SYNCDSTR0*/ 1920#define R0900_P2_SYNCDSTR0 0xf368 1921#define F0900_P2_SYNCD_CURRENT0 0xf36800ff 1922 1923/*P2_PDELSTATUS1*/ 1924#define R0900_P2_PDELSTATUS1 0xf369 1925#define F0900_P2_PKTDELIN_DELOCK 0xf3690080 1926#define F0900_P2_SYNCDUPDFL_BADDFL 0xf3690040 1927#define F0900_P2_CONTINUOUS_STREAM 0xf3690020 1928#define F0900_P2_UNACCEPTED_STREAM 0xf3690010 1929#define F0900_P2_BCH_ERROR_FLAG 0xf3690008 1930#define F0900_P2_PKTDELIN_LOCK 0xf3690002 1931#define F0900_P2_FIRST_LOCK 0xf3690001 1932 1933/*P2_PDELSTATUS2*/ 1934#define R0900_P2_PDELSTATUS2 0xf36a 1935#define F0900_P2_FRAME_MODCOD 0xf36a007c 1936#define F0900_P2_FRAME_TYPE 0xf36a0003 1937 1938/*P2_BBFCRCKO1*/ 1939#define R0900_P2_BBFCRCKO1 0xf36b 1940#define F0900_P2_BBHCRC_KOCNT1 0xf36b00ff 1941 1942/*P2_BBFCRCKO0*/ 1943#define R0900_P2_BBFCRCKO0 0xf36c 1944#define F0900_P2_BBHCRC_KOCNT0 0xf36c00ff 1945 1946/*P2_UPCRCKO1*/ 1947#define R0900_P2_UPCRCKO1 0xf36d 1948#define F0900_P2_PKTCRC_KOCNT1 0xf36d00ff 1949 1950/*P2_UPCRCKO0*/ 1951#define R0900_P2_UPCRCKO0 0xf36e 1952#define F0900_P2_PKTCRC_KOCNT0 0xf36e00ff 1953 1954/*P2_PDELCTRL3*/ 1955#define R0900_P2_PDELCTRL3 0xf36f 1956#define F0900_P2_PKTDEL_CONTFAIL 0xf36f0080 1957#define F0900_P2_NOFIFO_BCHERR 0xf36f0020 1958 1959/*P2_TSSTATEM*/ 1960#define R0900_P2_TSSTATEM 0xf370 1961#define F0900_P2_TSDIL_ON 0xf3700080 1962#define F0900_P2_TSRS_ON 0xf3700020 1963#define F0900_P2_TSDESCRAMB_ON 0xf3700010 1964#define F0900_P2_TSFRAME_MODE 0xf3700008 1965#define F0900_P2_TS_DISABLE 0xf3700004 1966#define F0900_P2_TSOUT_NOSYNC 0xf3700001 1967 1968/*P2_TSCFGH*/ 1969#define R0900_P2_TSCFGH 0xf372 1970#define F0900_P2_TSFIFO_DVBCI 0xf3720080 1971#define F0900_P2_TSFIFO_SERIAL 0xf3720040 1972#define F0900_P2_TSFIFO_TEIUPDATE 0xf3720020 1973#define F0900_P2_TSFIFO_DUTY50 0xf3720010 1974#define F0900_P2_TSFIFO_HSGNLOUT 0xf3720008 1975#define F0900_P2_TSFIFO_ERRMODE 0xf3720006 1976#define F0900_P2_RST_HWARE 0xf3720001 1977 1978/*P2_TSCFGM*/ 1979#define R0900_P2_TSCFGM 0xf373 1980#define F0900_P2_TSFIFO_MANSPEED 0xf37300c0 1981#define F0900_P2_TSFIFO_PERMDATA 0xf3730020 1982#define F0900_P2_TSFIFO_DPUNACT 0xf3730002 1983#define F0900_P2_TSFIFO_INVDATA 0xf3730001 1984 1985/*P2_TSCFGL*/ 1986#define R0900_P2_TSCFGL 0xf374 1987#define F0900_P2_TSFIFO_BCLKDEL1CK 0xf37400c0 1988#define F0900_P2_BCHERROR_MODE 0xf3740030 1989#define F0900_P2_TSFIFO_NSGNL2DATA 0xf3740008 1990#define F0900_P2_TSFIFO_EMBINDVB 0xf3740004 1991#define F0900_P2_TSFIFO_BITSPEED 0xf3740003 1992 1993/*P2_TSINSDELH*/ 1994#define R0900_P2_TSINSDELH 0xf376 1995#define F0900_P2_TSDEL_SYNCBYTE 0xf3760080 1996#define F0900_P2_TSDEL_XXHEADER 0xf3760040 1997#define F0900_P2_TSDEL_BBHEADER 0xf3760020 1998#define F0900_P2_TSDEL_DATAFIELD 0xf3760010 1999#define F0900_P2_TSINSDEL_ISCR 0xf3760008 2000#define F0900_P2_TSINSDEL_NPD 0xf3760004 2001#define F0900_P2_TSINSDEL_RSPARITY 0xf3760002 2002#define F0900_P2_TSINSDEL_CRC8 0xf3760001 2003 2004/*P2_TSDIVN*/ 2005#define R0900_P2_TSDIVN 0xf379 2006#define F0900_P2_TSFIFO_SPEEDMODE 0xf37900c0 2007 2008/*P2_TSCFG4*/ 2009#define R0900_P2_TSCFG4 0xf37a 2010#define F0900_P2_TSFIFO_TSSPEEDMODE 0xf37a00c0 2011 2012/*P2_TSSPEED*/ 2013#define R0900_P2_TSSPEED 0xf380 2014#define F0900_P2_TSFIFO_OUTSPEED 0xf38000ff 2015 2016/*P2_TSSTATUS*/ 2017#define R0900_P2_TSSTATUS 0xf381 2018#define F0900_P2_TSFIFO_LINEOK 0xf3810080 2019#define F0900_P2_TSFIFO_ERROR 0xf3810040 2020#define F0900_P2_DIL_READY 0xf3810001 2021 2022/*P2_TSSTATUS2*/ 2023#define R0900_P2_TSSTATUS2 0xf382 2024#define F0900_P2_TSFIFO_DEMODSEL 0xf3820080 2025#define F0900_P2_TSFIFOSPEED_STORE 0xf3820040 2026#define F0900_P2_DILXX_RESET 0xf3820020 2027#define F0900_P2_TSSERIAL_IMPOS 0xf3820010 2028#define F0900_P2_SCRAMBDETECT 0xf3820002 2029 2030/*P2_TSBITRATE1*/ 2031#define R0900_P2_TSBITRATE1 0xf383 2032#define F0900_P2_TSFIFO_BITRATE1 0xf38300ff 2033 2034/*P2_TSBITRATE0*/ 2035#define R0900_P2_TSBITRATE0 0xf384 2036#define F0900_P2_TSFIFO_BITRATE0 0xf38400ff 2037 2038/*P2_ERRCTRL1*/ 2039#define R0900_P2_ERRCTRL1 0xf398 2040#define F0900_P2_ERR_SOURCE1 0xf39800f0 2041#define F0900_P2_NUM_EVENT1 0xf3980007 2042 2043/*P2_ERRCNT12*/ 2044#define R0900_P2_ERRCNT12 0xf399 2045#define F0900_P2_ERRCNT1_OLDVALUE 0xf3990080 2046#define F0900_P2_ERR_CNT12 0xf399007f 2047 2048/*P2_ERRCNT11*/ 2049#define R0900_P2_ERRCNT11 0xf39a 2050#define F0900_P2_ERR_CNT11 0xf39a00ff 2051 2052/*P2_ERRCNT10*/ 2053#define R0900_P2_ERRCNT10 0xf39b 2054#define F0900_P2_ERR_CNT10 0xf39b00ff 2055 2056/*P2_ERRCTRL2*/ 2057#define R0900_P2_ERRCTRL2 0xf39c 2058#define F0900_P2_ERR_SOURCE2 0xf39c00f0 2059#define F0900_P2_NUM_EVENT2 0xf39c0007 2060 2061/*P2_ERRCNT22*/ 2062#define R0900_P2_ERRCNT22 0xf39d 2063#define F0900_P2_ERRCNT2_OLDVALUE 0xf39d0080 2064#define F0900_P2_ERR_CNT22 0xf39d007f 2065 2066/*P2_ERRCNT21*/ 2067#define R0900_P2_ERRCNT21 0xf39e 2068#define F0900_P2_ERR_CNT21 0xf39e00ff 2069 2070/*P2_ERRCNT20*/ 2071#define R0900_P2_ERRCNT20 0xf39f 2072#define F0900_P2_ERR_CNT20 0xf39f00ff 2073 2074/*P2_FECSPY*/ 2075#define R0900_P2_FECSPY 0xf3a0 2076#define F0900_P2_SPY_ENABLE 0xf3a00080 2077#define F0900_P2_NO_SYNCBYTE 0xf3a00040 2078#define F0900_P2_SERIAL_MODE 0xf3a00020 2079#define F0900_P2_UNUSUAL_PACKET 0xf3a00010 2080#define F0900_P2_BERMETER_DATAMODE 0xf3a00008 2081#define F0900_P2_BERMETER_LMODE 0xf3a00002 2082#define F0900_P2_BERMETER_RESET 0xf3a00001 2083 2084/*P2_FSPYCFG*/ 2085#define R0900_P2_FSPYCFG 0xf3a1 2086#define F0900_P2_FECSPY_INPUT 0xf3a100c0 2087#define F0900_P2_RST_ON_ERROR 0xf3a10020 2088#define F0900_P2_ONE_SHOT 0xf3a10010 2089#define F0900_P2_I2C_MODE 0xf3a1000c 2090#define F0900_P2_SPY_HYSTERESIS 0xf3a10003 2091 2092/*P2_FSPYDATA*/ 2093#define R0900_P2_FSPYDATA 0xf3a2 2094#define F0900_P2_SPY_STUFFING 0xf3a20080 2095#define F0900_P2_SPY_CNULLPKT 0xf3a20020 2096#define F0900_P2_SPY_OUTDATA_MODE 0xf3a2001f 2097 2098/*P2_FSPYOUT*/ 2099#define R0900_P2_FSPYOUT 0xf3a3 2100#define F0900_P2_FSPY_DIRECT 0xf3a30080 2101#define F0900_P2_STUFF_MODE 0xf3a30007 2102 2103/*P2_FSTATUS*/ 2104#define R0900_P2_FSTATUS 0xf3a4 2105#define F0900_P2_SPY_ENDSIM 0xf3a40080 2106#define F0900_P2_VALID_SIM 0xf3a40040 2107#define F0900_P2_FOUND_SIGNAL 0xf3a40020 2108#define F0900_P2_DSS_SYNCBYTE 0xf3a40010 2109#define F0900_P2_RESULT_STATE 0xf3a4000f 2110 2111/*P2_FBERCPT4*/ 2112#define R0900_P2_FBERCPT4 0xf3a8 2113#define F0900_P2_FBERMETER_CPT4 0xf3a800ff 2114 2115/*P2_FBERCPT3*/ 2116#define R0900_P2_FBERCPT3 0xf3a9 2117#define F0900_P2_FBERMETER_CPT3 0xf3a900ff 2118 2119/*P2_FBERCPT2*/ 2120#define R0900_P2_FBERCPT2 0xf3aa 2121#define F0900_P2_FBERMETER_CPT2 0xf3aa00ff 2122 2123/*P2_FBERCPT1*/ 2124#define R0900_P2_FBERCPT1 0xf3ab 2125#define F0900_P2_FBERMETER_CPT1 0xf3ab00ff 2126 2127/*P2_FBERCPT0*/ 2128#define R0900_P2_FBERCPT0 0xf3ac 2129#define F0900_P2_FBERMETER_CPT0 0xf3ac00ff 2130 2131/*P2_FBERERR2*/ 2132#define R0900_P2_FBERERR2 0xf3ad 2133#define F0900_P2_FBERMETER_ERR2 0xf3ad00ff 2134 2135/*P2_FBERERR1*/ 2136#define R0900_P2_FBERERR1 0xf3ae 2137#define F0900_P2_FBERMETER_ERR1 0xf3ae00ff 2138 2139/*P2_FBERERR0*/ 2140#define R0900_P2_FBERERR0 0xf3af 2141#define F0900_P2_FBERMETER_ERR0 0xf3af00ff 2142 2143/*P2_FSPYBER*/ 2144#define R0900_P2_FSPYBER 0xf3b2 2145#define F0900_P2_FSPYBER_SYNCBYTE 0xf3b20010 2146#define F0900_P2_FSPYBER_UNSYNC 0xf3b20008 2147#define F0900_P2_FSPYBER_CTIME 0xf3b20007 2148 2149/*P1_IQCONST*/ 2150#define R0900_P1_IQCONST 0xf400 2151#define IQCONST REGx(R0900_P1_IQCONST) 2152#define F0900_P1_CONSTEL_SELECT 0xf4000060 2153#define F0900_P1_IQSYMB_SEL 0xf400001f 2154 2155/*P1_NOSCFG*/ 2156#define R0900_P1_NOSCFG 0xf401 2157#define NOSCFG REGx(R0900_P1_NOSCFG) 2158#define F0900_P1_DUMMYPL_NOSDATA 0xf4010020 2159#define F0900_P1_NOSPLH_BETA 0xf4010018 2160#define F0900_P1_NOSDATA_BETA 0xf4010007 2161 2162/*P1_ISYMB*/ 2163#define R0900_P1_ISYMB 0xf402 2164#define ISYMB REGx(R0900_P1_ISYMB) 2165#define F0900_P1_I_SYMBOL 0xf40201ff 2166 2167/*P1_QSYMB*/ 2168#define R0900_P1_QSYMB 0xf403 2169#define QSYMB REGx(R0900_P1_QSYMB) 2170#define F0900_P1_Q_SYMBOL 0xf40301ff 2171 2172/*P1_AGC1CFG*/ 2173#define R0900_P1_AGC1CFG 0xf404 2174#define AGC1CFG REGx(R0900_P1_AGC1CFG) 2175#define F0900_P1_DC_FROZEN 0xf4040080 2176#define F0900_P1_DC_CORRECT 0xf4040040 2177#define F0900_P1_AMM_FROZEN 0xf4040020 2178#define F0900_P1_AMM_CORRECT 0xf4040010 2179#define F0900_P1_QUAD_FROZEN 0xf4040008 2180#define F0900_P1_QUAD_CORRECT 0xf4040004 2181 2182/*P1_AGC1CN*/ 2183#define R0900_P1_AGC1CN 0xf406 2184#define AGC1CN REGx(R0900_P1_AGC1CN) 2185#define F0900_P1_AGC1_LOCKED 0xf4060080 2186#define F0900_P1_AGC1_MINPOWER 0xf4060010 2187#define F0900_P1_AGCOUT_FAST 0xf4060008 2188#define F0900_P1_AGCIQ_BETA 0xf4060007 2189 2190/*P1_AGC1REF*/ 2191#define R0900_P1_AGC1REF 0xf407 2192#define AGC1REF REGx(R0900_P1_AGC1REF) 2193#define F0900_P1_AGCIQ_REF 0xf40700ff 2194 2195/*P1_IDCCOMP*/ 2196#define R0900_P1_IDCCOMP 0xf408 2197#define IDCCOMP REGx(R0900_P1_IDCCOMP) 2198#define F0900_P1_IAVERAGE_ADJ 0xf40801ff 2199 2200/*P1_QDCCOMP*/ 2201#define R0900_P1_QDCCOMP 0xf409 2202#define QDCCOMP REGx(R0900_P1_QDCCOMP) 2203#define F0900_P1_QAVERAGE_ADJ 0xf40901ff 2204 2205/*P1_POWERI*/ 2206#define R0900_P1_POWERI 0xf40a 2207#define POWERI REGx(R0900_P1_POWERI) 2208#define F0900_P1_POWER_I 0xf40a00ff 2209#define POWER_I FLDx(F0900_P1_POWER_I) 2210 2211/*P1_POWERQ*/ 2212#define R0900_P1_POWERQ 0xf40b 2213#define POWERQ REGx(R0900_P1_POWERQ) 2214#define F0900_P1_POWER_Q 0xf40b00ff 2215#define POWER_Q FLDx(F0900_P1_POWER_Q) 2216 2217/*P1_AGC1AMM*/ 2218#define R0900_P1_AGC1AMM 0xf40c 2219#define AGC1AMM REGx(R0900_P1_AGC1AMM) 2220#define F0900_P1_AMM_VALUE 0xf40c00ff 2221 2222/*P1_AGC1QUAD*/ 2223#define R0900_P1_AGC1QUAD 0xf40d 2224#define AGC1QUAD REGx(R0900_P1_AGC1QUAD) 2225#define F0900_P1_QUAD_VALUE 0xf40d01ff 2226 2227/*P1_AGCIQIN1*/ 2228#define R0900_P1_AGCIQIN1 0xf40e 2229#define AGCIQIN1 REGx(R0900_P1_AGCIQIN1) 2230#define F0900_P1_AGCIQ_VALUE1 0xf40e00ff 2231#define AGCIQ_VALUE1 FLDx(F0900_P1_AGCIQ_VALUE1) 2232 2233/*P1_AGCIQIN0*/ 2234#define R0900_P1_AGCIQIN0 0xf40f 2235#define AGCIQIN0 REGx(R0900_P1_AGCIQIN0) 2236#define F0900_P1_AGCIQ_VALUE0 0xf40f00ff 2237#define AGCIQ_VALUE0 FLDx(F0900_P1_AGCIQ_VALUE0) 2238 2239/*P1_DEMOD*/ 2240#define R0900_P1_DEMOD 0xf410 2241#define DEMOD REGx(R0900_P1_DEMOD) 2242#define F0900_P1_MANUALS2_ROLLOFF 0xf4100080 2243#define MANUALS2_ROLLOFF FLDx(F0900_P1_MANUALS2_ROLLOFF) 2244 2245#define F0900_P1_SPECINV_CONTROL 0xf4100030 2246#define SPECINV_CONTROL FLDx(F0900_P1_SPECINV_CONTROL) 2247#define F0900_P1_FORCE_ENASAMP 0xf4100008 2248#define F0900_P1_MANUALSX_ROLLOFF 0xf4100004 2249#define MANUALSX_ROLLOFF FLDx(F0900_P1_MANUALSX_ROLLOFF) 2250#define F0900_P1_ROLLOFF_CONTROL 0xf4100003 2251#define ROLLOFF_CONTROL FLDx(F0900_P1_ROLLOFF_CONTROL) 2252 2253/*P1_DMDMODCOD*/ 2254#define R0900_P1_DMDMODCOD 0xf411 2255#define DMDMODCOD REGx(R0900_P1_DMDMODCOD) 2256#define F0900_P1_MANUAL_MODCOD 0xf4110080 2257#define F0900_P1_DEMOD_MODCOD 0xf411007c 2258#define DEMOD_MODCOD FLDx(F0900_P1_DEMOD_MODCOD) 2259#define F0900_P1_DEMOD_TYPE 0xf4110003 2260#define DEMOD_TYPE FLDx(F0900_P1_DEMOD_TYPE) 2261 2262/*P1_DSTATUS*/ 2263#define R0900_P1_DSTATUS 0xf412 2264#define DSTATUS REGx(R0900_P1_DSTATUS) 2265#define F0900_P1_CAR_LOCK 0xf4120080 2266#define F0900_P1_TMGLOCK_QUALITY 0xf4120060 2267#define TMGLOCK_QUALITY FLDx(F0900_P1_TMGLOCK_QUALITY) 2268#define F0900_P1_LOCK_DEFINITIF 0xf4120008 2269#define LOCK_DEFINITIF FLDx(F0900_P1_LOCK_DEFINITIF) 2270#define F0900_P1_OVADC_DETECT 0xf4120001 2271 2272/*P1_DSTATUS2*/ 2273#define R0900_P1_DSTATUS2 0xf413 2274#define DSTATUS2 REGx(R0900_P1_DSTATUS2) 2275#define F0900_P1_DEMOD_DELOCK 0xf4130080 2276#define F0900_P1_AGC1_NOSIGNALACK 0xf4130008 2277#define F0900_P1_AGC2_OVERFLOW 0xf4130004 2278#define F0900_P1_CFR_OVERFLOW 0xf4130002 2279#define F0900_P1_GAMMA_OVERUNDER 0xf4130001 2280 2281/*P1_DMDCFGMD*/ 2282#define R0900_P1_DMDCFGMD 0xf414 2283#define DMDCFGMD REGx(R0900_P1_DMDCFGMD) 2284#define F0900_P1_DVBS2_ENABLE 0xf4140080 2285#define DVBS2_ENABLE FLDx(F0900_P1_DVBS2_ENABLE) 2286#define F0900_P1_DVBS1_ENABLE 0xf4140040 2287#define DVBS1_ENABLE FLDx(F0900_P1_DVBS1_ENABLE) 2288#define F0900_P1_SCAN_ENABLE 0xf4140010 2289#define SCAN_ENABLE FLDx(F0900_P1_SCAN_ENABLE) 2290#define F0900_P1_CFR_AUTOSCAN 0xf4140008 2291#define CFR_AUTOSCAN FLDx(F0900_P1_CFR_AUTOSCAN) 2292#define F0900_P1_TUN_RNG 0xf4140003 2293 2294/*P1_DMDCFG2*/ 2295#define R0900_P1_DMDCFG2 0xf415 2296#define DMDCFG2 REGx(R0900_P1_DMDCFG2) 2297#define F0900_P1_S1S2_SEQUENTIAL 0xf4150040 2298#define S1S2_SEQUENTIAL FLDx(F0900_P1_S1S2_SEQUENTIAL) 2299#define F0900_P1_INFINITE_RELOCK 0xf4150010 2300 2301/*P1_DMDISTATE*/ 2302#define R0900_P1_DMDISTATE 0xf416 2303#define DMDISTATE REGx(R0900_P1_DMDISTATE) 2304#define F0900_P1_I2C_DEMOD_MODE 0xf416001f 2305#define DEMOD_MODE FLDx(F0900_P1_I2C_DEMOD_MODE) 2306 2307/*P1_DMDT0M*/ 2308#define R0900_P1_DMDT0M 0xf417 2309#define DMDT0M REGx(R0900_P1_DMDT0M) 2310#define F0900_P1_DMDT0_MIN 0xf41700ff 2311 2312/*P1_DMDSTATE*/ 2313#define R0900_P1_DMDSTATE 0xf41b 2314#define DMDSTATE REGx(R0900_P1_DMDSTATE) 2315#define F0900_P1_HEADER_MODE 0xf41b0060 2316#define HEADER_MODE FLDx(F0900_P1_HEADER_MODE) 2317 2318/*P1_DMDFLYW*/ 2319#define R0900_P1_DMDFLYW 0xf41c 2320#define DMDFLYW REGx(R0900_P1_DMDFLYW) 2321#define F0900_P1_I2C_IRQVAL 0xf41c00f0 2322#define F0900_P1_FLYWHEEL_CPT 0xf41c000f 2323#define FLYWHEEL_CPT FLDx(F0900_P1_FLYWHEEL_CPT) 2324 2325/*P1_DSTATUS3*/ 2326#define R0900_P1_DSTATUS3 0xf41d 2327#define DSTATUS3 REGx(R0900_P1_DSTATUS3) 2328#define F0900_P1_DEMOD_CFGMODE 0xf41d0060 2329 2330/*P1_DMDCFG3*/ 2331#define R0900_P1_DMDCFG3 0xf41e 2332#define DMDCFG3 REGx(R0900_P1_DMDCFG3) 2333#define F0900_P1_NOSTOP_FIFOFULL 0xf41e0008 2334 2335/*P1_DMDCFG4*/ 2336#define R0900_P1_DMDCFG4 0xf41f 2337#define DMDCFG4 REGx(R0900_P1_DMDCFG4) 2338#define F0900_P1_TUNER_NRELAUNCH 0xf41f0008 2339 2340/*P1_CORRELMANT*/ 2341#define R0900_P1_CORRELMANT 0xf420 2342#define CORRELMANT REGx(R0900_P1_CORRELMANT) 2343#define F0900_P1_CORREL_MANT 0xf42000ff 2344 2345/*P1_CORRELABS*/ 2346#define R0900_P1_CORRELABS 0xf421 2347#define CORRELABS REGx(R0900_P1_CORRELABS) 2348#define F0900_P1_CORREL_ABS 0xf42100ff 2349 2350/*P1_CORRELEXP*/ 2351#define R0900_P1_CORRELEXP 0xf422 2352#define CORRELEXP REGx(R0900_P1_CORRELEXP) 2353#define F0900_P1_CORREL_ABSEXP 0xf42200f0 2354#define F0900_P1_CORREL_EXP 0xf422000f 2355 2356/*P1_PLHMODCOD*/ 2357#define R0900_P1_PLHMODCOD 0xf424 2358#define PLHMODCOD REGx(R0900_P1_PLHMODCOD) 2359#define F0900_P1_SPECINV_DEMOD 0xf4240080 2360#define SPECINV_DEMOD FLDx(F0900_P1_SPECINV_DEMOD) 2361#define F0900_P1_PLH_MODCOD 0xf424007c 2362#define F0900_P1_PLH_TYPE 0xf4240003 2363 2364/*P1_DMDREG*/ 2365#define R0900_P1_DMDREG 0xf425 2366#define DMDREG REGx(R0900_P1_DMDREG) 2367#define F0900_P1_DECIM_PLFRAMES 0xf4250001 2368 2369/*P1_AGC2O*/ 2370#define R0900_P1_AGC2O 0xf42c 2371#define AGC2O REGx(R0900_P1_AGC2O) 2372#define F0900_P1_AGC2_COEF 0xf42c0007 2373 2374/*P1_AGC2REF*/ 2375#define R0900_P1_AGC2REF 0xf42d 2376#define AGC2REF REGx(R0900_P1_AGC2REF) 2377#define F0900_P1_AGC2_REF 0xf42d00ff 2378 2379/*P1_AGC1ADJ*/ 2380#define R0900_P1_AGC1ADJ 0xf42e 2381#define AGC1ADJ REGx(R0900_P1_AGC1ADJ) 2382#define F0900_P1_AGC1_ADJUSTED 0xf42e007f 2383 2384/*P1_AGC2I1*/ 2385#define R0900_P1_AGC2I1 0xf436 2386#define AGC2I1 REGx(R0900_P1_AGC2I1) 2387#define F0900_P1_AGC2_INTEGRATOR1 0xf43600ff 2388 2389/*P1_AGC2I0*/ 2390#define R0900_P1_AGC2I0 0xf437 2391#define AGC2I0 REGx(R0900_P1_AGC2I0) 2392#define F0900_P1_AGC2_INTEGRATOR0 0xf43700ff 2393 2394/*P1_CARCFG*/ 2395#define R0900_P1_CARCFG 0xf438 2396#define CARCFG REGx(R0900_P1_CARCFG) 2397#define F0900_P1_CFRUPLOW_AUTO 0xf4380080 2398#define F0900_P1_CFRUPLOW_TEST 0xf4380040 2399#define F0900_P1_ROTAON 0xf4380004 2400#define F0900_P1_PH_DET_ALGO 0xf4380003 2401 2402/*P1_ACLC*/ 2403#define R0900_P1_ACLC 0xf439 2404#define ACLC REGx(R0900_P1_ACLC) 2405#define F0900_P1_CAR_ALPHA_MANT 0xf4390030 2406#define F0900_P1_CAR_ALPHA_EXP 0xf439000f 2407 2408/*P1_BCLC*/ 2409#define R0900_P1_BCLC 0xf43a 2410#define BCLC REGx(R0900_P1_BCLC) 2411#define F0900_P1_CAR_BETA_MANT 0xf43a0030 2412#define F0900_P1_CAR_BETA_EXP 0xf43a000f 2413 2414/*P1_CARFREQ*/ 2415#define R0900_P1_CARFREQ 0xf43d 2416#define CARFREQ REGx(R0900_P1_CARFREQ) 2417#define F0900_P1_KC_COARSE_EXP 0xf43d00f0 2418#define F0900_P1_BETA_FREQ 0xf43d000f 2419 2420/*P1_CARHDR*/ 2421#define R0900_P1_CARHDR 0xf43e 2422#define CARHDR REGx(R0900_P1_CARHDR) 2423#define F0900_P1_K_FREQ_HDR 0xf43e00ff 2424 2425/*P1_LDT*/ 2426#define R0900_P1_LDT 0xf43f 2427#define LDT REGx(R0900_P1_LDT) 2428#define F0900_P1_CARLOCK_THRES 0xf43f01ff 2429 2430/*P1_LDT2*/ 2431#define R0900_P1_LDT2 0xf440 2432#define LDT2 REGx(R0900_P1_LDT2) 2433#define F0900_P1_CARLOCK_THRES2 0xf44001ff 2434 2435/*P1_CFRICFG*/ 2436#define R0900_P1_CFRICFG 0xf441 2437#define CFRICFG REGx(R0900_P1_CFRICFG) 2438#define F0900_P1_NEG_CFRSTEP 0xf4410001 2439 2440/*P1_CFRUP1*/ 2441#define R0900_P1_CFRUP1 0xf442 2442#define CFRUP1 REGx(R0900_P1_CFRUP1) 2443#define F0900_P1_CFR_UP1 0xf44201ff 2444#define CFR_UP1 FLDx(F0900_P1_CFR_UP1) 2445 2446/*P1_CFRUP0*/ 2447#define R0900_P1_CFRUP0 0xf443 2448#define CFRUP0 REGx(R0900_P1_CFRUP0) 2449#define F0900_P1_CFR_UP0 0xf44300ff 2450#define CFR_UP0 FLDx(F0900_P1_CFR_UP0) 2451 2452/*P1_CFRLOW1*/ 2453#define R0900_P1_CFRLOW1 0xf446 2454#define CFRLOW1 REGx(R0900_P1_CFRLOW1) 2455#define F0900_P1_CFR_LOW1 0xf44601ff 2456#define CFR_LOW1 FLDx(F0900_P1_CFR_LOW1) 2457 2458/*P1_CFRLOW0*/ 2459#define R0900_P1_CFRLOW0 0xf447 2460#define CFRLOW0 REGx(R0900_P1_CFRLOW0) 2461#define F0900_P1_CFR_LOW0 0xf44700ff 2462#define CFR_LOW0 FLDx(F0900_P1_CFR_LOW0) 2463 2464/*P1_CFRINIT1*/ 2465#define R0900_P1_CFRINIT1 0xf448 2466#define CFRINIT1 REGx(R0900_P1_CFRINIT1) 2467#define F0900_P1_CFR_INIT1 0xf44801ff 2468#define CFR_INIT1 FLDx(F0900_P1_CFR_INIT1) 2469 2470/*P1_CFRINIT0*/ 2471#define R0900_P1_CFRINIT0 0xf449 2472#define CFRINIT0 REGx(R0900_P1_CFRINIT0) 2473#define F0900_P1_CFR_INIT0 0xf44900ff 2474#define CFR_INIT0 FLDx(F0900_P1_CFR_INIT0) 2475 2476/*P1_CFRINC1*/ 2477#define R0900_P1_CFRINC1 0xf44a 2478#define CFRINC1 REGx(R0900_P1_CFRINC1) 2479#define F0900_P1_MANUAL_CFRINC 0xf44a0080 2480#define F0900_P1_CFR_INC1 0xf44a003f 2481 2482/*P1_CFRINC0*/ 2483#define R0900_P1_CFRINC0 0xf44b 2484#define CFRINC0 REGx(R0900_P1_CFRINC0) 2485#define F0900_P1_CFR_INC0 0xf44b00f8 2486 2487/*P1_CFR2*/ 2488#define R0900_P1_CFR2 0xf44c 2489#define CFR2 REGx(R0900_P1_CFR2) 2490#define F0900_P1_CAR_FREQ2 0xf44c01ff 2491#define CAR_FREQ2 FLDx(F0900_P1_CAR_FREQ2) 2492 2493/*P1_CFR1*/ 2494#define R0900_P1_CFR1 0xf44d 2495#define CFR1 REGx(R0900_P1_CFR1) 2496#define F0900_P1_CAR_FREQ1 0xf44d00ff 2497#define CAR_FREQ1 FLDx(F0900_P1_CAR_FREQ1) 2498 2499/*P1_CFR0*/ 2500#define R0900_P1_CFR0 0xf44e 2501#define CFR0 REGx(R0900_P1_CFR0) 2502#define F0900_P1_CAR_FREQ0 0xf44e00ff 2503#define CAR_FREQ0 FLDx(F0900_P1_CAR_FREQ0) 2504 2505/*P1_LDI*/ 2506#define R0900_P1_LDI 0xf44f 2507#define LDI REGx(R0900_P1_LDI) 2508#define F0900_P1_LOCK_DET_INTEGR 0xf44f01ff 2509 2510/*P1_TMGCFG*/ 2511#define R0900_P1_TMGCFG 0xf450 2512#define TMGCFG REGx(R0900_P1_TMGCFG) 2513#define F0900_P1_TMGLOCK_BETA 0xf45000c0 2514#define F0900_P1_DO_TIMING_CORR 0xf4500010 2515#define F0900_P1_TMG_MINFREQ 0xf4500003 2516 2517/*P1_RTC*/ 2518#define R0900_P1_RTC 0xf451 2519#define RTC REGx(R0900_P1_RTC) 2520#define F0900_P1_TMGALPHA_EXP 0xf45100f0 2521#define F0900_P1_TMGBETA_EXP 0xf451000f 2522 2523/*P1_RTCS2*/ 2524#define R0900_P1_RTCS2 0xf452 2525#define RTCS2 REGx(R0900_P1_RTCS2) 2526#define F0900_P1_TMGALPHAS2_EXP 0xf45200f0 2527#define F0900_P1_TMGBETAS2_EXP 0xf452000f 2528 2529/*P1_TMGTHRISE*/ 2530#define R0900_P1_TMGTHRISE 0xf453 2531#define TMGTHRISE REGx(R0900_P1_TMGTHRISE) 2532#define F0900_P1_TMGLOCK_THRISE 0xf45300ff 2533 2534/*P1_TMGTHFALL*/ 2535#define R0900_P1_TMGTHFALL 0xf454 2536#define TMGTHFALL REGx(R0900_P1_TMGTHFALL) 2537#define F0900_P1_TMGLOCK_THFALL 0xf45400ff 2538 2539/*P1_SFRUPRATIO*/ 2540#define R0900_P1_SFRUPRATIO 0xf455 2541#define SFRUPRATIO REGx(R0900_P1_SFRUPRATIO) 2542#define F0900_P1_SFR_UPRATIO 0xf45500ff 2543 2544/*P1_SFRLOWRATIO*/ 2545#define R0900_P1_SFRLOWRATIO 0xf456 2546#define F0900_P1_SFR_LOWRATIO 0xf45600ff 2547 2548/*P1_KREFTMG*/ 2549#define R0900_P1_KREFTMG 0xf458 2550#define KREFTMG REGx(R0900_P1_KREFTMG) 2551#define F0900_P1_KREF_TMG 0xf45800ff 2552 2553/*P1_SFRSTEP*/ 2554#define R0900_P1_SFRSTEP 0xf459 2555#define SFRSTEP REGx(R0900_P1_SFRSTEP) 2556#define F0900_P1_SFR_SCANSTEP 0xf45900f0 2557#define F0900_P1_SFR_CENTERSTEP 0xf459000f 2558 2559/*P1_TMGCFG2*/ 2560#define R0900_P1_TMGCFG2 0xf45a 2561#define TMGCFG2 REGx(R0900_P1_TMGCFG2) 2562#define F0900_P1_SFRRATIO_FINE 0xf45a0001 2563 2564/*P1_KREFTMG2*/ 2565#define R0900_P1_KREFTMG2 0xf45b 2566#define KREFTMG2 REGx(R0900_P1_KREFTMG2) 2567#define F0900_P1_KREF_TMG2 0xf45b00ff 2568 2569/*P1_SFRINIT1*/ 2570#define R0900_P1_SFRINIT1 0xf45e 2571#define SFRINIT1 REGx(R0900_P1_SFRINIT1) 2572#define F0900_P1_SFR_INIT1 0xf45e007f 2573 2574/*P1_SFRINIT0*/ 2575#define R0900_P1_SFRINIT0 0xf45f 2576#define SFRINIT0 REGx(R0900_P1_SFRINIT0) 2577#define F0900_P1_SFR_INIT0 0xf45f00ff 2578 2579/*P1_SFRUP1*/ 2580#define R0900_P1_SFRUP1 0xf460 2581#define SFRUP1 REGx(R0900_P1_SFRUP1) 2582#define F0900_P1_AUTO_GUP 0xf4600080 2583#define AUTO_GUP FLDx(F0900_P1_AUTO_GUP) 2584#define F0900_P1_SYMB_FREQ_UP1 0xf460007f 2585 2586/*P1_SFRUP0*/ 2587#define R0900_P1_SFRUP0 0xf461 2588#define SFRUP0 REGx(R0900_P1_SFRUP0) 2589#define F0900_P1_SYMB_FREQ_UP0 0xf46100ff 2590 2591/*P1_SFRLOW1*/ 2592#define R0900_P1_SFRLOW1 0xf462 2593#define SFRLOW1 REGx(R0900_P1_SFRLOW1) 2594#define F0900_P1_AUTO_GLOW 0xf4620080 2595#define AUTO_GLOW FLDx(F0900_P1_AUTO_GLOW) 2596#define F0900_P1_SYMB_FREQ_LOW1 0xf462007f 2597 2598/*P1_SFRLOW0*/ 2599#define R0900_P1_SFRLOW0 0xf463 2600#define SFRLOW0 REGx(R0900_P1_SFRLOW0) 2601#define F0900_P1_SYMB_FREQ_LOW0 0xf46300ff 2602 2603/*P1_SFR3*/ 2604#define R0900_P1_SFR3 0xf464 2605#define SFR3 REGx(R0900_P1_SFR3) 2606#define F0900_P1_SYMB_FREQ3 0xf46400ff 2607#define SYMB_FREQ3 FLDx(F0900_P1_SYMB_FREQ3) 2608 2609/*P1_SFR2*/ 2610#define R0900_P1_SFR2 0xf465 2611#define SFR2 REGx(R0900_P1_SFR2) 2612#define F0900_P1_SYMB_FREQ2 0xf46500ff 2613#define SYMB_FREQ2 FLDx(F0900_P1_SYMB_FREQ2) 2614 2615/*P1_SFR1*/ 2616#define R0900_P1_SFR1 0xf466 2617#define SFR1 REGx(R0900_P1_SFR1) 2618#define F0900_P1_SYMB_FREQ1 0xf46600ff 2619#define SYMB_FREQ1 FLDx(F0900_P1_SYMB_FREQ1) 2620 2621/*P1_SFR0*/ 2622#define R0900_P1_SFR0 0xf467 2623#define SFR0 REGx(R0900_P1_SFR0) 2624#define F0900_P1_SYMB_FREQ0 0xf46700ff 2625#define SYMB_FREQ0 FLDx(F0900_P1_SYMB_FREQ0) 2626 2627/*P1_TMGREG2*/ 2628#define R0900_P1_TMGREG2 0xf468 2629#define TMGREG2 REGx(R0900_P1_TMGREG2) 2630#define F0900_P1_TMGREG2 0xf46800ff 2631 2632/*P1_TMGREG1*/ 2633#define R0900_P1_TMGREG1 0xf469 2634#define TMGREG1 REGx(R0900_P1_TMGREG1) 2635#define F0900_P1_TMGREG1 0xf46900ff 2636 2637/*P1_TMGREG0*/ 2638#define R0900_P1_TMGREG0 0xf46a 2639#define TMGREG0 REGx(R0900_P1_TMGREG0) 2640#define F0900_P1_TMGREG0 0xf46a00ff 2641 2642/*P1_TMGLOCK1*/ 2643#define R0900_P1_TMGLOCK1 0xf46b 2644#define TMGLOCK1 REGx(R0900_P1_TMGLOCK1) 2645#define F0900_P1_TMGLOCK_LEVEL1 0xf46b01ff 2646 2647/*P1_TMGLOCK0*/ 2648#define R0900_P1_TMGLOCK0 0xf46c 2649#define TMGLOCK0 REGx(R0900_P1_TMGLOCK0) 2650#define F0900_P1_TMGLOCK_LEVEL0 0xf46c00ff 2651 2652/*P1_TMGOBS*/ 2653#define R0900_P1_TMGOBS 0xf46d 2654#define TMGOBS REGx(R0900_P1_TMGOBS) 2655#define F0900_P1_ROLLOFF_STATUS 0xf46d00c0 2656#define ROLLOFF_STATUS FLDx(F0900_P1_ROLLOFF_STATUS) 2657 2658/*P1_EQUALCFG*/ 2659#define R0900_P1_EQUALCFG 0xf46f 2660#define EQUALCFG REGx(R0900_P1_EQUALCFG) 2661#define F0900_P1_EQUAL_ON 0xf46f0040 2662#define F0900_P1_MU_EQUALDFE 0xf46f0007 2663 2664/*P1_EQUAI1*/ 2665#define R0900_P1_EQUAI1 0xf470 2666#define EQUAI1 REGx(R0900_P1_EQUAI1) 2667#define F0900_P1_EQUA_ACCI1 0xf47001ff 2668 2669/*P1_EQUAQ1*/ 2670#define R0900_P1_EQUAQ1 0xf471 2671#define EQUAQ1 REGx(R0900_P1_EQUAQ1) 2672#define F0900_P1_EQUA_ACCQ1 0xf47101ff 2673 2674/*P1_EQUAI2*/ 2675#define R0900_P1_EQUAI2 0xf472 2676#define EQUAI2 REGx(R0900_P1_EQUAI2) 2677#define F0900_P1_EQUA_ACCI2 0xf47201ff 2678 2679/*P1_EQUAQ2*/ 2680#define R0900_P1_EQUAQ2 0xf473 2681#define EQUAQ2 REGx(R0900_P1_EQUAQ2) 2682#define F0900_P1_EQUA_ACCQ2 0xf47301ff 2683 2684/*P1_EQUAI3*/ 2685#define R0900_P1_EQUAI3 0xf474 2686#define EQUAI3 REGx(R0900_P1_EQUAI3) 2687#define F0900_P1_EQUA_ACCI3 0xf47401ff 2688 2689/*P1_EQUAQ3*/ 2690#define R0900_P1_EQUAQ3 0xf475 2691#define EQUAQ3 REGx(R0900_P1_EQUAQ3) 2692#define F0900_P1_EQUA_ACCQ3 0xf47501ff 2693 2694/*P1_EQUAI4*/ 2695#define R0900_P1_EQUAI4 0xf476 2696#define EQUAI4 REGx(R0900_P1_EQUAI4) 2697#define F0900_P1_EQUA_ACCI4 0xf47601ff 2698 2699/*P1_EQUAQ4*/ 2700#define R0900_P1_EQUAQ4 0xf477 2701#define EQUAQ4 REGx(R0900_P1_EQUAQ4) 2702#define F0900_P1_EQUA_ACCQ4 0xf47701ff 2703 2704/*P1_EQUAI5*/ 2705#define R0900_P1_EQUAI5 0xf478 2706#define EQUAI5 REGx(R0900_P1_EQUAI5) 2707#define F0900_P1_EQUA_ACCI5 0xf47801ff 2708 2709/*P1_EQUAQ5*/ 2710#define R0900_P1_EQUAQ5 0xf479 2711#define EQUAQ5 REGx(R0900_P1_EQUAQ5) 2712#define F0900_P1_EQUA_ACCQ5 0xf47901ff 2713 2714/*P1_EQUAI6*/ 2715#define R0900_P1_EQUAI6 0xf47a 2716#define EQUAI6 REGx(R0900_P1_EQUAI6) 2717#define F0900_P1_EQUA_ACCI6 0xf47a01ff 2718 2719/*P1_EQUAQ6*/ 2720#define R0900_P1_EQUAQ6 0xf47b 2721#define EQUAQ6 REGx(R0900_P1_EQUAQ6) 2722#define F0900_P1_EQUA_ACCQ6 0xf47b01ff 2723 2724/*P1_EQUAI7*/ 2725#define R0900_P1_EQUAI7 0xf47c 2726#define EQUAI7 REGx(R0900_P1_EQUAI7) 2727#define F0900_P1_EQUA_ACCI7 0xf47c01ff 2728 2729/*P1_EQUAQ7*/ 2730#define R0900_P1_EQUAQ7 0xf47d 2731#define EQUAQ7 REGx(R0900_P1_EQUAQ7) 2732#define F0900_P1_EQUA_ACCQ7 0xf47d01ff 2733 2734/*P1_EQUAI8*/ 2735#define R0900_P1_EQUAI8 0xf47e 2736#define EQUAI8 REGx(R0900_P1_EQUAI8) 2737#define F0900_P1_EQUA_ACCI8 0xf47e01ff 2738 2739/*P1_EQUAQ8*/ 2740#define R0900_P1_EQUAQ8 0xf47f 2741#define EQUAQ8 REGx(R0900_P1_EQUAQ8) 2742#define F0900_P1_EQUA_ACCQ8 0xf47f01ff 2743 2744/*P1_NNOSDATAT1*/ 2745#define R0900_P1_NNOSDATAT1 0xf480 2746#define NNOSDATAT1 REGx(R0900_P1_NNOSDATAT1) 2747#define F0900_P1_NOSDATAT_NORMED1 0xf48000ff 2748#define NOSDATAT_NORMED1 FLDx(F0900_P1_NOSDATAT_NORMED1) 2749 2750/*P1_NNOSDATAT0*/ 2751#define R0900_P1_NNOSDATAT0 0xf481 2752#define NNOSDATAT0 REGx(R0900_P1_NNOSDATAT0) 2753#define F0900_P1_NOSDATAT_NORMED0 0xf48100ff 2754#define NOSDATAT_NORMED0 FLDx(F0900_P1_NOSDATAT_NORMED0) 2755 2756/*P1_NNOSDATA1*/ 2757#define R0900_P1_NNOSDATA1 0xf482 2758#define NNOSDATA1 REGx(R0900_P1_NNOSDATA1) 2759#define F0900_P1_NOSDATA_NORMED1 0xf48200ff 2760 2761/*P1_NNOSDATA0*/ 2762#define R0900_P1_NNOSDATA0 0xf483 2763#define NNOSDATA0 REGx(R0900_P1_NNOSDATA0) 2764#define F0900_P1_NOSDATA_NORMED0 0xf48300ff 2765 2766/*P1_NNOSPLHT1*/ 2767#define R0900_P1_NNOSPLHT1 0xf484 2768#define NNOSPLHT1 REGx(R0900_P1_NNOSPLHT1) 2769#define F0900_P1_NOSPLHT_NORMED1 0xf48400ff 2770#define NOSPLHT_NORMED1 FLDx(F0900_P1_NOSPLHT_NORMED1) 2771 2772/*P1_NNOSPLHT0*/ 2773#define R0900_P1_NNOSPLHT0 0xf485 2774#define NNOSPLHT0 REGx(R0900_P1_NNOSPLHT0) 2775#define F0900_P1_NOSPLHT_NORMED0 0xf48500ff 2776#define NOSPLHT_NORMED0 FLDx(F0900_P1_NOSPLHT_NORMED0) 2777 2778/*P1_NNOSPLH1*/ 2779#define R0900_P1_NNOSPLH1 0xf486 2780#define NNOSPLH1 REGx(R0900_P1_NNOSPLH1) 2781#define F0900_P1_NOSPLH_NORMED1 0xf48600ff 2782 2783/*P1_NNOSPLH0*/ 2784#define R0900_P1_NNOSPLH0 0xf487 2785#define NNOSPLH0 REGx(R0900_P1_NNOSPLH0) 2786#define F0900_P1_NOSPLH_NORMED0 0xf48700ff 2787 2788/*P1_NOSDATAT1*/ 2789#define R0900_P1_NOSDATAT1 0xf488 2790#define NOSDATAT1 REGx(R0900_P1_NOSDATAT1) 2791#define F0900_P1_NOSDATAT_UNNORMED1 0xf48800ff 2792 2793/*P1_NOSDATAT0*/ 2794#define R0900_P1_NOSDATAT0 0xf489 2795#define NOSDATAT0 REGx(R0900_P1_NOSDATAT0) 2796#define F0900_P1_NOSDATAT_UNNORMED0 0xf48900ff 2797 2798/*P1_NOSDATA1*/ 2799#define R0900_P1_NOSDATA1 0xf48a 2800#define NOSDATA1 REGx(R0900_P1_NOSDATA1) 2801#define F0900_P1_NOSDATA_UNNORMED1 0xf48a00ff 2802 2803/*P1_NOSDATA0*/ 2804#define R0900_P1_NOSDATA0 0xf48b 2805#define NOSDATA0 REGx(R0900_P1_NOSDATA0) 2806#define F0900_P1_NOSDATA_UNNORMED0 0xf48b00ff 2807 2808/*P1_NOSPLHT1*/ 2809#define R0900_P1_NOSPLHT1 0xf48c 2810#define NOSPLHT1 REGx(R0900_P1_NOSPLHT1) 2811#define F0900_P1_NOSPLHT_UNNORMED1 0xf48c00ff 2812 2813/*P1_NOSPLHT0*/ 2814#define R0900_P1_NOSPLHT0 0xf48d 2815#define NOSPLHT0 REGx(R0900_P1_NOSPLHT0) 2816#define F0900_P1_NOSPLHT_UNNORMED0 0xf48d00ff 2817 2818/*P1_NOSPLH1*/ 2819#define R0900_P1_NOSPLH1 0xf48e 2820#define NOSPLH1 REGx(R0900_P1_NOSPLH1) 2821#define F0900_P1_NOSPLH_UNNORMED1 0xf48e00ff 2822 2823/*P1_NOSPLH0*/ 2824#define R0900_P1_NOSPLH0 0xf48f 2825#define NOSPLH0 REGx(R0900_P1_NOSPLH0) 2826#define F0900_P1_NOSPLH_UNNORMED0 0xf48f00ff 2827 2828/*P1_CAR2CFG*/ 2829#define R0900_P1_CAR2CFG 0xf490 2830#define CAR2CFG REGx(R0900_P1_CAR2CFG) 2831#define F0900_P1_CARRIER3_DISABLE 0xf4900040 2832#define F0900_P1_ROTA2ON 0xf4900004 2833#define F0900_P1_PH_DET_ALGO2 0xf4900003 2834 2835/*P1_CFR2CFR1*/ 2836#define R0900_P1_CFR2CFR1 0xf491 2837#define CFR2CFR1 REGx(R0900_P1_CFR2CFR1) 2838#define F0900_P1_CFR2TOCFR1_DVBS1 0xf49100c0 2839#define F0900_P1_EN_S2CAR2CENTER 0xf4910020 2840#define F0900_P1_DIS_BCHERRCFR2 0xf4910010 2841#define F0900_P1_CFR2TOCFR1_BETA 0xf4910007 2842 2843/*P1_CFR22*/ 2844#define R0900_P1_CFR22 0xf493 2845#define CFR22 REGx(R0900_P1_CFR22) 2846#define F0900_P1_CAR2_FREQ2 0xf49301ff 2847 2848/*P1_CFR21*/ 2849#define R0900_P1_CFR21 0xf494 2850#define CFR21 REGx(R0900_P1_CFR21) 2851#define F0900_P1_CAR2_FREQ1 0xf49400ff 2852 2853/*P1_CFR20*/ 2854#define R0900_P1_CFR20 0xf495 2855#define CFR20 REGx(R0900_P1_CFR20) 2856#define F0900_P1_CAR2_FREQ0 0xf49500ff 2857 2858/*P1_ACLC2S2Q*/ 2859#define R0900_P1_ACLC2S2Q 0xf497 2860#define ACLC2S2Q REGx(R0900_P1_ACLC2S2Q) 2861#define F0900_P1_ENAB_SPSKSYMB 0xf4970080 2862#define F0900_P1_CAR2S2_Q_ALPH_M 0xf4970030 2863#define F0900_P1_CAR2S2_Q_ALPH_E 0xf497000f 2864 2865/*P1_ACLC2S28*/ 2866#define R0900_P1_ACLC2S28 0xf498 2867#define ACLC2S28 REGx(R0900_P1_ACLC2S28) 2868#define F0900_P1_OLDI3Q_MODE 0xf4980080 2869#define F0900_P1_CAR2S2_8_ALPH_M 0xf4980030 2870#define F0900_P1_CAR2S2_8_ALPH_E 0xf498000f 2871 2872/*P1_ACLC2S216A*/ 2873#define R0900_P1_ACLC2S216A 0xf499 2874#define ACLC2S216A REGx(R0900_P1_ACLC2S216A) 2875#define F0900_P1_DIS_C3STOPA2 0xf4990080 2876#define F0900_P1_CAR2S2_16ADERAT 0xf4990040 2877#define F0900_P1_CAR2S2_16A_ALPH_M 0xf4990030 2878#define F0900_P1_CAR2S2_16A_ALPH_E 0xf499000f 2879 2880/*P1_ACLC2S232A*/ 2881#define R0900_P1_ACLC2S232A 0xf49a 2882#define ACLC2S232A REGx(R0900_P1_ACLC2S232A) 2883#define F0900_P1_CAR2S2_32ADERAT 0xf49a0040 2884#define F0900_P1_CAR2S2_32A_ALPH_M 0xf49a0030 2885#define F0900_P1_CAR2S2_32A_ALPH_E 0xf49a000f 2886 2887/*P1_BCLC2S2Q*/ 2888#define R0900_P1_BCLC2S2Q 0xf49c 2889#define BCLC2S2Q REGx(R0900_P1_BCLC2S2Q) 2890#define F0900_P1_CAR2S2_Q_BETA_M 0xf49c0030 2891#define F0900_P1_CAR2S2_Q_BETA_E 0xf49c000f 2892 2893/*P1_BCLC2S28*/ 2894#define R0900_P1_BCLC2S28 0xf49d 2895#define BCLC2S28 REGx(R0900_P1_BCLC2S28) 2896#define F0900_P1_CAR2S2_8_BETA_M 0xf49d0030 2897#define F0900_P1_CAR2S2_8_BETA_E 0xf49d000f 2898 2899/*P1_BCLC2S216A*/ 2900#define R0900_P1_BCLC2S216A 0xf49e 2901#define BCLC2S216A REGx(R0900_P1_BCLC2S216A) 2902 2903/*P1_BCLC2S232A*/ 2904#define R0900_P1_BCLC2S232A 0xf49f 2905#define BCLC2S232A REGx(R0900_P1_BCLC2S232A) 2906 2907/*P1_PLROOT2*/ 2908#define R0900_P1_PLROOT2 0xf4ac 2909#define PLROOT2 REGx(R0900_P1_PLROOT2) 2910#define F0900_P1_PLSCRAMB_MODE 0xf4ac000c 2911#define F0900_P1_PLSCRAMB_ROOT2 0xf4ac0003 2912 2913/*P1_PLROOT1*/ 2914#define R0900_P1_PLROOT1 0xf4ad 2915#define PLROOT1 REGx(R0900_P1_PLROOT1) 2916#define F0900_P1_PLSCRAMB_ROOT1 0xf4ad00ff 2917 2918/*P1_PLROOT0*/ 2919#define R0900_P1_PLROOT0 0xf4ae 2920#define PLROOT0 REGx(R0900_P1_PLROOT0) 2921#define F0900_P1_PLSCRAMB_ROOT0 0xf4ae00ff 2922 2923/*P1_MODCODLST0*/ 2924#define R0900_P1_MODCODLST0 0xf4b0 2925#define MODCODLST0 REGx(R0900_P1_MODCODLST0) 2926 2927/*P1_MODCODLST1*/ 2928#define R0900_P1_MODCODLST1 0xf4b1 2929#define MODCODLST1 REGx(R0900_P1_MODCODLST1) 2930#define F0900_P1_DIS_MODCOD29 0xf4b100f0 2931#define F0900_P1_DIS_32PSK_9_10 0xf4b1000f 2932 2933/*P1_MODCODLST2*/ 2934#define R0900_P1_MODCODLST2 0xf4b2 2935#define MODCODLST2 REGx(R0900_P1_MODCODLST2) 2936#define F0900_P1_DIS_32PSK_8_9 0xf4b200f0 2937#define F0900_P1_DIS_32PSK_5_6 0xf4b2000f 2938 2939/*P1_MODCODLST3*/ 2940#define R0900_P1_MODCODLST3 0xf4b3 2941#define MODCODLST3 REGx(R0900_P1_MODCODLST3) 2942#define F0900_P1_DIS_32PSK_4_5 0xf4b300f0 2943#define F0900_P1_DIS_32PSK_3_4 0xf4b3000f 2944 2945/*P1_MODCODLST4*/ 2946#define R0900_P1_MODCODLST4 0xf4b4 2947#define MODCODLST4 REGx(R0900_P1_MODCODLST4) 2948#define F0900_P1_DIS_16PSK_9_10 0xf4b400f0 2949#define F0900_P1_DIS_16PSK_8_9 0xf4b4000f 2950 2951/*P1_MODCODLST5*/ 2952#define R0900_P1_MODCODLST5 0xf4b5 2953#define MODCODLST5 REGx(R0900_P1_MODCODLST5) 2954#define F0900_P1_DIS_16PSK_5_6 0xf4b500f0 2955#define F0900_P1_DIS_16PSK_4_5 0xf4b5000f 2956 2957/*P1_MODCODLST6*/ 2958#define R0900_P1_MODCODLST6 0xf4b6 2959#define MODCODLST6 REGx(R0900_P1_MODCODLST6) 2960#define F0900_P1_DIS_16PSK_3_4 0xf4b600f0 2961#define F0900_P1_DIS_16PSK_2_3 0xf4b6000f 2962 2963/*P1_MODCODLST7*/ 2964#define R0900_P1_MODCODLST7 0xf4b7 2965#define MODCODLST7 REGx(R0900_P1_MODCODLST7) 2966#define F0900_P1_DIS_8P_9_10 0xf4b700f0 2967#define F0900_P1_DIS_8P_8_9 0xf4b7000f 2968 2969/*P1_MODCODLST8*/ 2970#define R0900_P1_MODCODLST8 0xf4b8 2971#define MODCODLST8 REGx(R0900_P1_MODCODLST8) 2972#define F0900_P1_DIS_8P_5_6 0xf4b800f0 2973#define F0900_P1_DIS_8P_3_4 0xf4b8000f 2974 2975/*P1_MODCODLST9*/ 2976#define R0900_P1_MODCODLST9 0xf4b9 2977#define MODCODLST9 REGx(R0900_P1_MODCODLST9) 2978#define F0900_P1_DIS_8P_2_3 0xf4b900f0 2979#define F0900_P1_DIS_8P_3_5 0xf4b9000f 2980 2981/*P1_MODCODLSTA*/ 2982#define R0900_P1_MODCODLSTA 0xf4ba 2983#define MODCODLSTA REGx(R0900_P1_MODCODLSTA) 2984#define F0900_P1_DIS_QP_9_10 0xf4ba00f0 2985#define F0900_P1_DIS_QP_8_9 0xf4ba000f 2986 2987/*P1_MODCODLSTB*/ 2988#define R0900_P1_MODCODLSTB 0xf4bb 2989#define MODCODLSTB REGx(R0900_P1_MODCODLSTB) 2990#define F0900_P1_DIS_QP_5_6 0xf4bb00f0 2991#define F0900_P1_DIS_QP_4_5 0xf4bb000f 2992 2993/*P1_MODCODLSTC*/ 2994#define R0900_P1_MODCODLSTC 0xf4bc 2995#define MODCODLSTC REGx(R0900_P1_MODCODLSTC) 2996#define F0900_P1_DIS_QP_3_4 0xf4bc00f0 2997#define F0900_P1_DIS_QP_2_3 0xf4bc000f 2998 2999/*P1_MODCODLSTD*/ 3000#define R0900_P1_MODCODLSTD 0xf4bd 3001#define MODCODLSTD REGx(R0900_P1_MODCODLSTD) 3002#define F0900_P1_DIS_QP_3_5 0xf4bd00f0 3003#define F0900_P1_DIS_QP_1_2 0xf4bd000f 3004 3005/*P1_MODCODLSTE*/ 3006#define R0900_P1_MODCODLSTE 0xf4be 3007#define MODCODLSTE REGx(R0900_P1_MODCODLSTE) 3008#define F0900_P1_DIS_QP_2_5 0xf4be00f0 3009#define F0900_P1_DIS_QP_1_3 0xf4be000f 3010 3011/*P1_MODCODLSTF*/ 3012#define R0900_P1_MODCODLSTF 0xf4bf 3013#define MODCODLSTF REGx(R0900_P1_MODCODLSTF) 3014#define F0900_P1_DIS_QP_1_4 0xf4bf00f0 3015 3016/*P1_GAUSSR0*/ 3017#define R0900_P1_GAUSSR0 0xf4c0 3018#define GAUSSR0 REGx(R0900_P1_GAUSSR0) 3019#define F0900_P1_EN_CCIMODE 0xf4c00080 3020#define F0900_P1_R0_GAUSSIEN 0xf4c0007f 3021 3022/*P1_CCIR0*/ 3023#define R0900_P1_CCIR0 0xf4c1 3024#define CCIR0 REGx(R0900_P1_CCIR0) 3025#define F0900_P1_CCIDETECT_PLHONLY 0xf4c10080 3026#define F0900_P1_R0_CCI 0xf4c1007f 3027 3028/*P1_CCIQUANT*/ 3029#define R0900_P1_CCIQUANT 0xf4c2 3030#define CCIQUANT REGx(R0900_P1_CCIQUANT) 3031#define F0900_P1_CCI_BETA 0xf4c200e0 3032#define F0900_P1_CCI_QUANT 0xf4c2001f 3033 3034/*P1_CCITHRES*/ 3035#define R0900_P1_CCITHRES 0xf4c3 3036#define CCITHRES REGx(R0900_P1_CCITHRES) 3037#define F0900_P1_CCI_THRESHOLD 0xf4c300ff 3038 3039/*P1_CCIACC*/ 3040#define R0900_P1_CCIACC 0xf4c4 3041#define CCIACC REGx(R0900_P1_CCIACC) 3042#define F0900_P1_CCI_VALUE 0xf4c400ff 3043 3044/*P1_DMDRESCFG*/ 3045#define R0900_P1_DMDRESCFG 0xf4c6 3046#define DMDRESCFG REGx(R0900_P1_DMDRESCFG) 3047#define F0900_P1_DMDRES_RESET 0xf4c60080 3048#define F0900_P1_DMDRES_STRALL 0xf4c60008 3049#define F0900_P1_DMDRES_NEWONLY 0xf4c60004 3050#define F0900_P1_DMDRES_NOSTORE 0xf4c60002 3051 3052/*P1_DMDRESADR*/ 3053#define R0900_P1_DMDRESADR 0xf4c7 3054#define DMDRESADR REGx(R0900_P1_DMDRESADR) 3055#define F0900_P1_DMDRES_VALIDCFR 0xf4c70040 3056#define F0900_P1_DMDRES_MEMFULL 0xf4c70030 3057#define F0900_P1_DMDRES_RESNBR 0xf4c7000f 3058 3059/*P1_DMDRESDATA7*/ 3060#define R0900_P1_DMDRESDATA7 0xf4c8 3061#define F0900_P1_DMDRES_DATA7 0xf4c800ff 3062 3063/*P1_DMDRESDATA6*/ 3064#define R0900_P1_DMDRESDATA6 0xf4c9 3065#define F0900_P1_DMDRES_DATA6 0xf4c900ff 3066 3067/*P1_DMDRESDATA5*/ 3068#define R0900_P1_DMDRESDATA5 0xf4ca 3069#define F0900_P1_DMDRES_DATA5 0xf4ca00ff 3070 3071/*P1_DMDRESDATA4*/ 3072#define R0900_P1_DMDRESDATA4 0xf4cb 3073#define F0900_P1_DMDRES_DATA4 0xf4cb00ff 3074 3075/*P1_DMDRESDATA3*/ 3076#define R0900_P1_DMDRESDATA3 0xf4cc 3077#define F0900_P1_DMDRES_DATA3 0xf4cc00ff 3078 3079/*P1_DMDRESDATA2*/ 3080#define R0900_P1_DMDRESDATA2 0xf4cd 3081#define F0900_P1_DMDRES_DATA2 0xf4cd00ff 3082 3083/*P1_DMDRESDATA1*/ 3084#define R0900_P1_DMDRESDATA1 0xf4ce 3085#define F0900_P1_DMDRES_DATA1 0xf4ce00ff 3086 3087/*P1_DMDRESDATA0*/ 3088#define R0900_P1_DMDRESDATA0 0xf4cf 3089#define F0900_P1_DMDRES_DATA0 0xf4cf00ff 3090 3091/*P1_FFEI1*/ 3092#define R0900_P1_FFEI1 0xf4d0 3093#define FFEI1 REGx(R0900_P1_FFEI1) 3094#define F0900_P1_FFE_ACCI1 0xf4d001ff 3095 3096/*P1_FFEQ1*/ 3097#define R0900_P1_FFEQ1 0xf4d1 3098#define FFEQ1 REGx(R0900_P1_FFEQ1) 3099#define F0900_P1_FFE_ACCQ1 0xf4d101ff 3100 3101/*P1_FFEI2*/ 3102#define R0900_P1_FFEI2 0xf4d2 3103#define FFEI2 REGx(R0900_P1_FFEI2) 3104#define F0900_P1_FFE_ACCI2 0xf4d201ff 3105 3106/*P1_FFEQ2*/ 3107#define R0900_P1_FFEQ2 0xf4d3 3108#define FFEQ2 REGx(R0900_P1_FFEQ2) 3109#define F0900_P1_FFE_ACCQ2 0xf4d301ff 3110 3111/*P1_FFEI3*/ 3112#define R0900_P1_FFEI3 0xf4d4 3113#define FFEI3 REGx(R0900_P1_FFEI3) 3114#define F0900_P1_FFE_ACCI3 0xf4d401ff 3115 3116/*P1_FFEQ3*/ 3117#define R0900_P1_FFEQ3 0xf4d5 3118#define FFEQ3 REGx(R0900_P1_FFEQ3) 3119#define F0900_P1_FFE_ACCQ3 0xf4d501ff 3120 3121/*P1_FFEI4*/ 3122#define R0900_P1_FFEI4 0xf4d6 3123#define FFEI4 REGx(R0900_P1_FFEI4) 3124#define F0900_P1_FFE_ACCI4 0xf4d601ff 3125 3126/*P1_FFEQ4*/ 3127#define R0900_P1_FFEQ4 0xf4d7 3128#define FFEQ4 REGx(R0900_P1_FFEQ4) 3129#define F0900_P1_FFE_ACCQ4 0xf4d701ff 3130 3131/*P1_FFECFG*/ 3132#define R0900_P1_FFECFG 0xf4d8 3133#define FFECFG REGx(R0900_P1_FFECFG) 3134#define F0900_P1_EQUALFFE_ON 0xf4d80040 3135#define F0900_P1_MU_EQUALFFE 0xf4d80007 3136 3137/*P1_TNRCFG*/ 3138#define R0900_P1_TNRCFG 0xf4e0 3139#define TNRCFG REGx(R0900_P1_TNRCFG) 3140#define F0900_P1_TUN_ACKFAIL 0xf4e00080 3141#define F0900_P1_TUN_TYPE 0xf4e00070 3142#define F0900_P1_TUN_SECSTOP 0xf4e00008 3143#define F0900_P1_TUN_VCOSRCH 0xf4e00004 3144#define F0900_P1_TUN_MADDRESS 0xf4e00003 3145 3146/*P1_TNRCFG2*/ 3147#define R0900_P1_TNRCFG2 0xf4e1 3148#define TNRCFG2 REGx(R0900_P1_TNRCFG2) 3149#define F0900_P1_TUN_IQSWAP 0xf4e10080 3150#define F0900_P1_DIS_BWCALC 0xf4e10004 3151#define F0900_P1_SHORT_WAITSTATES 0xf4e10002 3152 3153/*P1_TNRXTAL*/ 3154#define R0900_P1_TNRXTAL 0xf4e4 3155#define TNRXTAL REGx(R0900_P1_TNRXTAL) 3156#define F0900_P1_TUN_XTALFREQ 0xf4e4001f 3157 3158/*P1_TNRSTEPS*/ 3159#define R0900_P1_TNRSTEPS 0xf4e7 3160#define TNRSTEPS REGx(R0900_P1_TNRSTEPS) 3161#define F0900_P1_TUNER_BW0P125 0xf4e70080 3162#define F0900_P1_BWINC_OFFSET 0xf4e70170 3163#define F0900_P1_SOFTSTEP_RNG 0xf4e70008 3164#define F0900_P1_TUN_BWOFFSET 0xf4e70007 3165 3166/*P1_TNRGAIN*/ 3167#define R0900_P1_TNRGAIN 0xf4e8 3168#define TNRGAIN REGx(R0900_P1_TNRGAIN) 3169#define F0900_P1_TUN_KDIVEN 0xf4e800c0 3170#define F0900_P1_STB6X00_OCK 0xf4e80030 3171#define F0900_P1_TUN_GAIN 0xf4e8000f 3172 3173/*P1_TNRRF1*/ 3174#define R0900_P1_TNRRF1 0xf4e9 3175#define TNRRF1 REGx(R0900_P1_TNRRF1) 3176#define F0900_P1_TUN_RFFREQ2 0xf4e900ff 3177#define TUN_RFFREQ2 FLDx(F0900_P1_TUN_RFFREQ2) 3178 3179/*P1_TNRRF0*/ 3180#define R0900_P1_TNRRF0 0xf4ea 3181#define TNRRF0 REGx(R0900_P1_TNRRF0) 3182#define F0900_P1_TUN_RFFREQ1 0xf4ea00ff 3183#define TUN_RFFREQ1 FLDx(F0900_P1_TUN_RFFREQ1) 3184 3185/*P1_TNRBW*/ 3186#define R0900_P1_TNRBW 0xf4eb 3187#define TNRBW REGx(R0900_P1_TNRBW) 3188#define F0900_P1_TUN_RFFREQ0 0xf4eb00c0 3189#define TUN_RFFREQ0 FLDx(F0900_P1_TUN_RFFREQ0) 3190#define F0900_P1_TUN_BW 0xf4eb003f 3191#define TUN_BW FLDx(F0900_P1_TUN_BW) 3192 3193/*P1_TNRADJ*/ 3194#define R0900_P1_TNRADJ 0xf4ec 3195#define TNRADJ REGx(R0900_P1_TNRADJ) 3196#define F0900_P1_STB61X0_CALTIME 0xf4ec0040 3197 3198/*P1_TNRCTL2*/ 3199#define R0900_P1_TNRCTL2 0xf4ed 3200#define TNRCTL2 REGx(R0900_P1_TNRCTL2) 3201#define F0900_P1_STB61X0_RCCKOFF 0xf4ed0080 3202#define F0900_P1_STB61X0_ICP_SDOFF 0xf4ed0040 3203#define F0900_P1_STB61X0_DCLOOPOFF 0xf4ed0020 3204#define F0900_P1_STB61X0_REFOUTSEL 0xf4ed0010 3205#define F0900_P1_STB61X0_CALOFF 0xf4ed0008 3206#define F0900_P1_STB6XX0_LPT_BEN 0xf4ed0004 3207#define F0900_P1_STB6XX0_RX_OSCP 0xf4ed0002 3208#define F0900_P1_STB6XX0_SYN 0xf4ed0001 3209 3210/*P1_TNRCFG3*/ 3211#define R0900_P1_TNRCFG3 0xf4ee 3212#define TNRCFG3 REGx(R0900_P1_TNRCFG3) 3213#define F0900_P1_TUN_PLLFREQ 0xf4ee001c 3214#define F0900_P1_TUN_I2CFREQ_MODE 0xf4ee0003 3215 3216/*P1_TNRLAUNCH*/ 3217#define R0900_P1_TNRLAUNCH 0xf4f0 3218#define TNRLAUNCH REGx(R0900_P1_TNRLAUNCH) 3219 3220/*P1_TNRLD*/ 3221#define R0900_P1_TNRLD 0xf4f0 3222#define TNRLD REGx(R0900_P1_TNRLD) 3223#define F0900_P1_TUNLD_VCOING 0xf4f00080 3224#define F0900_P1_TUN_REG1FAIL 0xf4f00040 3225#define F0900_P1_TUN_REG2FAIL 0xf4f00020 3226#define F0900_P1_TUN_REG3FAIL 0xf4f00010 3227#define F0900_P1_TUN_REG4FAIL 0xf4f00008 3228#define F0900_P1_TUN_REG5FAIL 0xf4f00004 3229#define F0900_P1_TUN_BWING 0xf4f00002 3230#define F0900_P1_TUN_LOCKED 0xf4f00001 3231 3232/*P1_TNROBSL*/ 3233#define R0900_P1_TNROBSL 0xf4f6 3234#define TNROBSL REGx(R0900_P1_TNROBSL) 3235#define F0900_P1_TUN_I2CABORTED 0xf4f60080 3236#define F0900_P1_TUN_LPEN 0xf4f60040 3237#define F0900_P1_TUN_FCCK 0xf4f60020 3238#define F0900_P1_TUN_I2CLOCKED 0xf4f60010 3239#define F0900_P1_TUN_PROGDONE 0xf4f6000c 3240#define F0900_P1_TUN_RFRESTE1 0xf4f60003 3241#define TUN_RFRESTE1 FLDx(F0900_P1_TUN_RFRESTE1) 3242 3243/*P1_TNRRESTE*/ 3244#define R0900_P1_TNRRESTE 0xf4f7 3245#define TNRRESTE REGx(R0900_P1_TNRRESTE) 3246#define F0900_P1_TUN_RFRESTE0 0xf4f700ff 3247#define TUN_RFRESTE0 FLDx(F0900_P1_TUN_RFRESTE0) 3248 3249/*P1_SMAPCOEF7*/ 3250#define R0900_P1_SMAPCOEF7 0xf500 3251#define SMAPCOEF7 REGx(R0900_P1_SMAPCOEF7) 3252#define F0900_P1_DIS_QSCALE 0xf5000080 3253#define F0900_P1_SMAPCOEF_Q_LLR12 0xf500017f 3254 3255/*P1_SMAPCOEF6*/ 3256#define R0900_P1_SMAPCOEF6 0xf501 3257#define SMAPCOEF6 REGx(R0900_P1_SMAPCOEF6) 3258#define F0900_P1_ADJ_8PSKLLR1 0xf5010004 3259#define F0900_P1_OLD_8PSKLLR1 0xf5010002 3260#define F0900_P1_DIS_AB8PSK 0xf5010001 3261 3262/*P1_SMAPCOEF5*/ 3263#define R0900_P1_SMAPCOEF5 0xf502 3264#define SMAPCOEF5 REGx(R0900_P1_SMAPCOEF5) 3265#define F0900_P1_DIS_8SCALE 0xf5020080 3266#define F0900_P1_SMAPCOEF_8P_LLR23 0xf502017f 3267 3268/*P1_NCO2MAX1*/ 3269#define R0900_P1_NCO2MAX1 0xf514 3270#define NCO2MAX1 REGx(R0900_P1_NCO2MAX1) 3271#define F0900_P1_TETA2_MAXVABS1 0xf51400ff 3272 3273/*P1_NCO2MAX0*/ 3274#define R0900_P1_NCO2MAX0 0xf515 3275#define NCO2MAX0 REGx(R0900_P1_NCO2MAX0) 3276#define F0900_P1_TETA2_MAXVABS0 0xf51500ff 3277 3278/*P1_NCO2FR1*/ 3279#define R0900_P1_NCO2FR1 0xf516 3280#define NCO2FR1 REGx(R0900_P1_NCO2FR1) 3281#define F0900_P1_NCO2FINAL_ANGLE1 0xf51600ff 3282 3283/*P1_NCO2FR0*/ 3284#define R0900_P1_NCO2FR0 0xf517 3285#define NCO2FR0 REGx(R0900_P1_NCO2FR0) 3286#define F0900_P1_NCO2FINAL_ANGLE0 0xf51700ff 3287 3288/*P1_CFR2AVRGE1*/ 3289#define R0900_P1_CFR2AVRGE1 0xf518 3290#define CFR2AVRGE1 REGx(R0900_P1_CFR2AVRGE1) 3291#define F0900_P1_I2C_CFR2AVERAGE1 0xf51800ff 3292 3293/*P1_CFR2AVRGE0*/ 3294#define R0900_P1_CFR2AVRGE0 0xf519 3295#define CFR2AVRGE0 REGx(R0900_P1_CFR2AVRGE0) 3296#define F0900_P1_I2C_CFR2AVERAGE0 0xf51900ff 3297 3298/*P1_DMDPLHSTAT*/ 3299#define R0900_P1_DMDPLHSTAT 0xf520 3300#define DMDPLHSTAT REGx(R0900_P1_DMDPLHSTAT) 3301#define F0900_P1_PLH_STATISTIC 0xf52000ff 3302 3303/*P1_LOCKTIME3*/ 3304#define R0900_P1_LOCKTIME3 0xf522 3305#define LOCKTIME3 REGx(R0900_P1_LOCKTIME3) 3306#define F0900_P1_DEMOD_LOCKTIME3 0xf52200ff 3307 3308/*P1_LOCKTIME2*/ 3309#define R0900_P1_LOCKTIME2 0xf523 3310#define LOCKTIME2 REGx(R0900_P1_LOCKTIME2) 3311#define F0900_P1_DEMOD_LOCKTIME2 0xf52300ff 3312 3313/*P1_LOCKTIME1*/ 3314#define R0900_P1_LOCKTIME1 0xf524 3315#define LOCKTIME1 REGx(R0900_P1_LOCKTIME1) 3316#define F0900_P1_DEMOD_LOCKTIME1 0xf52400ff 3317 3318/*P1_LOCKTIME0*/ 3319#define R0900_P1_LOCKTIME0 0xf525 3320#define LOCKTIME0 REGx(R0900_P1_LOCKTIME0) 3321#define F0900_P1_DEMOD_LOCKTIME0 0xf52500ff 3322 3323/*P1_VITSCALE*/ 3324#define R0900_P1_VITSCALE 0xf532 3325#define VITSCALE REGx(R0900_P1_VITSCALE) 3326#define F0900_P1_NVTH_NOSRANGE 0xf5320080 3327#define F0900_P1_VERROR_MAXMODE 0xf5320040 3328#define F0900_P1_NSLOWSN_LOCKED 0xf5320008 3329#define F0900_P1_DIS_RSFLOCK 0xf5320002 3330 3331/*P1_FECM*/ 3332#define R0900_P1_FECM 0xf533 3333#define FECM REGx(R0900_P1_FECM) 3334#define F0900_P1_DSS_DVB 0xf5330080 3335#define DSS_DVB FLDx(F0900_P1_DSS_DVB) 3336#define F0900_P1_DSS_SRCH 0xf5330010 3337#define F0900_P1_SYNCVIT 0xf5330002 3338#define F0900_P1_IQINV 0xf5330001 3339#define IQINV FLDx(F0900_P1_IQINV) 3340 3341/*P1_VTH12*/ 3342#define R0900_P1_VTH12 0xf534 3343#define VTH12 REGx(R0900_P1_VTH12) 3344#define F0900_P1_VTH12 0xf53400ff 3345 3346/*P1_VTH23*/ 3347#define R0900_P1_VTH23 0xf535 3348#define VTH23 REGx(R0900_P1_VTH23) 3349#define F0900_P1_VTH23 0xf53500ff 3350 3351/*P1_VTH34*/ 3352#define R0900_P1_VTH34 0xf536 3353#define VTH34 REGx(R0900_P1_VTH34) 3354#define F0900_P1_VTH34 0xf53600ff 3355 3356/*P1_VTH56*/ 3357#define R0900_P1_VTH56 0xf537 3358#define VTH56 REGx(R0900_P1_VTH56) 3359#define F0900_P1_VTH56 0xf53700ff 3360 3361/*P1_VTH67*/ 3362#define R0900_P1_VTH67 0xf538 3363#define VTH67 REGx(R0900_P1_VTH67) 3364#define F0900_P1_VTH67 0xf53800ff 3365 3366/*P1_VTH78*/ 3367#define R0900_P1_VTH78 0xf539 3368#define VTH78 REGx(R0900_P1_VTH78) 3369#define F0900_P1_VTH78 0xf53900ff 3370 3371/*P1_VITCURPUN*/ 3372#define R0900_P1_VITCURPUN 0xf53a 3373#define VITCURPUN REGx(R0900_P1_VITCURPUN) 3374#define F0900_P1_VIT_CURPUN 0xf53a001f 3375#define VIT_CURPUN FLDx(F0900_P1_VIT_CURPUN) 3376 3377/*P1_VERROR*/ 3378#define R0900_P1_VERROR 0xf53b 3379#define VERROR REGx(R0900_P1_VERROR) 3380#define F0900_P1_REGERR_VIT 0xf53b00ff 3381 3382/*P1_PRVIT*/ 3383#define R0900_P1_PRVIT 0xf53c 3384#define PRVIT REGx(R0900_P1_PRVIT) 3385#define F0900_P1_DIS_VTHLOCK 0xf53c0040 3386#define F0900_P1_E7_8VIT 0xf53c0020 3387#define F0900_P1_E6_7VIT 0xf53c0010 3388#define F0900_P1_E5_6VIT 0xf53c0008 3389#define F0900_P1_E3_4VIT 0xf53c0004 3390#define F0900_P1_E2_3VIT 0xf53c0002 3391#define F0900_P1_E1_2VIT 0xf53c0001 3392 3393/*P1_VAVSRVIT*/ 3394#define R0900_P1_VAVSRVIT 0xf53d 3395#define VAVSRVIT REGx(R0900_P1_VAVSRVIT) 3396#define F0900_P1_AMVIT 0xf53d0080 3397#define F0900_P1_FROZENVIT 0xf53d0040 3398#define F0900_P1_SNVIT 0xf53d0030 3399#define F0900_P1_TOVVIT 0xf53d000c 3400#define F0900_P1_HYPVIT 0xf53d0003 3401 3402/*P1_VSTATUSVIT*/ 3403#define R0900_P1_VSTATUSVIT 0xf53e 3404#define VSTATUSVIT REGx(R0900_P1_VSTATUSVIT) 3405#define F0900_P1_PRFVIT 0xf53e0010 3406#define PRFVIT FLDx(F0900_P1_PRFVIT) 3407#define F0900_P1_LOCKEDVIT 0xf53e0008 3408#define LOCKEDVIT FLDx(F0900_P1_LOCKEDVIT) 3409 3410/*P1_VTHINUSE*/ 3411#define R0900_P1_VTHINUSE 0xf53f 3412#define VTHINUSE REGx(R0900_P1_VTHINUSE) 3413#define F0900_P1_VIT_INUSE 0xf53f00ff 3414 3415/*P1_KDIV12*/ 3416#define R0900_P1_KDIV12 0xf540 3417#define KDIV12 REGx(R0900_P1_KDIV12) 3418#define F0900_P1_K_DIVIDER_12 0xf540007f 3419 3420/*P1_KDIV23*/ 3421#define R0900_P1_KDIV23 0xf541 3422#define KDIV23 REGx(R0900_P1_KDIV23) 3423#define F0900_P1_K_DIVIDER_23 0xf541007f 3424 3425/*P1_KDIV34*/ 3426#define R0900_P1_KDIV34 0xf542 3427#define KDIV34 REGx(R0900_P1_KDIV34) 3428#define F0900_P1_K_DIVIDER_34 0xf542007f 3429 3430/*P1_KDIV56*/ 3431#define R0900_P1_KDIV56 0xf543 3432#define KDIV56 REGx(R0900_P1_KDIV56) 3433#define F0900_P1_K_DIVIDER_56 0xf543007f 3434 3435/*P1_KDIV67*/ 3436#define R0900_P1_KDIV67 0xf544 3437#define KDIV67 REGx(R0900_P1_KDIV67) 3438#define F0900_P1_K_DIVIDER_67 0xf544007f 3439 3440/*P1_KDIV78*/ 3441#define R0900_P1_KDIV78 0xf545 3442#define KDIV78 REGx(R0900_P1_KDIV78) 3443#define F0900_P1_K_DIVIDER_78 0xf545007f 3444 3445/*P1_PDELCTRL1*/ 3446#define R0900_P1_PDELCTRL1 0xf550 3447#define PDELCTRL1 REGx(R0900_P1_PDELCTRL1) 3448#define F0900_P1_INV_MISMASK 0xf5500080 3449#define INV_MISMASK FLDx(F0900_P1_INV_MISMASK) 3450#define F0900_P1_FILTER_EN 0xf5500020 3451#define FILTER_EN FLDx(F0900_P1_FILTER_EN) 3452#define F0900_P1_EN_MIS00 0xf5500002 3453#define EN_MIS00 FLDx(F0900_P1_EN_MIS00) 3454#define F0900_P1_ALGOSWRST 0xf5500001 3455#define ALGOSWRST FLDx(F0900_P1_ALGOSWRST) 3456 3457/*P1_PDELCTRL2*/ 3458#define R0900_P1_PDELCTRL2 0xf551 3459#define PDELCTRL2 REGx(R0900_P1_PDELCTRL2) 3460#define F0900_P1_RESET_UPKO_COUNT 0xf5510040 3461#define RESET_UPKO_COUNT FLDx(F0900_P1_RESET_UPKO_COUNT) 3462#define F0900_P1_FRAME_MODE 0xf5510002 3463#define F0900_P1_NOBCHERRFLG_USE 0xf5510001 3464 3465/*P1_HYSTTHRESH*/ 3466#define R0900_P1_HYSTTHRESH 0xf554 3467#define HYSTTHRESH REGx(R0900_P1_HYSTTHRESH) 3468#define F0900_P1_UNLCK_THRESH 0xf55400f0 3469#define F0900_P1_DELIN_LCK_THRESH 0xf554000f 3470 3471/*P1_ISIENTRY*/ 3472#define R0900_P1_ISIENTRY 0xf55e 3473#define ISIENTRY REGx(R0900_P1_ISIENTRY) 3474#define F0900_P1_ISI_ENTRY 0xf55e00ff 3475 3476/*P1_ISIBITENA*/ 3477#define R0900_P1_ISIBITENA 0xf55f 3478#define ISIBITENA REGx(R0900_P1_ISIBITENA) 3479#define F0900_P1_ISI_BIT_EN 0xf55f00ff 3480 3481/*P1_MATSTR1*/ 3482#define R0900_P1_MATSTR1 0xf560 3483#define MATSTR1 REGx(R0900_P1_MATSTR1) 3484#define F0900_P1_MATYPE_CURRENT1 0xf56000ff 3485 3486/*P1_MATSTR0*/ 3487#define R0900_P1_MATSTR0 0xf561 3488#define MATSTR0 REGx(R0900_P1_MATSTR0) 3489#define F0900_P1_MATYPE_CURRENT0 0xf56100ff 3490 3491/*P1_UPLSTR1*/ 3492#define R0900_P1_UPLSTR1 0xf562 3493#define UPLSTR1 REGx(R0900_P1_UPLSTR1) 3494#define F0900_P1_UPL_CURRENT1 0xf56200ff 3495 3496/*P1_UPLSTR0*/ 3497#define R0900_P1_UPLSTR0 0xf563 3498#define UPLSTR0 REGx(R0900_P1_UPLSTR0) 3499#define F0900_P1_UPL_CURRENT0 0xf56300ff 3500 3501/*P1_DFLSTR1*/ 3502#define R0900_P1_DFLSTR1 0xf564 3503#define DFLSTR1 REGx(R0900_P1_DFLSTR1) 3504#define F0900_P1_DFL_CURRENT1 0xf56400ff 3505 3506/*P1_DFLSTR0*/ 3507#define R0900_P1_DFLSTR0 0xf565 3508#define DFLSTR0 REGx(R0900_P1_DFLSTR0) 3509#define F0900_P1_DFL_CURRENT0 0xf56500ff 3510 3511/*P1_SYNCSTR*/ 3512#define R0900_P1_SYNCSTR 0xf566 3513#define SYNCSTR REGx(R0900_P1_SYNCSTR) 3514#define F0900_P1_SYNC_CURRENT 0xf56600ff 3515 3516/*P1_SYNCDSTR1*/ 3517#define R0900_P1_SYNCDSTR1 0xf567 3518#define SYNCDSTR1 REGx(R0900_P1_SYNCDSTR1) 3519#define F0900_P1_SYNCD_CURRENT1 0xf56700ff 3520 3521/*P1_SYNCDSTR0*/ 3522#define R0900_P1_SYNCDSTR0 0xf568 3523#define SYNCDSTR0 REGx(R0900_P1_SYNCDSTR0) 3524#define F0900_P1_SYNCD_CURRENT0 0xf56800ff 3525 3526/*P1_PDELSTATUS1*/ 3527#define R0900_P1_PDELSTATUS1 0xf569 3528#define F0900_P1_PKTDELIN_DELOCK 0xf5690080 3529#define F0900_P1_SYNCDUPDFL_BADDFL 0xf5690040 3530#define F0900_P1_CONTINUOUS_STREAM 0xf5690020 3531#define F0900_P1_UNACCEPTED_STREAM 0xf5690010 3532#define F0900_P1_BCH_ERROR_FLAG 0xf5690008 3533#define F0900_P1_PKTDELIN_LOCK 0xf5690002 3534#define PKTDELIN_LOCK FLDx(F0900_P1_PKTDELIN_LOCK) 3535#define F0900_P1_FIRST_LOCK 0xf5690001 3536 3537/*P1_PDELSTATUS2*/ 3538#define R0900_P1_PDELSTATUS2 0xf56a 3539#define F0900_P1_FRAME_MODCOD 0xf56a007c 3540#define F0900_P1_FRAME_TYPE 0xf56a0003 3541 3542/*P1_BBFCRCKO1*/ 3543#define R0900_P1_BBFCRCKO1 0xf56b 3544#define BBFCRCKO1 REGx(R0900_P1_BBFCRCKO1) 3545#define F0900_P1_BBHCRC_KOCNT1 0xf56b00ff 3546 3547/*P1_BBFCRCKO0*/ 3548#define R0900_P1_BBFCRCKO0 0xf56c 3549#define BBFCRCKO0 REGx(R0900_P1_BBFCRCKO0) 3550#define F0900_P1_BBHCRC_KOCNT0 0xf56c00ff 3551 3552/*P1_UPCRCKO1*/ 3553#define R0900_P1_UPCRCKO1 0xf56d 3554#define UPCRCKO1 REGx(R0900_P1_UPCRCKO1) 3555#define F0900_P1_PKTCRC_KOCNT1 0xf56d00ff 3556 3557/*P1_UPCRCKO0*/ 3558#define R0900_P1_UPCRCKO0 0xf56e 3559#define UPCRCKO0 REGx(R0900_P1_UPCRCKO0) 3560#define F0900_P1_PKTCRC_KOCNT0 0xf56e00ff 3561 3562/*P1_PDELCTRL3*/ 3563#define R0900_P1_PDELCTRL3 0xf56f 3564#define PDELCTRL3 REGx(R0900_P1_PDELCTRL3) 3565#define F0900_P1_PKTDEL_CONTFAIL 0xf56f0080 3566#define F0900_P1_NOFIFO_BCHERR 0xf56f0020 3567 3568/*P1_TSSTATEM*/ 3569#define R0900_P1_TSSTATEM 0xf570 3570#define TSSTATEM REGx(R0900_P1_TSSTATEM) 3571#define F0900_P1_TSDIL_ON 0xf5700080 3572#define F0900_P1_TSRS_ON 0xf5700020 3573#define F0900_P1_TSDESCRAMB_ON 0xf5700010 3574#define F0900_P1_TSFRAME_MODE 0xf5700008 3575#define F0900_P1_TS_DISABLE 0xf5700004 3576#define F0900_P1_TSOUT_NOSYNC 0xf5700001 3577 3578/*P1_TSCFGH*/ 3579#define R0900_P1_TSCFGH 0xf572 3580#define TSCFGH REGx(R0900_P1_TSCFGH) 3581#define F0900_P1_TSFIFO_DVBCI 0xf5720080 3582#define F0900_P1_TSFIFO_SERIAL 0xf5720040 3583#define F0900_P1_TSFIFO_TEIUPDATE 0xf5720020 3584#define F0900_P1_TSFIFO_DUTY50 0xf5720010 3585#define F0900_P1_TSFIFO_HSGNLOUT 0xf5720008 3586#define F0900_P1_TSFIFO_ERRMODE 0xf5720006 3587#define F0900_P1_RST_HWARE 0xf5720001 3588#define RST_HWARE FLDx(F0900_P1_RST_HWARE) 3589 3590/*P1_TSCFGM*/ 3591#define R0900_P1_TSCFGM 0xf573 3592#define TSCFGM REGx(R0900_P1_TSCFGM) 3593#define F0900_P1_TSFIFO_MANSPEED 0xf57300c0 3594#define F0900_P1_TSFIFO_PERMDATA 0xf5730020 3595#define F0900_P1_TSFIFO_DPUNACT 0xf5730002 3596#define F0900_P1_TSFIFO_INVDATA 0xf5730001 3597 3598/*P1_TSCFGL*/ 3599#define R0900_P1_TSCFGL 0xf574 3600#define TSCFGL REGx(R0900_P1_TSCFGL) 3601#define F0900_P1_TSFIFO_BCLKDEL1CK 0xf57400c0 3602#define F0900_P1_BCHERROR_MODE 0xf5740030 3603#define F0900_P1_TSFIFO_NSGNL2DATA 0xf5740008 3604#define F0900_P1_TSFIFO_EMBINDVB 0xf5740004 3605#define F0900_P1_TSFIFO_BITSPEED 0xf5740003 3606 3607/*P1_TSINSDELH*/ 3608#define R0900_P1_TSINSDELH 0xf576 3609#define TSINSDELH REGx(R0900_P1_TSINSDELH) 3610#define F0900_P1_TSDEL_SYNCBYTE 0xf5760080 3611#define F0900_P1_TSDEL_XXHEADER 0xf5760040 3612#define F0900_P1_TSDEL_BBHEADER 0xf5760020 3613#define F0900_P1_TSDEL_DATAFIELD 0xf5760010 3614#define F0900_P1_TSINSDEL_ISCR 0xf5760008 3615#define F0900_P1_TSINSDEL_NPD 0xf5760004 3616#define F0900_P1_TSINSDEL_RSPARITY 0xf5760002 3617#define F0900_P1_TSINSDEL_CRC8 0xf5760001 3618 3619/*P1_TSDIVN*/ 3620#define R0900_P1_TSDIVN 0xf579 3621#define TSDIVN REGx(R0900_P1_TSDIVN) 3622#define F0900_P1_TSFIFO_SPEEDMODE 0xf57900c0 3623 3624/*P1_TSCFG4*/ 3625#define R0900_P1_TSCFG4 0xf57a 3626#define TSCFG4 REGx(R0900_P1_TSCFG4) 3627#define F0900_P1_TSFIFO_TSSPEEDMODE 0xf57a00c0 3628 3629/*P1_TSSPEED*/ 3630#define R0900_P1_TSSPEED 0xf580 3631#define TSSPEED REGx(R0900_P1_TSSPEED) 3632#define F0900_P1_TSFIFO_OUTSPEED 0xf58000ff 3633 3634/*P1_TSSTATUS*/ 3635#define R0900_P1_TSSTATUS 0xf581 3636#define TSSTATUS REGx(R0900_P1_TSSTATUS) 3637#define F0900_P1_TSFIFO_LINEOK 0xf5810080 3638#define TSFIFO_LINEOK FLDx(F0900_P1_TSFIFO_LINEOK) 3639#define F0900_P1_TSFIFO_ERROR 0xf5810040 3640#define F0900_P1_DIL_READY 0xf5810001 3641 3642/*P1_TSSTATUS2*/ 3643#define R0900_P1_TSSTATUS2 0xf582 3644#define TSSTATUS2 REGx(R0900_P1_TSSTATUS2) 3645#define F0900_P1_TSFIFO_DEMODSEL 0xf5820080 3646#define F0900_P1_TSFIFOSPEED_STORE 0xf5820040 3647#define F0900_P1_DILXX_RESET 0xf5820020 3648#define F0900_P1_TSSERIAL_IMPOS 0xf5820010 3649#define F0900_P1_SCRAMBDETECT 0xf5820002 3650 3651/*P1_TSBITRATE1*/ 3652#define R0900_P1_TSBITRATE1 0xf583 3653#define TSBITRATE1 REGx(R0900_P1_TSBITRATE1) 3654#define F0900_P1_TSFIFO_BITRATE1 0xf58300ff 3655 3656/*P1_TSBITRATE0*/ 3657#define R0900_P1_TSBITRATE0 0xf584 3658#define TSBITRATE0 REGx(R0900_P1_TSBITRATE0) 3659#define F0900_P1_TSFIFO_BITRATE0 0xf58400ff 3660 3661/*P1_ERRCTRL1*/ 3662#define R0900_P1_ERRCTRL1 0xf598 3663#define ERRCTRL1 REGx(R0900_P1_ERRCTRL1) 3664#define F0900_P1_ERR_SOURCE1 0xf59800f0 3665#define F0900_P1_NUM_EVENT1 0xf5980007 3666 3667/*P1_ERRCNT12*/ 3668#define R0900_P1_ERRCNT12 0xf599 3669#define ERRCNT12 REGx(R0900_P1_ERRCNT12) 3670#define F0900_P1_ERRCNT1_OLDVALUE 0xf5990080 3671#define F0900_P1_ERR_CNT12 0xf599007f 3672#define ERR_CNT12 FLDx(F0900_P1_ERR_CNT12) 3673 3674/*P1_ERRCNT11*/ 3675#define R0900_P1_ERRCNT11 0xf59a 3676#define ERRCNT11 REGx(R0900_P1_ERRCNT11) 3677#define F0900_P1_ERR_CNT11 0xf59a00ff 3678#define ERR_CNT11 FLDx(F0900_P1_ERR_CNT11) 3679 3680/*P1_ERRCNT10*/ 3681#define R0900_P1_ERRCNT10 0xf59b 3682#define ERRCNT10 REGx(R0900_P1_ERRCNT10) 3683#define F0900_P1_ERR_CNT10 0xf59b00ff 3684#define ERR_CNT10 FLDx(F0900_P1_ERR_CNT10) 3685 3686/*P1_ERRCTRL2*/ 3687#define R0900_P1_ERRCTRL2 0xf59c 3688#define ERRCTRL2 REGx(R0900_P1_ERRCTRL2) 3689#define F0900_P1_ERR_SOURCE2 0xf59c00f0 3690#define F0900_P1_NUM_EVENT2 0xf59c0007 3691 3692/*P1_ERRCNT22*/ 3693#define R0900_P1_ERRCNT22 0xf59d 3694#define ERRCNT22 REGx(R0900_P1_ERRCNT22) 3695#define F0900_P1_ERRCNT2_OLDVALUE 0xf59d0080 3696#define F0900_P1_ERR_CNT22 0xf59d007f 3697#define ERR_CNT22 FLDx(F0900_P1_ERR_CNT22) 3698 3699/*P1_ERRCNT21*/ 3700#define R0900_P1_ERRCNT21 0xf59e 3701#define ERRCNT21 REGx(R0900_P1_ERRCNT21) 3702#define F0900_P1_ERR_CNT21 0xf59e00ff 3703#define ERR_CNT21 FLDx(F0900_P1_ERR_CNT21) 3704 3705/*P1_ERRCNT20*/ 3706#define R0900_P1_ERRCNT20 0xf59f 3707#define ERRCNT20 REGx(R0900_P1_ERRCNT20) 3708#define F0900_P1_ERR_CNT20 0xf59f00ff 3709#define ERR_CNT20 FLDx(F0900_P1_ERR_CNT20) 3710 3711/*P1_FECSPY*/ 3712#define R0900_P1_FECSPY 0xf5a0 3713#define FECSPY REGx(R0900_P1_FECSPY) 3714#define F0900_P1_SPY_ENABLE 0xf5a00080 3715#define F0900_P1_NO_SYNCBYTE 0xf5a00040 3716#define F0900_P1_SERIAL_MODE 0xf5a00020 3717#define F0900_P1_UNUSUAL_PACKET 0xf5a00010 3718#define F0900_P1_BERMETER_DATAMODE 0xf5a00008 3719#define F0900_P1_BERMETER_LMODE 0xf5a00002 3720#define F0900_P1_BERMETER_RESET 0xf5a00001 3721 3722/*P1_FSPYCFG*/ 3723#define R0900_P1_FSPYCFG 0xf5a1 3724#define FSPYCFG REGx(R0900_P1_FSPYCFG) 3725#define F0900_P1_FECSPY_INPUT 0xf5a100c0 3726#define F0900_P1_RST_ON_ERROR 0xf5a10020 3727#define F0900_P1_ONE_SHOT 0xf5a10010 3728#define F0900_P1_I2C_MODE 0xf5a1000c 3729#define F0900_P1_SPY_HYSTERESIS 0xf5a10003 3730 3731/*P1_FSPYDATA*/ 3732#define R0900_P1_FSPYDATA 0xf5a2 3733#define FSPYDATA REGx(R0900_P1_FSPYDATA) 3734#define F0900_P1_SPY_STUFFING 0xf5a20080 3735#define F0900_P1_SPY_CNULLPKT 0xf5a20020 3736#define F0900_P1_SPY_OUTDATA_MODE 0xf5a2001f 3737 3738/*P1_FSPYOUT*/ 3739#define R0900_P1_FSPYOUT 0xf5a3 3740#define FSPYOUT REGx(R0900_P1_FSPYOUT) 3741#define F0900_P1_FSPY_DIRECT 0xf5a30080 3742#define F0900_P1_STUFF_MODE 0xf5a30007 3743 3744/*P1_FSTATUS*/ 3745#define R0900_P1_FSTATUS 0xf5a4 3746#define FSTATUS REGx(R0900_P1_FSTATUS) 3747#define F0900_P1_SPY_ENDSIM 0xf5a40080 3748#define F0900_P1_VALID_SIM 0xf5a40040 3749#define F0900_P1_FOUND_SIGNAL 0xf5a40020 3750#define F0900_P1_DSS_SYNCBYTE 0xf5a40010 3751#define F0900_P1_RESULT_STATE 0xf5a4000f 3752 3753/*P1_FBERCPT4*/ 3754#define R0900_P1_FBERCPT4 0xf5a8 3755#define FBERCPT4 REGx(R0900_P1_FBERCPT4) 3756#define F0900_P1_FBERMETER_CPT4 0xf5a800ff 3757 3758/*P1_FBERCPT3*/ 3759#define R0900_P1_FBERCPT3 0xf5a9 3760#define FBERCPT3 REGx(R0900_P1_FBERCPT3) 3761#define F0900_P1_FBERMETER_CPT3 0xf5a900ff 3762 3763/*P1_FBERCPT2*/ 3764#define R0900_P1_FBERCPT2 0xf5aa 3765#define FBERCPT2 REGx(R0900_P1_FBERCPT2) 3766#define F0900_P1_FBERMETER_CPT2 0xf5aa00ff 3767 3768/*P1_FBERCPT1*/ 3769#define R0900_P1_FBERCPT1 0xf5ab 3770#define FBERCPT1 REGx(R0900_P1_FBERCPT1) 3771#define F0900_P1_FBERMETER_CPT1 0xf5ab00ff 3772 3773/*P1_FBERCPT0*/ 3774#define R0900_P1_FBERCPT0 0xf5ac 3775#define FBERCPT0 REGx(R0900_P1_FBERCPT0) 3776#define F0900_P1_FBERMETER_CPT0 0xf5ac00ff 3777 3778/*P1_FBERERR2*/ 3779#define R0900_P1_FBERERR2 0xf5ad 3780#define FBERERR2 REGx(R0900_P1_FBERERR2) 3781#define F0900_P1_FBERMETER_ERR2 0xf5ad00ff 3782 3783/*P1_FBERERR1*/ 3784#define R0900_P1_FBERERR1 0xf5ae 3785#define FBERERR1 REGx(R0900_P1_FBERERR1) 3786#define F0900_P1_FBERMETER_ERR1 0xf5ae00ff 3787 3788/*P1_FBERERR0*/ 3789#define R0900_P1_FBERERR0 0xf5af 3790#define FBERERR0 REGx(R0900_P1_FBERERR0) 3791#define F0900_P1_FBERMETER_ERR0 0xf5af00ff 3792 3793/*P1_FSPYBER*/ 3794#define R0900_P1_FSPYBER 0xf5b2 3795#define FSPYBER REGx(R0900_P1_FSPYBER) 3796#define F0900_P1_FSPYBER_SYNCBYTE 0xf5b20010 3797#define F0900_P1_FSPYBER_UNSYNC 0xf5b20008 3798#define F0900_P1_FSPYBER_CTIME 0xf5b20007 3799 3800/*RCCFG2*/ 3801#define R0900_RCCFG2 0xf600 3802 3803/*TSGENERAL*/ 3804#define R0900_TSGENERAL 0xf630 3805#define F0900_TSFIFO_DISTS2PAR 0xf6300040 3806#define F0900_MUXSTREAM_OUTMODE 0xf6300008 3807#define F0900_TSFIFO_PERMPARAL 0xf6300006 3808 3809/*TSGENERAL1X*/ 3810#define R0900_TSGENERAL1X 0xf670 3811 3812/*NBITER_NF4*/ 3813#define R0900_NBITER_NF4 0xfa03 3814#define F0900_NBITER_NF_QP_1_2 0xfa0300ff 3815 3816/*NBITER_NF5*/ 3817#define R0900_NBITER_NF5 0xfa04 3818#define F0900_NBITER_NF_QP_3_5 0xfa0400ff 3819 3820/*NBITER_NF6*/ 3821#define R0900_NBITER_NF6 0xfa05 3822#define F0900_NBITER_NF_QP_2_3 0xfa0500ff 3823 3824/*NBITER_NF7*/ 3825#define R0900_NBITER_NF7 0xfa06 3826#define F0900_NBITER_NF_QP_3_4 0xfa0600ff 3827 3828/*NBITER_NF8*/ 3829#define R0900_NBITER_NF8 0xfa07 3830#define F0900_NBITER_NF_QP_4_5 0xfa0700ff 3831 3832/*NBITER_NF9*/ 3833#define R0900_NBITER_NF9 0xfa08 3834#define F0900_NBITER_NF_QP_5_6 0xfa0800ff 3835 3836/*NBITER_NF10*/ 3837#define R0900_NBITER_NF10 0xfa09 3838#define F0900_NBITER_NF_QP_8_9 0xfa0900ff 3839 3840/*NBITER_NF11*/ 3841#define R0900_NBITER_NF11 0xfa0a 3842#define F0900_NBITER_NF_QP_9_10 0xfa0a00ff 3843 3844/*NBITER_NF12*/ 3845#define R0900_NBITER_NF12 0xfa0b 3846#define F0900_NBITER_NF_8P_3_5 0xfa0b00ff 3847 3848/*NBITER_NF13*/ 3849#define R0900_NBITER_NF13 0xfa0c 3850#define F0900_NBITER_NF_8P_2_3 0xfa0c00ff 3851 3852/*NBITER_NF14*/ 3853#define R0900_NBITER_NF14 0xfa0d 3854#define F0900_NBITER_NF_8P_3_4 0xfa0d00ff 3855 3856/*NBITER_NF15*/ 3857#define R0900_NBITER_NF15 0xfa0e 3858#define F0900_NBITER_NF_8P_5_6 0xfa0e00ff 3859 3860/*NBITER_NF16*/ 3861#define R0900_NBITER_NF16 0xfa0f 3862#define F0900_NBITER_NF_8P_8_9 0xfa0f00ff 3863 3864/*NBITER_NF17*/ 3865#define R0900_NBITER_NF17 0xfa10 3866#define F0900_NBITER_NF_8P_9_10 0xfa1000ff 3867 3868/*NBITERNOERR*/ 3869#define R0900_NBITERNOERR 0xfa3f 3870#define F0900_NBITER_STOP_CRIT 0xfa3f000f 3871 3872/*GAINLLR_NF4*/ 3873#define R0900_GAINLLR_NF4 0xfa43 3874#define F0900_GAINLLR_NF_QP_1_2 0xfa43007f 3875 3876/*GAINLLR_NF5*/ 3877#define R0900_GAINLLR_NF5 0xfa44 3878#define F0900_GAINLLR_NF_QP_3_5 0xfa44007f 3879 3880/*GAINLLR_NF6*/ 3881#define R0900_GAINLLR_NF6 0xfa45 3882#define F0900_GAINLLR_NF_QP_2_3 0xfa45007f 3883 3884/*GAINLLR_NF7*/ 3885#define R0900_GAINLLR_NF7 0xfa46 3886#define F0900_GAINLLR_NF_QP_3_4 0xfa46007f 3887 3888/*GAINLLR_NF8*/ 3889#define R0900_GAINLLR_NF8 0xfa47 3890#define F0900_GAINLLR_NF_QP_4_5 0xfa47007f 3891 3892/*GAINLLR_NF9*/ 3893#define R0900_GAINLLR_NF9 0xfa48 3894#define F0900_GAINLLR_NF_QP_5_6 0xfa48007f 3895 3896/*GAINLLR_NF10*/ 3897#define R0900_GAINLLR_NF10 0xfa49 3898#define F0900_GAINLLR_NF_QP_8_9 0xfa49007f 3899 3900/*GAINLLR_NF11*/ 3901#define R0900_GAINLLR_NF11 0xfa4a 3902#define F0900_GAINLLR_NF_QP_9_10 0xfa4a007f 3903 3904/*GAINLLR_NF12*/ 3905#define R0900_GAINLLR_NF12 0xfa4b 3906#define F0900_GAINLLR_NF_8P_3_5 0xfa4b007f 3907 3908/*GAINLLR_NF13*/ 3909#define R0900_GAINLLR_NF13 0xfa4c 3910#define F0900_GAINLLR_NF_8P_2_3 0xfa4c007f 3911 3912/*GAINLLR_NF14*/ 3913#define R0900_GAINLLR_NF14 0xfa4d 3914#define F0900_GAINLLR_NF_8P_3_4 0xfa4d007f 3915 3916/*GAINLLR_NF15*/ 3917#define R0900_GAINLLR_NF15 0xfa4e 3918#define F0900_GAINLLR_NF_8P_5_6 0xfa4e007f 3919 3920/*GAINLLR_NF16*/ 3921#define R0900_GAINLLR_NF16 0xfa4f 3922#define F0900_GAINLLR_NF_8P_8_9 0xfa4f007f 3923 3924/*GAINLLR_NF17*/ 3925#define R0900_GAINLLR_NF17 0xfa50 3926#define F0900_GAINLLR_NF_8P_9_10 0xfa50007f 3927 3928/*CFGEXT*/ 3929#define R0900_CFGEXT 0xfa80 3930#define F0900_STAGMODE 0xfa800080 3931#define F0900_BYPBCH 0xfa800040 3932#define F0900_BYPLDPC 0xfa800020 3933#define F0900_LDPCMODE 0xfa800010 3934#define F0900_INVLLRSIGN 0xfa800008 3935#define F0900_SHORTMULT 0xfa800004 3936#define F0900_EXTERNTX 0xfa800001 3937 3938/*GENCFG*/ 3939#define R0900_GENCFG 0xfa86 3940#define F0900_BROADCAST 0xfa860010 3941#define F0900_PRIORITY 0xfa860002 3942#define F0900_DDEMOD 0xfa860001 3943 3944/*LDPCERR1*/ 3945#define R0900_LDPCERR1 0xfa96 3946#define F0900_LDPC_ERRORS_COUNTER1 0xfa9600ff 3947 3948/*LDPCERR0*/ 3949#define R0900_LDPCERR0 0xfa97 3950#define F0900_LDPC_ERRORS_COUNTER0 0xfa9700ff 3951 3952/*BCHERR*/ 3953#define R0900_BCHERR 0xfa98 3954#define F0900_ERRORFLAG 0xfa980010 3955#define F0900_BCH_ERRORS_COUNTER 0xfa98000f 3956 3957/*TSTRES0*/ 3958#define R0900_TSTRES0 0xff11 3959#define F0900_FRESFEC 0xff110080 3960 3961/*P2_TCTL4*/ 3962#define R0900_P2_TCTL4 0xff28 3963#define F0900_P2_PN4_SELECT 0xff280020 3964 3965/*P1_TCTL4*/ 3966#define R0900_P1_TCTL4 0xff48 3967#define TCTL4 shiftx(R0900_P1_TCTL4, demod, 0x20) 3968#define F0900_P1_PN4_SELECT 0xff480020 3969 3970/*P2_TSTDISRX*/ 3971#define R0900_P2_TSTDISRX 0xff65 3972#define F0900_P2_PIN_SELECT1 0xff650008 3973 3974/*P1_TSTDISRX*/ 3975#define R0900_P1_TSTDISRX 0xff67 3976#define TSTDISRX shiftx(R0900_P1_TSTDISRX, demod, 2) 3977#define F0900_P1_PIN_SELECT1 0xff670008 3978#define PIN_SELECT1 shiftx(F0900_P1_PIN_SELECT1, demod, 0x20000) 3979 3980#define STV0900_NBREGS 723 3981#define STV0900_NBFIELDS 1420 3982 3983#endif 3984 3985