1/* 2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#include <rdma/ib_mad.h> 34#include <rdma/ib_smi.h> 35#include <rdma/ib_sa.h> 36#include <rdma/ib_cache.h> 37 38#include <linux/random.h> 39#include <linux/mlx4/cmd.h> 40#include <linux/gfp.h> 41#include <rdma/ib_pma.h> 42 43#include "mlx4_ib.h" 44 45enum { 46 MLX4_IB_VENDOR_CLASS1 = 0x9, 47 MLX4_IB_VENDOR_CLASS2 = 0xa 48}; 49 50#define MLX4_TUN_SEND_WRID_SHIFT 34 51#define MLX4_TUN_QPN_SHIFT 32 52#define MLX4_TUN_WRID_RECV (((u64) 1) << MLX4_TUN_SEND_WRID_SHIFT) 53#define MLX4_TUN_SET_WRID_QPN(a) (((u64) ((a) & 0x3)) << MLX4_TUN_QPN_SHIFT) 54 55#define MLX4_TUN_IS_RECV(a) (((a) >> MLX4_TUN_SEND_WRID_SHIFT) & 0x1) 56#define MLX4_TUN_WRID_QPN(a) (((a) >> MLX4_TUN_QPN_SHIFT) & 0x3) 57 58 /* Port mgmt change event handling */ 59 60#define GET_BLK_PTR_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.block_ptr) 61#define GET_MASK_FROM_EQE(eqe) be32_to_cpu(eqe->event.port_mgmt_change.params.tbl_change_info.tbl_entries_mask) 62#define NUM_IDX_IN_PKEY_TBL_BLK 32 63#define GUID_TBL_ENTRY_SIZE 8 /* size in bytes */ 64#define GUID_TBL_BLK_NUM_ENTRIES 8 65#define GUID_TBL_BLK_SIZE (GUID_TBL_ENTRY_SIZE * GUID_TBL_BLK_NUM_ENTRIES) 66 67/* Counters should be saturate once they reach their maximum value */ 68#define ASSIGN_32BIT_COUNTER(counter, value) do {\ 69 if ((value) > U32_MAX) \ 70 counter = cpu_to_be32(U32_MAX); \ 71 else \ 72 counter = cpu_to_be32(value); \ 73} while (0) 74 75struct mlx4_mad_rcv_buf { 76 struct ib_grh grh; 77 u8 payload[256]; 78} __packed; 79 80struct mlx4_mad_snd_buf { 81 u8 payload[256]; 82} __packed; 83 84struct mlx4_tunnel_mad { 85 struct ib_grh grh; 86 struct mlx4_ib_tunnel_header hdr; 87 struct ib_mad mad; 88} __packed; 89 90struct mlx4_rcv_tunnel_mad { 91 struct mlx4_rcv_tunnel_hdr hdr; 92 struct ib_grh grh; 93 struct ib_mad mad; 94} __packed; 95 96static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num); 97static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num); 98static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 99 int block, u32 change_bitmap); 100 101__be64 mlx4_ib_gen_node_guid(void) 102{ 103#define NODE_GUID_HI ((u64) (((u64)IB_OPENIB_OUI) << 40)) 104 return cpu_to_be64(NODE_GUID_HI | prandom_u32()); 105} 106 107__be64 mlx4_ib_get_new_demux_tid(struct mlx4_ib_demux_ctx *ctx) 108{ 109 return cpu_to_be64(atomic_inc_return(&ctx->tid)) | 110 cpu_to_be64(0xff00000000000000LL); 111} 112 113int mlx4_MAD_IFC(struct mlx4_ib_dev *dev, int mad_ifc_flags, 114 int port, struct ib_wc *in_wc, struct ib_grh *in_grh, 115 void *in_mad, void *response_mad) 116{ 117 struct mlx4_cmd_mailbox *inmailbox, *outmailbox; 118 void *inbox; 119 int err; 120 u32 in_modifier = port; 121 u8 op_modifier = 0; 122 123 inmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 124 if (IS_ERR(inmailbox)) 125 return PTR_ERR(inmailbox); 126 inbox = inmailbox->buf; 127 128 outmailbox = mlx4_alloc_cmd_mailbox(dev->dev); 129 if (IS_ERR(outmailbox)) { 130 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 131 return PTR_ERR(outmailbox); 132 } 133 134 memcpy(inbox, in_mad, 256); 135 136 /* 137 * Key check traps can't be generated unless we have in_wc to 138 * tell us where to send the trap. 139 */ 140 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_MKEY) || !in_wc) 141 op_modifier |= 0x1; 142 if ((mad_ifc_flags & MLX4_MAD_IFC_IGNORE_BKEY) || !in_wc) 143 op_modifier |= 0x2; 144 if (mlx4_is_mfunc(dev->dev) && 145 (mad_ifc_flags & MLX4_MAD_IFC_NET_VIEW || in_wc)) 146 op_modifier |= 0x8; 147 148 if (in_wc) { 149 struct { 150 __be32 my_qpn; 151 u32 reserved1; 152 __be32 rqpn; 153 u8 sl; 154 u8 g_path; 155 u16 reserved2[2]; 156 __be16 pkey; 157 u32 reserved3[11]; 158 u8 grh[40]; 159 } *ext_info; 160 161 memset(inbox + 256, 0, 256); 162 ext_info = inbox + 256; 163 164 ext_info->my_qpn = cpu_to_be32(in_wc->qp->qp_num); 165 ext_info->rqpn = cpu_to_be32(in_wc->src_qp); 166 ext_info->sl = in_wc->sl << 4; 167 ext_info->g_path = in_wc->dlid_path_bits | 168 (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); 169 ext_info->pkey = cpu_to_be16(in_wc->pkey_index); 170 171 if (in_grh) 172 memcpy(ext_info->grh, in_grh, 40); 173 174 op_modifier |= 0x4; 175 176 in_modifier |= in_wc->slid << 16; 177 } 178 179 err = mlx4_cmd_box(dev->dev, inmailbox->dma, outmailbox->dma, in_modifier, 180 mlx4_is_master(dev->dev) ? (op_modifier & ~0x8) : op_modifier, 181 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C, 182 (op_modifier & 0x8) ? MLX4_CMD_NATIVE : MLX4_CMD_WRAPPED); 183 184 if (!err) 185 memcpy(response_mad, outmailbox->buf, 256); 186 187 mlx4_free_cmd_mailbox(dev->dev, inmailbox); 188 mlx4_free_cmd_mailbox(dev->dev, outmailbox); 189 190 return err; 191} 192 193static void update_sm_ah(struct mlx4_ib_dev *dev, u8 port_num, u16 lid, u8 sl) 194{ 195 struct ib_ah *new_ah; 196 struct ib_ah_attr ah_attr; 197 unsigned long flags; 198 199 if (!dev->send_agent[port_num - 1][0]) 200 return; 201 202 memset(&ah_attr, 0, sizeof ah_attr); 203 ah_attr.dlid = lid; 204 ah_attr.sl = sl; 205 ah_attr.port_num = port_num; 206 207 new_ah = ib_create_ah(dev->send_agent[port_num - 1][0]->qp->pd, 208 &ah_attr); 209 if (IS_ERR(new_ah)) 210 return; 211 212 spin_lock_irqsave(&dev->sm_lock, flags); 213 if (dev->sm_ah[port_num - 1]) 214 ib_destroy_ah(dev->sm_ah[port_num - 1]); 215 dev->sm_ah[port_num - 1] = new_ah; 216 spin_unlock_irqrestore(&dev->sm_lock, flags); 217} 218 219/* 220 * Snoop SM MADs for port info, GUID info, and P_Key table sets, so we can 221 * synthesize LID change, Client-Rereg, GID change, and P_Key change events. 222 */ 223static void smp_snoop(struct ib_device *ibdev, u8 port_num, struct ib_mad *mad, 224 u16 prev_lid) 225{ 226 struct ib_port_info *pinfo; 227 u16 lid; 228 __be16 *base; 229 u32 bn, pkey_change_bitmap; 230 int i; 231 232 233 struct mlx4_ib_dev *dev = to_mdev(ibdev); 234 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 235 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 236 mad->mad_hdr.method == IB_MGMT_METHOD_SET) 237 switch (mad->mad_hdr.attr_id) { 238 case IB_SMP_ATTR_PORT_INFO: 239 pinfo = (struct ib_port_info *) ((struct ib_smp *) mad)->data; 240 lid = be16_to_cpu(pinfo->lid); 241 242 update_sm_ah(dev, port_num, 243 be16_to_cpu(pinfo->sm_lid), 244 pinfo->neighbormtu_mastersmsl & 0xf); 245 246 if (pinfo->clientrereg_resv_subnetto & 0x80) 247 handle_client_rereg_event(dev, port_num); 248 249 if (prev_lid != lid) 250 handle_lid_change_event(dev, port_num); 251 break; 252 253 case IB_SMP_ATTR_PKEY_TABLE: 254 if (!mlx4_is_mfunc(dev->dev)) { 255 mlx4_ib_dispatch_event(dev, port_num, 256 IB_EVENT_PKEY_CHANGE); 257 break; 258 } 259 260 /* at this point, we are running in the master. 261 * Slaves do not receive SMPs. 262 */ 263 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod) & 0xFFFF; 264 base = (__be16 *) &(((struct ib_smp *)mad)->data[0]); 265 pkey_change_bitmap = 0; 266 for (i = 0; i < 32; i++) { 267 pr_debug("PKEY[%d] = x%x\n", 268 i + bn*32, be16_to_cpu(base[i])); 269 if (be16_to_cpu(base[i]) != 270 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32]) { 271 pkey_change_bitmap |= (1 << i); 272 dev->pkeys.phys_pkey_cache[port_num - 1][i + bn*32] = 273 be16_to_cpu(base[i]); 274 } 275 } 276 pr_debug("PKEY Change event: port=%d, " 277 "block=0x%x, change_bitmap=0x%x\n", 278 port_num, bn, pkey_change_bitmap); 279 280 if (pkey_change_bitmap) { 281 mlx4_ib_dispatch_event(dev, port_num, 282 IB_EVENT_PKEY_CHANGE); 283 if (!dev->sriov.is_going_down) 284 __propagate_pkey_ev(dev, port_num, bn, 285 pkey_change_bitmap); 286 } 287 break; 288 289 case IB_SMP_ATTR_GUID_INFO: 290 /* paravirtualized master's guid is guid 0 -- does not change */ 291 if (!mlx4_is_master(dev->dev)) 292 mlx4_ib_dispatch_event(dev, port_num, 293 IB_EVENT_GID_CHANGE); 294 /*if master, notify relevant slaves*/ 295 if (mlx4_is_master(dev->dev) && 296 !dev->sriov.is_going_down) { 297 bn = be32_to_cpu(((struct ib_smp *)mad)->attr_mod); 298 mlx4_ib_update_cache_on_guid_change(dev, bn, port_num, 299 (u8 *)(&((struct ib_smp *)mad)->data)); 300 mlx4_ib_notify_slaves_on_guid_change(dev, bn, port_num, 301 (u8 *)(&((struct ib_smp *)mad)->data)); 302 } 303 break; 304 305 default: 306 break; 307 } 308} 309 310static void __propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 311 int block, u32 change_bitmap) 312{ 313 int i, ix, slave, err; 314 int have_event = 0; 315 316 for (slave = 0; slave < dev->dev->caps.sqp_demux; slave++) { 317 if (slave == mlx4_master_func_num(dev->dev)) 318 continue; 319 if (!mlx4_is_slave_active(dev->dev, slave)) 320 continue; 321 322 have_event = 0; 323 for (i = 0; i < 32; i++) { 324 if (!(change_bitmap & (1 << i))) 325 continue; 326 for (ix = 0; 327 ix < dev->dev->caps.pkey_table_len[port_num]; ix++) { 328 if (dev->pkeys.virt2phys_pkey[slave][port_num - 1] 329 [ix] == i + 32 * block) { 330 err = mlx4_gen_pkey_eqe(dev->dev, slave, port_num); 331 pr_debug("propagate_pkey_ev: slave %d," 332 " port %d, ix %d (%d)\n", 333 slave, port_num, ix, err); 334 have_event = 1; 335 break; 336 } 337 } 338 if (have_event) 339 break; 340 } 341 } 342} 343 344static void node_desc_override(struct ib_device *dev, 345 struct ib_mad *mad) 346{ 347 unsigned long flags; 348 349 if ((mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 350 mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 351 mad->mad_hdr.method == IB_MGMT_METHOD_GET_RESP && 352 mad->mad_hdr.attr_id == IB_SMP_ATTR_NODE_DESC) { 353 spin_lock_irqsave(&to_mdev(dev)->sm_lock, flags); 354 memcpy(((struct ib_smp *) mad)->data, dev->node_desc, 64); 355 spin_unlock_irqrestore(&to_mdev(dev)->sm_lock, flags); 356 } 357} 358 359static void forward_trap(struct mlx4_ib_dev *dev, u8 port_num, struct ib_mad *mad) 360{ 361 int qpn = mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_SUBN_LID_ROUTED; 362 struct ib_mad_send_buf *send_buf; 363 struct ib_mad_agent *agent = dev->send_agent[port_num - 1][qpn]; 364 int ret; 365 unsigned long flags; 366 367 if (agent) { 368 send_buf = ib_create_send_mad(agent, qpn, 0, 0, IB_MGMT_MAD_HDR, 369 IB_MGMT_MAD_DATA, GFP_ATOMIC); 370 if (IS_ERR(send_buf)) 371 return; 372 /* 373 * We rely here on the fact that MLX QPs don't use the 374 * address handle after the send is posted (this is 375 * wrong following the IB spec strictly, but we know 376 * it's OK for our devices). 377 */ 378 spin_lock_irqsave(&dev->sm_lock, flags); 379 memcpy(send_buf->mad, mad, sizeof *mad); 380 if ((send_buf->ah = dev->sm_ah[port_num - 1])) 381 ret = ib_post_send_mad(send_buf, NULL); 382 else 383 ret = -EINVAL; 384 spin_unlock_irqrestore(&dev->sm_lock, flags); 385 386 if (ret) 387 ib_free_send_mad(send_buf); 388 } 389} 390 391static int mlx4_ib_demux_sa_handler(struct ib_device *ibdev, int port, int slave, 392 struct ib_sa_mad *sa_mad) 393{ 394 int ret = 0; 395 396 /* dispatch to different sa handlers */ 397 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 398 case IB_SA_ATTR_MC_MEMBER_REC: 399 ret = mlx4_ib_mcg_demux_handler(ibdev, port, slave, sa_mad); 400 break; 401 default: 402 break; 403 } 404 return ret; 405} 406 407int mlx4_ib_find_real_gid(struct ib_device *ibdev, u8 port, __be64 guid) 408{ 409 struct mlx4_ib_dev *dev = to_mdev(ibdev); 410 int i; 411 412 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 413 if (dev->sriov.demux[port - 1].guid_cache[i] == guid) 414 return i; 415 } 416 return -1; 417} 418 419 420static int find_slave_port_pkey_ix(struct mlx4_ib_dev *dev, int slave, 421 u8 port, u16 pkey, u16 *ix) 422{ 423 int i, ret; 424 u8 unassigned_pkey_ix, pkey_ix, partial_ix = 0xFF; 425 u16 slot_pkey; 426 427 if (slave == mlx4_master_func_num(dev->dev)) 428 return ib_find_cached_pkey(&dev->ib_dev, port, pkey, ix); 429 430 unassigned_pkey_ix = dev->dev->phys_caps.pkey_phys_table_len[port] - 1; 431 432 for (i = 0; i < dev->dev->caps.pkey_table_len[port]; i++) { 433 if (dev->pkeys.virt2phys_pkey[slave][port - 1][i] == unassigned_pkey_ix) 434 continue; 435 436 pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][i]; 437 438 ret = ib_get_cached_pkey(&dev->ib_dev, port, pkey_ix, &slot_pkey); 439 if (ret) 440 continue; 441 if ((slot_pkey & 0x7FFF) == (pkey & 0x7FFF)) { 442 if (slot_pkey & 0x8000) { 443 *ix = (u16) pkey_ix; 444 return 0; 445 } else { 446 /* take first partial pkey index found */ 447 if (partial_ix == 0xFF) 448 partial_ix = pkey_ix; 449 } 450 } 451 } 452 453 if (partial_ix < 0xFF) { 454 *ix = (u16) partial_ix; 455 return 0; 456 } 457 458 return -EINVAL; 459} 460 461int mlx4_ib_send_to_slave(struct mlx4_ib_dev *dev, int slave, u8 port, 462 enum ib_qp_type dest_qpt, struct ib_wc *wc, 463 struct ib_grh *grh, struct ib_mad *mad) 464{ 465 struct ib_sge list; 466 struct ib_send_wr wr, *bad_wr; 467 struct mlx4_ib_demux_pv_ctx *tun_ctx; 468 struct mlx4_ib_demux_pv_qp *tun_qp; 469 struct mlx4_rcv_tunnel_mad *tun_mad; 470 struct ib_ah_attr attr; 471 struct ib_ah *ah; 472 struct ib_qp *src_qp = NULL; 473 unsigned tun_tx_ix = 0; 474 int dqpn; 475 int ret = 0; 476 u16 tun_pkey_ix; 477 u16 cached_pkey; 478 u8 is_eth = dev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH; 479 480 if (dest_qpt > IB_QPT_GSI) 481 return -EINVAL; 482 483 tun_ctx = dev->sriov.demux[port-1].tun[slave]; 484 485 /* check if proxy qp created */ 486 if (!tun_ctx || tun_ctx->state != DEMUX_PV_STATE_ACTIVE) 487 return -EAGAIN; 488 489 if (!dest_qpt) 490 tun_qp = &tun_ctx->qp[0]; 491 else 492 tun_qp = &tun_ctx->qp[1]; 493 494 /* compute P_Key index to put in tunnel header for slave */ 495 if (dest_qpt) { 496 u16 pkey_ix; 497 ret = ib_get_cached_pkey(&dev->ib_dev, port, wc->pkey_index, &cached_pkey); 498 if (ret) 499 return -EINVAL; 500 501 ret = find_slave_port_pkey_ix(dev, slave, port, cached_pkey, &pkey_ix); 502 if (ret) 503 return -EINVAL; 504 tun_pkey_ix = pkey_ix; 505 } else 506 tun_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 507 508 dqpn = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave + port + (dest_qpt * 2) - 1; 509 510 /* get tunnel tx data buf for slave */ 511 src_qp = tun_qp->qp; 512 513 /* create ah. Just need an empty one with the port num for the post send. 514 * The driver will set the force loopback bit in post_send */ 515 memset(&attr, 0, sizeof attr); 516 attr.port_num = port; 517 if (is_eth) { 518 memcpy(&attr.grh.dgid.raw[0], &grh->dgid.raw[0], 16); 519 attr.ah_flags = IB_AH_GRH; 520 } 521 ah = ib_create_ah(tun_ctx->pd, &attr); 522 if (IS_ERR(ah)) 523 return -ENOMEM; 524 525 /* allocate tunnel tx buf after pass failure returns */ 526 spin_lock(&tun_qp->tx_lock); 527 if (tun_qp->tx_ix_head - tun_qp->tx_ix_tail >= 528 (MLX4_NUM_TUNNEL_BUFS - 1)) 529 ret = -EAGAIN; 530 else 531 tun_tx_ix = (++tun_qp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 532 spin_unlock(&tun_qp->tx_lock); 533 if (ret) 534 goto out; 535 536 tun_mad = (struct mlx4_rcv_tunnel_mad *) (tun_qp->tx_ring[tun_tx_ix].buf.addr); 537 if (tun_qp->tx_ring[tun_tx_ix].ah) 538 ib_destroy_ah(tun_qp->tx_ring[tun_tx_ix].ah); 539 tun_qp->tx_ring[tun_tx_ix].ah = ah; 540 ib_dma_sync_single_for_cpu(&dev->ib_dev, 541 tun_qp->tx_ring[tun_tx_ix].buf.map, 542 sizeof (struct mlx4_rcv_tunnel_mad), 543 DMA_TO_DEVICE); 544 545 /* copy over to tunnel buffer */ 546 if (grh) 547 memcpy(&tun_mad->grh, grh, sizeof *grh); 548 memcpy(&tun_mad->mad, mad, sizeof *mad); 549 550 /* adjust tunnel data */ 551 tun_mad->hdr.pkey_index = cpu_to_be16(tun_pkey_ix); 552 tun_mad->hdr.flags_src_qp = cpu_to_be32(wc->src_qp & 0xFFFFFF); 553 tun_mad->hdr.g_ml_path = (grh && (wc->wc_flags & IB_WC_GRH)) ? 0x80 : 0; 554 555 if (is_eth) { 556 u16 vlan = 0; 557 if (mlx4_get_slave_default_vlan(dev->dev, port, slave, &vlan, 558 NULL)) { 559 /* VST mode */ 560 if (vlan != wc->vlan_id) 561 /* Packet vlan is not the VST-assigned vlan. 562 * Drop the packet. 563 */ 564 goto out; 565 else 566 /* Remove the vlan tag before forwarding 567 * the packet to the VF. 568 */ 569 vlan = 0xffff; 570 } else { 571 vlan = wc->vlan_id; 572 } 573 574 tun_mad->hdr.sl_vid = cpu_to_be16(vlan); 575 memcpy((char *)&tun_mad->hdr.mac_31_0, &(wc->smac[0]), 4); 576 memcpy((char *)&tun_mad->hdr.slid_mac_47_32, &(wc->smac[4]), 2); 577 } else { 578 tun_mad->hdr.sl_vid = cpu_to_be16(((u16)(wc->sl)) << 12); 579 tun_mad->hdr.slid_mac_47_32 = cpu_to_be16(wc->slid); 580 } 581 582 ib_dma_sync_single_for_device(&dev->ib_dev, 583 tun_qp->tx_ring[tun_tx_ix].buf.map, 584 sizeof (struct mlx4_rcv_tunnel_mad), 585 DMA_TO_DEVICE); 586 587 list.addr = tun_qp->tx_ring[tun_tx_ix].buf.map; 588 list.length = sizeof (struct mlx4_rcv_tunnel_mad); 589 list.lkey = tun_ctx->mr->lkey; 590 591 wr.wr.ud.ah = ah; 592 wr.wr.ud.port_num = port; 593 wr.wr.ud.remote_qkey = IB_QP_SET_QKEY; 594 wr.wr.ud.remote_qpn = dqpn; 595 wr.next = NULL; 596 wr.wr_id = ((u64) tun_tx_ix) | MLX4_TUN_SET_WRID_QPN(dest_qpt); 597 wr.sg_list = &list; 598 wr.num_sge = 1; 599 wr.opcode = IB_WR_SEND; 600 wr.send_flags = IB_SEND_SIGNALED; 601 602 ret = ib_post_send(src_qp, &wr, &bad_wr); 603out: 604 if (ret) 605 ib_destroy_ah(ah); 606 return ret; 607} 608 609static int mlx4_ib_demux_mad(struct ib_device *ibdev, u8 port, 610 struct ib_wc *wc, struct ib_grh *grh, 611 struct ib_mad *mad) 612{ 613 struct mlx4_ib_dev *dev = to_mdev(ibdev); 614 int err; 615 int slave; 616 u8 *slave_id; 617 int is_eth = 0; 618 619 if (rdma_port_get_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND) 620 is_eth = 0; 621 else 622 is_eth = 1; 623 624 if (is_eth) { 625 if (!(wc->wc_flags & IB_WC_GRH)) { 626 mlx4_ib_warn(ibdev, "RoCE grh not present.\n"); 627 return -EINVAL; 628 } 629 if (mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_CM) { 630 mlx4_ib_warn(ibdev, "RoCE mgmt class is not CM\n"); 631 return -EINVAL; 632 } 633 if (mlx4_get_slave_from_roce_gid(dev->dev, port, grh->dgid.raw, &slave)) { 634 mlx4_ib_warn(ibdev, "failed matching grh\n"); 635 return -ENOENT; 636 } 637 if (slave >= dev->dev->caps.sqp_demux) { 638 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 639 slave, dev->dev->caps.sqp_demux); 640 return -ENOENT; 641 } 642 643 if (mlx4_ib_demux_cm_handler(ibdev, port, NULL, mad)) 644 return 0; 645 646 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 647 if (err) 648 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 649 slave, err); 650 return 0; 651 } 652 653 /* Initially assume that this mad is for us */ 654 slave = mlx4_master_func_num(dev->dev); 655 656 /* See if the slave id is encoded in a response mad */ 657 if (mad->mad_hdr.method & 0x80) { 658 slave_id = (u8 *) &mad->mad_hdr.tid; 659 slave = *slave_id; 660 if (slave != 255) /*255 indicates the dom0*/ 661 *slave_id = 0; /* remap tid */ 662 } 663 664 /* If a grh is present, we demux according to it */ 665 if (wc->wc_flags & IB_WC_GRH) { 666 slave = mlx4_ib_find_real_gid(ibdev, port, grh->dgid.global.interface_id); 667 if (slave < 0) { 668 mlx4_ib_warn(ibdev, "failed matching grh\n"); 669 return -ENOENT; 670 } 671 } 672 /* Class-specific handling */ 673 switch (mad->mad_hdr.mgmt_class) { 674 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 675 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 676 /* 255 indicates the dom0 */ 677 if (slave != 255 && slave != mlx4_master_func_num(dev->dev)) { 678 if (!mlx4_vf_smi_enabled(dev->dev, slave, port)) 679 return -EPERM; 680 /* for a VF. drop unsolicited MADs */ 681 if (!(mad->mad_hdr.method & IB_MGMT_METHOD_RESP)) { 682 mlx4_ib_warn(ibdev, "demux QP0. rejecting unsolicited mad for slave %d class 0x%x, method 0x%x\n", 683 slave, mad->mad_hdr.mgmt_class, 684 mad->mad_hdr.method); 685 return -EINVAL; 686 } 687 } 688 break; 689 case IB_MGMT_CLASS_SUBN_ADM: 690 if (mlx4_ib_demux_sa_handler(ibdev, port, slave, 691 (struct ib_sa_mad *) mad)) 692 return 0; 693 break; 694 case IB_MGMT_CLASS_CM: 695 if (mlx4_ib_demux_cm_handler(ibdev, port, &slave, mad)) 696 return 0; 697 break; 698 case IB_MGMT_CLASS_DEVICE_MGMT: 699 if (mad->mad_hdr.method != IB_MGMT_METHOD_GET_RESP) 700 return 0; 701 break; 702 default: 703 /* Drop unsupported classes for slaves in tunnel mode */ 704 if (slave != mlx4_master_func_num(dev->dev)) { 705 pr_debug("dropping unsupported ingress mad from class:%d " 706 "for slave:%d\n", mad->mad_hdr.mgmt_class, slave); 707 return 0; 708 } 709 } 710 /*make sure that no slave==255 was not handled yet.*/ 711 if (slave >= dev->dev->caps.sqp_demux) { 712 mlx4_ib_warn(ibdev, "slave id: %d is bigger than allowed:%d\n", 713 slave, dev->dev->caps.sqp_demux); 714 return -ENOENT; 715 } 716 717 err = mlx4_ib_send_to_slave(dev, slave, port, wc->qp->qp_type, wc, grh, mad); 718 if (err) 719 pr_debug("failed sending to slave %d via tunnel qp (%d)\n", 720 slave, err); 721 return 0; 722} 723 724static int ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 725 struct ib_wc *in_wc, struct ib_grh *in_grh, 726 struct ib_mad *in_mad, struct ib_mad *out_mad) 727{ 728 u16 slid, prev_lid = 0; 729 int err; 730 struct ib_port_attr pattr; 731 732 if (in_wc && in_wc->qp->qp_num) { 733 pr_debug("received MAD: slid:%d sqpn:%d " 734 "dlid_bits:%d dqpn:%d wc_flags:0x%x, cls %x, mtd %x, atr %x\n", 735 in_wc->slid, in_wc->src_qp, 736 in_wc->dlid_path_bits, 737 in_wc->qp->qp_num, 738 in_wc->wc_flags, 739 in_mad->mad_hdr.mgmt_class, in_mad->mad_hdr.method, 740 be16_to_cpu(in_mad->mad_hdr.attr_id)); 741 if (in_wc->wc_flags & IB_WC_GRH) { 742 pr_debug("sgid_hi:0x%016llx sgid_lo:0x%016llx\n", 743 be64_to_cpu(in_grh->sgid.global.subnet_prefix), 744 be64_to_cpu(in_grh->sgid.global.interface_id)); 745 pr_debug("dgid_hi:0x%016llx dgid_lo:0x%016llx\n", 746 be64_to_cpu(in_grh->dgid.global.subnet_prefix), 747 be64_to_cpu(in_grh->dgid.global.interface_id)); 748 } 749 } 750 751 slid = in_wc ? in_wc->slid : be16_to_cpu(IB_LID_PERMISSIVE); 752 753 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP && slid == 0) { 754 forward_trap(to_mdev(ibdev), port_num, in_mad); 755 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 756 } 757 758 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 759 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) { 760 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 761 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET && 762 in_mad->mad_hdr.method != IB_MGMT_METHOD_TRAP_REPRESS) 763 return IB_MAD_RESULT_SUCCESS; 764 765 /* 766 * Don't process SMInfo queries -- the SMA can't handle them. 767 */ 768 if (in_mad->mad_hdr.attr_id == IB_SMP_ATTR_SM_INFO) 769 return IB_MAD_RESULT_SUCCESS; 770 } else if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_PERF_MGMT || 771 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS1 || 772 in_mad->mad_hdr.mgmt_class == MLX4_IB_VENDOR_CLASS2 || 773 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_CONG_MGMT) { 774 if (in_mad->mad_hdr.method != IB_MGMT_METHOD_GET && 775 in_mad->mad_hdr.method != IB_MGMT_METHOD_SET) 776 return IB_MAD_RESULT_SUCCESS; 777 } else 778 return IB_MAD_RESULT_SUCCESS; 779 780 if ((in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED || 781 in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) && 782 in_mad->mad_hdr.method == IB_MGMT_METHOD_SET && 783 in_mad->mad_hdr.attr_id == IB_SMP_ATTR_PORT_INFO && 784 !ib_query_port(ibdev, port_num, &pattr)) 785 prev_lid = pattr.lid; 786 787 err = mlx4_MAD_IFC(to_mdev(ibdev), 788 (mad_flags & IB_MAD_IGNORE_MKEY ? MLX4_MAD_IFC_IGNORE_MKEY : 0) | 789 (mad_flags & IB_MAD_IGNORE_BKEY ? MLX4_MAD_IFC_IGNORE_BKEY : 0) | 790 MLX4_MAD_IFC_NET_VIEW, 791 port_num, in_wc, in_grh, in_mad, out_mad); 792 if (err) 793 return IB_MAD_RESULT_FAILURE; 794 795 if (!out_mad->mad_hdr.status) { 796 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)) 797 smp_snoop(ibdev, port_num, in_mad, prev_lid); 798 /* slaves get node desc from FW */ 799 if (!mlx4_is_slave(to_mdev(ibdev)->dev)) 800 node_desc_override(ibdev, out_mad); 801 } 802 803 /* set return bit in status of directed route responses */ 804 if (in_mad->mad_hdr.mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) 805 out_mad->mad_hdr.status |= cpu_to_be16(1 << 15); 806 807 if (in_mad->mad_hdr.method == IB_MGMT_METHOD_TRAP_REPRESS) 808 /* no response for trap repress */ 809 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_CONSUMED; 810 811 return IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 812} 813 814static void edit_counter(struct mlx4_counter *cnt, 815 struct ib_pma_portcounters *pma_cnt) 816{ 817 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_data, 818 (be64_to_cpu(cnt->tx_bytes) >> 2)); 819 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_data, 820 (be64_to_cpu(cnt->rx_bytes) >> 2)); 821 ASSIGN_32BIT_COUNTER(pma_cnt->port_xmit_packets, 822 be64_to_cpu(cnt->tx_frames)); 823 ASSIGN_32BIT_COUNTER(pma_cnt->port_rcv_packets, 824 be64_to_cpu(cnt->rx_frames)); 825} 826 827static int iboe_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 828 struct ib_wc *in_wc, struct ib_grh *in_grh, 829 struct ib_mad *in_mad, struct ib_mad *out_mad) 830{ 831 struct mlx4_cmd_mailbox *mailbox; 832 struct mlx4_ib_dev *dev = to_mdev(ibdev); 833 int err; 834 u32 inmod = dev->counters[port_num - 1] & 0xffff; 835 u8 mode; 836 837 if (in_mad->mad_hdr.mgmt_class != IB_MGMT_CLASS_PERF_MGMT) 838 return -EINVAL; 839 840 mailbox = mlx4_alloc_cmd_mailbox(dev->dev); 841 if (IS_ERR(mailbox)) 842 return IB_MAD_RESULT_FAILURE; 843 844 err = mlx4_cmd_box(dev->dev, 0, mailbox->dma, inmod, 0, 845 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C, 846 MLX4_CMD_WRAPPED); 847 if (err) 848 err = IB_MAD_RESULT_FAILURE; 849 else { 850 memset(out_mad->data, 0, sizeof out_mad->data); 851 mode = ((struct mlx4_counter *)mailbox->buf)->counter_mode; 852 switch (mode & 0xf) { 853 case 0: 854 edit_counter(mailbox->buf, 855 (void *)(out_mad->data + 40)); 856 err = IB_MAD_RESULT_SUCCESS | IB_MAD_RESULT_REPLY; 857 break; 858 default: 859 err = IB_MAD_RESULT_FAILURE; 860 } 861 } 862 863 mlx4_free_cmd_mailbox(dev->dev, mailbox); 864 865 return err; 866} 867 868int mlx4_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 869 struct ib_wc *in_wc, struct ib_grh *in_grh, 870 struct ib_mad *in_mad, struct ib_mad *out_mad) 871{ 872 switch (rdma_port_get_link_layer(ibdev, port_num)) { 873 case IB_LINK_LAYER_INFINIBAND: 874 return ib_process_mad(ibdev, mad_flags, port_num, in_wc, 875 in_grh, in_mad, out_mad); 876 case IB_LINK_LAYER_ETHERNET: 877 return iboe_process_mad(ibdev, mad_flags, port_num, in_wc, 878 in_grh, in_mad, out_mad); 879 default: 880 return -EINVAL; 881 } 882} 883 884static void send_handler(struct ib_mad_agent *agent, 885 struct ib_mad_send_wc *mad_send_wc) 886{ 887 if (mad_send_wc->send_buf->context[0]) 888 ib_destroy_ah(mad_send_wc->send_buf->context[0]); 889 ib_free_send_mad(mad_send_wc->send_buf); 890} 891 892int mlx4_ib_mad_init(struct mlx4_ib_dev *dev) 893{ 894 struct ib_mad_agent *agent; 895 int p, q; 896 int ret; 897 enum rdma_link_layer ll; 898 899 for (p = 0; p < dev->num_ports; ++p) { 900 ll = rdma_port_get_link_layer(&dev->ib_dev, p + 1); 901 for (q = 0; q <= 1; ++q) { 902 if (ll == IB_LINK_LAYER_INFINIBAND) { 903 agent = ib_register_mad_agent(&dev->ib_dev, p + 1, 904 q ? IB_QPT_GSI : IB_QPT_SMI, 905 NULL, 0, send_handler, 906 NULL, NULL, 0); 907 if (IS_ERR(agent)) { 908 ret = PTR_ERR(agent); 909 goto err; 910 } 911 dev->send_agent[p][q] = agent; 912 } else 913 dev->send_agent[p][q] = NULL; 914 } 915 } 916 917 return 0; 918 919err: 920 for (p = 0; p < dev->num_ports; ++p) 921 for (q = 0; q <= 1; ++q) 922 if (dev->send_agent[p][q]) 923 ib_unregister_mad_agent(dev->send_agent[p][q]); 924 925 return ret; 926} 927 928void mlx4_ib_mad_cleanup(struct mlx4_ib_dev *dev) 929{ 930 struct ib_mad_agent *agent; 931 int p, q; 932 933 for (p = 0; p < dev->num_ports; ++p) { 934 for (q = 0; q <= 1; ++q) { 935 agent = dev->send_agent[p][q]; 936 if (agent) { 937 dev->send_agent[p][q] = NULL; 938 ib_unregister_mad_agent(agent); 939 } 940 } 941 942 if (dev->sm_ah[p]) 943 ib_destroy_ah(dev->sm_ah[p]); 944 } 945} 946 947static void handle_lid_change_event(struct mlx4_ib_dev *dev, u8 port_num) 948{ 949 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_LID_CHANGE); 950 951 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 952 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 953 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK); 954} 955 956static void handle_client_rereg_event(struct mlx4_ib_dev *dev, u8 port_num) 957{ 958 /* re-configure the alias-guid and mcg's */ 959 if (mlx4_is_master(dev->dev)) { 960 mlx4_ib_invalidate_all_guid_record(dev, port_num); 961 962 if (!dev->sriov.is_going_down) { 963 mlx4_ib_mcg_port_cleanup(&dev->sriov.demux[port_num - 1], 0); 964 mlx4_gen_slaves_port_mgt_ev(dev->dev, port_num, 965 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK); 966 } 967 } 968 mlx4_ib_dispatch_event(dev, port_num, IB_EVENT_CLIENT_REREGISTER); 969} 970 971static void propagate_pkey_ev(struct mlx4_ib_dev *dev, int port_num, 972 struct mlx4_eqe *eqe) 973{ 974 __propagate_pkey_ev(dev, port_num, GET_BLK_PTR_FROM_EQE(eqe), 975 GET_MASK_FROM_EQE(eqe)); 976} 977 978static void handle_slaves_guid_change(struct mlx4_ib_dev *dev, u8 port_num, 979 u32 guid_tbl_blk_num, u32 change_bitmap) 980{ 981 struct ib_smp *in_mad = NULL; 982 struct ib_smp *out_mad = NULL; 983 u16 i; 984 985 if (!mlx4_is_mfunc(dev->dev) || !mlx4_is_master(dev->dev)) 986 return; 987 988 in_mad = kmalloc(sizeof *in_mad, GFP_KERNEL); 989 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL); 990 if (!in_mad || !out_mad) { 991 mlx4_ib_warn(&dev->ib_dev, "failed to allocate memory for guid info mads\n"); 992 goto out; 993 } 994 995 guid_tbl_blk_num *= 4; 996 997 for (i = 0; i < 4; i++) { 998 if (change_bitmap && (!((change_bitmap >> (8 * i)) & 0xff))) 999 continue; 1000 memset(in_mad, 0, sizeof *in_mad); 1001 memset(out_mad, 0, sizeof *out_mad); 1002 1003 in_mad->base_version = 1; 1004 in_mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1005 in_mad->class_version = 1; 1006 in_mad->method = IB_MGMT_METHOD_GET; 1007 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO; 1008 in_mad->attr_mod = cpu_to_be32(guid_tbl_blk_num + i); 1009 1010 if (mlx4_MAD_IFC(dev, 1011 MLX4_MAD_IFC_IGNORE_KEYS | MLX4_MAD_IFC_NET_VIEW, 1012 port_num, NULL, NULL, in_mad, out_mad)) { 1013 mlx4_ib_warn(&dev->ib_dev, "Failed in get GUID INFO MAD_IFC\n"); 1014 goto out; 1015 } 1016 1017 mlx4_ib_update_cache_on_guid_change(dev, guid_tbl_blk_num + i, 1018 port_num, 1019 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1020 mlx4_ib_notify_slaves_on_guid_change(dev, guid_tbl_blk_num + i, 1021 port_num, 1022 (u8 *)(&((struct ib_smp *)out_mad)->data)); 1023 } 1024 1025out: 1026 kfree(in_mad); 1027 kfree(out_mad); 1028 return; 1029} 1030 1031void handle_port_mgmt_change_event(struct work_struct *work) 1032{ 1033 struct ib_event_work *ew = container_of(work, struct ib_event_work, work); 1034 struct mlx4_ib_dev *dev = ew->ib_dev; 1035 struct mlx4_eqe *eqe = &(ew->ib_eqe); 1036 u8 port = eqe->event.port_mgmt_change.port; 1037 u32 changed_attr; 1038 u32 tbl_block; 1039 u32 change_bitmap; 1040 1041 switch (eqe->subtype) { 1042 case MLX4_DEV_PMC_SUBTYPE_PORT_INFO: 1043 changed_attr = be32_to_cpu(eqe->event.port_mgmt_change.params.port_info.changed_attr); 1044 1045 /* Update the SM ah - This should be done before handling 1046 the other changed attributes so that MADs can be sent to the SM */ 1047 if (changed_attr & MSTR_SM_CHANGE_MASK) { 1048 u16 lid = be16_to_cpu(eqe->event.port_mgmt_change.params.port_info.mstr_sm_lid); 1049 u8 sl = eqe->event.port_mgmt_change.params.port_info.mstr_sm_sl & 0xf; 1050 update_sm_ah(dev, port, lid, sl); 1051 } 1052 1053 /* Check if it is a lid change event */ 1054 if (changed_attr & MLX4_EQ_PORT_INFO_LID_CHANGE_MASK) 1055 handle_lid_change_event(dev, port); 1056 1057 /* Generate GUID changed event */ 1058 if (changed_attr & MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK) { 1059 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1060 /*if master, notify all slaves*/ 1061 if (mlx4_is_master(dev->dev)) 1062 mlx4_gen_slaves_port_mgt_ev(dev->dev, port, 1063 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK); 1064 } 1065 1066 if (changed_attr & MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK) 1067 handle_client_rereg_event(dev, port); 1068 break; 1069 1070 case MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE: 1071 mlx4_ib_dispatch_event(dev, port, IB_EVENT_PKEY_CHANGE); 1072 if (mlx4_is_master(dev->dev) && !dev->sriov.is_going_down) 1073 propagate_pkey_ev(dev, port, eqe); 1074 break; 1075 case MLX4_DEV_PMC_SUBTYPE_GUID_INFO: 1076 /* paravirtualized master's guid is guid 0 -- does not change */ 1077 if (!mlx4_is_master(dev->dev)) 1078 mlx4_ib_dispatch_event(dev, port, IB_EVENT_GID_CHANGE); 1079 /*if master, notify relevant slaves*/ 1080 else if (!dev->sriov.is_going_down) { 1081 tbl_block = GET_BLK_PTR_FROM_EQE(eqe); 1082 change_bitmap = GET_MASK_FROM_EQE(eqe); 1083 handle_slaves_guid_change(dev, port, tbl_block, change_bitmap); 1084 } 1085 break; 1086 default: 1087 pr_warn("Unsupported subtype 0x%x for " 1088 "Port Management Change event\n", eqe->subtype); 1089 } 1090 1091 kfree(ew); 1092} 1093 1094void mlx4_ib_dispatch_event(struct mlx4_ib_dev *dev, u8 port_num, 1095 enum ib_event_type type) 1096{ 1097 struct ib_event event; 1098 1099 event.device = &dev->ib_dev; 1100 event.element.port_num = port_num; 1101 event.event = type; 1102 1103 ib_dispatch_event(&event); 1104} 1105 1106static void mlx4_ib_tunnel_comp_handler(struct ib_cq *cq, void *arg) 1107{ 1108 unsigned long flags; 1109 struct mlx4_ib_demux_pv_ctx *ctx = cq->cq_context; 1110 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1111 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 1112 if (!dev->sriov.is_going_down && ctx->state == DEMUX_PV_STATE_ACTIVE) 1113 queue_work(ctx->wq, &ctx->work); 1114 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 1115} 1116 1117static int mlx4_ib_post_pv_qp_buf(struct mlx4_ib_demux_pv_ctx *ctx, 1118 struct mlx4_ib_demux_pv_qp *tun_qp, 1119 int index) 1120{ 1121 struct ib_sge sg_list; 1122 struct ib_recv_wr recv_wr, *bad_recv_wr; 1123 int size; 1124 1125 size = (tun_qp->qp->qp_type == IB_QPT_UD) ? 1126 sizeof (struct mlx4_tunnel_mad) : sizeof (struct mlx4_mad_rcv_buf); 1127 1128 sg_list.addr = tun_qp->ring[index].map; 1129 sg_list.length = size; 1130 sg_list.lkey = ctx->mr->lkey; 1131 1132 recv_wr.next = NULL; 1133 recv_wr.sg_list = &sg_list; 1134 recv_wr.num_sge = 1; 1135 recv_wr.wr_id = (u64) index | MLX4_TUN_WRID_RECV | 1136 MLX4_TUN_SET_WRID_QPN(tun_qp->proxy_qpt); 1137 ib_dma_sync_single_for_device(ctx->ib_dev, tun_qp->ring[index].map, 1138 size, DMA_FROM_DEVICE); 1139 return ib_post_recv(tun_qp->qp, &recv_wr, &bad_recv_wr); 1140} 1141 1142static int mlx4_ib_multiplex_sa_handler(struct ib_device *ibdev, int port, 1143 int slave, struct ib_sa_mad *sa_mad) 1144{ 1145 int ret = 0; 1146 1147 /* dispatch to different sa handlers */ 1148 switch (be16_to_cpu(sa_mad->mad_hdr.attr_id)) { 1149 case IB_SA_ATTR_MC_MEMBER_REC: 1150 ret = mlx4_ib_mcg_multiplex_handler(ibdev, port, slave, sa_mad); 1151 break; 1152 default: 1153 break; 1154 } 1155 return ret; 1156} 1157 1158static int is_proxy_qp0(struct mlx4_ib_dev *dev, int qpn, int slave) 1159{ 1160 int proxy_start = dev->dev->phys_caps.base_proxy_sqpn + 8 * slave; 1161 1162 return (qpn >= proxy_start && qpn <= proxy_start + 1); 1163} 1164 1165 1166int mlx4_ib_send_to_wire(struct mlx4_ib_dev *dev, int slave, u8 port, 1167 enum ib_qp_type dest_qpt, u16 pkey_index, 1168 u32 remote_qpn, u32 qkey, struct ib_ah_attr *attr, 1169 u8 *s_mac, struct ib_mad *mad) 1170{ 1171 struct ib_sge list; 1172 struct ib_send_wr wr, *bad_wr; 1173 struct mlx4_ib_demux_pv_ctx *sqp_ctx; 1174 struct mlx4_ib_demux_pv_qp *sqp; 1175 struct mlx4_mad_snd_buf *sqp_mad; 1176 struct ib_ah *ah; 1177 struct ib_qp *send_qp = NULL; 1178 unsigned wire_tx_ix = 0; 1179 int ret = 0; 1180 u16 wire_pkey_ix; 1181 int src_qpnum; 1182 u8 sgid_index; 1183 1184 1185 sqp_ctx = dev->sriov.sqps[port-1]; 1186 1187 /* check if proxy qp created */ 1188 if (!sqp_ctx || sqp_ctx->state != DEMUX_PV_STATE_ACTIVE) 1189 return -EAGAIN; 1190 1191 if (dest_qpt == IB_QPT_SMI) { 1192 src_qpnum = 0; 1193 sqp = &sqp_ctx->qp[0]; 1194 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][0]; 1195 } else { 1196 src_qpnum = 1; 1197 sqp = &sqp_ctx->qp[1]; 1198 wire_pkey_ix = dev->pkeys.virt2phys_pkey[slave][port - 1][pkey_index]; 1199 } 1200 1201 send_qp = sqp->qp; 1202 1203 /* create ah */ 1204 sgid_index = attr->grh.sgid_index; 1205 attr->grh.sgid_index = 0; 1206 ah = ib_create_ah(sqp_ctx->pd, attr); 1207 if (IS_ERR(ah)) 1208 return -ENOMEM; 1209 attr->grh.sgid_index = sgid_index; 1210 to_mah(ah)->av.ib.gid_index = sgid_index; 1211 /* get rid of force-loopback bit */ 1212 to_mah(ah)->av.ib.port_pd &= cpu_to_be32(0x7FFFFFFF); 1213 spin_lock(&sqp->tx_lock); 1214 if (sqp->tx_ix_head - sqp->tx_ix_tail >= 1215 (MLX4_NUM_TUNNEL_BUFS - 1)) 1216 ret = -EAGAIN; 1217 else 1218 wire_tx_ix = (++sqp->tx_ix_head) & (MLX4_NUM_TUNNEL_BUFS - 1); 1219 spin_unlock(&sqp->tx_lock); 1220 if (ret) 1221 goto out; 1222 1223 sqp_mad = (struct mlx4_mad_snd_buf *) (sqp->tx_ring[wire_tx_ix].buf.addr); 1224 if (sqp->tx_ring[wire_tx_ix].ah) 1225 ib_destroy_ah(sqp->tx_ring[wire_tx_ix].ah); 1226 sqp->tx_ring[wire_tx_ix].ah = ah; 1227 ib_dma_sync_single_for_cpu(&dev->ib_dev, 1228 sqp->tx_ring[wire_tx_ix].buf.map, 1229 sizeof (struct mlx4_mad_snd_buf), 1230 DMA_TO_DEVICE); 1231 1232 memcpy(&sqp_mad->payload, mad, sizeof *mad); 1233 1234 ib_dma_sync_single_for_device(&dev->ib_dev, 1235 sqp->tx_ring[wire_tx_ix].buf.map, 1236 sizeof (struct mlx4_mad_snd_buf), 1237 DMA_TO_DEVICE); 1238 1239 list.addr = sqp->tx_ring[wire_tx_ix].buf.map; 1240 list.length = sizeof (struct mlx4_mad_snd_buf); 1241 list.lkey = sqp_ctx->mr->lkey; 1242 1243 wr.wr.ud.ah = ah; 1244 wr.wr.ud.port_num = port; 1245 wr.wr.ud.pkey_index = wire_pkey_ix; 1246 wr.wr.ud.remote_qkey = qkey; 1247 wr.wr.ud.remote_qpn = remote_qpn; 1248 wr.next = NULL; 1249 wr.wr_id = ((u64) wire_tx_ix) | MLX4_TUN_SET_WRID_QPN(src_qpnum); 1250 wr.sg_list = &list; 1251 wr.num_sge = 1; 1252 wr.opcode = IB_WR_SEND; 1253 wr.send_flags = IB_SEND_SIGNALED; 1254 if (s_mac) 1255 memcpy(to_mah(ah)->av.eth.s_mac, s_mac, 6); 1256 1257 1258 ret = ib_post_send(send_qp, &wr, &bad_wr); 1259out: 1260 if (ret) 1261 ib_destroy_ah(ah); 1262 return ret; 1263} 1264 1265static int get_slave_base_gid_ix(struct mlx4_ib_dev *dev, int slave, int port) 1266{ 1267 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1268 return slave; 1269 return mlx4_get_base_gid_ix(dev->dev, slave, port); 1270} 1271 1272static void fill_in_real_sgid_index(struct mlx4_ib_dev *dev, int slave, int port, 1273 struct ib_ah_attr *ah_attr) 1274{ 1275 if (rdma_port_get_link_layer(&dev->ib_dev, port) == IB_LINK_LAYER_INFINIBAND) 1276 ah_attr->grh.sgid_index = slave; 1277 else 1278 ah_attr->grh.sgid_index += get_slave_base_gid_ix(dev, slave, port); 1279} 1280 1281static void mlx4_ib_multiplex_mad(struct mlx4_ib_demux_pv_ctx *ctx, struct ib_wc *wc) 1282{ 1283 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 1284 struct mlx4_ib_demux_pv_qp *tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc->wr_id)]; 1285 int wr_ix = wc->wr_id & (MLX4_NUM_TUNNEL_BUFS - 1); 1286 struct mlx4_tunnel_mad *tunnel = tun_qp->ring[wr_ix].addr; 1287 struct mlx4_ib_ah ah; 1288 struct ib_ah_attr ah_attr; 1289 u8 *slave_id; 1290 int slave; 1291 int port; 1292 1293 /* Get slave that sent this packet */ 1294 if (wc->src_qp < dev->dev->phys_caps.base_proxy_sqpn || 1295 wc->src_qp >= dev->dev->phys_caps.base_proxy_sqpn + 8 * MLX4_MFUNC_MAX || 1296 (wc->src_qp & 0x1) != ctx->port - 1 || 1297 wc->src_qp & 0x4) { 1298 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d\n", wc->src_qp); 1299 return; 1300 } 1301 slave = ((wc->src_qp & ~0x7) - dev->dev->phys_caps.base_proxy_sqpn) / 8; 1302 if (slave != ctx->slave) { 1303 mlx4_ib_warn(ctx->ib_dev, "can't multiplex bad sqp:%d: " 1304 "belongs to another slave\n", wc->src_qp); 1305 return; 1306 } 1307 1308 /* Map transaction ID */ 1309 ib_dma_sync_single_for_cpu(ctx->ib_dev, tun_qp->ring[wr_ix].map, 1310 sizeof (struct mlx4_tunnel_mad), 1311 DMA_FROM_DEVICE); 1312 switch (tunnel->mad.mad_hdr.method) { 1313 case IB_MGMT_METHOD_SET: 1314 case IB_MGMT_METHOD_GET: 1315 case IB_MGMT_METHOD_REPORT: 1316 case IB_SA_METHOD_GET_TABLE: 1317 case IB_SA_METHOD_DELETE: 1318 case IB_SA_METHOD_GET_MULTI: 1319 case IB_SA_METHOD_GET_TRACE_TBL: 1320 slave_id = (u8 *) &tunnel->mad.mad_hdr.tid; 1321 if (*slave_id) { 1322 mlx4_ib_warn(ctx->ib_dev, "egress mad has non-null tid msb:%d " 1323 "class:%d slave:%d\n", *slave_id, 1324 tunnel->mad.mad_hdr.mgmt_class, slave); 1325 return; 1326 } else 1327 *slave_id = slave; 1328 default: 1329 /* nothing */; 1330 } 1331 1332 /* Class-specific handling */ 1333 switch (tunnel->mad.mad_hdr.mgmt_class) { 1334 case IB_MGMT_CLASS_SUBN_LID_ROUTED: 1335 case IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE: 1336 if (slave != mlx4_master_func_num(dev->dev) && 1337 !mlx4_vf_smi_enabled(dev->dev, slave, ctx->port)) 1338 return; 1339 break; 1340 case IB_MGMT_CLASS_SUBN_ADM: 1341 if (mlx4_ib_multiplex_sa_handler(ctx->ib_dev, ctx->port, slave, 1342 (struct ib_sa_mad *) &tunnel->mad)) 1343 return; 1344 break; 1345 case IB_MGMT_CLASS_CM: 1346 if (mlx4_ib_multiplex_cm_handler(ctx->ib_dev, ctx->port, slave, 1347 (struct ib_mad *) &tunnel->mad)) 1348 return; 1349 break; 1350 case IB_MGMT_CLASS_DEVICE_MGMT: 1351 if (tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_GET && 1352 tunnel->mad.mad_hdr.method != IB_MGMT_METHOD_SET) 1353 return; 1354 break; 1355 default: 1356 /* Drop unsupported classes for slaves in tunnel mode */ 1357 if (slave != mlx4_master_func_num(dev->dev)) { 1358 mlx4_ib_warn(ctx->ib_dev, "dropping unsupported egress mad from class:%d " 1359 "for slave:%d\n", tunnel->mad.mad_hdr.mgmt_class, slave); 1360 return; 1361 } 1362 } 1363 1364 /* We are using standard ib_core services to send the mad, so generate a 1365 * stadard address handle by decoding the tunnelled mlx4_ah fields */ 1366 memcpy(&ah.av, &tunnel->hdr.av, sizeof (struct mlx4_av)); 1367 ah.ibah.device = ctx->ib_dev; 1368 mlx4_ib_query_ah(&ah.ibah, &ah_attr); 1369 if (ah_attr.ah_flags & IB_AH_GRH) 1370 fill_in_real_sgid_index(dev, slave, ctx->port, &ah_attr); 1371 1372 port = mlx4_slave_convert_port(dev->dev, slave, ah_attr.port_num); 1373 if (port < 0) 1374 return; 1375 ah_attr.port_num = port; 1376 memcpy(ah_attr.dmac, tunnel->hdr.mac, 6); 1377 ah_attr.vlan_id = be16_to_cpu(tunnel->hdr.vlan); 1378 /* if slave have default vlan use it */ 1379 mlx4_get_slave_default_vlan(dev->dev, ctx->port, slave, 1380 &ah_attr.vlan_id, &ah_attr.sl); 1381 1382 mlx4_ib_send_to_wire(dev, slave, ctx->port, 1383 is_proxy_qp0(dev, wc->src_qp, slave) ? 1384 IB_QPT_SMI : IB_QPT_GSI, 1385 be16_to_cpu(tunnel->hdr.pkey_index), 1386 be32_to_cpu(tunnel->hdr.remote_qpn), 1387 be32_to_cpu(tunnel->hdr.qkey), 1388 &ah_attr, wc->smac, &tunnel->mad); 1389} 1390 1391static int mlx4_ib_alloc_pv_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1392 enum ib_qp_type qp_type, int is_tun) 1393{ 1394 int i; 1395 struct mlx4_ib_demux_pv_qp *tun_qp; 1396 int rx_buf_size, tx_buf_size; 1397 1398 if (qp_type > IB_QPT_GSI) 1399 return -EINVAL; 1400 1401 tun_qp = &ctx->qp[qp_type]; 1402 1403 tun_qp->ring = kzalloc(sizeof (struct mlx4_ib_buf) * MLX4_NUM_TUNNEL_BUFS, 1404 GFP_KERNEL); 1405 if (!tun_qp->ring) 1406 return -ENOMEM; 1407 1408 tun_qp->tx_ring = kcalloc(MLX4_NUM_TUNNEL_BUFS, 1409 sizeof (struct mlx4_ib_tun_tx_buf), 1410 GFP_KERNEL); 1411 if (!tun_qp->tx_ring) { 1412 kfree(tun_qp->ring); 1413 tun_qp->ring = NULL; 1414 return -ENOMEM; 1415 } 1416 1417 if (is_tun) { 1418 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1419 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1420 } else { 1421 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1422 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1423 } 1424 1425 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1426 tun_qp->ring[i].addr = kmalloc(rx_buf_size, GFP_KERNEL); 1427 if (!tun_qp->ring[i].addr) 1428 goto err; 1429 tun_qp->ring[i].map = ib_dma_map_single(ctx->ib_dev, 1430 tun_qp->ring[i].addr, 1431 rx_buf_size, 1432 DMA_FROM_DEVICE); 1433 if (ib_dma_mapping_error(ctx->ib_dev, tun_qp->ring[i].map)) { 1434 kfree(tun_qp->ring[i].addr); 1435 goto err; 1436 } 1437 } 1438 1439 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1440 tun_qp->tx_ring[i].buf.addr = 1441 kmalloc(tx_buf_size, GFP_KERNEL); 1442 if (!tun_qp->tx_ring[i].buf.addr) 1443 goto tx_err; 1444 tun_qp->tx_ring[i].buf.map = 1445 ib_dma_map_single(ctx->ib_dev, 1446 tun_qp->tx_ring[i].buf.addr, 1447 tx_buf_size, 1448 DMA_TO_DEVICE); 1449 if (ib_dma_mapping_error(ctx->ib_dev, 1450 tun_qp->tx_ring[i].buf.map)) { 1451 kfree(tun_qp->tx_ring[i].buf.addr); 1452 goto tx_err; 1453 } 1454 tun_qp->tx_ring[i].ah = NULL; 1455 } 1456 spin_lock_init(&tun_qp->tx_lock); 1457 tun_qp->tx_ix_head = 0; 1458 tun_qp->tx_ix_tail = 0; 1459 tun_qp->proxy_qpt = qp_type; 1460 1461 return 0; 1462 1463tx_err: 1464 while (i > 0) { 1465 --i; 1466 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1467 tx_buf_size, DMA_TO_DEVICE); 1468 kfree(tun_qp->tx_ring[i].buf.addr); 1469 } 1470 kfree(tun_qp->tx_ring); 1471 tun_qp->tx_ring = NULL; 1472 i = MLX4_NUM_TUNNEL_BUFS; 1473err: 1474 while (i > 0) { 1475 --i; 1476 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1477 rx_buf_size, DMA_FROM_DEVICE); 1478 kfree(tun_qp->ring[i].addr); 1479 } 1480 kfree(tun_qp->ring); 1481 tun_qp->ring = NULL; 1482 return -ENOMEM; 1483} 1484 1485static void mlx4_ib_free_pv_qp_bufs(struct mlx4_ib_demux_pv_ctx *ctx, 1486 enum ib_qp_type qp_type, int is_tun) 1487{ 1488 int i; 1489 struct mlx4_ib_demux_pv_qp *tun_qp; 1490 int rx_buf_size, tx_buf_size; 1491 1492 if (qp_type > IB_QPT_GSI) 1493 return; 1494 1495 tun_qp = &ctx->qp[qp_type]; 1496 if (is_tun) { 1497 rx_buf_size = sizeof (struct mlx4_tunnel_mad); 1498 tx_buf_size = sizeof (struct mlx4_rcv_tunnel_mad); 1499 } else { 1500 rx_buf_size = sizeof (struct mlx4_mad_rcv_buf); 1501 tx_buf_size = sizeof (struct mlx4_mad_snd_buf); 1502 } 1503 1504 1505 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1506 ib_dma_unmap_single(ctx->ib_dev, tun_qp->ring[i].map, 1507 rx_buf_size, DMA_FROM_DEVICE); 1508 kfree(tun_qp->ring[i].addr); 1509 } 1510 1511 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1512 ib_dma_unmap_single(ctx->ib_dev, tun_qp->tx_ring[i].buf.map, 1513 tx_buf_size, DMA_TO_DEVICE); 1514 kfree(tun_qp->tx_ring[i].buf.addr); 1515 if (tun_qp->tx_ring[i].ah) 1516 ib_destroy_ah(tun_qp->tx_ring[i].ah); 1517 } 1518 kfree(tun_qp->tx_ring); 1519 kfree(tun_qp->ring); 1520} 1521 1522static void mlx4_ib_tunnel_comp_worker(struct work_struct *work) 1523{ 1524 struct mlx4_ib_demux_pv_ctx *ctx; 1525 struct mlx4_ib_demux_pv_qp *tun_qp; 1526 struct ib_wc wc; 1527 int ret; 1528 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1529 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1530 1531 while (ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1532 tun_qp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1533 if (wc.status == IB_WC_SUCCESS) { 1534 switch (wc.opcode) { 1535 case IB_WC_RECV: 1536 mlx4_ib_multiplex_mad(ctx, &wc); 1537 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, 1538 wc.wr_id & 1539 (MLX4_NUM_TUNNEL_BUFS - 1)); 1540 if (ret) 1541 pr_err("Failed reposting tunnel " 1542 "buf:%lld\n", wc.wr_id); 1543 break; 1544 case IB_WC_SEND: 1545 pr_debug("received tunnel send completion:" 1546 "wrid=0x%llx, status=0x%x\n", 1547 wc.wr_id, wc.status); 1548 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1549 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1550 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1551 = NULL; 1552 spin_lock(&tun_qp->tx_lock); 1553 tun_qp->tx_ix_tail++; 1554 spin_unlock(&tun_qp->tx_lock); 1555 1556 break; 1557 default: 1558 break; 1559 } 1560 } else { 1561 pr_debug("mlx4_ib: completion error in tunnel: %d." 1562 " status = %d, wrid = 0x%llx\n", 1563 ctx->slave, wc.status, wc.wr_id); 1564 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1565 ib_destroy_ah(tun_qp->tx_ring[wc.wr_id & 1566 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1567 tun_qp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1568 = NULL; 1569 spin_lock(&tun_qp->tx_lock); 1570 tun_qp->tx_ix_tail++; 1571 spin_unlock(&tun_qp->tx_lock); 1572 } 1573 } 1574 } 1575} 1576 1577static void pv_qp_event_handler(struct ib_event *event, void *qp_context) 1578{ 1579 struct mlx4_ib_demux_pv_ctx *sqp = qp_context; 1580 1581 /* It's worse than that! He's dead, Jim! */ 1582 pr_err("Fatal error (%d) on a MAD QP on port %d\n", 1583 event->event, sqp->port); 1584} 1585 1586static int create_pv_sqp(struct mlx4_ib_demux_pv_ctx *ctx, 1587 enum ib_qp_type qp_type, int create_tun) 1588{ 1589 int i, ret; 1590 struct mlx4_ib_demux_pv_qp *tun_qp; 1591 struct mlx4_ib_qp_tunnel_init_attr qp_init_attr; 1592 struct ib_qp_attr attr; 1593 int qp_attr_mask_INIT; 1594 1595 if (qp_type > IB_QPT_GSI) 1596 return -EINVAL; 1597 1598 tun_qp = &ctx->qp[qp_type]; 1599 1600 memset(&qp_init_attr, 0, sizeof qp_init_attr); 1601 qp_init_attr.init_attr.send_cq = ctx->cq; 1602 qp_init_attr.init_attr.recv_cq = ctx->cq; 1603 qp_init_attr.init_attr.sq_sig_type = IB_SIGNAL_ALL_WR; 1604 qp_init_attr.init_attr.cap.max_send_wr = MLX4_NUM_TUNNEL_BUFS; 1605 qp_init_attr.init_attr.cap.max_recv_wr = MLX4_NUM_TUNNEL_BUFS; 1606 qp_init_attr.init_attr.cap.max_send_sge = 1; 1607 qp_init_attr.init_attr.cap.max_recv_sge = 1; 1608 if (create_tun) { 1609 qp_init_attr.init_attr.qp_type = IB_QPT_UD; 1610 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_TUNNEL_QP; 1611 qp_init_attr.port = ctx->port; 1612 qp_init_attr.slave = ctx->slave; 1613 qp_init_attr.proxy_qp_type = qp_type; 1614 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | 1615 IB_QP_QKEY | IB_QP_PORT; 1616 } else { 1617 qp_init_attr.init_attr.qp_type = qp_type; 1618 qp_init_attr.init_attr.create_flags = MLX4_IB_SRIOV_SQP; 1619 qp_attr_mask_INIT = IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_QKEY; 1620 } 1621 qp_init_attr.init_attr.port_num = ctx->port; 1622 qp_init_attr.init_attr.qp_context = ctx; 1623 qp_init_attr.init_attr.event_handler = pv_qp_event_handler; 1624 tun_qp->qp = ib_create_qp(ctx->pd, &qp_init_attr.init_attr); 1625 if (IS_ERR(tun_qp->qp)) { 1626 ret = PTR_ERR(tun_qp->qp); 1627 tun_qp->qp = NULL; 1628 pr_err("Couldn't create %s QP (%d)\n", 1629 create_tun ? "tunnel" : "special", ret); 1630 return ret; 1631 } 1632 1633 memset(&attr, 0, sizeof attr); 1634 attr.qp_state = IB_QPS_INIT; 1635 ret = 0; 1636 if (create_tun) 1637 ret = find_slave_port_pkey_ix(to_mdev(ctx->ib_dev), ctx->slave, 1638 ctx->port, IB_DEFAULT_PKEY_FULL, 1639 &attr.pkey_index); 1640 if (ret || !create_tun) 1641 attr.pkey_index = 1642 to_mdev(ctx->ib_dev)->pkeys.virt2phys_pkey[ctx->slave][ctx->port - 1][0]; 1643 attr.qkey = IB_QP1_QKEY; 1644 attr.port_num = ctx->port; 1645 ret = ib_modify_qp(tun_qp->qp, &attr, qp_attr_mask_INIT); 1646 if (ret) { 1647 pr_err("Couldn't change %s qp state to INIT (%d)\n", 1648 create_tun ? "tunnel" : "special", ret); 1649 goto err_qp; 1650 } 1651 attr.qp_state = IB_QPS_RTR; 1652 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE); 1653 if (ret) { 1654 pr_err("Couldn't change %s qp state to RTR (%d)\n", 1655 create_tun ? "tunnel" : "special", ret); 1656 goto err_qp; 1657 } 1658 attr.qp_state = IB_QPS_RTS; 1659 attr.sq_psn = 0; 1660 ret = ib_modify_qp(tun_qp->qp, &attr, IB_QP_STATE | IB_QP_SQ_PSN); 1661 if (ret) { 1662 pr_err("Couldn't change %s qp state to RTS (%d)\n", 1663 create_tun ? "tunnel" : "special", ret); 1664 goto err_qp; 1665 } 1666 1667 for (i = 0; i < MLX4_NUM_TUNNEL_BUFS; i++) { 1668 ret = mlx4_ib_post_pv_qp_buf(ctx, tun_qp, i); 1669 if (ret) { 1670 pr_err(" mlx4_ib_post_pv_buf error" 1671 " (err = %d, i = %d)\n", ret, i); 1672 goto err_qp; 1673 } 1674 } 1675 return 0; 1676 1677err_qp: 1678 ib_destroy_qp(tun_qp->qp); 1679 tun_qp->qp = NULL; 1680 return ret; 1681} 1682 1683/* 1684 * IB MAD completion callback for real SQPs 1685 */ 1686static void mlx4_ib_sqp_comp_worker(struct work_struct *work) 1687{ 1688 struct mlx4_ib_demux_pv_ctx *ctx; 1689 struct mlx4_ib_demux_pv_qp *sqp; 1690 struct ib_wc wc; 1691 struct ib_grh *grh; 1692 struct ib_mad *mad; 1693 1694 ctx = container_of(work, struct mlx4_ib_demux_pv_ctx, work); 1695 ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1696 1697 while (mlx4_ib_poll_cq(ctx->cq, 1, &wc) == 1) { 1698 sqp = &ctx->qp[MLX4_TUN_WRID_QPN(wc.wr_id)]; 1699 if (wc.status == IB_WC_SUCCESS) { 1700 switch (wc.opcode) { 1701 case IB_WC_SEND: 1702 ib_destroy_ah(sqp->tx_ring[wc.wr_id & 1703 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1704 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1705 = NULL; 1706 spin_lock(&sqp->tx_lock); 1707 sqp->tx_ix_tail++; 1708 spin_unlock(&sqp->tx_lock); 1709 break; 1710 case IB_WC_RECV: 1711 mad = (struct ib_mad *) &(((struct mlx4_mad_rcv_buf *) 1712 (sqp->ring[wc.wr_id & 1713 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->payload); 1714 grh = &(((struct mlx4_mad_rcv_buf *) 1715 (sqp->ring[wc.wr_id & 1716 (MLX4_NUM_TUNNEL_BUFS - 1)].addr))->grh); 1717 mlx4_ib_demux_mad(ctx->ib_dev, ctx->port, &wc, grh, mad); 1718 if (mlx4_ib_post_pv_qp_buf(ctx, sqp, wc.wr_id & 1719 (MLX4_NUM_TUNNEL_BUFS - 1))) 1720 pr_err("Failed reposting SQP " 1721 "buf:%lld\n", wc.wr_id); 1722 break; 1723 default: 1724 BUG_ON(1); 1725 break; 1726 } 1727 } else { 1728 pr_debug("mlx4_ib: completion error in tunnel: %d." 1729 " status = %d, wrid = 0x%llx\n", 1730 ctx->slave, wc.status, wc.wr_id); 1731 if (!MLX4_TUN_IS_RECV(wc.wr_id)) { 1732 ib_destroy_ah(sqp->tx_ring[wc.wr_id & 1733 (MLX4_NUM_TUNNEL_BUFS - 1)].ah); 1734 sqp->tx_ring[wc.wr_id & (MLX4_NUM_TUNNEL_BUFS - 1)].ah 1735 = NULL; 1736 spin_lock(&sqp->tx_lock); 1737 sqp->tx_ix_tail++; 1738 spin_unlock(&sqp->tx_lock); 1739 } 1740 } 1741 } 1742} 1743 1744static int alloc_pv_object(struct mlx4_ib_dev *dev, int slave, int port, 1745 struct mlx4_ib_demux_pv_ctx **ret_ctx) 1746{ 1747 struct mlx4_ib_demux_pv_ctx *ctx; 1748 1749 *ret_ctx = NULL; 1750 ctx = kzalloc(sizeof (struct mlx4_ib_demux_pv_ctx), GFP_KERNEL); 1751 if (!ctx) { 1752 pr_err("failed allocating pv resource context " 1753 "for port %d, slave %d\n", port, slave); 1754 return -ENOMEM; 1755 } 1756 1757 ctx->ib_dev = &dev->ib_dev; 1758 ctx->port = port; 1759 ctx->slave = slave; 1760 *ret_ctx = ctx; 1761 return 0; 1762} 1763 1764static void free_pv_object(struct mlx4_ib_dev *dev, int slave, int port) 1765{ 1766 if (dev->sriov.demux[port - 1].tun[slave]) { 1767 kfree(dev->sriov.demux[port - 1].tun[slave]); 1768 dev->sriov.demux[port - 1].tun[slave] = NULL; 1769 } 1770} 1771 1772static int create_pv_resources(struct ib_device *ibdev, int slave, int port, 1773 int create_tun, struct mlx4_ib_demux_pv_ctx *ctx) 1774{ 1775 int ret, cq_size; 1776 1777 if (ctx->state != DEMUX_PV_STATE_DOWN) 1778 return -EEXIST; 1779 1780 ctx->state = DEMUX_PV_STATE_STARTING; 1781 /* have QP0 only if link layer is IB */ 1782 if (rdma_port_get_link_layer(ibdev, ctx->port) == 1783 IB_LINK_LAYER_INFINIBAND) 1784 ctx->has_smi = 1; 1785 1786 if (ctx->has_smi) { 1787 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_SMI, create_tun); 1788 if (ret) { 1789 pr_err("Failed allocating qp0 tunnel bufs (%d)\n", ret); 1790 goto err_out; 1791 } 1792 } 1793 1794 ret = mlx4_ib_alloc_pv_bufs(ctx, IB_QPT_GSI, create_tun); 1795 if (ret) { 1796 pr_err("Failed allocating qp1 tunnel bufs (%d)\n", ret); 1797 goto err_out_qp0; 1798 } 1799 1800 cq_size = 2 * MLX4_NUM_TUNNEL_BUFS; 1801 if (ctx->has_smi) 1802 cq_size *= 2; 1803 1804 ctx->cq = ib_create_cq(ctx->ib_dev, mlx4_ib_tunnel_comp_handler, 1805 NULL, ctx, cq_size, 0); 1806 if (IS_ERR(ctx->cq)) { 1807 ret = PTR_ERR(ctx->cq); 1808 pr_err("Couldn't create tunnel CQ (%d)\n", ret); 1809 goto err_buf; 1810 } 1811 1812 ctx->pd = ib_alloc_pd(ctx->ib_dev); 1813 if (IS_ERR(ctx->pd)) { 1814 ret = PTR_ERR(ctx->pd); 1815 pr_err("Couldn't create tunnel PD (%d)\n", ret); 1816 goto err_cq; 1817 } 1818 1819 ctx->mr = ib_get_dma_mr(ctx->pd, IB_ACCESS_LOCAL_WRITE); 1820 if (IS_ERR(ctx->mr)) { 1821 ret = PTR_ERR(ctx->mr); 1822 pr_err("Couldn't get tunnel DMA MR (%d)\n", ret); 1823 goto err_pd; 1824 } 1825 1826 if (ctx->has_smi) { 1827 ret = create_pv_sqp(ctx, IB_QPT_SMI, create_tun); 1828 if (ret) { 1829 pr_err("Couldn't create %s QP0 (%d)\n", 1830 create_tun ? "tunnel for" : "", ret); 1831 goto err_mr; 1832 } 1833 } 1834 1835 ret = create_pv_sqp(ctx, IB_QPT_GSI, create_tun); 1836 if (ret) { 1837 pr_err("Couldn't create %s QP1 (%d)\n", 1838 create_tun ? "tunnel for" : "", ret); 1839 goto err_qp0; 1840 } 1841 1842 if (create_tun) 1843 INIT_WORK(&ctx->work, mlx4_ib_tunnel_comp_worker); 1844 else 1845 INIT_WORK(&ctx->work, mlx4_ib_sqp_comp_worker); 1846 1847 ctx->wq = to_mdev(ibdev)->sriov.demux[port - 1].wq; 1848 1849 ret = ib_req_notify_cq(ctx->cq, IB_CQ_NEXT_COMP); 1850 if (ret) { 1851 pr_err("Couldn't arm tunnel cq (%d)\n", ret); 1852 goto err_wq; 1853 } 1854 ctx->state = DEMUX_PV_STATE_ACTIVE; 1855 return 0; 1856 1857err_wq: 1858 ctx->wq = NULL; 1859 ib_destroy_qp(ctx->qp[1].qp); 1860 ctx->qp[1].qp = NULL; 1861 1862 1863err_qp0: 1864 if (ctx->has_smi) 1865 ib_destroy_qp(ctx->qp[0].qp); 1866 ctx->qp[0].qp = NULL; 1867 1868err_mr: 1869 ib_dereg_mr(ctx->mr); 1870 ctx->mr = NULL; 1871 1872err_pd: 1873 ib_dealloc_pd(ctx->pd); 1874 ctx->pd = NULL; 1875 1876err_cq: 1877 ib_destroy_cq(ctx->cq); 1878 ctx->cq = NULL; 1879 1880err_buf: 1881 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, create_tun); 1882 1883err_out_qp0: 1884 if (ctx->has_smi) 1885 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, create_tun); 1886err_out: 1887 ctx->state = DEMUX_PV_STATE_DOWN; 1888 return ret; 1889} 1890 1891static void destroy_pv_resources(struct mlx4_ib_dev *dev, int slave, int port, 1892 struct mlx4_ib_demux_pv_ctx *ctx, int flush) 1893{ 1894 if (!ctx) 1895 return; 1896 if (ctx->state > DEMUX_PV_STATE_DOWN) { 1897 ctx->state = DEMUX_PV_STATE_DOWNING; 1898 if (flush) 1899 flush_workqueue(ctx->wq); 1900 if (ctx->has_smi) { 1901 ib_destroy_qp(ctx->qp[0].qp); 1902 ctx->qp[0].qp = NULL; 1903 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_SMI, 1); 1904 } 1905 ib_destroy_qp(ctx->qp[1].qp); 1906 ctx->qp[1].qp = NULL; 1907 mlx4_ib_free_pv_qp_bufs(ctx, IB_QPT_GSI, 1); 1908 ib_dereg_mr(ctx->mr); 1909 ctx->mr = NULL; 1910 ib_dealloc_pd(ctx->pd); 1911 ctx->pd = NULL; 1912 ib_destroy_cq(ctx->cq); 1913 ctx->cq = NULL; 1914 ctx->state = DEMUX_PV_STATE_DOWN; 1915 } 1916} 1917 1918static int mlx4_ib_tunnels_update(struct mlx4_ib_dev *dev, int slave, 1919 int port, int do_init) 1920{ 1921 int ret = 0; 1922 1923 if (!do_init) { 1924 clean_vf_mcast(&dev->sriov.demux[port - 1], slave); 1925 /* for master, destroy real sqp resources */ 1926 if (slave == mlx4_master_func_num(dev->dev)) 1927 destroy_pv_resources(dev, slave, port, 1928 dev->sriov.sqps[port - 1], 1); 1929 /* destroy the tunnel qp resources */ 1930 destroy_pv_resources(dev, slave, port, 1931 dev->sriov.demux[port - 1].tun[slave], 1); 1932 return 0; 1933 } 1934 1935 /* create the tunnel qp resources */ 1936 ret = create_pv_resources(&dev->ib_dev, slave, port, 1, 1937 dev->sriov.demux[port - 1].tun[slave]); 1938 1939 /* for master, create the real sqp resources */ 1940 if (!ret && slave == mlx4_master_func_num(dev->dev)) 1941 ret = create_pv_resources(&dev->ib_dev, slave, port, 0, 1942 dev->sriov.sqps[port - 1]); 1943 return ret; 1944} 1945 1946void mlx4_ib_tunnels_update_work(struct work_struct *work) 1947{ 1948 struct mlx4_ib_demux_work *dmxw; 1949 1950 dmxw = container_of(work, struct mlx4_ib_demux_work, work); 1951 mlx4_ib_tunnels_update(dmxw->dev, dmxw->slave, (int) dmxw->port, 1952 dmxw->do_init); 1953 kfree(dmxw); 1954 return; 1955} 1956 1957static int mlx4_ib_alloc_demux_ctx(struct mlx4_ib_dev *dev, 1958 struct mlx4_ib_demux_ctx *ctx, 1959 int port) 1960{ 1961 char name[12]; 1962 int ret = 0; 1963 int i; 1964 1965 ctx->tun = kcalloc(dev->dev->caps.sqp_demux, 1966 sizeof (struct mlx4_ib_demux_pv_ctx *), GFP_KERNEL); 1967 if (!ctx->tun) 1968 return -ENOMEM; 1969 1970 ctx->dev = dev; 1971 ctx->port = port; 1972 ctx->ib_dev = &dev->ib_dev; 1973 1974 for (i = 0; 1975 i < min(dev->dev->caps.sqp_demux, 1976 (u16)(dev->dev->persist->num_vfs + 1)); 1977 i++) { 1978 struct mlx4_active_ports actv_ports = 1979 mlx4_get_active_ports(dev->dev, i); 1980 1981 if (!test_bit(port - 1, actv_ports.ports)) 1982 continue; 1983 1984 ret = alloc_pv_object(dev, i, port, &ctx->tun[i]); 1985 if (ret) { 1986 ret = -ENOMEM; 1987 goto err_mcg; 1988 } 1989 } 1990 1991 ret = mlx4_ib_mcg_port_init(ctx); 1992 if (ret) { 1993 pr_err("Failed initializing mcg para-virt (%d)\n", ret); 1994 goto err_mcg; 1995 } 1996 1997 snprintf(name, sizeof name, "mlx4_ibt%d", port); 1998 ctx->wq = create_singlethread_workqueue(name); 1999 if (!ctx->wq) { 2000 pr_err("Failed to create tunnelling WQ for port %d\n", port); 2001 ret = -ENOMEM; 2002 goto err_wq; 2003 } 2004 2005 snprintf(name, sizeof name, "mlx4_ibud%d", port); 2006 ctx->ud_wq = create_singlethread_workqueue(name); 2007 if (!ctx->ud_wq) { 2008 pr_err("Failed to create up/down WQ for port %d\n", port); 2009 ret = -ENOMEM; 2010 goto err_udwq; 2011 } 2012 2013 return 0; 2014 2015err_udwq: 2016 destroy_workqueue(ctx->wq); 2017 ctx->wq = NULL; 2018 2019err_wq: 2020 mlx4_ib_mcg_port_cleanup(ctx, 1); 2021err_mcg: 2022 for (i = 0; i < dev->dev->caps.sqp_demux; i++) 2023 free_pv_object(dev, i, port); 2024 kfree(ctx->tun); 2025 ctx->tun = NULL; 2026 return ret; 2027} 2028 2029static void mlx4_ib_free_sqp_ctx(struct mlx4_ib_demux_pv_ctx *sqp_ctx) 2030{ 2031 if (sqp_ctx->state > DEMUX_PV_STATE_DOWN) { 2032 sqp_ctx->state = DEMUX_PV_STATE_DOWNING; 2033 flush_workqueue(sqp_ctx->wq); 2034 if (sqp_ctx->has_smi) { 2035 ib_destroy_qp(sqp_ctx->qp[0].qp); 2036 sqp_ctx->qp[0].qp = NULL; 2037 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_SMI, 0); 2038 } 2039 ib_destroy_qp(sqp_ctx->qp[1].qp); 2040 sqp_ctx->qp[1].qp = NULL; 2041 mlx4_ib_free_pv_qp_bufs(sqp_ctx, IB_QPT_GSI, 0); 2042 ib_dereg_mr(sqp_ctx->mr); 2043 sqp_ctx->mr = NULL; 2044 ib_dealloc_pd(sqp_ctx->pd); 2045 sqp_ctx->pd = NULL; 2046 ib_destroy_cq(sqp_ctx->cq); 2047 sqp_ctx->cq = NULL; 2048 sqp_ctx->state = DEMUX_PV_STATE_DOWN; 2049 } 2050} 2051 2052static void mlx4_ib_free_demux_ctx(struct mlx4_ib_demux_ctx *ctx) 2053{ 2054 int i; 2055 if (ctx) { 2056 struct mlx4_ib_dev *dev = to_mdev(ctx->ib_dev); 2057 mlx4_ib_mcg_port_cleanup(ctx, 1); 2058 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2059 if (!ctx->tun[i]) 2060 continue; 2061 if (ctx->tun[i]->state > DEMUX_PV_STATE_DOWN) 2062 ctx->tun[i]->state = DEMUX_PV_STATE_DOWNING; 2063 } 2064 flush_workqueue(ctx->wq); 2065 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2066 destroy_pv_resources(dev, i, ctx->port, ctx->tun[i], 0); 2067 free_pv_object(dev, i, ctx->port); 2068 } 2069 kfree(ctx->tun); 2070 destroy_workqueue(ctx->ud_wq); 2071 destroy_workqueue(ctx->wq); 2072 } 2073} 2074 2075static void mlx4_ib_master_tunnels(struct mlx4_ib_dev *dev, int do_init) 2076{ 2077 int i; 2078 2079 if (!mlx4_is_master(dev->dev)) 2080 return; 2081 /* initialize or tear down tunnel QPs for the master */ 2082 for (i = 0; i < dev->dev->caps.num_ports; i++) 2083 mlx4_ib_tunnels_update(dev, mlx4_master_func_num(dev->dev), i + 1, do_init); 2084 return; 2085} 2086 2087int mlx4_ib_init_sriov(struct mlx4_ib_dev *dev) 2088{ 2089 int i = 0; 2090 int err; 2091 2092 if (!mlx4_is_mfunc(dev->dev)) 2093 return 0; 2094 2095 dev->sriov.is_going_down = 0; 2096 spin_lock_init(&dev->sriov.going_down_lock); 2097 mlx4_ib_cm_paravirt_init(dev); 2098 2099 mlx4_ib_warn(&dev->ib_dev, "multi-function enabled\n"); 2100 2101 if (mlx4_is_slave(dev->dev)) { 2102 mlx4_ib_warn(&dev->ib_dev, "operating in qp1 tunnel mode\n"); 2103 return 0; 2104 } 2105 2106 for (i = 0; i < dev->dev->caps.sqp_demux; i++) { 2107 if (i == mlx4_master_func_num(dev->dev)) 2108 mlx4_put_slave_node_guid(dev->dev, i, dev->ib_dev.node_guid); 2109 else 2110 mlx4_put_slave_node_guid(dev->dev, i, mlx4_ib_gen_node_guid()); 2111 } 2112 2113 err = mlx4_ib_init_alias_guid_service(dev); 2114 if (err) { 2115 mlx4_ib_warn(&dev->ib_dev, "Failed init alias guid process.\n"); 2116 goto paravirt_err; 2117 } 2118 err = mlx4_ib_device_register_sysfs(dev); 2119 if (err) { 2120 mlx4_ib_warn(&dev->ib_dev, "Failed to register sysfs\n"); 2121 goto sysfs_err; 2122 } 2123 2124 mlx4_ib_warn(&dev->ib_dev, "initializing demux service for %d qp1 clients\n", 2125 dev->dev->caps.sqp_demux); 2126 for (i = 0; i < dev->num_ports; i++) { 2127 union ib_gid gid; 2128 err = __mlx4_ib_query_gid(&dev->ib_dev, i + 1, 0, &gid, 1); 2129 if (err) 2130 goto demux_err; 2131 dev->sriov.demux[i].guid_cache[0] = gid.global.interface_id; 2132 err = alloc_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1, 2133 &dev->sriov.sqps[i]); 2134 if (err) 2135 goto demux_err; 2136 err = mlx4_ib_alloc_demux_ctx(dev, &dev->sriov.demux[i], i + 1); 2137 if (err) 2138 goto free_pv; 2139 } 2140 mlx4_ib_master_tunnels(dev, 1); 2141 return 0; 2142 2143free_pv: 2144 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2145demux_err: 2146 while (--i >= 0) { 2147 free_pv_object(dev, mlx4_master_func_num(dev->dev), i + 1); 2148 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2149 } 2150 mlx4_ib_device_unregister_sysfs(dev); 2151 2152sysfs_err: 2153 mlx4_ib_destroy_alias_guid_service(dev); 2154 2155paravirt_err: 2156 mlx4_ib_cm_paravirt_clean(dev, -1); 2157 2158 return err; 2159} 2160 2161void mlx4_ib_close_sriov(struct mlx4_ib_dev *dev) 2162{ 2163 int i; 2164 unsigned long flags; 2165 2166 if (!mlx4_is_mfunc(dev->dev)) 2167 return; 2168 2169 spin_lock_irqsave(&dev->sriov.going_down_lock, flags); 2170 dev->sriov.is_going_down = 1; 2171 spin_unlock_irqrestore(&dev->sriov.going_down_lock, flags); 2172 if (mlx4_is_master(dev->dev)) { 2173 for (i = 0; i < dev->num_ports; i++) { 2174 flush_workqueue(dev->sriov.demux[i].ud_wq); 2175 mlx4_ib_free_sqp_ctx(dev->sriov.sqps[i]); 2176 kfree(dev->sriov.sqps[i]); 2177 dev->sriov.sqps[i] = NULL; 2178 mlx4_ib_free_demux_ctx(&dev->sriov.demux[i]); 2179 } 2180 2181 mlx4_ib_cm_paravirt_clean(dev, -1); 2182 mlx4_ib_destroy_alias_guid_service(dev); 2183 mlx4_ib_device_unregister_sysfs(dev); 2184 } 2185} 2186