1/* linux/drivers/i2c/busses/i2c-s3c2410.c 2 * 3 * Copyright (C) 2004,2005,2009 Simtec Electronics 4 * Ben Dooks <ben@simtec.co.uk> 5 * 6 * S3C2410 I2C Controller 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17*/ 18 19#include <linux/kernel.h> 20#include <linux/module.h> 21 22#include <linux/i2c.h> 23#include <linux/init.h> 24#include <linux/time.h> 25#include <linux/interrupt.h> 26#include <linux/delay.h> 27#include <linux/errno.h> 28#include <linux/err.h> 29#include <linux/platform_device.h> 30#include <linux/pm_runtime.h> 31#include <linux/clk.h> 32#include <linux/cpufreq.h> 33#include <linux/slab.h> 34#include <linux/io.h> 35#include <linux/of.h> 36#include <linux/of_gpio.h> 37#include <linux/pinctrl/consumer.h> 38#include <linux/mfd/syscon.h> 39#include <linux/regmap.h> 40 41#include <asm/irq.h> 42 43#include <linux/platform_data/i2c-s3c2410.h> 44 45/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */ 46 47#define S3C2410_IICCON 0x00 48#define S3C2410_IICSTAT 0x04 49#define S3C2410_IICADD 0x08 50#define S3C2410_IICDS 0x0C 51#define S3C2440_IICLC 0x10 52 53#define S3C2410_IICCON_ACKEN (1 << 7) 54#define S3C2410_IICCON_TXDIV_16 (0 << 6) 55#define S3C2410_IICCON_TXDIV_512 (1 << 6) 56#define S3C2410_IICCON_IRQEN (1 << 5) 57#define S3C2410_IICCON_IRQPEND (1 << 4) 58#define S3C2410_IICCON_SCALE(x) ((x) & 0xf) 59#define S3C2410_IICCON_SCALEMASK (0xf) 60 61#define S3C2410_IICSTAT_MASTER_RX (2 << 6) 62#define S3C2410_IICSTAT_MASTER_TX (3 << 6) 63#define S3C2410_IICSTAT_SLAVE_RX (0 << 6) 64#define S3C2410_IICSTAT_SLAVE_TX (1 << 6) 65#define S3C2410_IICSTAT_MODEMASK (3 << 6) 66 67#define S3C2410_IICSTAT_START (1 << 5) 68#define S3C2410_IICSTAT_BUSBUSY (1 << 5) 69#define S3C2410_IICSTAT_TXRXEN (1 << 4) 70#define S3C2410_IICSTAT_ARBITR (1 << 3) 71#define S3C2410_IICSTAT_ASSLAVE (1 << 2) 72#define S3C2410_IICSTAT_ADDR0 (1 << 1) 73#define S3C2410_IICSTAT_LASTBIT (1 << 0) 74 75#define S3C2410_IICLC_SDA_DELAY0 (0 << 0) 76#define S3C2410_IICLC_SDA_DELAY5 (1 << 0) 77#define S3C2410_IICLC_SDA_DELAY10 (2 << 0) 78#define S3C2410_IICLC_SDA_DELAY15 (3 << 0) 79#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0) 80 81#define S3C2410_IICLC_FILTER_ON (1 << 2) 82 83/* Treat S3C2410 as baseline hardware, anything else is supported via quirks */ 84#define QUIRK_S3C2440 (1 << 0) 85#define QUIRK_HDMIPHY (1 << 1) 86#define QUIRK_NO_GPIO (1 << 2) 87#define QUIRK_POLL (1 << 3) 88 89/* Max time to wait for bus to become idle after a xfer (in us) */ 90#define S3C2410_IDLE_TIMEOUT 5000 91 92/* Exynos5 Sysreg offset */ 93#define EXYNOS5_SYS_I2C_CFG 0x0234 94 95/* i2c controller state */ 96enum s3c24xx_i2c_state { 97 STATE_IDLE, 98 STATE_START, 99 STATE_READ, 100 STATE_WRITE, 101 STATE_STOP 102}; 103 104struct s3c24xx_i2c { 105 wait_queue_head_t wait; 106 kernel_ulong_t quirks; 107 unsigned int suspended:1; 108 109 struct i2c_msg *msg; 110 unsigned int msg_num; 111 unsigned int msg_idx; 112 unsigned int msg_ptr; 113 114 unsigned int tx_setup; 115 unsigned int irq; 116 117 enum s3c24xx_i2c_state state; 118 unsigned long clkrate; 119 120 void __iomem *regs; 121 struct clk *clk; 122 struct device *dev; 123 struct i2c_adapter adap; 124 125 struct s3c2410_platform_i2c *pdata; 126 int gpios[2]; 127 struct pinctrl *pctrl; 128#if defined(CONFIG_ARM_S3C24XX_CPUFREQ) 129 struct notifier_block freq_transition; 130#endif 131 struct regmap *sysreg; 132 unsigned int sys_i2c_cfg; 133}; 134 135static struct platform_device_id s3c24xx_driver_ids[] = { 136 { 137 .name = "s3c2410-i2c", 138 .driver_data = 0, 139 }, { 140 .name = "s3c2440-i2c", 141 .driver_data = QUIRK_S3C2440, 142 }, { 143 .name = "s3c2440-hdmiphy-i2c", 144 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO, 145 }, { }, 146}; 147MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); 148 149static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat); 150 151#ifdef CONFIG_OF 152static const struct of_device_id s3c24xx_i2c_match[] = { 153 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 }, 154 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 }, 155 { .compatible = "samsung,s3c2440-hdmiphy-i2c", 156 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) }, 157 { .compatible = "samsung,exynos5440-i2c", 158 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) }, 159 { .compatible = "samsung,exynos5-sata-phy-i2c", 160 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) }, 161 {}, 162}; 163MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match); 164#endif 165 166/* s3c24xx_get_device_quirks 167 * 168 * Get controller type either from device tree or platform device variant. 169*/ 170 171static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev) 172{ 173 if (pdev->dev.of_node) { 174 const struct of_device_id *match; 175 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); 176 return (kernel_ulong_t)match->data; 177 } 178 179 return platform_get_device_id(pdev)->driver_data; 180} 181 182/* s3c24xx_i2c_master_complete 183 * 184 * complete the message and wake up the caller, using the given return code, 185 * or zero to mean ok. 186*/ 187 188static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret) 189{ 190 dev_dbg(i2c->dev, "master_complete %d\n", ret); 191 192 i2c->msg_ptr = 0; 193 i2c->msg = NULL; 194 i2c->msg_idx++; 195 i2c->msg_num = 0; 196 if (ret) 197 i2c->msg_idx = ret; 198 199 if (!(i2c->quirks & QUIRK_POLL)) 200 wake_up(&i2c->wait); 201} 202 203static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c) 204{ 205 unsigned long tmp; 206 207 tmp = readl(i2c->regs + S3C2410_IICCON); 208 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 209} 210 211static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c) 212{ 213 unsigned long tmp; 214 215 tmp = readl(i2c->regs + S3C2410_IICCON); 216 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); 217} 218 219/* irq enable/disable functions */ 220 221static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c) 222{ 223 unsigned long tmp; 224 225 tmp = readl(i2c->regs + S3C2410_IICCON); 226 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 227} 228 229static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c) 230{ 231 unsigned long tmp; 232 233 tmp = readl(i2c->regs + S3C2410_IICCON); 234 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); 235} 236 237static bool is_ack(struct s3c24xx_i2c *i2c) 238{ 239 int tries; 240 241 for (tries = 50; tries; --tries) { 242 if (readl(i2c->regs + S3C2410_IICCON) 243 & S3C2410_IICCON_IRQPEND) { 244 if (!(readl(i2c->regs + S3C2410_IICSTAT) 245 & S3C2410_IICSTAT_LASTBIT)) 246 return true; 247 } 248 usleep_range(1000, 2000); 249 } 250 dev_err(i2c->dev, "ack was not received\n"); 251 return false; 252} 253 254/* s3c24xx_i2c_message_start 255 * 256 * put the start of a message onto the bus 257*/ 258 259static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 260 struct i2c_msg *msg) 261{ 262 unsigned int addr = (msg->addr & 0x7f) << 1; 263 unsigned long stat; 264 unsigned long iiccon; 265 266 stat = 0; 267 stat |= S3C2410_IICSTAT_TXRXEN; 268 269 if (msg->flags & I2C_M_RD) { 270 stat |= S3C2410_IICSTAT_MASTER_RX; 271 addr |= 1; 272 } else 273 stat |= S3C2410_IICSTAT_MASTER_TX; 274 275 if (msg->flags & I2C_M_REV_DIR_ADDR) 276 addr ^= 1; 277 278 /* todo - check for whether ack wanted or not */ 279 s3c24xx_i2c_enable_ack(i2c); 280 281 iiccon = readl(i2c->regs + S3C2410_IICCON); 282 writel(stat, i2c->regs + S3C2410_IICSTAT); 283 284 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); 285 writeb(addr, i2c->regs + S3C2410_IICDS); 286 287 /* delay here to ensure the data byte has gotten onto the bus 288 * before the transaction is started */ 289 290 ndelay(i2c->tx_setup); 291 292 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); 293 writel(iiccon, i2c->regs + S3C2410_IICCON); 294 295 stat |= S3C2410_IICSTAT_START; 296 writel(stat, i2c->regs + S3C2410_IICSTAT); 297 298 if (i2c->quirks & QUIRK_POLL) { 299 while ((i2c->msg_num != 0) && is_ack(i2c)) { 300 i2c_s3c_irq_nextbyte(i2c, stat); 301 stat = readl(i2c->regs + S3C2410_IICSTAT); 302 303 if (stat & S3C2410_IICSTAT_ARBITR) 304 dev_err(i2c->dev, "deal with arbitration loss\n"); 305 } 306 } 307} 308 309static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret) 310{ 311 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); 312 313 dev_dbg(i2c->dev, "STOP\n"); 314 315 /* 316 * The datasheet says that the STOP sequence should be: 317 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') 318 * 2) I2CCON.4 = 0 - Clear IRQPEND 319 * 3) Wait until the stop condition takes effect. 320 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN 321 * 322 * Where, step "4*" is only for buses with the "HDMIPHY" quirk. 323 * 324 * However, after much experimentation, it appears that: 325 * a) normal buses automatically clear BUSY and transition from 326 * Master->Slave when they complete generating a STOP condition. 327 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4 328 * after starting the STOP generation here. 329 * b) HDMIPHY bus does neither, so there is no way to do step 3. 330 * There is no indication when this bus has finished generating 331 * STOP. 332 * 333 * In fact, we have found that as soon as the IRQPEND bit is cleared in 334 * step 2, the HDMIPHY bus generates the STOP condition, and then 335 * immediately starts transferring another data byte, even though the 336 * bus is supposedly stopped. This is presumably because the bus is 337 * still in "Master" mode, and its BUSY bit is still set. 338 * 339 * To avoid these extra post-STOP transactions on HDMI phy devices, we 340 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly, 341 * instead of first generating a proper STOP condition. This should 342 * float SDA & SCK terminating the transfer. Subsequent transfers 343 * start with a proper START condition, and proceed normally. 344 * 345 * The HDMIPHY bus is an internal bus that always has exactly two 346 * devices, the host as Master and the HDMIPHY device as the slave. 347 * Skipping the STOP condition has been tested on this bus and works. 348 */ 349 if (i2c->quirks & QUIRK_HDMIPHY) { 350 /* Stop driving the I2C pins */ 351 iicstat &= ~S3C2410_IICSTAT_TXRXEN; 352 } else { 353 /* stop the transfer */ 354 iicstat &= ~S3C2410_IICSTAT_START; 355 } 356 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 357 358 i2c->state = STATE_STOP; 359 360 s3c24xx_i2c_master_complete(i2c, ret); 361 s3c24xx_i2c_disable_irq(i2c); 362} 363 364/* helper functions to determine the current state in the set of 365 * messages we are sending */ 366 367/* is_lastmsg() 368 * 369 * returns TRUE if the current message is the last in the set 370*/ 371 372static inline int is_lastmsg(struct s3c24xx_i2c *i2c) 373{ 374 return i2c->msg_idx >= (i2c->msg_num - 1); 375} 376 377/* is_msglast 378 * 379 * returns TRUE if we this is the last byte in the current message 380*/ 381 382static inline int is_msglast(struct s3c24xx_i2c *i2c) 383{ 384 /* msg->len is always 1 for the first byte of smbus block read. 385 * Actual length will be read from slave. More bytes will be 386 * read according to the length then. */ 387 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 388 return 0; 389 390 return i2c->msg_ptr == i2c->msg->len-1; 391} 392 393/* is_msgend 394 * 395 * returns TRUE if we reached the end of the current message 396*/ 397 398static inline int is_msgend(struct s3c24xx_i2c *i2c) 399{ 400 return i2c->msg_ptr >= i2c->msg->len; 401} 402 403/* i2c_s3c_irq_nextbyte 404 * 405 * process an interrupt and work out what to do 406 */ 407 408static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat) 409{ 410 unsigned long tmp; 411 unsigned char byte; 412 int ret = 0; 413 414 switch (i2c->state) { 415 416 case STATE_IDLE: 417 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); 418 goto out; 419 420 case STATE_STOP: 421 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); 422 s3c24xx_i2c_disable_irq(i2c); 423 goto out_ack; 424 425 case STATE_START: 426 /* last thing we did was send a start condition on the 427 * bus, or started a new i2c message 428 */ 429 430 if (iicstat & S3C2410_IICSTAT_LASTBIT && 431 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 432 /* ack was not received... */ 433 434 dev_dbg(i2c->dev, "ack was not received\n"); 435 s3c24xx_i2c_stop(i2c, -ENXIO); 436 goto out_ack; 437 } 438 439 if (i2c->msg->flags & I2C_M_RD) 440 i2c->state = STATE_READ; 441 else 442 i2c->state = STATE_WRITE; 443 444 /* terminate the transfer if there is nothing to do 445 * as this is used by the i2c probe to find devices. */ 446 447 if (is_lastmsg(i2c) && i2c->msg->len == 0) { 448 s3c24xx_i2c_stop(i2c, 0); 449 goto out_ack; 450 } 451 452 if (i2c->state == STATE_READ) 453 goto prepare_read; 454 455 /* fall through to the write state, as we will need to 456 * send a byte as well */ 457 458 case STATE_WRITE: 459 /* we are writing data to the device... check for the 460 * end of the message, and if so, work out what to do 461 */ 462 463 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { 464 if (iicstat & S3C2410_IICSTAT_LASTBIT) { 465 dev_dbg(i2c->dev, "WRITE: No Ack\n"); 466 467 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); 468 goto out_ack; 469 } 470 } 471 472 retry_write: 473 474 if (!is_msgend(i2c)) { 475 byte = i2c->msg->buf[i2c->msg_ptr++]; 476 writeb(byte, i2c->regs + S3C2410_IICDS); 477 478 /* delay after writing the byte to allow the 479 * data setup time on the bus, as writing the 480 * data to the register causes the first bit 481 * to appear on SDA, and SCL will change as 482 * soon as the interrupt is acknowledged */ 483 484 ndelay(i2c->tx_setup); 485 486 } else if (!is_lastmsg(i2c)) { 487 /* we need to go to the next i2c message */ 488 489 dev_dbg(i2c->dev, "WRITE: Next Message\n"); 490 491 i2c->msg_ptr = 0; 492 i2c->msg_idx++; 493 i2c->msg++; 494 495 /* check to see if we need to do another message */ 496 if (i2c->msg->flags & I2C_M_NOSTART) { 497 498 if (i2c->msg->flags & I2C_M_RD) { 499 /* cannot do this, the controller 500 * forces us to send a new START 501 * when we change direction */ 502 503 s3c24xx_i2c_stop(i2c, -EINVAL); 504 } 505 506 goto retry_write; 507 } else { 508 /* send the new start */ 509 s3c24xx_i2c_message_start(i2c, i2c->msg); 510 i2c->state = STATE_START; 511 } 512 513 } else { 514 /* send stop */ 515 516 s3c24xx_i2c_stop(i2c, 0); 517 } 518 break; 519 520 case STATE_READ: 521 /* we have a byte of data in the data register, do 522 * something with it, and then work out whether we are 523 * going to do any more read/write 524 */ 525 526 byte = readb(i2c->regs + S3C2410_IICDS); 527 i2c->msg->buf[i2c->msg_ptr++] = byte; 528 529 /* Add actual length to read for smbus block read */ 530 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) 531 i2c->msg->len += byte; 532 prepare_read: 533 if (is_msglast(i2c)) { 534 /* last byte of buffer */ 535 536 if (is_lastmsg(i2c)) 537 s3c24xx_i2c_disable_ack(i2c); 538 539 } else if (is_msgend(i2c)) { 540 /* ok, we've read the entire buffer, see if there 541 * is anything else we need to do */ 542 543 if (is_lastmsg(i2c)) { 544 /* last message, send stop and complete */ 545 dev_dbg(i2c->dev, "READ: Send Stop\n"); 546 547 s3c24xx_i2c_stop(i2c, 0); 548 } else { 549 /* go to the next transfer */ 550 dev_dbg(i2c->dev, "READ: Next Transfer\n"); 551 552 i2c->msg_ptr = 0; 553 i2c->msg_idx++; 554 i2c->msg++; 555 } 556 } 557 558 break; 559 } 560 561 /* acknowlegde the IRQ and get back on with the work */ 562 563 out_ack: 564 tmp = readl(i2c->regs + S3C2410_IICCON); 565 tmp &= ~S3C2410_IICCON_IRQPEND; 566 writel(tmp, i2c->regs + S3C2410_IICCON); 567 out: 568 return ret; 569} 570 571/* s3c24xx_i2c_irq 572 * 573 * top level IRQ servicing routine 574*/ 575 576static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id) 577{ 578 struct s3c24xx_i2c *i2c = dev_id; 579 unsigned long status; 580 unsigned long tmp; 581 582 status = readl(i2c->regs + S3C2410_IICSTAT); 583 584 if (status & S3C2410_IICSTAT_ARBITR) { 585 /* deal with arbitration loss */ 586 dev_err(i2c->dev, "deal with arbitration loss\n"); 587 } 588 589 if (i2c->state == STATE_IDLE) { 590 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); 591 592 tmp = readl(i2c->regs + S3C2410_IICCON); 593 tmp &= ~S3C2410_IICCON_IRQPEND; 594 writel(tmp, i2c->regs + S3C2410_IICCON); 595 goto out; 596 } 597 598 /* pretty much this leaves us with the fact that we've 599 * transmitted or received whatever byte we last sent */ 600 601 i2c_s3c_irq_nextbyte(i2c, status); 602 603 out: 604 return IRQ_HANDLED; 605} 606 607/* 608 * Disable the bus so that we won't get any interrupts from now on, or try 609 * to drive any lines. This is the default state when we don't have 610 * anything to send/receive. 611 * 612 * If there is an event on the bus, or we have a pre-existing event at 613 * kernel boot time, we may not notice the event and the I2C controller 614 * will lock the bus with the I2C clock line low indefinitely. 615 */ 616static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c) 617{ 618 unsigned long tmp; 619 620 /* Stop driving the I2C pins */ 621 tmp = readl(i2c->regs + S3C2410_IICSTAT); 622 tmp &= ~S3C2410_IICSTAT_TXRXEN; 623 writel(tmp, i2c->regs + S3C2410_IICSTAT); 624 625 /* We don't expect any interrupts now, and don't want send acks */ 626 tmp = readl(i2c->regs + S3C2410_IICCON); 627 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND | 628 S3C2410_IICCON_ACKEN); 629 writel(tmp, i2c->regs + S3C2410_IICCON); 630} 631 632 633/* s3c24xx_i2c_set_master 634 * 635 * get the i2c bus for a master transaction 636*/ 637 638static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c) 639{ 640 unsigned long iicstat; 641 int timeout = 400; 642 643 while (timeout-- > 0) { 644 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 645 646 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY)) 647 return 0; 648 649 msleep(1); 650 } 651 652 return -ETIMEDOUT; 653} 654 655/* s3c24xx_i2c_wait_idle 656 * 657 * wait for the i2c bus to become idle. 658*/ 659 660static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c) 661{ 662 unsigned long iicstat; 663 ktime_t start, now; 664 unsigned long delay; 665 int spins; 666 667 /* ensure the stop has been through the bus */ 668 669 dev_dbg(i2c->dev, "waiting for bus idle\n"); 670 671 start = now = ktime_get(); 672 673 /* 674 * Most of the time, the bus is already idle within a few usec of the 675 * end of a transaction. However, really slow i2c devices can stretch 676 * the clock, delaying STOP generation. 677 * 678 * On slower SoCs this typically happens within a very small number of 679 * instructions so busy wait briefly to avoid scheduling overhead. 680 */ 681 spins = 3; 682 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 683 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { 684 cpu_relax(); 685 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 686 } 687 688 /* 689 * If we do get an appreciable delay as a compromise between idle 690 * detection latency for the normal, fast case, and system load in the 691 * slow device case, use an exponential back off in the polling loop, 692 * up to 1/10th of the total timeout, then continue to poll at a 693 * constant rate up to the timeout. 694 */ 695 delay = 1; 696 while ((iicstat & S3C2410_IICSTAT_START) && 697 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) { 698 usleep_range(delay, 2 * delay); 699 if (delay < S3C2410_IDLE_TIMEOUT / 10) 700 delay <<= 1; 701 now = ktime_get(); 702 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 703 } 704 705 if (iicstat & S3C2410_IICSTAT_START) 706 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); 707} 708 709/* s3c24xx_i2c_doxfer 710 * 711 * this starts an i2c transfer 712*/ 713 714static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 715 struct i2c_msg *msgs, int num) 716{ 717 unsigned long timeout; 718 int ret; 719 720 if (i2c->suspended) 721 return -EIO; 722 723 ret = s3c24xx_i2c_set_master(i2c); 724 if (ret != 0) { 725 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); 726 ret = -EAGAIN; 727 goto out; 728 } 729 730 i2c->msg = msgs; 731 i2c->msg_num = num; 732 i2c->msg_ptr = 0; 733 i2c->msg_idx = 0; 734 i2c->state = STATE_START; 735 736 s3c24xx_i2c_enable_irq(i2c); 737 s3c24xx_i2c_message_start(i2c, msgs); 738 739 if (i2c->quirks & QUIRK_POLL) { 740 ret = i2c->msg_idx; 741 742 if (ret != num) 743 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 744 745 goto out; 746 } 747 748 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 749 750 ret = i2c->msg_idx; 751 752 /* having these next two as dev_err() makes life very 753 * noisy when doing an i2cdetect */ 754 755 if (timeout == 0) 756 dev_dbg(i2c->dev, "timeout\n"); 757 else if (ret != num) 758 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 759 760 /* For QUIRK_HDMIPHY, bus is already disabled */ 761 if (i2c->quirks & QUIRK_HDMIPHY) 762 goto out; 763 764 s3c24xx_i2c_wait_idle(i2c); 765 766 s3c24xx_i2c_disable_bus(i2c); 767 768 out: 769 i2c->state = STATE_IDLE; 770 771 return ret; 772} 773 774/* s3c24xx_i2c_xfer 775 * 776 * first port of call from the i2c bus code when an message needs 777 * transferring across the i2c bus. 778*/ 779 780static int s3c24xx_i2c_xfer(struct i2c_adapter *adap, 781 struct i2c_msg *msgs, int num) 782{ 783 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; 784 int retry; 785 int ret; 786 787 pm_runtime_get_sync(&adap->dev); 788 ret = clk_enable(i2c->clk); 789 if (ret) 790 return ret; 791 792 for (retry = 0; retry < adap->retries; retry++) { 793 794 ret = s3c24xx_i2c_doxfer(i2c, msgs, num); 795 796 if (ret != -EAGAIN) { 797 clk_disable(i2c->clk); 798 pm_runtime_put(&adap->dev); 799 return ret; 800 } 801 802 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); 803 804 udelay(100); 805 } 806 807 clk_disable(i2c->clk); 808 pm_runtime_put(&adap->dev); 809 return -EREMOTEIO; 810} 811 812/* declare our i2c functionality */ 813static u32 s3c24xx_i2c_func(struct i2c_adapter *adap) 814{ 815 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART | 816 I2C_FUNC_PROTOCOL_MANGLING; 817} 818 819/* i2c bus registration info */ 820 821static const struct i2c_algorithm s3c24xx_i2c_algorithm = { 822 .master_xfer = s3c24xx_i2c_xfer, 823 .functionality = s3c24xx_i2c_func, 824}; 825 826/* s3c24xx_i2c_calcdivisor 827 * 828 * return the divisor settings for a given frequency 829*/ 830 831static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted, 832 unsigned int *div1, unsigned int *divs) 833{ 834 unsigned int calc_divs = clkin / wanted; 835 unsigned int calc_div1; 836 837 if (calc_divs > (16*16)) 838 calc_div1 = 512; 839 else 840 calc_div1 = 16; 841 842 calc_divs += calc_div1-1; 843 calc_divs /= calc_div1; 844 845 if (calc_divs == 0) 846 calc_divs = 1; 847 if (calc_divs > 17) 848 calc_divs = 17; 849 850 *divs = calc_divs; 851 *div1 = calc_div1; 852 853 return clkin / (calc_divs * calc_div1); 854} 855 856/* s3c24xx_i2c_clockrate 857 * 858 * work out a divisor for the user requested frequency setting, 859 * either by the requested frequency, or scanning the acceptable 860 * range of frequencies until something is found 861*/ 862 863static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got) 864{ 865 struct s3c2410_platform_i2c *pdata = i2c->pdata; 866 unsigned long clkin = clk_get_rate(i2c->clk); 867 unsigned int divs, div1; 868 unsigned long target_frequency; 869 u32 iiccon; 870 int freq; 871 872 i2c->clkrate = clkin; 873 clkin /= 1000; /* clkin now in KHz */ 874 875 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); 876 877 target_frequency = pdata->frequency ? pdata->frequency : 100000; 878 879 target_frequency /= 1000; /* Target frequency now in KHz */ 880 881 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); 882 883 if (freq > target_frequency) { 884 dev_err(i2c->dev, 885 "Unable to achieve desired frequency %luKHz." \ 886 " Lowest achievable %dKHz\n", target_frequency, freq); 887 return -EINVAL; 888 } 889 890 *got = freq; 891 892 iiccon = readl(i2c->regs + S3C2410_IICCON); 893 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512); 894 iiccon |= (divs-1); 895 896 if (div1 == 512) 897 iiccon |= S3C2410_IICCON_TXDIV_512; 898 899 if (i2c->quirks & QUIRK_POLL) 900 iiccon |= S3C2410_IICCON_SCALE(2); 901 902 writel(iiccon, i2c->regs + S3C2410_IICCON); 903 904 if (i2c->quirks & QUIRK_S3C2440) { 905 unsigned long sda_delay; 906 907 if (pdata->sda_delay) { 908 sda_delay = clkin * pdata->sda_delay; 909 sda_delay = DIV_ROUND_UP(sda_delay, 1000000); 910 sda_delay = DIV_ROUND_UP(sda_delay, 5); 911 if (sda_delay > 3) 912 sda_delay = 3; 913 sda_delay |= S3C2410_IICLC_FILTER_ON; 914 } else 915 sda_delay = 0; 916 917 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); 918 writel(sda_delay, i2c->regs + S3C2440_IICLC); 919 } 920 921 return 0; 922} 923 924#if defined(CONFIG_ARM_S3C24XX_CPUFREQ) 925 926#define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition) 927 928static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb, 929 unsigned long val, void *data) 930{ 931 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 932 unsigned int got; 933 int delta_f; 934 int ret; 935 936 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; 937 938 /* if we're post-change and the input clock has slowed down 939 * or at pre-change and the clock is about to speed up, then 940 * adjust our clock rate. <0 is slow, >0 speedup. 941 */ 942 943 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 944 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 945 i2c_lock_adapter(&i2c->adap); 946 ret = s3c24xx_i2c_clockrate(i2c, &got); 947 i2c_unlock_adapter(&i2c->adap); 948 949 if (ret < 0) 950 dev_err(i2c->dev, "cannot find frequency\n"); 951 else 952 dev_info(i2c->dev, "setting freq %d\n", got); 953 } 954 955 return 0; 956} 957 958static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 959{ 960 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; 961 962 return cpufreq_register_notifier(&i2c->freq_transition, 963 CPUFREQ_TRANSITION_NOTIFIER); 964} 965 966static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 967{ 968 cpufreq_unregister_notifier(&i2c->freq_transition, 969 CPUFREQ_TRANSITION_NOTIFIER); 970} 971 972#else 973static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c) 974{ 975 return 0; 976} 977 978static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c) 979{ 980} 981#endif 982 983#ifdef CONFIG_OF 984static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 985{ 986 int idx, gpio, ret; 987 988 if (i2c->quirks & QUIRK_NO_GPIO) 989 return 0; 990 991 for (idx = 0; idx < 2; idx++) { 992 gpio = of_get_gpio(i2c->dev->of_node, idx); 993 if (!gpio_is_valid(gpio)) { 994 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio); 995 goto free_gpio; 996 } 997 i2c->gpios[idx] = gpio; 998 999 ret = gpio_request(gpio, "i2c-bus"); 1000 if (ret) { 1001 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio); 1002 goto free_gpio; 1003 } 1004 } 1005 return 0; 1006 1007free_gpio: 1008 while (--idx >= 0) 1009 gpio_free(i2c->gpios[idx]); 1010 return -EINVAL; 1011} 1012 1013static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 1014{ 1015 unsigned int idx; 1016 1017 if (i2c->quirks & QUIRK_NO_GPIO) 1018 return; 1019 1020 for (idx = 0; idx < 2; idx++) 1021 gpio_free(i2c->gpios[idx]); 1022} 1023#else 1024static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c) 1025{ 1026 return 0; 1027} 1028 1029static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c) 1030{ 1031} 1032#endif 1033 1034/* s3c24xx_i2c_init 1035 * 1036 * initialise the controller, set the IO lines and frequency 1037*/ 1038 1039static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c) 1040{ 1041 struct s3c2410_platform_i2c *pdata; 1042 unsigned int freq; 1043 1044 /* get the plafrom data */ 1045 1046 pdata = i2c->pdata; 1047 1048 /* write slave address */ 1049 1050 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 1051 1052 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); 1053 1054 writel(0, i2c->regs + S3C2410_IICCON); 1055 writel(0, i2c->regs + S3C2410_IICSTAT); 1056 1057 /* we need to work out the divisors for the clock... */ 1058 1059 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) { 1060 dev_err(i2c->dev, "cannot meet bus frequency required\n"); 1061 return -EINVAL; 1062 } 1063 1064 /* todo - check that the i2c lines aren't being dragged anywhere */ 1065 1066 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); 1067 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n", 1068 readl(i2c->regs + S3C2410_IICCON)); 1069 1070 return 0; 1071} 1072 1073#ifdef CONFIG_OF 1074/* s3c24xx_i2c_parse_dt 1075 * 1076 * Parse the device tree node and retreive the platform data. 1077*/ 1078 1079static void 1080s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 1081{ 1082 struct s3c2410_platform_i2c *pdata = i2c->pdata; 1083 int id; 1084 1085 if (!np) 1086 return; 1087 1088 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ 1089 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); 1090 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 1091 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 1092 (u32 *)&pdata->frequency); 1093 /* 1094 * Exynos5's legacy i2c controller and new high speed i2c 1095 * controller have muxed interrupt sources. By default the 1096 * interrupts for 4-channel HS-I2C controller are enabled. 1097 * If nodes for first four channels of legacy i2c controller 1098 * are available then re-configure the interrupts via the 1099 * system register. 1100 */ 1101 id = of_alias_get_id(np, "i2c"); 1102 i2c->sysreg = syscon_regmap_lookup_by_phandle(np, 1103 "samsung,sysreg-phandle"); 1104 if (IS_ERR(i2c->sysreg)) 1105 return; 1106 1107 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0); 1108} 1109#else 1110static void 1111s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 1112{ 1113 return; 1114} 1115#endif 1116 1117/* s3c24xx_i2c_probe 1118 * 1119 * called by the bus driver when a suitable device is found 1120*/ 1121 1122static int s3c24xx_i2c_probe(struct platform_device *pdev) 1123{ 1124 struct s3c24xx_i2c *i2c; 1125 struct s3c2410_platform_i2c *pdata = NULL; 1126 struct resource *res; 1127 int ret; 1128 1129 if (!pdev->dev.of_node) { 1130 pdata = dev_get_platdata(&pdev->dev); 1131 if (!pdata) { 1132 dev_err(&pdev->dev, "no platform data\n"); 1133 return -EINVAL; 1134 } 1135 } 1136 1137 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); 1138 if (!i2c) 1139 return -ENOMEM; 1140 1141 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1142 if (!i2c->pdata) 1143 return -ENOMEM; 1144 1145 i2c->quirks = s3c24xx_get_device_quirks(pdev); 1146 i2c->sysreg = ERR_PTR(-ENOENT); 1147 if (pdata) 1148 memcpy(i2c->pdata, pdata, sizeof(*pdata)); 1149 else 1150 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); 1151 1152 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); 1153 i2c->adap.owner = THIS_MODULE; 1154 i2c->adap.algo = &s3c24xx_i2c_algorithm; 1155 i2c->adap.retries = 2; 1156 i2c->adap.class = I2C_CLASS_DEPRECATED; 1157 i2c->tx_setup = 50; 1158 1159 init_waitqueue_head(&i2c->wait); 1160 1161 /* find the clock and enable it */ 1162 1163 i2c->dev = &pdev->dev; 1164 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); 1165 if (IS_ERR(i2c->clk)) { 1166 dev_err(&pdev->dev, "cannot get clock\n"); 1167 return -ENOENT; 1168 } 1169 1170 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); 1171 1172 1173 /* map the registers */ 1174 1175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1176 i2c->regs = devm_ioremap_resource(&pdev->dev, res); 1177 1178 if (IS_ERR(i2c->regs)) 1179 return PTR_ERR(i2c->regs); 1180 1181 dev_dbg(&pdev->dev, "registers %p (%p)\n", 1182 i2c->regs, res); 1183 1184 /* setup info block for the i2c core */ 1185 1186 i2c->adap.algo_data = i2c; 1187 i2c->adap.dev.parent = &pdev->dev; 1188 1189 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); 1190 1191 /* inititalise the i2c gpio lines */ 1192 1193 if (i2c->pdata->cfg_gpio) { 1194 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); 1195 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) { 1196 return -EINVAL; 1197 } 1198 1199 /* initialise the i2c controller */ 1200 1201 clk_prepare_enable(i2c->clk); 1202 ret = s3c24xx_i2c_init(i2c); 1203 clk_disable(i2c->clk); 1204 if (ret != 0) { 1205 dev_err(&pdev->dev, "I2C controller init failed\n"); 1206 return ret; 1207 } 1208 /* find the IRQ for this unit (note, this relies on the init call to 1209 * ensure no current IRQs pending 1210 */ 1211 1212 if (!(i2c->quirks & QUIRK_POLL)) { 1213 i2c->irq = ret = platform_get_irq(pdev, 0); 1214 if (ret <= 0) { 1215 dev_err(&pdev->dev, "cannot find IRQ\n"); 1216 clk_unprepare(i2c->clk); 1217 return ret; 1218 } 1219 1220 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0, 1221 dev_name(&pdev->dev), i2c); 1222 1223 if (ret != 0) { 1224 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1225 clk_unprepare(i2c->clk); 1226 return ret; 1227 } 1228 } 1229 1230 ret = s3c24xx_i2c_register_cpufreq(i2c); 1231 if (ret < 0) { 1232 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); 1233 clk_unprepare(i2c->clk); 1234 return ret; 1235 } 1236 1237 /* Note, previous versions of the driver used i2c_add_adapter() 1238 * to add the bus at any number. We now pass the bus number via 1239 * the platform data, so if unset it will now default to always 1240 * being bus 0. 1241 */ 1242 1243 i2c->adap.nr = i2c->pdata->bus_num; 1244 i2c->adap.dev.of_node = pdev->dev.of_node; 1245 1246 platform_set_drvdata(pdev, i2c); 1247 1248 pm_runtime_enable(&pdev->dev); 1249 1250 ret = i2c_add_numbered_adapter(&i2c->adap); 1251 if (ret < 0) { 1252 dev_err(&pdev->dev, "failed to add bus to i2c core\n"); 1253 pm_runtime_disable(&pdev->dev); 1254 s3c24xx_i2c_deregister_cpufreq(i2c); 1255 clk_unprepare(i2c->clk); 1256 return ret; 1257 } 1258 1259 pm_runtime_enable(&i2c->adap.dev); 1260 1261 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); 1262 return 0; 1263} 1264 1265/* s3c24xx_i2c_remove 1266 * 1267 * called when device is removed from the bus 1268*/ 1269 1270static int s3c24xx_i2c_remove(struct platform_device *pdev) 1271{ 1272 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1273 1274 clk_unprepare(i2c->clk); 1275 1276 pm_runtime_disable(&i2c->adap.dev); 1277 pm_runtime_disable(&pdev->dev); 1278 1279 s3c24xx_i2c_deregister_cpufreq(i2c); 1280 1281 i2c_del_adapter(&i2c->adap); 1282 1283 if (pdev->dev.of_node && IS_ERR(i2c->pctrl)) 1284 s3c24xx_i2c_dt_gpio_free(i2c); 1285 1286 return 0; 1287} 1288 1289#ifdef CONFIG_PM_SLEEP 1290static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1291{ 1292 struct platform_device *pdev = to_platform_device(dev); 1293 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1294 1295 i2c->suspended = 1; 1296 1297 if (!IS_ERR(i2c->sysreg)) 1298 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg); 1299 1300 return 0; 1301} 1302 1303static int s3c24xx_i2c_resume_noirq(struct device *dev) 1304{ 1305 struct platform_device *pdev = to_platform_device(dev); 1306 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1307 int ret; 1308 1309 if (!IS_ERR(i2c->sysreg)) 1310 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg); 1311 1312 ret = clk_enable(i2c->clk); 1313 if (ret) 1314 return ret; 1315 s3c24xx_i2c_init(i2c); 1316 clk_disable(i2c->clk); 1317 i2c->suspended = 0; 1318 1319 return 0; 1320} 1321#endif 1322 1323#ifdef CONFIG_PM 1324static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1325#ifdef CONFIG_PM_SLEEP 1326 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 1327 .resume_noirq = s3c24xx_i2c_resume_noirq, 1328 .freeze_noirq = s3c24xx_i2c_suspend_noirq, 1329 .thaw_noirq = s3c24xx_i2c_resume_noirq, 1330 .poweroff_noirq = s3c24xx_i2c_suspend_noirq, 1331 .restore_noirq = s3c24xx_i2c_resume_noirq, 1332#endif 1333}; 1334 1335#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 1336#else 1337#define S3C24XX_DEV_PM_OPS NULL 1338#endif 1339 1340/* device driver for platform bus bits */ 1341 1342static struct platform_driver s3c24xx_i2c_driver = { 1343 .probe = s3c24xx_i2c_probe, 1344 .remove = s3c24xx_i2c_remove, 1345 .id_table = s3c24xx_driver_ids, 1346 .driver = { 1347 .name = "s3c-i2c", 1348 .pm = S3C24XX_DEV_PM_OPS, 1349 .of_match_table = of_match_ptr(s3c24xx_i2c_match), 1350 }, 1351}; 1352 1353static int __init i2c_adap_s3c_init(void) 1354{ 1355 return platform_driver_register(&s3c24xx_i2c_driver); 1356} 1357subsys_initcall(i2c_adap_s3c_init); 1358 1359static void __exit i2c_adap_s3c_exit(void) 1360{ 1361 platform_driver_unregister(&s3c24xx_i2c_driver); 1362} 1363module_exit(i2c_adap_s3c_exit); 1364 1365MODULE_DESCRIPTION("S3C24XX I2C Bus driver"); 1366MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); 1367MODULE_LICENSE("GPL"); 1368