1/* 2 * Driver for I2C adapter in Rockchip RK3xxx SoC 3 * 4 * Max Schwarz <max.schwarz@online.de> 5 * based on the patches by Rockchip Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/i2c.h> 15#include <linux/interrupt.h> 16#include <linux/errno.h> 17#include <linux/err.h> 18#include <linux/platform_device.h> 19#include <linux/io.h> 20#include <linux/of_address.h> 21#include <linux/of_irq.h> 22#include <linux/spinlock.h> 23#include <linux/clk.h> 24#include <linux/wait.h> 25#include <linux/mfd/syscon.h> 26#include <linux/regmap.h> 27#include <linux/math64.h> 28 29 30/* Register Map */ 31#define REG_CON 0x00 /* control register */ 32#define REG_CLKDIV 0x04 /* clock divisor register */ 33#define REG_MRXADDR 0x08 /* slave address for REGISTER_TX */ 34#define REG_MRXRADDR 0x0c /* slave register address for REGISTER_TX */ 35#define REG_MTXCNT 0x10 /* number of bytes to be transmitted */ 36#define REG_MRXCNT 0x14 /* number of bytes to be received */ 37#define REG_IEN 0x18 /* interrupt enable */ 38#define REG_IPD 0x1c /* interrupt pending */ 39#define REG_FCNT 0x20 /* finished count */ 40 41/* Data buffer offsets */ 42#define TXBUFFER_BASE 0x100 43#define RXBUFFER_BASE 0x200 44 45/* REG_CON bits */ 46#define REG_CON_EN BIT(0) 47enum { 48 REG_CON_MOD_TX = 0, /* transmit data */ 49 REG_CON_MOD_REGISTER_TX, /* select register and restart */ 50 REG_CON_MOD_RX, /* receive data */ 51 REG_CON_MOD_REGISTER_RX, /* broken: transmits read addr AND writes 52 * register addr */ 53}; 54#define REG_CON_MOD(mod) ((mod) << 1) 55#define REG_CON_MOD_MASK (BIT(1) | BIT(2)) 56#define REG_CON_START BIT(3) 57#define REG_CON_STOP BIT(4) 58#define REG_CON_LASTACK BIT(5) /* 1: send NACK after last received byte */ 59#define REG_CON_ACTACK BIT(6) /* 1: stop if NACK is received */ 60 61/* REG_MRXADDR bits */ 62#define REG_MRXADDR_VALID(x) BIT(24 + (x)) /* [x*8+7:x*8] of MRX[R]ADDR valid */ 63 64/* REG_IEN/REG_IPD bits */ 65#define REG_INT_BTF BIT(0) /* a byte was transmitted */ 66#define REG_INT_BRF BIT(1) /* a byte was received */ 67#define REG_INT_MBTF BIT(2) /* master data transmit finished */ 68#define REG_INT_MBRF BIT(3) /* master data receive finished */ 69#define REG_INT_START BIT(4) /* START condition generated */ 70#define REG_INT_STOP BIT(5) /* STOP condition generated */ 71#define REG_INT_NAKRCV BIT(6) /* NACK received */ 72#define REG_INT_ALL 0x7f 73 74/* Constants */ 75#define WAIT_TIMEOUT 200 /* ms */ 76#define DEFAULT_SCL_RATE (100 * 1000) /* Hz */ 77 78enum rk3x_i2c_state { 79 STATE_IDLE, 80 STATE_START, 81 STATE_READ, 82 STATE_WRITE, 83 STATE_STOP 84}; 85 86/** 87 * @grf_offset: offset inside the grf regmap for setting the i2c type 88 */ 89struct rk3x_i2c_soc_data { 90 int grf_offset; 91}; 92 93struct rk3x_i2c { 94 struct i2c_adapter adap; 95 struct device *dev; 96 struct rk3x_i2c_soc_data *soc_data; 97 98 /* Hardware resources */ 99 void __iomem *regs; 100 struct clk *clk; 101 struct notifier_block clk_rate_nb; 102 103 /* Settings */ 104 unsigned int scl_frequency; 105 unsigned int scl_rise_ns; 106 unsigned int scl_fall_ns; 107 unsigned int sda_fall_ns; 108 109 /* Synchronization & notification */ 110 spinlock_t lock; 111 wait_queue_head_t wait; 112 bool busy; 113 114 /* Current message */ 115 struct i2c_msg *msg; 116 u8 addr; 117 unsigned int mode; 118 bool is_last_msg; 119 120 /* I2C state machine */ 121 enum rk3x_i2c_state state; 122 unsigned int processed; /* sent/received bytes */ 123 int error; 124}; 125 126static inline void i2c_writel(struct rk3x_i2c *i2c, u32 value, 127 unsigned int offset) 128{ 129 writel(value, i2c->regs + offset); 130} 131 132static inline u32 i2c_readl(struct rk3x_i2c *i2c, unsigned int offset) 133{ 134 return readl(i2c->regs + offset); 135} 136 137/* Reset all interrupt pending bits */ 138static inline void rk3x_i2c_clean_ipd(struct rk3x_i2c *i2c) 139{ 140 i2c_writel(i2c, REG_INT_ALL, REG_IPD); 141} 142 143/** 144 * Generate a START condition, which triggers a REG_INT_START interrupt. 145 */ 146static void rk3x_i2c_start(struct rk3x_i2c *i2c) 147{ 148 u32 val; 149 150 rk3x_i2c_clean_ipd(i2c); 151 i2c_writel(i2c, REG_INT_START, REG_IEN); 152 153 /* enable adapter with correct mode, send START condition */ 154 val = REG_CON_EN | REG_CON_MOD(i2c->mode) | REG_CON_START; 155 156 /* if we want to react to NACK, set ACTACK bit */ 157 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 158 val |= REG_CON_ACTACK; 159 160 i2c_writel(i2c, val, REG_CON); 161} 162 163/** 164 * Generate a STOP condition, which triggers a REG_INT_STOP interrupt. 165 * 166 * @error: Error code to return in rk3x_i2c_xfer 167 */ 168static void rk3x_i2c_stop(struct rk3x_i2c *i2c, int error) 169{ 170 unsigned int ctrl; 171 172 i2c->processed = 0; 173 i2c->msg = NULL; 174 i2c->error = error; 175 176 if (i2c->is_last_msg) { 177 /* Enable stop interrupt */ 178 i2c_writel(i2c, REG_INT_STOP, REG_IEN); 179 180 i2c->state = STATE_STOP; 181 182 ctrl = i2c_readl(i2c, REG_CON); 183 ctrl |= REG_CON_STOP; 184 i2c_writel(i2c, ctrl, REG_CON); 185 } else { 186 /* Signal rk3x_i2c_xfer to start the next message. */ 187 i2c->busy = false; 188 i2c->state = STATE_IDLE; 189 190 /* 191 * The HW is actually not capable of REPEATED START. But we can 192 * get the intended effect by resetting its internal state 193 * and issuing an ordinary START. 194 */ 195 i2c_writel(i2c, 0, REG_CON); 196 197 /* signal that we are finished with the current msg */ 198 wake_up(&i2c->wait); 199 } 200} 201 202/** 203 * Setup a read according to i2c->msg 204 */ 205static void rk3x_i2c_prepare_read(struct rk3x_i2c *i2c) 206{ 207 unsigned int len = i2c->msg->len - i2c->processed; 208 u32 con; 209 210 con = i2c_readl(i2c, REG_CON); 211 212 /* 213 * The hw can read up to 32 bytes at a time. If we need more than one 214 * chunk, send an ACK after the last byte of the current chunk. 215 */ 216 if (len > 32) { 217 len = 32; 218 con &= ~REG_CON_LASTACK; 219 } else { 220 con |= REG_CON_LASTACK; 221 } 222 223 /* make sure we are in plain RX mode if we read a second chunk */ 224 if (i2c->processed != 0) { 225 con &= ~REG_CON_MOD_MASK; 226 con |= REG_CON_MOD(REG_CON_MOD_RX); 227 } 228 229 i2c_writel(i2c, con, REG_CON); 230 i2c_writel(i2c, len, REG_MRXCNT); 231} 232 233/** 234 * Fill the transmit buffer with data from i2c->msg 235 */ 236static void rk3x_i2c_fill_transmit_buf(struct rk3x_i2c *i2c) 237{ 238 unsigned int i, j; 239 u32 cnt = 0; 240 u32 val; 241 u8 byte; 242 243 for (i = 0; i < 8; ++i) { 244 val = 0; 245 for (j = 0; j < 4; ++j) { 246 if ((i2c->processed == i2c->msg->len) && (cnt != 0)) 247 break; 248 249 if (i2c->processed == 0 && cnt == 0) 250 byte = (i2c->addr & 0x7f) << 1; 251 else 252 byte = i2c->msg->buf[i2c->processed++]; 253 254 val |= byte << (j * 8); 255 cnt++; 256 } 257 258 i2c_writel(i2c, val, TXBUFFER_BASE + 4 * i); 259 260 if (i2c->processed == i2c->msg->len) 261 break; 262 } 263 264 i2c_writel(i2c, cnt, REG_MTXCNT); 265} 266 267 268/* IRQ handlers for individual states */ 269 270static void rk3x_i2c_handle_start(struct rk3x_i2c *i2c, unsigned int ipd) 271{ 272 if (!(ipd & REG_INT_START)) { 273 rk3x_i2c_stop(i2c, -EIO); 274 dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd); 275 rk3x_i2c_clean_ipd(i2c); 276 return; 277 } 278 279 /* ack interrupt */ 280 i2c_writel(i2c, REG_INT_START, REG_IPD); 281 282 /* disable start bit */ 283 i2c_writel(i2c, i2c_readl(i2c, REG_CON) & ~REG_CON_START, REG_CON); 284 285 /* enable appropriate interrupts and transition */ 286 if (i2c->mode == REG_CON_MOD_TX) { 287 i2c_writel(i2c, REG_INT_MBTF | REG_INT_NAKRCV, REG_IEN); 288 i2c->state = STATE_WRITE; 289 rk3x_i2c_fill_transmit_buf(i2c); 290 } else { 291 /* in any other case, we are going to be reading. */ 292 i2c_writel(i2c, REG_INT_MBRF | REG_INT_NAKRCV, REG_IEN); 293 i2c->state = STATE_READ; 294 rk3x_i2c_prepare_read(i2c); 295 } 296} 297 298static void rk3x_i2c_handle_write(struct rk3x_i2c *i2c, unsigned int ipd) 299{ 300 if (!(ipd & REG_INT_MBTF)) { 301 rk3x_i2c_stop(i2c, -EIO); 302 dev_err(i2c->dev, "unexpected irq in WRITE: 0x%x\n", ipd); 303 rk3x_i2c_clean_ipd(i2c); 304 return; 305 } 306 307 /* ack interrupt */ 308 i2c_writel(i2c, REG_INT_MBTF, REG_IPD); 309 310 /* are we finished? */ 311 if (i2c->processed == i2c->msg->len) 312 rk3x_i2c_stop(i2c, i2c->error); 313 else 314 rk3x_i2c_fill_transmit_buf(i2c); 315} 316 317static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) 318{ 319 unsigned int i; 320 unsigned int len = i2c->msg->len - i2c->processed; 321 u32 uninitialized_var(val); 322 u8 byte; 323 324 /* we only care for MBRF here. */ 325 if (!(ipd & REG_INT_MBRF)) 326 return; 327 328 /* ack interrupt */ 329 i2c_writel(i2c, REG_INT_MBRF, REG_IPD); 330 331 /* Can only handle a maximum of 32 bytes at a time */ 332 if (len > 32) 333 len = 32; 334 335 /* read the data from receive buffer */ 336 for (i = 0; i < len; ++i) { 337 if (i % 4 == 0) 338 val = i2c_readl(i2c, RXBUFFER_BASE + (i / 4) * 4); 339 340 byte = (val >> ((i % 4) * 8)) & 0xff; 341 i2c->msg->buf[i2c->processed++] = byte; 342 } 343 344 /* are we finished? */ 345 if (i2c->processed == i2c->msg->len) 346 rk3x_i2c_stop(i2c, i2c->error); 347 else 348 rk3x_i2c_prepare_read(i2c); 349} 350 351static void rk3x_i2c_handle_stop(struct rk3x_i2c *i2c, unsigned int ipd) 352{ 353 unsigned int con; 354 355 if (!(ipd & REG_INT_STOP)) { 356 rk3x_i2c_stop(i2c, -EIO); 357 dev_err(i2c->dev, "unexpected irq in STOP: 0x%x\n", ipd); 358 rk3x_i2c_clean_ipd(i2c); 359 return; 360 } 361 362 /* ack interrupt */ 363 i2c_writel(i2c, REG_INT_STOP, REG_IPD); 364 365 /* disable STOP bit */ 366 con = i2c_readl(i2c, REG_CON); 367 con &= ~REG_CON_STOP; 368 i2c_writel(i2c, con, REG_CON); 369 370 i2c->busy = false; 371 i2c->state = STATE_IDLE; 372 373 /* signal rk3x_i2c_xfer that we are finished */ 374 wake_up(&i2c->wait); 375} 376 377static irqreturn_t rk3x_i2c_irq(int irqno, void *dev_id) 378{ 379 struct rk3x_i2c *i2c = dev_id; 380 unsigned int ipd; 381 382 spin_lock(&i2c->lock); 383 384 ipd = i2c_readl(i2c, REG_IPD); 385 if (i2c->state == STATE_IDLE) { 386 dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd); 387 rk3x_i2c_clean_ipd(i2c); 388 goto out; 389 } 390 391 dev_dbg(i2c->dev, "IRQ: state %d, ipd: %x\n", i2c->state, ipd); 392 393 /* Clean interrupt bits we don't care about */ 394 ipd &= ~(REG_INT_BRF | REG_INT_BTF); 395 396 if (ipd & REG_INT_NAKRCV) { 397 /* 398 * We got a NACK in the last operation. Depending on whether 399 * IGNORE_NAK is set, we have to stop the operation and report 400 * an error. 401 */ 402 i2c_writel(i2c, REG_INT_NAKRCV, REG_IPD); 403 404 ipd &= ~REG_INT_NAKRCV; 405 406 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) 407 rk3x_i2c_stop(i2c, -ENXIO); 408 } 409 410 /* is there anything left to handle? */ 411 if ((ipd & REG_INT_ALL) == 0) 412 goto out; 413 414 switch (i2c->state) { 415 case STATE_START: 416 rk3x_i2c_handle_start(i2c, ipd); 417 break; 418 case STATE_WRITE: 419 rk3x_i2c_handle_write(i2c, ipd); 420 break; 421 case STATE_READ: 422 rk3x_i2c_handle_read(i2c, ipd); 423 break; 424 case STATE_STOP: 425 rk3x_i2c_handle_stop(i2c, ipd); 426 break; 427 case STATE_IDLE: 428 break; 429 } 430 431out: 432 spin_unlock(&i2c->lock); 433 return IRQ_HANDLED; 434} 435 436/** 437 * Calculate divider values for desired SCL frequency 438 * 439 * @clk_rate: I2C input clock rate 440 * @scl_rate: Desired SCL rate 441 * @scl_rise_ns: How many ns it takes for SCL to rise. 442 * @scl_fall_ns: How many ns it takes for SCL to fall. 443 * @sda_fall_ns: How many ns it takes for SDA to fall. 444 * @div_low: Divider output for low 445 * @div_high: Divider output for high 446 * 447 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case 448 * a best-effort divider value is returned in divs. If the target rate is 449 * too high, we silently use the highest possible rate. 450 */ 451static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate, 452 unsigned long scl_rise_ns, 453 unsigned long scl_fall_ns, 454 unsigned long sda_fall_ns, 455 unsigned long *div_low, unsigned long *div_high) 456{ 457 unsigned long spec_min_low_ns, spec_min_high_ns; 458 unsigned long spec_setup_start, spec_max_data_hold_ns; 459 unsigned long data_hold_buffer_ns; 460 461 unsigned long min_low_ns, min_high_ns; 462 unsigned long max_low_ns, min_total_ns; 463 464 unsigned long clk_rate_khz, scl_rate_khz; 465 466 unsigned long min_low_div, min_high_div; 467 unsigned long max_low_div; 468 469 unsigned long min_div_for_hold, min_total_div; 470 unsigned long extra_div, extra_low_div, ideal_low_div; 471 472 int ret = 0; 473 474 /* Only support standard-mode and fast-mode */ 475 if (WARN_ON(scl_rate > 400000)) 476 scl_rate = 400000; 477 478 /* prevent scl_rate_khz from becoming 0 */ 479 if (WARN_ON(scl_rate < 1000)) 480 scl_rate = 1000; 481 482 /* 483 * min_low_ns: The minimum number of ns we need to hold low to 484 * meet I2C specification, should include fall time. 485 * min_high_ns: The minimum number of ns we need to hold high to 486 * meet I2C specification, should include rise time. 487 * max_low_ns: The maximum number of ns we can hold low to meet 488 * I2C specification. 489 * 490 * Note: max_low_ns should be (maximum data hold time * 2 - buffer) 491 * This is because the i2c host on Rockchip holds the data line 492 * for half the low time. 493 */ 494 if (scl_rate <= 100000) { 495 /* Standard-mode */ 496 spec_min_low_ns = 4700; 497 spec_setup_start = 4700; 498 spec_min_high_ns = 4000; 499 spec_max_data_hold_ns = 3450; 500 data_hold_buffer_ns = 50; 501 } else { 502 /* Fast-mode */ 503 spec_min_low_ns = 1300; 504 spec_setup_start = 600; 505 spec_min_high_ns = 600; 506 spec_max_data_hold_ns = 900; 507 data_hold_buffer_ns = 50; 508 } 509 min_high_ns = scl_rise_ns + spec_min_high_ns; 510 511 /* 512 * Timings for repeated start: 513 * - controller appears to drop SDA at .875x (7/8) programmed clk high. 514 * - controller appears to keep SCL high for 2x programmed clk high. 515 * 516 * We need to account for those rules in picking our "high" time so 517 * we meet tSU;STA and tHD;STA times. 518 */ 519 min_high_ns = max(min_high_ns, 520 DIV_ROUND_UP((scl_rise_ns + spec_setup_start) * 1000, 875)); 521 min_high_ns = max(min_high_ns, 522 DIV_ROUND_UP((scl_rise_ns + spec_setup_start + 523 sda_fall_ns + spec_min_high_ns), 2)); 524 525 min_low_ns = scl_fall_ns + spec_min_low_ns; 526 max_low_ns = spec_max_data_hold_ns * 2 - data_hold_buffer_ns; 527 min_total_ns = min_low_ns + min_high_ns; 528 529 /* Adjust to avoid overflow */ 530 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000); 531 scl_rate_khz = scl_rate / 1000; 532 533 /* 534 * We need the total div to be >= this number 535 * so we don't clock too fast. 536 */ 537 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8); 538 539 /* These are the min dividers needed for min hold times. */ 540 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000); 541 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000); 542 min_div_for_hold = (min_low_div + min_high_div); 543 544 /* 545 * This is the maximum divider so we don't go over the maximum. 546 * We don't round up here (we round down) since this is a maximum. 547 */ 548 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000); 549 550 if (min_low_div > max_low_div) { 551 WARN_ONCE(true, 552 "Conflicting, min_low_div %lu, max_low_div %lu\n", 553 min_low_div, max_low_div); 554 max_low_div = min_low_div; 555 } 556 557 if (min_div_for_hold > min_total_div) { 558 /* 559 * Time needed to meet hold requirements is important. 560 * Just use that. 561 */ 562 *div_low = min_low_div; 563 *div_high = min_high_div; 564 } else { 565 /* 566 * We've got to distribute some time among the low and high 567 * so we don't run too fast. 568 */ 569 extra_div = min_total_div - min_div_for_hold; 570 571 /* 572 * We'll try to split things up perfectly evenly, 573 * biasing slightly towards having a higher div 574 * for low (spend more time low). 575 */ 576 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 577 scl_rate_khz * 8 * min_total_ns); 578 579 /* Don't allow it to go over the maximum */ 580 if (ideal_low_div > max_low_div) 581 ideal_low_div = max_low_div; 582 583 /* 584 * Handle when the ideal low div is going to take up 585 * more than we have. 586 */ 587 if (ideal_low_div > min_low_div + extra_div) 588 ideal_low_div = min_low_div + extra_div; 589 590 /* Give low the "ideal" and give high whatever extra is left */ 591 extra_low_div = ideal_low_div - min_low_div; 592 *div_low = ideal_low_div; 593 *div_high = min_high_div + (extra_div - extra_low_div); 594 } 595 596 /* 597 * Adjust to the fact that the hardware has an implicit "+1". 598 * NOTE: Above calculations always produce div_low > 0 and div_high > 0. 599 */ 600 *div_low = *div_low - 1; 601 *div_high = *div_high - 1; 602 603 /* Maximum divider supported by hw is 0xffff */ 604 if (*div_low > 0xffff) { 605 *div_low = 0xffff; 606 ret = -EINVAL; 607 } 608 609 if (*div_high > 0xffff) { 610 *div_high = 0xffff; 611 ret = -EINVAL; 612 } 613 614 return ret; 615} 616 617static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate) 618{ 619 unsigned long div_low, div_high; 620 u64 t_low_ns, t_high_ns; 621 int ret; 622 623 ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, i2c->scl_rise_ns, 624 i2c->scl_fall_ns, i2c->sda_fall_ns, 625 &div_low, &div_high); 626 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency); 627 628 clk_enable(i2c->clk); 629 i2c_writel(i2c, (div_high << 16) | (div_low & 0xffff), REG_CLKDIV); 630 clk_disable(i2c->clk); 631 632 t_low_ns = div_u64(((u64)div_low + 1) * 8 * 1000000000, clk_rate); 633 t_high_ns = div_u64(((u64)div_high + 1) * 8 * 1000000000, clk_rate); 634 dev_dbg(i2c->dev, 635 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n", 636 clk_rate / 1000, 637 1000000000 / i2c->scl_frequency, 638 t_low_ns, t_high_ns); 639} 640 641/** 642 * rk3x_i2c_clk_notifier_cb - Clock rate change callback 643 * @nb: Pointer to notifier block 644 * @event: Notification reason 645 * @data: Pointer to notification data object 646 * 647 * The callback checks whether a valid bus frequency can be generated after the 648 * change. If so, the change is acknowledged, otherwise the change is aborted. 649 * New dividers are written to the HW in the pre- or post change notification 650 * depending on the scaling direction. 651 * 652 * Code adapted from i2c-cadence.c. 653 * 654 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK 655 * to acknowedge the change, NOTIFY_DONE if the notification is 656 * considered irrelevant. 657 */ 658static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long 659 event, void *data) 660{ 661 struct clk_notifier_data *ndata = data; 662 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb); 663 unsigned long div_low, div_high; 664 665 switch (event) { 666 case PRE_RATE_CHANGE: 667 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency, 668 i2c->scl_rise_ns, i2c->scl_fall_ns, 669 i2c->sda_fall_ns, 670 &div_low, &div_high) != 0) 671 return NOTIFY_STOP; 672 673 /* scale up */ 674 if (ndata->new_rate > ndata->old_rate) 675 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 676 677 return NOTIFY_OK; 678 case POST_RATE_CHANGE: 679 /* scale down */ 680 if (ndata->new_rate < ndata->old_rate) 681 rk3x_i2c_adapt_div(i2c, ndata->new_rate); 682 return NOTIFY_OK; 683 case ABORT_RATE_CHANGE: 684 /* scale up */ 685 if (ndata->new_rate > ndata->old_rate) 686 rk3x_i2c_adapt_div(i2c, ndata->old_rate); 687 return NOTIFY_OK; 688 default: 689 return NOTIFY_DONE; 690 } 691} 692 693/** 694 * Setup I2C registers for an I2C operation specified by msgs, num. 695 * 696 * Must be called with i2c->lock held. 697 * 698 * @msgs: I2C msgs to process 699 * @num: Number of msgs 700 * 701 * returns: Number of I2C msgs processed or negative in case of error 702 */ 703static int rk3x_i2c_setup(struct rk3x_i2c *i2c, struct i2c_msg *msgs, int num) 704{ 705 u32 addr = (msgs[0].addr & 0x7f) << 1; 706 int ret = 0; 707 708 /* 709 * The I2C adapter can issue a small (len < 4) write packet before 710 * reading. This speeds up SMBus-style register reads. 711 * The MRXADDR/MRXRADDR hold the slave address and the slave register 712 * address in this case. 713 */ 714 715 if (num >= 2 && msgs[0].len < 4 && 716 !(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD)) { 717 u32 reg_addr = 0; 718 int i; 719 720 dev_dbg(i2c->dev, "Combined write/read from addr 0x%x\n", 721 addr >> 1); 722 723 /* Fill MRXRADDR with the register address(es) */ 724 for (i = 0; i < msgs[0].len; ++i) { 725 reg_addr |= msgs[0].buf[i] << (i * 8); 726 reg_addr |= REG_MRXADDR_VALID(i); 727 } 728 729 /* msgs[0] is handled by hw. */ 730 i2c->msg = &msgs[1]; 731 732 i2c->mode = REG_CON_MOD_REGISTER_TX; 733 734 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), REG_MRXADDR); 735 i2c_writel(i2c, reg_addr, REG_MRXRADDR); 736 737 ret = 2; 738 } else { 739 /* 740 * We'll have to do it the boring way and process the msgs 741 * one-by-one. 742 */ 743 744 if (msgs[0].flags & I2C_M_RD) { 745 addr |= 1; /* set read bit */ 746 747 /* 748 * We have to transmit the slave addr first. Use 749 * MOD_REGISTER_TX for that purpose. 750 */ 751 i2c->mode = REG_CON_MOD_REGISTER_TX; 752 i2c_writel(i2c, addr | REG_MRXADDR_VALID(0), 753 REG_MRXADDR); 754 i2c_writel(i2c, 0, REG_MRXRADDR); 755 } else { 756 i2c->mode = REG_CON_MOD_TX; 757 } 758 759 i2c->msg = &msgs[0]; 760 761 ret = 1; 762 } 763 764 i2c->addr = msgs[0].addr; 765 i2c->busy = true; 766 i2c->state = STATE_START; 767 i2c->processed = 0; 768 i2c->error = 0; 769 770 rk3x_i2c_clean_ipd(i2c); 771 772 return ret; 773} 774 775static int rk3x_i2c_xfer(struct i2c_adapter *adap, 776 struct i2c_msg *msgs, int num) 777{ 778 struct rk3x_i2c *i2c = (struct rk3x_i2c *)adap->algo_data; 779 unsigned long timeout, flags; 780 int ret = 0; 781 int i; 782 783 spin_lock_irqsave(&i2c->lock, flags); 784 785 clk_enable(i2c->clk); 786 787 i2c->is_last_msg = false; 788 789 /* 790 * Process msgs. We can handle more than one message at once (see 791 * rk3x_i2c_setup()). 792 */ 793 for (i = 0; i < num; i += ret) { 794 ret = rk3x_i2c_setup(i2c, msgs + i, num - i); 795 796 if (ret < 0) { 797 dev_err(i2c->dev, "rk3x_i2c_setup() failed\n"); 798 break; 799 } 800 801 if (i + ret >= num) 802 i2c->is_last_msg = true; 803 804 spin_unlock_irqrestore(&i2c->lock, flags); 805 806 rk3x_i2c_start(i2c); 807 808 timeout = wait_event_timeout(i2c->wait, !i2c->busy, 809 msecs_to_jiffies(WAIT_TIMEOUT)); 810 811 spin_lock_irqsave(&i2c->lock, flags); 812 813 if (timeout == 0) { 814 dev_err(i2c->dev, "timeout, ipd: 0x%02x, state: %d\n", 815 i2c_readl(i2c, REG_IPD), i2c->state); 816 817 /* Force a STOP condition without interrupt */ 818 i2c_writel(i2c, 0, REG_IEN); 819 i2c_writel(i2c, REG_CON_EN | REG_CON_STOP, REG_CON); 820 821 i2c->state = STATE_IDLE; 822 823 ret = -ETIMEDOUT; 824 break; 825 } 826 827 if (i2c->error) { 828 ret = i2c->error; 829 break; 830 } 831 } 832 833 clk_disable(i2c->clk); 834 spin_unlock_irqrestore(&i2c->lock, flags); 835 836 return ret < 0 ? ret : num; 837} 838 839static u32 rk3x_i2c_func(struct i2c_adapter *adap) 840{ 841 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING; 842} 843 844static const struct i2c_algorithm rk3x_i2c_algorithm = { 845 .master_xfer = rk3x_i2c_xfer, 846 .functionality = rk3x_i2c_func, 847}; 848 849static struct rk3x_i2c_soc_data soc_data[3] = { 850 { .grf_offset = 0x154 }, /* rk3066 */ 851 { .grf_offset = 0x0a4 }, /* rk3188 */ 852 { .grf_offset = -1 }, /* no I2C switching needed */ 853}; 854 855static const struct of_device_id rk3x_i2c_match[] = { 856 { .compatible = "rockchip,rk3066-i2c", .data = (void *)&soc_data[0] }, 857 { .compatible = "rockchip,rk3188-i2c", .data = (void *)&soc_data[1] }, 858 { .compatible = "rockchip,rk3288-i2c", .data = (void *)&soc_data[2] }, 859 {}, 860}; 861 862static int rk3x_i2c_probe(struct platform_device *pdev) 863{ 864 struct device_node *np = pdev->dev.of_node; 865 const struct of_device_id *match; 866 struct rk3x_i2c *i2c; 867 struct resource *mem; 868 int ret = 0; 869 int bus_nr; 870 u32 value; 871 int irq; 872 unsigned long clk_rate; 873 874 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); 875 if (!i2c) 876 return -ENOMEM; 877 878 match = of_match_node(rk3x_i2c_match, np); 879 i2c->soc_data = (struct rk3x_i2c_soc_data *)match->data; 880 881 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", 882 &i2c->scl_frequency)) { 883 dev_info(&pdev->dev, "using default SCL frequency: %d\n", 884 DEFAULT_SCL_RATE); 885 i2c->scl_frequency = DEFAULT_SCL_RATE; 886 } 887 888 if (i2c->scl_frequency == 0 || i2c->scl_frequency > 400 * 1000) { 889 dev_warn(&pdev->dev, "invalid SCL frequency specified.\n"); 890 dev_warn(&pdev->dev, "using default SCL frequency: %d\n", 891 DEFAULT_SCL_RATE); 892 i2c->scl_frequency = DEFAULT_SCL_RATE; 893 } 894 895 /* 896 * Read rise and fall time from device tree. If not available use 897 * the default maximum timing from the specification. 898 */ 899 if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-rising-time-ns", 900 &i2c->scl_rise_ns)) { 901 if (i2c->scl_frequency <= 100000) 902 i2c->scl_rise_ns = 1000; 903 else 904 i2c->scl_rise_ns = 300; 905 } 906 if (of_property_read_u32(pdev->dev.of_node, "i2c-scl-falling-time-ns", 907 &i2c->scl_fall_ns)) 908 i2c->scl_fall_ns = 300; 909 if (of_property_read_u32(pdev->dev.of_node, "i2c-sda-falling-time-ns", 910 &i2c->scl_fall_ns)) 911 i2c->sda_fall_ns = i2c->scl_fall_ns; 912 913 strlcpy(i2c->adap.name, "rk3x-i2c", sizeof(i2c->adap.name)); 914 i2c->adap.owner = THIS_MODULE; 915 i2c->adap.algo = &rk3x_i2c_algorithm; 916 i2c->adap.retries = 3; 917 i2c->adap.dev.of_node = np; 918 i2c->adap.algo_data = i2c; 919 i2c->adap.dev.parent = &pdev->dev; 920 921 i2c->dev = &pdev->dev; 922 923 spin_lock_init(&i2c->lock); 924 init_waitqueue_head(&i2c->wait); 925 926 i2c->clk = devm_clk_get(&pdev->dev, NULL); 927 if (IS_ERR(i2c->clk)) { 928 dev_err(&pdev->dev, "cannot get clock\n"); 929 return PTR_ERR(i2c->clk); 930 } 931 932 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 933 i2c->regs = devm_ioremap_resource(&pdev->dev, mem); 934 if (IS_ERR(i2c->regs)) 935 return PTR_ERR(i2c->regs); 936 937 /* Try to set the I2C adapter number from dt */ 938 bus_nr = of_alias_get_id(np, "i2c"); 939 940 /* 941 * Switch to new interface if the SoC also offers the old one. 942 * The control bit is located in the GRF register space. 943 */ 944 if (i2c->soc_data->grf_offset >= 0) { 945 struct regmap *grf; 946 947 grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 948 if (IS_ERR(grf)) { 949 dev_err(&pdev->dev, 950 "rk3x-i2c needs 'rockchip,grf' property\n"); 951 return PTR_ERR(grf); 952 } 953 954 if (bus_nr < 0) { 955 dev_err(&pdev->dev, "rk3x-i2c needs i2cX alias"); 956 return -EINVAL; 957 } 958 959 /* 27+i: write mask, 11+i: value */ 960 value = BIT(27 + bus_nr) | BIT(11 + bus_nr); 961 962 ret = regmap_write(grf, i2c->soc_data->grf_offset, value); 963 if (ret != 0) { 964 dev_err(i2c->dev, "Could not write to GRF: %d\n", ret); 965 return ret; 966 } 967 } 968 969 /* IRQ setup */ 970 irq = platform_get_irq(pdev, 0); 971 if (irq < 0) { 972 dev_err(&pdev->dev, "cannot find rk3x IRQ\n"); 973 return irq; 974 } 975 976 ret = devm_request_irq(&pdev->dev, irq, rk3x_i2c_irq, 977 0, dev_name(&pdev->dev), i2c); 978 if (ret < 0) { 979 dev_err(&pdev->dev, "cannot request IRQ\n"); 980 return ret; 981 } 982 983 platform_set_drvdata(pdev, i2c); 984 985 ret = clk_prepare(i2c->clk); 986 if (ret < 0) { 987 dev_err(&pdev->dev, "Could not prepare clock\n"); 988 return ret; 989 } 990 991 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb; 992 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb); 993 if (ret != 0) { 994 dev_err(&pdev->dev, "Unable to register clock notifier\n"); 995 goto err_clk; 996 } 997 998 clk_rate = clk_get_rate(i2c->clk); 999 rk3x_i2c_adapt_div(i2c, clk_rate); 1000 1001 ret = i2c_add_adapter(&i2c->adap); 1002 if (ret < 0) { 1003 dev_err(&pdev->dev, "Could not register adapter\n"); 1004 goto err_clk_notifier; 1005 } 1006 1007 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs); 1008 1009 return 0; 1010 1011err_clk_notifier: 1012 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1013err_clk: 1014 clk_unprepare(i2c->clk); 1015 return ret; 1016} 1017 1018static int rk3x_i2c_remove(struct platform_device *pdev) 1019{ 1020 struct rk3x_i2c *i2c = platform_get_drvdata(pdev); 1021 1022 i2c_del_adapter(&i2c->adap); 1023 1024 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb); 1025 clk_unprepare(i2c->clk); 1026 1027 return 0; 1028} 1029 1030static struct platform_driver rk3x_i2c_driver = { 1031 .probe = rk3x_i2c_probe, 1032 .remove = rk3x_i2c_remove, 1033 .driver = { 1034 .name = "rk3x-i2c", 1035 .of_match_table = rk3x_i2c_match, 1036 }, 1037}; 1038 1039module_platform_driver(rk3x_i2c_driver); 1040 1041MODULE_DESCRIPTION("Rockchip RK3xxx I2C Bus driver"); 1042MODULE_AUTHOR("Max Schwarz <max.schwarz@online.de>"); 1043MODULE_LICENSE("GPL v2"); 1044