1 /*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
22 */
23 #include <drm/drmP.h>
24 #include "radeon.h"
25 #include "avivod.h"
26 #include "atom.h"
27 #include "r600_dpm.h"
28 #include <linux/power_supply.h>
29 #include <linux/hwmon.h>
30 #include <linux/hwmon-sysfs.h>
31
32 #define RADEON_IDLE_LOOP_MS 100
33 #define RADEON_RECLOCK_DELAY_MS 200
34 #define RADEON_WAIT_VBLANK_TIMEOUT 200
35
36 static const char *radeon_pm_state_type_name[5] = {
37 "",
38 "Powersave",
39 "Battery",
40 "Balanced",
41 "Performance",
42 };
43
44 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
45 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
46 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
48 static void radeon_pm_update_profile(struct radeon_device *rdev);
49 static void radeon_pm_set_clocks(struct radeon_device *rdev);
50
radeon_pm_get_type_index(struct radeon_device * rdev,enum radeon_pm_state_type ps_type,int instance)51 int radeon_pm_get_type_index(struct radeon_device *rdev,
52 enum radeon_pm_state_type ps_type,
53 int instance)
54 {
55 int i;
56 int found_instance = -1;
57
58 for (i = 0; i < rdev->pm.num_power_states; i++) {
59 if (rdev->pm.power_state[i].type == ps_type) {
60 found_instance++;
61 if (found_instance == instance)
62 return i;
63 }
64 }
65 /* return default if no match */
66 return rdev->pm.default_power_state_index;
67 }
68
radeon_pm_acpi_event_handler(struct radeon_device * rdev)69 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
70 {
71 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
72 mutex_lock(&rdev->pm.mutex);
73 if (power_supply_is_system_supplied() > 0)
74 rdev->pm.dpm.ac_power = true;
75 else
76 rdev->pm.dpm.ac_power = false;
77 if (rdev->family == CHIP_ARUBA) {
78 if (rdev->asic->dpm.enable_bapm)
79 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power);
80 }
81 mutex_unlock(&rdev->pm.mutex);
82 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
83 if (rdev->pm.profile == PM_PROFILE_AUTO) {
84 mutex_lock(&rdev->pm.mutex);
85 radeon_pm_update_profile(rdev);
86 radeon_pm_set_clocks(rdev);
87 mutex_unlock(&rdev->pm.mutex);
88 }
89 }
90 }
91
radeon_pm_update_profile(struct radeon_device * rdev)92 static void radeon_pm_update_profile(struct radeon_device *rdev)
93 {
94 switch (rdev->pm.profile) {
95 case PM_PROFILE_DEFAULT:
96 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
97 break;
98 case PM_PROFILE_AUTO:
99 if (power_supply_is_system_supplied() > 0) {
100 if (rdev->pm.active_crtc_count > 1)
101 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
102 else
103 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
104 } else {
105 if (rdev->pm.active_crtc_count > 1)
106 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
107 else
108 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
109 }
110 break;
111 case PM_PROFILE_LOW:
112 if (rdev->pm.active_crtc_count > 1)
113 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
114 else
115 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
116 break;
117 case PM_PROFILE_MID:
118 if (rdev->pm.active_crtc_count > 1)
119 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
120 else
121 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
122 break;
123 case PM_PROFILE_HIGH:
124 if (rdev->pm.active_crtc_count > 1)
125 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
126 else
127 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
128 break;
129 }
130
131 if (rdev->pm.active_crtc_count == 0) {
132 rdev->pm.requested_power_state_index =
133 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
134 rdev->pm.requested_clock_mode_index =
135 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
136 } else {
137 rdev->pm.requested_power_state_index =
138 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
139 rdev->pm.requested_clock_mode_index =
140 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
141 }
142 }
143
radeon_unmap_vram_bos(struct radeon_device * rdev)144 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
145 {
146 struct radeon_bo *bo, *n;
147
148 if (list_empty(&rdev->gem.objects))
149 return;
150
151 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
152 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
153 ttm_bo_unmap_virtual(&bo->tbo);
154 }
155 }
156
radeon_sync_with_vblank(struct radeon_device * rdev)157 static void radeon_sync_with_vblank(struct radeon_device *rdev)
158 {
159 if (rdev->pm.active_crtcs) {
160 rdev->pm.vblank_sync = false;
161 wait_event_timeout(
162 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
164 }
165 }
166
radeon_set_power_state(struct radeon_device * rdev)167 static void radeon_set_power_state(struct radeon_device *rdev)
168 {
169 u32 sclk, mclk;
170 bool misc_after = false;
171
172 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
173 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
174 return;
175
176 if (radeon_gui_idle(rdev)) {
177 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
178 clock_info[rdev->pm.requested_clock_mode_index].sclk;
179 if (sclk > rdev->pm.default_sclk)
180 sclk = rdev->pm.default_sclk;
181
182 /* starting with BTC, there is one state that is used for both
183 * MH and SH. Difference is that we always use the high clock index for
184 * mclk and vddci.
185 */
186 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
187 (rdev->family >= CHIP_BARTS) &&
188 rdev->pm.active_crtc_count &&
189 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
190 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
191 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
192 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
193 else
194 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
195 clock_info[rdev->pm.requested_clock_mode_index].mclk;
196
197 if (mclk > rdev->pm.default_mclk)
198 mclk = rdev->pm.default_mclk;
199
200 /* upvolt before raising clocks, downvolt after lowering clocks */
201 if (sclk < rdev->pm.current_sclk)
202 misc_after = true;
203
204 radeon_sync_with_vblank(rdev);
205
206 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
207 if (!radeon_pm_in_vbl(rdev))
208 return;
209 }
210
211 radeon_pm_prepare(rdev);
212
213 if (!misc_after)
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
216
217 /* set engine clock */
218 if (sclk != rdev->pm.current_sclk) {
219 radeon_pm_debug_check_in_vbl(rdev, false);
220 radeon_set_engine_clock(rdev, sclk);
221 radeon_pm_debug_check_in_vbl(rdev, true);
222 rdev->pm.current_sclk = sclk;
223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
224 }
225
226 /* set memory clock */
227 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
228 radeon_pm_debug_check_in_vbl(rdev, false);
229 radeon_set_memory_clock(rdev, mclk);
230 radeon_pm_debug_check_in_vbl(rdev, true);
231 rdev->pm.current_mclk = mclk;
232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
233 }
234
235 if (misc_after)
236 /* voltage, pcie lanes, etc.*/
237 radeon_pm_misc(rdev);
238
239 radeon_pm_finish(rdev);
240
241 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
242 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
243 } else
244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
245 }
246
radeon_pm_set_clocks(struct radeon_device * rdev)247 static void radeon_pm_set_clocks(struct radeon_device *rdev)
248 {
249 int i, r;
250
251 /* no need to take locks, etc. if nothing's going to change */
252 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
253 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
254 return;
255
256 mutex_lock(&rdev->ddev->struct_mutex);
257 down_write(&rdev->pm.mclk_lock);
258 mutex_lock(&rdev->ring_lock);
259
260 /* wait for the rings to drain */
261 for (i = 0; i < RADEON_NUM_RINGS; i++) {
262 struct radeon_ring *ring = &rdev->ring[i];
263 if (!ring->ready) {
264 continue;
265 }
266 r = radeon_fence_wait_empty(rdev, i);
267 if (r) {
268 /* needs a GPU reset dont reset here */
269 mutex_unlock(&rdev->ring_lock);
270 up_write(&rdev->pm.mclk_lock);
271 mutex_unlock(&rdev->ddev->struct_mutex);
272 return;
273 }
274 }
275
276 radeon_unmap_vram_bos(rdev);
277
278 if (rdev->irq.installed) {
279 for (i = 0; i < rdev->num_crtc; i++) {
280 if (rdev->pm.active_crtcs & (1 << i)) {
281 rdev->pm.req_vblank |= (1 << i);
282 drm_vblank_get(rdev->ddev, i);
283 }
284 }
285 }
286
287 radeon_set_power_state(rdev);
288
289 if (rdev->irq.installed) {
290 for (i = 0; i < rdev->num_crtc; i++) {
291 if (rdev->pm.req_vblank & (1 << i)) {
292 rdev->pm.req_vblank &= ~(1 << i);
293 drm_vblank_put(rdev->ddev, i);
294 }
295 }
296 }
297
298 /* update display watermarks based on new power state */
299 radeon_update_bandwidth_info(rdev);
300 if (rdev->pm.active_crtc_count)
301 radeon_bandwidth_update(rdev);
302
303 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
304
305 mutex_unlock(&rdev->ring_lock);
306 up_write(&rdev->pm.mclk_lock);
307 mutex_unlock(&rdev->ddev->struct_mutex);
308 }
309
radeon_pm_print_states(struct radeon_device * rdev)310 static void radeon_pm_print_states(struct radeon_device *rdev)
311 {
312 int i, j;
313 struct radeon_power_state *power_state;
314 struct radeon_pm_clock_info *clock_info;
315
316 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
317 for (i = 0; i < rdev->pm.num_power_states; i++) {
318 power_state = &rdev->pm.power_state[i];
319 DRM_DEBUG_DRIVER("State %d: %s\n", i,
320 radeon_pm_state_type_name[power_state->type]);
321 if (i == rdev->pm.default_power_state_index)
322 DRM_DEBUG_DRIVER("\tDefault");
323 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
324 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
325 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
326 DRM_DEBUG_DRIVER("\tSingle display only\n");
327 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
328 for (j = 0; j < power_state->num_clock_modes; j++) {
329 clock_info = &(power_state->clock_info[j]);
330 if (rdev->flags & RADEON_IS_IGP)
331 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
332 j,
333 clock_info->sclk * 10);
334 else
335 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
336 j,
337 clock_info->sclk * 10,
338 clock_info->mclk * 10,
339 clock_info->voltage.voltage);
340 }
341 }
342 }
343
radeon_get_pm_profile(struct device * dev,struct device_attribute * attr,char * buf)344 static ssize_t radeon_get_pm_profile(struct device *dev,
345 struct device_attribute *attr,
346 char *buf)
347 {
348 struct drm_device *ddev = dev_get_drvdata(dev);
349 struct radeon_device *rdev = ddev->dev_private;
350 int cp = rdev->pm.profile;
351
352 return snprintf(buf, PAGE_SIZE, "%s\n",
353 (cp == PM_PROFILE_AUTO) ? "auto" :
354 (cp == PM_PROFILE_LOW) ? "low" :
355 (cp == PM_PROFILE_MID) ? "mid" :
356 (cp == PM_PROFILE_HIGH) ? "high" : "default");
357 }
358
radeon_set_pm_profile(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)359 static ssize_t radeon_set_pm_profile(struct device *dev,
360 struct device_attribute *attr,
361 const char *buf,
362 size_t count)
363 {
364 struct drm_device *ddev = dev_get_drvdata(dev);
365 struct radeon_device *rdev = ddev->dev_private;
366
367 /* Can't set profile when the card is off */
368 if ((rdev->flags & RADEON_IS_PX) &&
369 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
370 return -EINVAL;
371
372 mutex_lock(&rdev->pm.mutex);
373 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
374 if (strncmp("default", buf, strlen("default")) == 0)
375 rdev->pm.profile = PM_PROFILE_DEFAULT;
376 else if (strncmp("auto", buf, strlen("auto")) == 0)
377 rdev->pm.profile = PM_PROFILE_AUTO;
378 else if (strncmp("low", buf, strlen("low")) == 0)
379 rdev->pm.profile = PM_PROFILE_LOW;
380 else if (strncmp("mid", buf, strlen("mid")) == 0)
381 rdev->pm.profile = PM_PROFILE_MID;
382 else if (strncmp("high", buf, strlen("high")) == 0)
383 rdev->pm.profile = PM_PROFILE_HIGH;
384 else {
385 count = -EINVAL;
386 goto fail;
387 }
388 radeon_pm_update_profile(rdev);
389 radeon_pm_set_clocks(rdev);
390 } else
391 count = -EINVAL;
392
393 fail:
394 mutex_unlock(&rdev->pm.mutex);
395
396 return count;
397 }
398
radeon_get_pm_method(struct device * dev,struct device_attribute * attr,char * buf)399 static ssize_t radeon_get_pm_method(struct device *dev,
400 struct device_attribute *attr,
401 char *buf)
402 {
403 struct drm_device *ddev = dev_get_drvdata(dev);
404 struct radeon_device *rdev = ddev->dev_private;
405 int pm = rdev->pm.pm_method;
406
407 return snprintf(buf, PAGE_SIZE, "%s\n",
408 (pm == PM_METHOD_DYNPM) ? "dynpm" :
409 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
410 }
411
radeon_set_pm_method(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)412 static ssize_t radeon_set_pm_method(struct device *dev,
413 struct device_attribute *attr,
414 const char *buf,
415 size_t count)
416 {
417 struct drm_device *ddev = dev_get_drvdata(dev);
418 struct radeon_device *rdev = ddev->dev_private;
419
420 /* Can't set method when the card is off */
421 if ((rdev->flags & RADEON_IS_PX) &&
422 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
423 count = -EINVAL;
424 goto fail;
425 }
426
427 /* we don't support the legacy modes with dpm */
428 if (rdev->pm.pm_method == PM_METHOD_DPM) {
429 count = -EINVAL;
430 goto fail;
431 }
432
433 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
434 mutex_lock(&rdev->pm.mutex);
435 rdev->pm.pm_method = PM_METHOD_DYNPM;
436 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
437 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
438 mutex_unlock(&rdev->pm.mutex);
439 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
440 mutex_lock(&rdev->pm.mutex);
441 /* disable dynpm */
442 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
443 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
444 rdev->pm.pm_method = PM_METHOD_PROFILE;
445 mutex_unlock(&rdev->pm.mutex);
446 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
447 } else {
448 count = -EINVAL;
449 goto fail;
450 }
451 radeon_pm_compute_clocks(rdev);
452 fail:
453 return count;
454 }
455
radeon_get_dpm_state(struct device * dev,struct device_attribute * attr,char * buf)456 static ssize_t radeon_get_dpm_state(struct device *dev,
457 struct device_attribute *attr,
458 char *buf)
459 {
460 struct drm_device *ddev = dev_get_drvdata(dev);
461 struct radeon_device *rdev = ddev->dev_private;
462 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
463
464 return snprintf(buf, PAGE_SIZE, "%s\n",
465 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
466 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
467 }
468
radeon_set_dpm_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)469 static ssize_t radeon_set_dpm_state(struct device *dev,
470 struct device_attribute *attr,
471 const char *buf,
472 size_t count)
473 {
474 struct drm_device *ddev = dev_get_drvdata(dev);
475 struct radeon_device *rdev = ddev->dev_private;
476
477 mutex_lock(&rdev->pm.mutex);
478 if (strncmp("battery", buf, strlen("battery")) == 0)
479 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
480 else if (strncmp("balanced", buf, strlen("balanced")) == 0)
481 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
482 else if (strncmp("performance", buf, strlen("performance")) == 0)
483 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
484 else {
485 mutex_unlock(&rdev->pm.mutex);
486 count = -EINVAL;
487 goto fail;
488 }
489 mutex_unlock(&rdev->pm.mutex);
490
491 /* Can't set dpm state when the card is off */
492 if (!(rdev->flags & RADEON_IS_PX) ||
493 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
494 radeon_pm_compute_clocks(rdev);
495
496 fail:
497 return count;
498 }
499
radeon_get_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,char * buf)500 static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev,
501 struct device_attribute *attr,
502 char *buf)
503 {
504 struct drm_device *ddev = dev_get_drvdata(dev);
505 struct radeon_device *rdev = ddev->dev_private;
506 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
507
508 if ((rdev->flags & RADEON_IS_PX) &&
509 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
510 return snprintf(buf, PAGE_SIZE, "off\n");
511
512 return snprintf(buf, PAGE_SIZE, "%s\n",
513 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" :
514 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high");
515 }
516
radeon_set_dpm_forced_performance_level(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)517 static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev,
518 struct device_attribute *attr,
519 const char *buf,
520 size_t count)
521 {
522 struct drm_device *ddev = dev_get_drvdata(dev);
523 struct radeon_device *rdev = ddev->dev_private;
524 enum radeon_dpm_forced_level level;
525 int ret = 0;
526
527 /* Can't force performance level when the card is off */
528 if ((rdev->flags & RADEON_IS_PX) &&
529 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
530 return -EINVAL;
531
532 mutex_lock(&rdev->pm.mutex);
533 if (strncmp("low", buf, strlen("low")) == 0) {
534 level = RADEON_DPM_FORCED_LEVEL_LOW;
535 } else if (strncmp("high", buf, strlen("high")) == 0) {
536 level = RADEON_DPM_FORCED_LEVEL_HIGH;
537 } else if (strncmp("auto", buf, strlen("auto")) == 0) {
538 level = RADEON_DPM_FORCED_LEVEL_AUTO;
539 } else {
540 count = -EINVAL;
541 goto fail;
542 }
543 if (rdev->asic->dpm.force_performance_level) {
544 if (rdev->pm.dpm.thermal_active) {
545 count = -EINVAL;
546 goto fail;
547 }
548 ret = radeon_dpm_force_performance_level(rdev, level);
549 if (ret)
550 count = -EINVAL;
551 }
552 fail:
553 mutex_unlock(&rdev->pm.mutex);
554
555 return count;
556 }
557
radeon_hwmon_get_pwm1_enable(struct device * dev,struct device_attribute * attr,char * buf)558 static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev,
559 struct device_attribute *attr,
560 char *buf)
561 {
562 struct radeon_device *rdev = dev_get_drvdata(dev);
563 u32 pwm_mode = 0;
564
565 if (rdev->asic->dpm.fan_ctrl_get_mode)
566 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev);
567
568 /* never 0 (full-speed), fuse or smc-controlled always */
569 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
570 }
571
radeon_hwmon_set_pwm1_enable(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)572 static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev,
573 struct device_attribute *attr,
574 const char *buf,
575 size_t count)
576 {
577 struct radeon_device *rdev = dev_get_drvdata(dev);
578 int err;
579 int value;
580
581 if(!rdev->asic->dpm.fan_ctrl_set_mode)
582 return -EINVAL;
583
584 err = kstrtoint(buf, 10, &value);
585 if (err)
586 return err;
587
588 switch (value) {
589 case 1: /* manual, percent-based */
590 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC);
591 break;
592 default: /* disable */
593 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0);
594 break;
595 }
596
597 return count;
598 }
599
radeon_hwmon_get_pwm1_min(struct device * dev,struct device_attribute * attr,char * buf)600 static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev,
601 struct device_attribute *attr,
602 char *buf)
603 {
604 return sprintf(buf, "%i\n", 0);
605 }
606
radeon_hwmon_get_pwm1_max(struct device * dev,struct device_attribute * attr,char * buf)607 static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev,
608 struct device_attribute *attr,
609 char *buf)
610 {
611 return sprintf(buf, "%i\n", 255);
612 }
613
radeon_hwmon_set_pwm1(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)614 static ssize_t radeon_hwmon_set_pwm1(struct device *dev,
615 struct device_attribute *attr,
616 const char *buf, size_t count)
617 {
618 struct radeon_device *rdev = dev_get_drvdata(dev);
619 int err;
620 u32 value;
621
622 err = kstrtou32(buf, 10, &value);
623 if (err)
624 return err;
625
626 value = (value * 100) / 255;
627
628 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value);
629 if (err)
630 return err;
631
632 return count;
633 }
634
radeon_hwmon_get_pwm1(struct device * dev,struct device_attribute * attr,char * buf)635 static ssize_t radeon_hwmon_get_pwm1(struct device *dev,
636 struct device_attribute *attr,
637 char *buf)
638 {
639 struct radeon_device *rdev = dev_get_drvdata(dev);
640 int err;
641 u32 speed;
642
643 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed);
644 if (err)
645 return err;
646
647 speed = (speed * 255) / 100;
648
649 return sprintf(buf, "%i\n", speed);
650 }
651
652 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
653 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
654 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
655 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
656 radeon_get_dpm_forced_performance_level,
657 radeon_set_dpm_forced_performance_level);
658
radeon_hwmon_show_temp(struct device * dev,struct device_attribute * attr,char * buf)659 static ssize_t radeon_hwmon_show_temp(struct device *dev,
660 struct device_attribute *attr,
661 char *buf)
662 {
663 struct radeon_device *rdev = dev_get_drvdata(dev);
664 struct drm_device *ddev = rdev->ddev;
665 int temp;
666
667 /* Can't get temperature when the card is off */
668 if ((rdev->flags & RADEON_IS_PX) &&
669 (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
670 return -EINVAL;
671
672 if (rdev->asic->pm.get_temperature)
673 temp = radeon_get_temperature(rdev);
674 else
675 temp = 0;
676
677 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
678 }
679
radeon_hwmon_show_temp_thresh(struct device * dev,struct device_attribute * attr,char * buf)680 static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev,
681 struct device_attribute *attr,
682 char *buf)
683 {
684 struct radeon_device *rdev = dev_get_drvdata(dev);
685 int hyst = to_sensor_dev_attr(attr)->index;
686 int temp;
687
688 if (hyst)
689 temp = rdev->pm.dpm.thermal.min_temp;
690 else
691 temp = rdev->pm.dpm.thermal.max_temp;
692
693 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
694 }
695
696 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
697 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0);
698 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1);
699 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0);
700 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0);
701 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0);
702 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0);
703
704
705 static struct attribute *hwmon_attributes[] = {
706 &sensor_dev_attr_temp1_input.dev_attr.attr,
707 &sensor_dev_attr_temp1_crit.dev_attr.attr,
708 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
709 &sensor_dev_attr_pwm1.dev_attr.attr,
710 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
711 &sensor_dev_attr_pwm1_min.dev_attr.attr,
712 &sensor_dev_attr_pwm1_max.dev_attr.attr,
713 NULL
714 };
715
hwmon_attributes_visible(struct kobject * kobj,struct attribute * attr,int index)716 static umode_t hwmon_attributes_visible(struct kobject *kobj,
717 struct attribute *attr, int index)
718 {
719 struct device *dev = container_of(kobj, struct device, kobj);
720 struct radeon_device *rdev = dev_get_drvdata(dev);
721 umode_t effective_mode = attr->mode;
722
723 /* Skip attributes if DPM is not enabled */
724 if (rdev->pm.pm_method != PM_METHOD_DPM &&
725 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
726 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
727 attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
728 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
729 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
730 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
731 return 0;
732
733 /* Skip fan attributes if fan is not present */
734 if (rdev->pm.no_fan &&
735 (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
736 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
737 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
738 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
739 return 0;
740
741 /* mask fan attributes if we have no bindings for this asic to expose */
742 if ((!rdev->asic->dpm.get_fan_speed_percent &&
743 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
744 (!rdev->asic->dpm.fan_ctrl_get_mode &&
745 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
746 effective_mode &= ~S_IRUGO;
747
748 if ((!rdev->asic->dpm.set_fan_speed_percent &&
749 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
750 (!rdev->asic->dpm.fan_ctrl_set_mode &&
751 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
752 effective_mode &= ~S_IWUSR;
753
754 /* hide max/min values if we can't both query and manage the fan */
755 if ((!rdev->asic->dpm.set_fan_speed_percent &&
756 !rdev->asic->dpm.get_fan_speed_percent) &&
757 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
758 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
759 return 0;
760
761 return effective_mode;
762 }
763
764 static const struct attribute_group hwmon_attrgroup = {
765 .attrs = hwmon_attributes,
766 .is_visible = hwmon_attributes_visible,
767 };
768
769 static const struct attribute_group *hwmon_groups[] = {
770 &hwmon_attrgroup,
771 NULL
772 };
773
radeon_hwmon_init(struct radeon_device * rdev)774 static int radeon_hwmon_init(struct radeon_device *rdev)
775 {
776 int err = 0;
777
778 switch (rdev->pm.int_thermal_type) {
779 case THERMAL_TYPE_RV6XX:
780 case THERMAL_TYPE_RV770:
781 case THERMAL_TYPE_EVERGREEN:
782 case THERMAL_TYPE_NI:
783 case THERMAL_TYPE_SUMO:
784 case THERMAL_TYPE_SI:
785 case THERMAL_TYPE_CI:
786 case THERMAL_TYPE_KV:
787 if (rdev->asic->pm.get_temperature == NULL)
788 return err;
789 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev,
790 "radeon", rdev,
791 hwmon_groups);
792 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
793 err = PTR_ERR(rdev->pm.int_hwmon_dev);
794 dev_err(rdev->dev,
795 "Unable to register hwmon device: %d\n", err);
796 }
797 break;
798 default:
799 break;
800 }
801
802 return err;
803 }
804
radeon_hwmon_fini(struct radeon_device * rdev)805 static void radeon_hwmon_fini(struct radeon_device *rdev)
806 {
807 if (rdev->pm.int_hwmon_dev)
808 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
809 }
810
radeon_dpm_thermal_work_handler(struct work_struct * work)811 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
812 {
813 struct radeon_device *rdev =
814 container_of(work, struct radeon_device,
815 pm.dpm.thermal.work);
816 /* switch to the thermal state */
817 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
818
819 if (!rdev->pm.dpm_enabled)
820 return;
821
822 if (rdev->asic->pm.get_temperature) {
823 int temp = radeon_get_temperature(rdev);
824
825 if (temp < rdev->pm.dpm.thermal.min_temp)
826 /* switch back the user state */
827 dpm_state = rdev->pm.dpm.user_state;
828 } else {
829 if (rdev->pm.dpm.thermal.high_to_low)
830 /* switch back the user state */
831 dpm_state = rdev->pm.dpm.user_state;
832 }
833 mutex_lock(&rdev->pm.mutex);
834 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
835 rdev->pm.dpm.thermal_active = true;
836 else
837 rdev->pm.dpm.thermal_active = false;
838 rdev->pm.dpm.state = dpm_state;
839 mutex_unlock(&rdev->pm.mutex);
840
841 radeon_pm_compute_clocks(rdev);
842 }
843
radeon_dpm_single_display(struct radeon_device * rdev)844 static bool radeon_dpm_single_display(struct radeon_device *rdev)
845 {
846 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ?
847 true : false;
848
849 /* check if the vblank period is too short to adjust the mclk */
850 if (single_display && rdev->asic->dpm.vblank_too_short) {
851 if (radeon_dpm_vblank_too_short(rdev))
852 single_display = false;
853 }
854
855 /* 120hz tends to be problematic even if they are under the
856 * vblank limit.
857 */
858 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
859 single_display = false;
860
861 return single_display;
862 }
863
radeon_dpm_pick_power_state(struct radeon_device * rdev,enum radeon_pm_state_type dpm_state)864 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
865 enum radeon_pm_state_type dpm_state)
866 {
867 int i;
868 struct radeon_ps *ps;
869 u32 ui_class;
870 bool single_display = radeon_dpm_single_display(rdev);
871
872 /* certain older asics have a separare 3D performance state,
873 * so try that first if the user selected performance
874 */
875 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
876 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
877 /* balanced states don't exist at the moment */
878 if (dpm_state == POWER_STATE_TYPE_BALANCED)
879 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
880
881 restart_search:
882 /* Pick the best power state based on current conditions */
883 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
884 ps = &rdev->pm.dpm.ps[i];
885 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
886 switch (dpm_state) {
887 /* user states */
888 case POWER_STATE_TYPE_BATTERY:
889 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
890 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
891 if (single_display)
892 return ps;
893 } else
894 return ps;
895 }
896 break;
897 case POWER_STATE_TYPE_BALANCED:
898 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
899 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
900 if (single_display)
901 return ps;
902 } else
903 return ps;
904 }
905 break;
906 case POWER_STATE_TYPE_PERFORMANCE:
907 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
908 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
909 if (single_display)
910 return ps;
911 } else
912 return ps;
913 }
914 break;
915 /* internal states */
916 case POWER_STATE_TYPE_INTERNAL_UVD:
917 if (rdev->pm.dpm.uvd_ps)
918 return rdev->pm.dpm.uvd_ps;
919 else
920 break;
921 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
922 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
923 return ps;
924 break;
925 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
926 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
927 return ps;
928 break;
929 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
930 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
931 return ps;
932 break;
933 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
934 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
935 return ps;
936 break;
937 case POWER_STATE_TYPE_INTERNAL_BOOT:
938 return rdev->pm.dpm.boot_ps;
939 case POWER_STATE_TYPE_INTERNAL_THERMAL:
940 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
941 return ps;
942 break;
943 case POWER_STATE_TYPE_INTERNAL_ACPI:
944 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
945 return ps;
946 break;
947 case POWER_STATE_TYPE_INTERNAL_ULV:
948 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
949 return ps;
950 break;
951 case POWER_STATE_TYPE_INTERNAL_3DPERF:
952 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
953 return ps;
954 break;
955 default:
956 break;
957 }
958 }
959 /* use a fallback state if we didn't match */
960 switch (dpm_state) {
961 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
962 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
963 goto restart_search;
964 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
965 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
966 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
967 if (rdev->pm.dpm.uvd_ps) {
968 return rdev->pm.dpm.uvd_ps;
969 } else {
970 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
971 goto restart_search;
972 }
973 case POWER_STATE_TYPE_INTERNAL_THERMAL:
974 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
975 goto restart_search;
976 case POWER_STATE_TYPE_INTERNAL_ACPI:
977 dpm_state = POWER_STATE_TYPE_BATTERY;
978 goto restart_search;
979 case POWER_STATE_TYPE_BATTERY:
980 case POWER_STATE_TYPE_BALANCED:
981 case POWER_STATE_TYPE_INTERNAL_3DPERF:
982 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
983 goto restart_search;
984 default:
985 break;
986 }
987
988 return NULL;
989 }
990
radeon_dpm_change_power_state_locked(struct radeon_device * rdev)991 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
992 {
993 int i;
994 struct radeon_ps *ps;
995 enum radeon_pm_state_type dpm_state;
996 int ret;
997 bool single_display = radeon_dpm_single_display(rdev);
998
999 /* if dpm init failed */
1000 if (!rdev->pm.dpm_enabled)
1001 return;
1002
1003 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
1004 /* add other state override checks here */
1005 if ((!rdev->pm.dpm.thermal_active) &&
1006 (!rdev->pm.dpm.uvd_active))
1007 rdev->pm.dpm.state = rdev->pm.dpm.user_state;
1008 }
1009 dpm_state = rdev->pm.dpm.state;
1010
1011 ps = radeon_dpm_pick_power_state(rdev, dpm_state);
1012 if (ps)
1013 rdev->pm.dpm.requested_ps = ps;
1014 else
1015 return;
1016
1017 /* no need to reprogram if nothing changed unless we are on BTC+ */
1018 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
1019 /* vce just modifies an existing state so force a change */
1020 if (ps->vce_active != rdev->pm.dpm.vce_active)
1021 goto force;
1022 /* user has made a display change (such as timing) */
1023 if (rdev->pm.dpm.single_display != single_display)
1024 goto force;
1025 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
1026 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1027 * all we need to do is update the display configuration.
1028 */
1029 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
1030 /* update display watermarks based on new power state */
1031 radeon_bandwidth_update(rdev);
1032 /* update displays */
1033 radeon_dpm_display_configuration_changed(rdev);
1034 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1035 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1036 }
1037 return;
1038 } else {
1039 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1040 * nothing to do, if the num crtcs is > 1 and state is the same,
1041 * update display configuration.
1042 */
1043 if (rdev->pm.dpm.new_active_crtcs ==
1044 rdev->pm.dpm.current_active_crtcs) {
1045 return;
1046 } else {
1047 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
1048 (rdev->pm.dpm.new_active_crtc_count > 1)) {
1049 /* update display watermarks based on new power state */
1050 radeon_bandwidth_update(rdev);
1051 /* update displays */
1052 radeon_dpm_display_configuration_changed(rdev);
1053 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1054 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1055 return;
1056 }
1057 }
1058 }
1059 }
1060
1061 force:
1062 if (radeon_dpm == 1) {
1063 printk("switching from power state:\n");
1064 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
1065 printk("switching to power state:\n");
1066 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
1067 }
1068
1069 mutex_lock(&rdev->ddev->struct_mutex);
1070 down_write(&rdev->pm.mclk_lock);
1071 mutex_lock(&rdev->ring_lock);
1072
1073 /* update whether vce is active */
1074 ps->vce_active = rdev->pm.dpm.vce_active;
1075
1076 ret = radeon_dpm_pre_set_power_state(rdev);
1077 if (ret)
1078 goto done;
1079
1080 /* update display watermarks based on new power state */
1081 radeon_bandwidth_update(rdev);
1082 /* update displays */
1083 radeon_dpm_display_configuration_changed(rdev);
1084
1085 /* wait for the rings to drain */
1086 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1087 struct radeon_ring *ring = &rdev->ring[i];
1088 if (ring->ready)
1089 radeon_fence_wait_empty(rdev, i);
1090 }
1091
1092 /* program the new power state */
1093 radeon_dpm_set_power_state(rdev);
1094
1095 /* update current power state */
1096 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
1097
1098 radeon_dpm_post_set_power_state(rdev);
1099
1100 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
1101 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
1102 rdev->pm.dpm.single_display = single_display;
1103
1104 if (rdev->asic->dpm.force_performance_level) {
1105 if (rdev->pm.dpm.thermal_active) {
1106 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level;
1107 /* force low perf level for thermal */
1108 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW);
1109 /* save the user's level */
1110 rdev->pm.dpm.forced_level = level;
1111 } else {
1112 /* otherwise, user selected level */
1113 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level);
1114 }
1115 }
1116
1117 done:
1118 mutex_unlock(&rdev->ring_lock);
1119 up_write(&rdev->pm.mclk_lock);
1120 mutex_unlock(&rdev->ddev->struct_mutex);
1121 }
1122
radeon_dpm_enable_uvd(struct radeon_device * rdev,bool enable)1123 void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable)
1124 {
1125 enum radeon_pm_state_type dpm_state;
1126
1127 if (rdev->asic->dpm.powergate_uvd) {
1128 mutex_lock(&rdev->pm.mutex);
1129 /* don't powergate anything if we
1130 have active but pause streams */
1131 enable |= rdev->pm.dpm.sd > 0;
1132 enable |= rdev->pm.dpm.hd > 0;
1133 /* enable/disable UVD */
1134 radeon_dpm_powergate_uvd(rdev, !enable);
1135 mutex_unlock(&rdev->pm.mutex);
1136 } else {
1137 if (enable) {
1138 mutex_lock(&rdev->pm.mutex);
1139 rdev->pm.dpm.uvd_active = true;
1140 /* disable this for now */
1141 #if 0
1142 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0))
1143 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD;
1144 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0))
1145 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1146 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1))
1147 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1148 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2))
1149 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2;
1150 else
1151 #endif
1152 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD;
1153 rdev->pm.dpm.state = dpm_state;
1154 mutex_unlock(&rdev->pm.mutex);
1155 } else {
1156 mutex_lock(&rdev->pm.mutex);
1157 rdev->pm.dpm.uvd_active = false;
1158 mutex_unlock(&rdev->pm.mutex);
1159 }
1160
1161 radeon_pm_compute_clocks(rdev);
1162 }
1163 }
1164
radeon_dpm_enable_vce(struct radeon_device * rdev,bool enable)1165 void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable)
1166 {
1167 if (enable) {
1168 mutex_lock(&rdev->pm.mutex);
1169 rdev->pm.dpm.vce_active = true;
1170 /* XXX select vce level based on ring/task */
1171 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL;
1172 mutex_unlock(&rdev->pm.mutex);
1173 } else {
1174 mutex_lock(&rdev->pm.mutex);
1175 rdev->pm.dpm.vce_active = false;
1176 mutex_unlock(&rdev->pm.mutex);
1177 }
1178
1179 radeon_pm_compute_clocks(rdev);
1180 }
1181
radeon_pm_suspend_old(struct radeon_device * rdev)1182 static void radeon_pm_suspend_old(struct radeon_device *rdev)
1183 {
1184 mutex_lock(&rdev->pm.mutex);
1185 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1186 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
1187 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
1188 }
1189 mutex_unlock(&rdev->pm.mutex);
1190
1191 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1192 }
1193
radeon_pm_suspend_dpm(struct radeon_device * rdev)1194 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
1195 {
1196 mutex_lock(&rdev->pm.mutex);
1197 /* disable dpm */
1198 radeon_dpm_disable(rdev);
1199 /* reset the power state */
1200 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1201 rdev->pm.dpm_enabled = false;
1202 mutex_unlock(&rdev->pm.mutex);
1203 }
1204
radeon_pm_suspend(struct radeon_device * rdev)1205 void radeon_pm_suspend(struct radeon_device *rdev)
1206 {
1207 if (rdev->pm.pm_method == PM_METHOD_DPM)
1208 radeon_pm_suspend_dpm(rdev);
1209 else
1210 radeon_pm_suspend_old(rdev);
1211 }
1212
radeon_pm_resume_old(struct radeon_device * rdev)1213 static void radeon_pm_resume_old(struct radeon_device *rdev)
1214 {
1215 /* set up the default clocks if the MC ucode is loaded */
1216 if ((rdev->family >= CHIP_BARTS) &&
1217 (rdev->family <= CHIP_CAYMAN) &&
1218 rdev->mc_fw) {
1219 if (rdev->pm.default_vddc)
1220 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1221 SET_VOLTAGE_TYPE_ASIC_VDDC);
1222 if (rdev->pm.default_vddci)
1223 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1224 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1225 if (rdev->pm.default_sclk)
1226 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1227 if (rdev->pm.default_mclk)
1228 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1229 }
1230 /* asic init will reset the default power state */
1231 mutex_lock(&rdev->pm.mutex);
1232 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1233 rdev->pm.current_clock_mode_index = 0;
1234 rdev->pm.current_sclk = rdev->pm.default_sclk;
1235 rdev->pm.current_mclk = rdev->pm.default_mclk;
1236 if (rdev->pm.power_state) {
1237 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
1238 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
1239 }
1240 if (rdev->pm.pm_method == PM_METHOD_DYNPM
1241 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
1242 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1243 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1244 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1245 }
1246 mutex_unlock(&rdev->pm.mutex);
1247 radeon_pm_compute_clocks(rdev);
1248 }
1249
radeon_pm_resume_dpm(struct radeon_device * rdev)1250 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
1251 {
1252 int ret;
1253
1254 /* asic init will reset to the boot state */
1255 mutex_lock(&rdev->pm.mutex);
1256 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1257 radeon_dpm_setup_asic(rdev);
1258 ret = radeon_dpm_enable(rdev);
1259 mutex_unlock(&rdev->pm.mutex);
1260 if (ret)
1261 goto dpm_resume_fail;
1262 rdev->pm.dpm_enabled = true;
1263 return;
1264
1265 dpm_resume_fail:
1266 DRM_ERROR("radeon: dpm resume failed\n");
1267 if ((rdev->family >= CHIP_BARTS) &&
1268 (rdev->family <= CHIP_CAYMAN) &&
1269 rdev->mc_fw) {
1270 if (rdev->pm.default_vddc)
1271 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1272 SET_VOLTAGE_TYPE_ASIC_VDDC);
1273 if (rdev->pm.default_vddci)
1274 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1275 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1276 if (rdev->pm.default_sclk)
1277 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1278 if (rdev->pm.default_mclk)
1279 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1280 }
1281 }
1282
radeon_pm_resume(struct radeon_device * rdev)1283 void radeon_pm_resume(struct radeon_device *rdev)
1284 {
1285 if (rdev->pm.pm_method == PM_METHOD_DPM)
1286 radeon_pm_resume_dpm(rdev);
1287 else
1288 radeon_pm_resume_old(rdev);
1289 }
1290
radeon_pm_init_old(struct radeon_device * rdev)1291 static int radeon_pm_init_old(struct radeon_device *rdev)
1292 {
1293 int ret;
1294
1295 rdev->pm.profile = PM_PROFILE_DEFAULT;
1296 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1297 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1298 rdev->pm.dynpm_can_upclock = true;
1299 rdev->pm.dynpm_can_downclock = true;
1300 rdev->pm.default_sclk = rdev->clock.default_sclk;
1301 rdev->pm.default_mclk = rdev->clock.default_mclk;
1302 rdev->pm.current_sclk = rdev->clock.default_sclk;
1303 rdev->pm.current_mclk = rdev->clock.default_mclk;
1304 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1305
1306 if (rdev->bios) {
1307 if (rdev->is_atom_bios)
1308 radeon_atombios_get_power_modes(rdev);
1309 else
1310 radeon_combios_get_power_modes(rdev);
1311 radeon_pm_print_states(rdev);
1312 radeon_pm_init_profile(rdev);
1313 /* set up the default clocks if the MC ucode is loaded */
1314 if ((rdev->family >= CHIP_BARTS) &&
1315 (rdev->family <= CHIP_CAYMAN) &&
1316 rdev->mc_fw) {
1317 if (rdev->pm.default_vddc)
1318 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1319 SET_VOLTAGE_TYPE_ASIC_VDDC);
1320 if (rdev->pm.default_vddci)
1321 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1322 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1323 if (rdev->pm.default_sclk)
1324 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1325 if (rdev->pm.default_mclk)
1326 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1327 }
1328 }
1329
1330 /* set up the internal thermal sensor if applicable */
1331 ret = radeon_hwmon_init(rdev);
1332 if (ret)
1333 return ret;
1334
1335 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
1336
1337 if (rdev->pm.num_power_states > 1) {
1338 if (radeon_debugfs_pm_init(rdev)) {
1339 DRM_ERROR("Failed to register debugfs file for PM!\n");
1340 }
1341
1342 DRM_INFO("radeon: power management initialized\n");
1343 }
1344
1345 return 0;
1346 }
1347
radeon_dpm_print_power_states(struct radeon_device * rdev)1348 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
1349 {
1350 int i;
1351
1352 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1353 printk("== power state %d ==\n", i);
1354 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
1355 }
1356 }
1357
radeon_pm_init_dpm(struct radeon_device * rdev)1358 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1359 {
1360 int ret;
1361
1362 /* default to balanced state */
1363 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
1364 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
1365 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1366 rdev->pm.default_sclk = rdev->clock.default_sclk;
1367 rdev->pm.default_mclk = rdev->clock.default_mclk;
1368 rdev->pm.current_sclk = rdev->clock.default_sclk;
1369 rdev->pm.current_mclk = rdev->clock.default_mclk;
1370 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1371
1372 if (rdev->bios && rdev->is_atom_bios)
1373 radeon_atombios_get_power_modes(rdev);
1374 else
1375 return -EINVAL;
1376
1377 /* set up the internal thermal sensor if applicable */
1378 ret = radeon_hwmon_init(rdev);
1379 if (ret)
1380 return ret;
1381
1382 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1383 mutex_lock(&rdev->pm.mutex);
1384 radeon_dpm_init(rdev);
1385 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1386 if (radeon_dpm == 1)
1387 radeon_dpm_print_power_states(rdev);
1388 radeon_dpm_setup_asic(rdev);
1389 ret = radeon_dpm_enable(rdev);
1390 mutex_unlock(&rdev->pm.mutex);
1391 if (ret)
1392 goto dpm_failed;
1393 rdev->pm.dpm_enabled = true;
1394
1395 if (radeon_debugfs_pm_init(rdev)) {
1396 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1397 }
1398
1399 DRM_INFO("radeon: dpm initialized\n");
1400
1401 return 0;
1402
1403 dpm_failed:
1404 rdev->pm.dpm_enabled = false;
1405 if ((rdev->family >= CHIP_BARTS) &&
1406 (rdev->family <= CHIP_CAYMAN) &&
1407 rdev->mc_fw) {
1408 if (rdev->pm.default_vddc)
1409 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1410 SET_VOLTAGE_TYPE_ASIC_VDDC);
1411 if (rdev->pm.default_vddci)
1412 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1413 SET_VOLTAGE_TYPE_ASIC_VDDCI);
1414 if (rdev->pm.default_sclk)
1415 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1416 if (rdev->pm.default_mclk)
1417 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1418 }
1419 DRM_ERROR("radeon: dpm initialization failed\n");
1420 return ret;
1421 }
1422
1423 struct radeon_dpm_quirk {
1424 u32 chip_vendor;
1425 u32 chip_device;
1426 u32 subsys_vendor;
1427 u32 subsys_device;
1428 };
1429
1430 /* cards with dpm stability problems */
1431 static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = {
1432 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1433 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 },
1434 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1435 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 },
1436 { 0, 0, 0, 0 },
1437 };
1438
radeon_pm_init(struct radeon_device * rdev)1439 int radeon_pm_init(struct radeon_device *rdev)
1440 {
1441 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list;
1442 bool disable_dpm = false;
1443
1444 /* Apply dpm quirks */
1445 while (p && p->chip_device != 0) {
1446 if (rdev->pdev->vendor == p->chip_vendor &&
1447 rdev->pdev->device == p->chip_device &&
1448 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
1449 rdev->pdev->subsystem_device == p->subsys_device) {
1450 disable_dpm = true;
1451 break;
1452 }
1453 ++p;
1454 }
1455
1456 /* enable dpm on rv6xx+ */
1457 switch (rdev->family) {
1458 case CHIP_RV610:
1459 case CHIP_RV630:
1460 case CHIP_RV620:
1461 case CHIP_RV635:
1462 case CHIP_RV670:
1463 case CHIP_RS780:
1464 case CHIP_RS880:
1465 case CHIP_RV770:
1466 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1467 if (!rdev->rlc_fw)
1468 rdev->pm.pm_method = PM_METHOD_PROFILE;
1469 else if ((rdev->family >= CHIP_RV770) &&
1470 (!(rdev->flags & RADEON_IS_IGP)) &&
1471 (!rdev->smc_fw))
1472 rdev->pm.pm_method = PM_METHOD_PROFILE;
1473 else if (radeon_dpm == 1)
1474 rdev->pm.pm_method = PM_METHOD_DPM;
1475 else
1476 rdev->pm.pm_method = PM_METHOD_PROFILE;
1477 break;
1478 case CHIP_RV730:
1479 case CHIP_RV710:
1480 case CHIP_RV740:
1481 case CHIP_CEDAR:
1482 case CHIP_REDWOOD:
1483 case CHIP_JUNIPER:
1484 case CHIP_CYPRESS:
1485 case CHIP_HEMLOCK:
1486 case CHIP_PALM:
1487 case CHIP_SUMO:
1488 case CHIP_SUMO2:
1489 case CHIP_BARTS:
1490 case CHIP_TURKS:
1491 case CHIP_CAICOS:
1492 case CHIP_CAYMAN:
1493 case CHIP_ARUBA:
1494 case CHIP_TAHITI:
1495 case CHIP_PITCAIRN:
1496 case CHIP_VERDE:
1497 case CHIP_OLAND:
1498 case CHIP_HAINAN:
1499 case CHIP_BONAIRE:
1500 case CHIP_KABINI:
1501 case CHIP_KAVERI:
1502 case CHIP_HAWAII:
1503 case CHIP_MULLINS:
1504 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1505 if (!rdev->rlc_fw)
1506 rdev->pm.pm_method = PM_METHOD_PROFILE;
1507 else if ((rdev->family >= CHIP_RV770) &&
1508 (!(rdev->flags & RADEON_IS_IGP)) &&
1509 (!rdev->smc_fw))
1510 rdev->pm.pm_method = PM_METHOD_PROFILE;
1511 else if (disable_dpm && (radeon_dpm == -1))
1512 rdev->pm.pm_method = PM_METHOD_PROFILE;
1513 else if (radeon_dpm == 0)
1514 rdev->pm.pm_method = PM_METHOD_PROFILE;
1515 else
1516 rdev->pm.pm_method = PM_METHOD_DPM;
1517 break;
1518 default:
1519 /* default to profile method */
1520 rdev->pm.pm_method = PM_METHOD_PROFILE;
1521 break;
1522 }
1523
1524 if (rdev->pm.pm_method == PM_METHOD_DPM)
1525 return radeon_pm_init_dpm(rdev);
1526 else
1527 return radeon_pm_init_old(rdev);
1528 }
1529
radeon_pm_late_init(struct radeon_device * rdev)1530 int radeon_pm_late_init(struct radeon_device *rdev)
1531 {
1532 int ret = 0;
1533
1534 if (rdev->pm.pm_method == PM_METHOD_DPM) {
1535 if (rdev->pm.dpm_enabled) {
1536 if (!rdev->pm.sysfs_initialized) {
1537 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1538 if (ret)
1539 DRM_ERROR("failed to create device file for dpm state\n");
1540 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1541 if (ret)
1542 DRM_ERROR("failed to create device file for dpm state\n");
1543 /* XXX: these are noops for dpm but are here for backwards compat */
1544 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1545 if (ret)
1546 DRM_ERROR("failed to create device file for power profile\n");
1547 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1548 if (ret)
1549 DRM_ERROR("failed to create device file for power method\n");
1550 if (!ret)
1551 rdev->pm.sysfs_initialized = true;
1552 }
1553
1554 mutex_lock(&rdev->pm.mutex);
1555 ret = radeon_dpm_late_enable(rdev);
1556 mutex_unlock(&rdev->pm.mutex);
1557 if (ret) {
1558 rdev->pm.dpm_enabled = false;
1559 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1560 } else {
1561 /* set the dpm state for PX since there won't be
1562 * a modeset to call this.
1563 */
1564 radeon_pm_compute_clocks(rdev);
1565 }
1566 }
1567 } else {
1568 if ((rdev->pm.num_power_states > 1) &&
1569 (!rdev->pm.sysfs_initialized)) {
1570 /* where's the best place to put these? */
1571 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1572 if (ret)
1573 DRM_ERROR("failed to create device file for power profile\n");
1574 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1575 if (ret)
1576 DRM_ERROR("failed to create device file for power method\n");
1577 if (!ret)
1578 rdev->pm.sysfs_initialized = true;
1579 }
1580 }
1581 return ret;
1582 }
1583
radeon_pm_fini_old(struct radeon_device * rdev)1584 static void radeon_pm_fini_old(struct radeon_device *rdev)
1585 {
1586 if (rdev->pm.num_power_states > 1) {
1587 mutex_lock(&rdev->pm.mutex);
1588 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1589 rdev->pm.profile = PM_PROFILE_DEFAULT;
1590 radeon_pm_update_profile(rdev);
1591 radeon_pm_set_clocks(rdev);
1592 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1593 /* reset default clocks */
1594 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1595 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1596 radeon_pm_set_clocks(rdev);
1597 }
1598 mutex_unlock(&rdev->pm.mutex);
1599
1600 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1601
1602 device_remove_file(rdev->dev, &dev_attr_power_profile);
1603 device_remove_file(rdev->dev, &dev_attr_power_method);
1604 }
1605
1606 radeon_hwmon_fini(rdev);
1607 kfree(rdev->pm.power_state);
1608 }
1609
radeon_pm_fini_dpm(struct radeon_device * rdev)1610 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1611 {
1612 if (rdev->pm.num_power_states > 1) {
1613 mutex_lock(&rdev->pm.mutex);
1614 radeon_dpm_disable(rdev);
1615 mutex_unlock(&rdev->pm.mutex);
1616
1617 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1618 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level);
1619 /* XXX backwards compat */
1620 device_remove_file(rdev->dev, &dev_attr_power_profile);
1621 device_remove_file(rdev->dev, &dev_attr_power_method);
1622 }
1623 radeon_dpm_fini(rdev);
1624
1625 radeon_hwmon_fini(rdev);
1626 kfree(rdev->pm.power_state);
1627 }
1628
radeon_pm_fini(struct radeon_device * rdev)1629 void radeon_pm_fini(struct radeon_device *rdev)
1630 {
1631 if (rdev->pm.pm_method == PM_METHOD_DPM)
1632 radeon_pm_fini_dpm(rdev);
1633 else
1634 radeon_pm_fini_old(rdev);
1635 }
1636
radeon_pm_compute_clocks_old(struct radeon_device * rdev)1637 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1638 {
1639 struct drm_device *ddev = rdev->ddev;
1640 struct drm_crtc *crtc;
1641 struct radeon_crtc *radeon_crtc;
1642
1643 if (rdev->pm.num_power_states < 2)
1644 return;
1645
1646 mutex_lock(&rdev->pm.mutex);
1647
1648 rdev->pm.active_crtcs = 0;
1649 rdev->pm.active_crtc_count = 0;
1650 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1651 list_for_each_entry(crtc,
1652 &ddev->mode_config.crtc_list, head) {
1653 radeon_crtc = to_radeon_crtc(crtc);
1654 if (radeon_crtc->enabled) {
1655 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1656 rdev->pm.active_crtc_count++;
1657 }
1658 }
1659 }
1660
1661 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1662 radeon_pm_update_profile(rdev);
1663 radeon_pm_set_clocks(rdev);
1664 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1665 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1666 if (rdev->pm.active_crtc_count > 1) {
1667 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1668 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1669
1670 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1671 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1672 radeon_pm_get_dynpm_state(rdev);
1673 radeon_pm_set_clocks(rdev);
1674
1675 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1676 }
1677 } else if (rdev->pm.active_crtc_count == 1) {
1678 /* TODO: Increase clocks if needed for current mode */
1679
1680 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1681 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1682 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1683 radeon_pm_get_dynpm_state(rdev);
1684 radeon_pm_set_clocks(rdev);
1685
1686 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1687 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1688 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1689 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1690 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1691 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1692 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1693 }
1694 } else { /* count == 0 */
1695 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1696 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1697
1698 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1699 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1700 radeon_pm_get_dynpm_state(rdev);
1701 radeon_pm_set_clocks(rdev);
1702 }
1703 }
1704 }
1705 }
1706
1707 mutex_unlock(&rdev->pm.mutex);
1708 }
1709
radeon_pm_compute_clocks_dpm(struct radeon_device * rdev)1710 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1711 {
1712 struct drm_device *ddev = rdev->ddev;
1713 struct drm_crtc *crtc;
1714 struct radeon_crtc *radeon_crtc;
1715
1716 if (!rdev->pm.dpm_enabled)
1717 return;
1718
1719 mutex_lock(&rdev->pm.mutex);
1720
1721 /* update active crtc counts */
1722 rdev->pm.dpm.new_active_crtcs = 0;
1723 rdev->pm.dpm.new_active_crtc_count = 0;
1724 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) {
1725 list_for_each_entry(crtc,
1726 &ddev->mode_config.crtc_list, head) {
1727 radeon_crtc = to_radeon_crtc(crtc);
1728 if (crtc->enabled) {
1729 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1730 rdev->pm.dpm.new_active_crtc_count++;
1731 }
1732 }
1733 }
1734
1735 /* update battery/ac status */
1736 if (power_supply_is_system_supplied() > 0)
1737 rdev->pm.dpm.ac_power = true;
1738 else
1739 rdev->pm.dpm.ac_power = false;
1740
1741 radeon_dpm_change_power_state_locked(rdev);
1742
1743 mutex_unlock(&rdev->pm.mutex);
1744
1745 }
1746
radeon_pm_compute_clocks(struct radeon_device * rdev)1747 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1748 {
1749 if (rdev->pm.pm_method == PM_METHOD_DPM)
1750 radeon_pm_compute_clocks_dpm(rdev);
1751 else
1752 radeon_pm_compute_clocks_old(rdev);
1753 }
1754
radeon_pm_in_vbl(struct radeon_device * rdev)1755 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1756 {
1757 int crtc, vpos, hpos, vbl_status;
1758 bool in_vbl = true;
1759
1760 /* Iterate over all active crtc's. All crtc's must be in vblank,
1761 * otherwise return in_vbl == false.
1762 */
1763 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1764 if (rdev->pm.active_crtcs & (1 << crtc)) {
1765 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, 0, &vpos, &hpos, NULL, NULL);
1766 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1767 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK))
1768 in_vbl = false;
1769 }
1770 }
1771
1772 return in_vbl;
1773 }
1774
radeon_pm_debug_check_in_vbl(struct radeon_device * rdev,bool finish)1775 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1776 {
1777 u32 stat_crtc = 0;
1778 bool in_vbl = radeon_pm_in_vbl(rdev);
1779
1780 if (in_vbl == false)
1781 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1782 finish ? "exit" : "entry");
1783 return in_vbl;
1784 }
1785
radeon_dynpm_idle_work_handler(struct work_struct * work)1786 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1787 {
1788 struct radeon_device *rdev;
1789 int resched;
1790 rdev = container_of(work, struct radeon_device,
1791 pm.dynpm_idle_work.work);
1792
1793 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1794 mutex_lock(&rdev->pm.mutex);
1795 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1796 int not_processed = 0;
1797 int i;
1798
1799 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1800 struct radeon_ring *ring = &rdev->ring[i];
1801
1802 if (ring->ready) {
1803 not_processed += radeon_fence_count_emitted(rdev, i);
1804 if (not_processed >= 3)
1805 break;
1806 }
1807 }
1808
1809 if (not_processed >= 3) { /* should upclock */
1810 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1811 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1812 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1813 rdev->pm.dynpm_can_upclock) {
1814 rdev->pm.dynpm_planned_action =
1815 DYNPM_ACTION_UPCLOCK;
1816 rdev->pm.dynpm_action_timeout = jiffies +
1817 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1818 }
1819 } else if (not_processed == 0) { /* should downclock */
1820 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1821 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1822 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1823 rdev->pm.dynpm_can_downclock) {
1824 rdev->pm.dynpm_planned_action =
1825 DYNPM_ACTION_DOWNCLOCK;
1826 rdev->pm.dynpm_action_timeout = jiffies +
1827 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1828 }
1829 }
1830
1831 /* Note, radeon_pm_set_clocks is called with static_switch set
1832 * to false since we want to wait for vbl to avoid flicker.
1833 */
1834 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1835 jiffies > rdev->pm.dynpm_action_timeout) {
1836 radeon_pm_get_dynpm_state(rdev);
1837 radeon_pm_set_clocks(rdev);
1838 }
1839
1840 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1841 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1842 }
1843 mutex_unlock(&rdev->pm.mutex);
1844 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1845 }
1846
1847 /*
1848 * Debugfs info
1849 */
1850 #if defined(CONFIG_DEBUG_FS)
1851
radeon_debugfs_pm_info(struct seq_file * m,void * data)1852 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1853 {
1854 struct drm_info_node *node = (struct drm_info_node *) m->private;
1855 struct drm_device *dev = node->minor->dev;
1856 struct radeon_device *rdev = dev->dev_private;
1857 struct drm_device *ddev = rdev->ddev;
1858
1859 if ((rdev->flags & RADEON_IS_PX) &&
1860 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1861 seq_printf(m, "PX asic powered off\n");
1862 } else if (rdev->pm.dpm_enabled) {
1863 mutex_lock(&rdev->pm.mutex);
1864 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1865 radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1866 else
1867 seq_printf(m, "Debugfs support not implemented for this asic\n");
1868 mutex_unlock(&rdev->pm.mutex);
1869 } else {
1870 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1871 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1872 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1873 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1874 else
1875 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1876 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1877 if (rdev->asic->pm.get_memory_clock)
1878 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1879 if (rdev->pm.current_vddc)
1880 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1881 if (rdev->asic->pm.get_pcie_lanes)
1882 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1883 }
1884
1885 return 0;
1886 }
1887
1888 static struct drm_info_list radeon_pm_info_list[] = {
1889 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1890 };
1891 #endif
1892
radeon_debugfs_pm_init(struct radeon_device * rdev)1893 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1894 {
1895 #if defined(CONFIG_DEBUG_FS)
1896 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1897 #else
1898 return 0;
1899 #endif
1900 }
1901