1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv04.h"
25
26#include <core/device.h>
27#include <core/gpuobj.h>
28#include <core/option.h>
29#include <subdev/timer.h>
30
31#define NV44_GART_SIZE (512 * 1024 * 1024)
32#define NV44_GART_PAGE (  4 * 1024)
33
34/*******************************************************************************
35 * VM map/unmap callbacks
36 ******************************************************************************/
37
38static void
39nv44_vm_fill(struct nvkm_gpuobj *pgt, dma_addr_t null,
40	     dma_addr_t *list, u32 pte, u32 cnt)
41{
42	u32 base = (pte << 2) & ~0x0000000f;
43	u32 tmp[4];
44
45	tmp[0] = nv_ro32(pgt, base + 0x0);
46	tmp[1] = nv_ro32(pgt, base + 0x4);
47	tmp[2] = nv_ro32(pgt, base + 0x8);
48	tmp[3] = nv_ro32(pgt, base + 0xc);
49
50	while (cnt--) {
51		u32 addr = list ? (*list++ >> 12) : (null >> 12);
52		switch (pte++ & 0x3) {
53		case 0:
54			tmp[0] &= ~0x07ffffff;
55			tmp[0] |= addr;
56			break;
57		case 1:
58			tmp[0] &= ~0xf8000000;
59			tmp[0] |= addr << 27;
60			tmp[1] &= ~0x003fffff;
61			tmp[1] |= addr >> 5;
62			break;
63		case 2:
64			tmp[1] &= ~0xffc00000;
65			tmp[1] |= addr << 22;
66			tmp[2] &= ~0x0001ffff;
67			tmp[2] |= addr >> 10;
68			break;
69		case 3:
70			tmp[2] &= ~0xfffe0000;
71			tmp[2] |= addr << 17;
72			tmp[3] &= ~0x00000fff;
73			tmp[3] |= addr >> 15;
74			break;
75		}
76	}
77
78	nv_wo32(pgt, base + 0x0, tmp[0]);
79	nv_wo32(pgt, base + 0x4, tmp[1]);
80	nv_wo32(pgt, base + 0x8, tmp[2]);
81	nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000);
82}
83
84static void
85nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
86	       struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
87{
88	struct nv04_mmu_priv *priv = (void *)vma->vm->mmu;
89	u32 tmp[4];
90	int i;
91
92	if (pte & 3) {
93		u32  max = 4 - (pte & 3);
94		u32 part = (cnt > max) ? max : cnt;
95		nv44_vm_fill(pgt, priv->null, list, pte, part);
96		pte  += part;
97		list += part;
98		cnt  -= part;
99	}
100
101	while (cnt >= 4) {
102		for (i = 0; i < 4; i++)
103			tmp[i] = *list++ >> 12;
104		nv_wo32(pgt, pte++ * 4, tmp[0] >>  0 | tmp[1] << 27);
105		nv_wo32(pgt, pte++ * 4, tmp[1] >>  5 | tmp[2] << 22);
106		nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17);
107		nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000);
108		cnt -= 4;
109	}
110
111	if (cnt)
112		nv44_vm_fill(pgt, priv->null, list, pte, cnt);
113}
114
115static void
116nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
117{
118	struct nv04_mmu_priv *priv = (void *)nvkm_mmu(pgt);
119
120	if (pte & 3) {
121		u32  max = 4 - (pte & 3);
122		u32 part = (cnt > max) ? max : cnt;
123		nv44_vm_fill(pgt, priv->null, NULL, pte, part);
124		pte  += part;
125		cnt  -= part;
126	}
127
128	while (cnt >= 4) {
129		nv_wo32(pgt, pte++ * 4, 0x00000000);
130		nv_wo32(pgt, pte++ * 4, 0x00000000);
131		nv_wo32(pgt, pte++ * 4, 0x00000000);
132		nv_wo32(pgt, pte++ * 4, 0x00000000);
133		cnt -= 4;
134	}
135
136	if (cnt)
137		nv44_vm_fill(pgt, priv->null, NULL, pte, cnt);
138}
139
140static void
141nv44_vm_flush(struct nvkm_vm *vm)
142{
143	struct nv04_mmu_priv *priv = (void *)vm->mmu;
144	nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE);
145	nv_wr32(priv, 0x100808, 0x00000020);
146	if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001))
147		nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808));
148	nv_wr32(priv, 0x100808, 0x00000000);
149}
150
151/*******************************************************************************
152 * MMU subdev
153 ******************************************************************************/
154
155static int
156nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
157	      struct nvkm_oclass *oclass, void *data, u32 size,
158	      struct nvkm_object **pobject)
159{
160	struct nvkm_device *device = nv_device(parent);
161	struct nv04_mmu_priv *priv;
162	int ret;
163
164	if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
165	    !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
166		return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
167					data, size, pobject);
168	}
169
170	ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
171			      "pciegart", &priv);
172	*pobject = nv_object(priv);
173	if (ret)
174		return ret;
175
176	priv->base.create = nv04_vm_create;
177	priv->base.limit = NV44_GART_SIZE;
178	priv->base.dma_bits = 39;
179	priv->base.pgt_bits = 32 - 12;
180	priv->base.spg_shift = 12;
181	priv->base.lpg_shift = 12;
182	priv->base.map_sg = nv44_vm_map_sg;
183	priv->base.unmap = nv44_vm_unmap;
184	priv->base.flush = nv44_vm_flush;
185
186	priv->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &priv->null);
187	if (!priv->nullp) {
188		nv_error(priv, "unable to allocate dummy pages\n");
189		return -ENOMEM;
190	}
191
192	ret = nvkm_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096,
193			     &priv->vm);
194	if (ret)
195		return ret;
196
197	ret = nvkm_gpuobj_new(nv_object(priv), NULL,
198			      (NV44_GART_SIZE / NV44_GART_PAGE) * 4,
199			      512 * 1024, NVOBJ_FLAG_ZERO_ALLOC,
200			      &priv->vm->pgt[0].obj[0]);
201	priv->vm->pgt[0].refcount[0] = 1;
202	if (ret)
203		return ret;
204
205	return 0;
206}
207
208static int
209nv44_mmu_init(struct nvkm_object *object)
210{
211	struct nv04_mmu_priv *priv = (void *)object;
212	struct nvkm_gpuobj *gart = priv->vm->pgt[0].obj[0];
213	u32 addr;
214	int ret;
215
216	ret = nvkm_mmu_init(&priv->base);
217	if (ret)
218		return ret;
219
220	/* calculate vram address of this PRAMIN block, object must be
221	 * allocated on 512KiB alignment, and not exceed a total size
222	 * of 512KiB for this to work correctly
223	 */
224	addr  = nv_rd32(priv, 0x10020c);
225	addr -= ((gart->addr >> 19) + 1) << 19;
226
227	nv_wr32(priv, 0x100850, 0x80000000);
228	nv_wr32(priv, 0x100818, priv->null);
229	nv_wr32(priv, 0x100804, NV44_GART_SIZE);
230	nv_wr32(priv, 0x100850, 0x00008000);
231	nv_mask(priv, 0x10008c, 0x00000200, 0x00000200);
232	nv_wr32(priv, 0x100820, 0x00000000);
233	nv_wr32(priv, 0x10082c, 0x00000001);
234	nv_wr32(priv, 0x100800, addr | 0x00000010);
235	return 0;
236}
237
238struct nvkm_oclass
239nv44_mmu_oclass = {
240	.handle = NV_SUBDEV(MMU, 0x44),
241	.ofuncs = &(struct nvkm_ofuncs) {
242		.ctor = nv44_mmu_ctor,
243		.dtor = nv04_mmu_dtor,
244		.init = nv44_mmu_init,
245		.fini = _nvkm_mmu_fini,
246	},
247};
248