1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv50.h"
25
26#include <subdev/bios.h>
27#include <subdev/bios/dcb.h>
28#include <subdev/bios/disp.h>
29#include <subdev/bios/init.h>
30#include <subdev/bios/pll.h>
31#include <subdev/clk/pll.h>
32#include <subdev/ibus.h>
33#include <subdev/vga.h>
34
35int
36nv50_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
37{
38	struct nv50_devinit_priv *priv = (void *)devinit;
39	struct nvkm_bios *bios = nvkm_bios(priv);
40	struct nvbios_pll info;
41	int N1, M1, N2, M2, P;
42	int ret;
43
44	ret = nvbios_pll_parse(bios, type, &info);
45	if (ret) {
46		nv_error(devinit, "failed to retrieve pll data, %d\n", ret);
47		return ret;
48	}
49
50	ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P);
51	if (!ret) {
52		nv_error(devinit, "failed pll calculation\n");
53		return ret;
54	}
55
56	switch (info.type) {
57	case PLL_VPLL0:
58	case PLL_VPLL1:
59		nv_wr32(priv, info.reg + 0, 0x10000611);
60		nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1);
61		nv_mask(priv, info.reg + 8, 0x7fff00ff, (P  << 28) |
62							(M2 << 16) | N2);
63		break;
64	case PLL_MEMORY:
65		nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) |
66						        (info.bias_p << 19) |
67							(P << 16));
68		nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
69		break;
70	default:
71		nv_mask(priv, info.reg + 0, 0x00070000, (P << 16));
72		nv_wr32(priv, info.reg + 4, (N1 << 8) | M1);
73		break;
74	}
75
76	return 0;
77}
78
79static u64
80nv50_devinit_disable(struct nvkm_devinit *devinit)
81{
82	struct nv50_devinit_priv *priv = (void *)devinit;
83	u32 r001540 = nv_rd32(priv, 0x001540);
84	u64 disable = 0ULL;
85
86	if (!(r001540 & 0x40000000))
87		disable |= (1ULL << NVDEV_ENGINE_MPEG);
88
89	return disable;
90}
91
92int
93nv50_devinit_init(struct nvkm_object *object)
94{
95	struct nvkm_bios *bios = nvkm_bios(object);
96	struct nvkm_ibus *ibus = nvkm_ibus(object);
97	struct nv50_devinit_priv *priv = (void *)object;
98	struct nvbios_outp info;
99	struct dcb_output outp;
100	u8  ver = 0xff, hdr, cnt, len;
101	int ret, i = 0;
102
103	if (!priv->base.post) {
104		if (!nv_rdvgac(priv, 0, 0x00) &&
105		    !nv_rdvgac(priv, 0, 0x1a)) {
106			nv_info(priv, "adaptor not initialised\n");
107			priv->base.post = true;
108		}
109	}
110
111	/* some boards appear to require certain priv register timeouts
112	 * to be bumped before runing devinit scripts.  not a clue why
113	 * the vbios engineers didn't make the scripts just work...
114	 */
115	if (priv->base.post && ibus)
116		nv_ofuncs(ibus)->init(nv_object(ibus));
117
118	ret = nvkm_devinit_init(&priv->base);
119	if (ret)
120		return ret;
121
122	/* if we ran the init tables, we have to execute the first script
123	 * pointer of each dcb entry's display encoder table in order
124	 * to properly initialise each encoder.
125	 */
126	while (priv->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) {
127		if (nvbios_outp_match(bios, outp.hasht, outp.hashm,
128				      &ver, &hdr, &cnt, &len, &info)) {
129			struct nvbios_init init = {
130				.subdev = nv_subdev(priv),
131				.bios = bios,
132				.offset = info.script[0],
133				.outp = &outp,
134				.crtc = -1,
135				.execute = 1,
136			};
137
138			nvbios_exec(&init);
139		}
140		i++;
141	}
142
143	return 0;
144}
145
146int
147nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
148		  struct nvkm_oclass *oclass, void *data, u32 size,
149		  struct nvkm_object **pobject)
150{
151	struct nv50_devinit_priv *priv;
152	int ret;
153
154	ret = nvkm_devinit_create(parent, engine, oclass, &priv);
155	*pobject = nv_object(priv);
156	if (ret)
157		return ret;
158
159	return 0;
160}
161
162struct nvkm_oclass *
163nv50_devinit_oclass = &(struct nvkm_devinit_impl) {
164	.base.handle = NV_SUBDEV(DEVINIT, 0x50),
165	.base.ofuncs = &(struct nvkm_ofuncs) {
166		.ctor = nv50_devinit_ctor,
167		.dtor = _nvkm_devinit_dtor,
168		.init = nv50_devinit_init,
169		.fini = _nvkm_devinit_fini,
170	},
171	.pll_set = nv50_devinit_pll_set,
172	.disable = nv50_devinit_disable,
173	.post = nvbios_init,
174}.base;
175