1/* 2 * Copyright 2013 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24#include "nv50.h" 25 26#include <subdev/bios.h> 27#include <subdev/bios/bit.h> 28#include <subdev/bios/pmu.h> 29 30static void 31pmu_code(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len, bool sec) 32{ 33 struct nvkm_bios *bios = nvkm_bios(priv); 34 int i; 35 36 nv_wr32(priv, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu); 37 for (i = 0; i < len; i += 4) { 38 if ((i & 0xff) == 0) 39 nv_wr32(priv, 0x10a188, (pmu + i) >> 8); 40 nv_wr32(priv, 0x10a184, nv_ro32(bios, img + i)); 41 } 42 43 while (i & 0xff) { 44 nv_wr32(priv, 0x10a184, 0x00000000); 45 i += 4; 46 } 47} 48 49static void 50pmu_data(struct nv50_devinit_priv *priv, u32 pmu, u32 img, u32 len) 51{ 52 struct nvkm_bios *bios = nvkm_bios(priv); 53 int i; 54 55 nv_wr32(priv, 0x10a1c0, 0x01000000 | pmu); 56 for (i = 0; i < len; i += 4) 57 nv_wr32(priv, 0x10a1c4, nv_ro32(bios, img + i)); 58} 59 60static u32 61pmu_args(struct nv50_devinit_priv *priv, u32 argp, u32 argi) 62{ 63 nv_wr32(priv, 0x10a1c0, argp); 64 nv_wr32(priv, 0x10a1c0, nv_rd32(priv, 0x10a1c4) + argi); 65 return nv_rd32(priv, 0x10a1c4); 66} 67 68static void 69pmu_exec(struct nv50_devinit_priv *priv, u32 init_addr) 70{ 71 nv_wr32(priv, 0x10a104, init_addr); 72 nv_wr32(priv, 0x10a10c, 0x00000000); 73 nv_wr32(priv, 0x10a100, 0x00000002); 74} 75 76static int 77pmu_load(struct nv50_devinit_priv *priv, u8 type, bool post, 78 u32 *init_addr_pmu, u32 *args_addr_pmu) 79{ 80 struct nvkm_bios *bios = nvkm_bios(priv); 81 struct nvbios_pmuR pmu; 82 83 if (!nvbios_pmuRm(bios, type, &pmu)) { 84 nv_error(priv, "VBIOS PMU fuc %02x not found\n", type); 85 return -EINVAL; 86 } 87 88 if (!post) 89 return 0; 90 91 pmu_code(priv, pmu.boot_addr_pmu, pmu.boot_addr, pmu.boot_size, false); 92 pmu_code(priv, pmu.code_addr_pmu, pmu.code_addr, pmu.code_size, true); 93 pmu_data(priv, pmu.data_addr_pmu, pmu.data_addr, pmu.data_size); 94 95 if (init_addr_pmu) { 96 *init_addr_pmu = pmu.init_addr_pmu; 97 *args_addr_pmu = pmu.args_addr_pmu; 98 return 0; 99 } 100 101 return pmu_exec(priv, pmu.init_addr_pmu), 0; 102} 103 104static int 105gm204_devinit_post(struct nvkm_subdev *subdev, bool post) 106{ 107 struct nv50_devinit_priv *priv = (void *)nvkm_devinit(subdev); 108 struct nvkm_bios *bios = nvkm_bios(priv); 109 struct bit_entry bit_I; 110 u32 init, args; 111 int ret; 112 113 if (bit_entry(bios, 'I', &bit_I) || bit_I.version != 1 || 114 bit_I.length < 0x1c) { 115 nv_error(priv, "VBIOS PMU init data not found\n"); 116 return -EINVAL; 117 } 118 119 /* reset PMU and load init table parser ucode */ 120 if (post) { 121 nv_mask(priv, 0x000200, 0x00002000, 0x00000000); 122 nv_mask(priv, 0x000200, 0x00002000, 0x00002000); 123 nv_rd32(priv, 0x000200); 124 while (nv_rd32(priv, 0x10a10c) & 0x00000006) { 125 } 126 } 127 128 ret = pmu_load(priv, 0x04, post, &init, &args); 129 if (ret) 130 return ret; 131 132 /* upload first chunk of init data */ 133 if (post) { 134 u32 pmu = pmu_args(priv, args + 0x08, 0x08); 135 u32 img = nv_ro16(bios, bit_I.offset + 0x14); 136 u32 len = nv_ro16(bios, bit_I.offset + 0x16); 137 pmu_data(priv, pmu, img, len); 138 } 139 140 /* upload second chunk of init data */ 141 if (post) { 142 u32 pmu = pmu_args(priv, args + 0x08, 0x10); 143 u32 img = nv_ro16(bios, bit_I.offset + 0x18); 144 u32 len = nv_ro16(bios, bit_I.offset + 0x1a); 145 pmu_data(priv, pmu, img, len); 146 } 147 148 /* execute init tables */ 149 if (post) { 150 nv_wr32(priv, 0x10a040, 0x00005000); 151 pmu_exec(priv, init); 152 while (!(nv_rd32(priv, 0x10a040) & 0x00002000)) { 153 } 154 } 155 156 /* load and execute some other ucode image (bios therm?) */ 157 return pmu_load(priv, 0x01, post, NULL, NULL); 158} 159 160struct nvkm_oclass * 161gm204_devinit_oclass = &(struct nvkm_devinit_impl) { 162 .base.handle = NV_SUBDEV(DEVINIT, 0x07), 163 .base.ofuncs = &(struct nvkm_ofuncs) { 164 .ctor = gf100_devinit_ctor, 165 .dtor = _nvkm_devinit_dtor, 166 .init = nv50_devinit_init, 167 .fini = _nvkm_devinit_fini, 168 }, 169 .pll_set = gf100_devinit_pll_set, 170 .disable = gm107_devinit_disable, 171 .post = gm204_devinit_post, 172}.base; 173