1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv50.h"
25#include "outpdp.h"
26
27#include <subdev/timer.h>
28
29static inline u32
30gm204_sor_soff(struct nvkm_output_dp *outp)
31{
32	return (ffs(outp->base.info.or) - 1) * 0x800;
33}
34
35static inline u32
36gm204_sor_loff(struct nvkm_output_dp *outp)
37{
38	return gm204_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
39}
40
41void
42gm204_sor_magic(struct nvkm_output *outp)
43{
44	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
45	const u32 soff = outp->or * 0x100;
46	const u32 data = outp->or + 1;
47	if (outp->info.sorconf.link & 1)
48		nv_mask(priv, 0x612308 + soff, 0x0000001f, 0x00000000 | data);
49	if (outp->info.sorconf.link & 2)
50		nv_mask(priv, 0x612388 + soff, 0x0000001f, 0x00000010 | data);
51}
52
53static inline u32
54gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
55{
56	return lane * 0x08;
57}
58
59static int
60gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
61{
62	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
63	const u32 soff = gm204_sor_soff(outp);
64	const u32 data = 0x01010101 * pattern;
65	if (outp->base.info.sorconf.link & 1)
66		nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data);
67	else
68		nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data);
69	return 0;
70}
71
72static int
73gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
74{
75	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
76	const u32 soff = gm204_sor_soff(outp);
77	const u32 loff = gm204_sor_loff(outp);
78	u32 mask = 0, i;
79
80	for (i = 0; i < nr; i++)
81		mask |= 1 << (gm204_sor_dp_lane_map(priv, i) >> 3);
82
83	nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
84	nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
85	nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000);
86	return 0;
87}
88
89static int
90gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
91		     int ln, int vs, int pe, int pc)
92{
93	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
94	struct nvkm_bios *bios = nvkm_bios(priv);
95	const u32 shift = gm204_sor_dp_lane_map(priv, ln);
96	const u32 loff = gm204_sor_loff(outp);
97	u32 addr, data[4];
98	u8  ver, hdr, cnt, len;
99	struct nvbios_dpout info;
100	struct nvbios_dpcfg ocfg;
101
102	addr = nvbios_dpout_match(bios, outp->base.info.hasht,
103					outp->base.info.hashm,
104				  &ver, &hdr, &cnt, &len, &info);
105	if (!addr)
106		return -ENODEV;
107
108	addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
109				  &ver, &hdr, &cnt, &len, &ocfg);
110	if (!addr)
111		return -EINVAL;
112
113	data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
114	data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
115	data[2] = nv_rd32(priv, 0x61c130 + loff);
116	if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
117		data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
118	nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
119	nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
120	nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
121	data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
122	nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
123	return 0;
124}
125
126struct nvkm_output_dp_impl
127gm204_sor_dp_impl = {
128	.base.base.handle = DCB_OUTPUT_DP,
129	.base.base.ofuncs = &(struct nvkm_ofuncs) {
130		.ctor = _nvkm_output_dp_ctor,
131		.dtor = _nvkm_output_dp_dtor,
132		.init = _nvkm_output_dp_init,
133		.fini = _nvkm_output_dp_fini,
134	},
135	.pattern = gm204_sor_dp_pattern,
136	.lnk_pwr = gm204_sor_dp_lnk_pwr,
137	.lnk_ctl = gf110_sor_dp_lnk_ctl,
138	.drv_ctl = gm204_sor_dp_drv_ctl,
139};
140