1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "priv.h"
25
26#include <subdev/bios.h>
27#include <subdev/bus.h>
28#include <subdev/gpio.h>
29#include <subdev/i2c.h>
30#include <subdev/clk.h>
31#include <subdev/therm.h>
32#include <subdev/devinit.h>
33#include <subdev/mc.h>
34#include <subdev/timer.h>
35#include <subdev/fb.h>
36#include <subdev/instmem.h>
37#include <subdev/mmu.h>
38
39#include <engine/dmaobj.h>
40#include <engine/fifo.h>
41#include <engine/sw.h>
42#include <engine/gr.h>
43#include <engine/disp.h>
44
45int
46nv20_identify(struct nvkm_device *device)
47{
48	switch (device->chipset) {
49	case 0x20:
50		device->cname = "NV20";
51		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
52		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
53		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
54		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
55		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
56		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
57		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
58		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
59		device->oclass[NVDEV_SUBDEV_FB     ] =  nv20_fb_oclass;
60		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
61		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
62		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
63		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
64		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
65		device->oclass[NVDEV_ENGINE_GR     ] = &nv20_gr_oclass;
66		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
67		break;
68	case 0x25:
69		device->cname = "NV25";
70		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
71		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
72		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
73		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
74		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
75		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
76		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
77		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
78		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
79		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
80		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
81		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
82		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
83		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
84		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
85		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
86		break;
87	case 0x28:
88		device->cname = "NV28";
89		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
90		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
91		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
92		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
93		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
94		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
95		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
96		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
97		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
98		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
99		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
100		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
101		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
102		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
103		device->oclass[NVDEV_ENGINE_GR     ] = &nv25_gr_oclass;
104		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
105		break;
106	case 0x2a:
107		device->cname = "NV2A";
108		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;
109		device->oclass[NVDEV_SUBDEV_GPIO   ] =  nv10_gpio_oclass;
110		device->oclass[NVDEV_SUBDEV_I2C    ] =  nv04_i2c_oclass;
111		device->oclass[NVDEV_SUBDEV_CLK    ] = &nv04_clk_oclass;
112		device->oclass[NVDEV_SUBDEV_DEVINIT] =  nv20_devinit_oclass;
113		device->oclass[NVDEV_SUBDEV_MC     ] =  nv04_mc_oclass;
114		device->oclass[NVDEV_SUBDEV_BUS    ] =  nv04_bus_oclass;
115		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
116		device->oclass[NVDEV_SUBDEV_FB     ] =  nv25_fb_oclass;
117		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv04_instmem_oclass;
118		device->oclass[NVDEV_SUBDEV_MMU    ] = &nv04_mmu_oclass;
119		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
120		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
121		device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
122		device->oclass[NVDEV_ENGINE_GR     ] = &nv2a_gr_oclass;
123		device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
124		break;
125	default:
126		nv_fatal(device, "unknown Kelvin chipset\n");
127		return -EINVAL;
128	}
129
130	return 0;
131}
132