1/* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18#ifndef __MSM_DRV_H__ 19#define __MSM_DRV_H__ 20 21#include <linux/kernel.h> 22#include <linux/clk.h> 23#include <linux/cpufreq.h> 24#include <linux/module.h> 25#include <linux/component.h> 26#include <linux/platform_device.h> 27#include <linux/pm.h> 28#include <linux/pm_runtime.h> 29#include <linux/slab.h> 30#include <linux/list.h> 31#include <linux/iommu.h> 32#include <linux/types.h> 33#include <asm/sizes.h> 34 35#ifndef CONFIG_OF 36#include <mach/board.h> 37#include <mach/socinfo.h> 38#include <mach/iommu_domains.h> 39#endif 40 41#include <drm/drmP.h> 42#include <drm/drm_atomic.h> 43#include <drm/drm_atomic_helper.h> 44#include <drm/drm_crtc_helper.h> 45#include <drm/drm_plane_helper.h> 46#include <drm/drm_fb_helper.h> 47#include <drm/msm_drm.h> 48#include <drm/drm_gem.h> 49 50struct msm_kms; 51struct msm_gpu; 52struct msm_mmu; 53struct msm_rd_state; 54struct msm_perf_state; 55struct msm_gem_submit; 56 57#define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ 58 59struct msm_file_private { 60 /* currently we don't do anything useful with this.. but when 61 * per-context address spaces are supported we'd keep track of 62 * the context's page-tables here. 63 */ 64 int dummy; 65}; 66 67struct msm_drm_private { 68 69 struct msm_kms *kms; 70 71 /* subordinate devices, if present: */ 72 struct platform_device *gpu_pdev; 73 74 /* possibly this should be in the kms component, but it is 75 * shared by both mdp4 and mdp5.. 76 */ 77 struct hdmi *hdmi; 78 79 /* eDP is for mdp5 only, but kms has not been created 80 * when edp_bind() and edp_init() are called. Here is the only 81 * place to keep the edp instance. 82 */ 83 struct msm_edp *edp; 84 85 /* DSI is shared by mdp4 and mdp5 */ 86 struct msm_dsi *dsi[2]; 87 88 /* when we have more than one 'msm_gpu' these need to be an array: */ 89 struct msm_gpu *gpu; 90 struct msm_file_private *lastctx; 91 92 struct drm_fb_helper *fbdev; 93 94 uint32_t next_fence, completed_fence; 95 wait_queue_head_t fence_event; 96 97 struct msm_rd_state *rd; 98 struct msm_perf_state *perf; 99 100 /* list of GEM objects: */ 101 struct list_head inactive_list; 102 103 struct workqueue_struct *wq; 104 105 /* callbacks deferred until bo is inactive: */ 106 struct list_head fence_cbs; 107 108 /* crtcs pending async atomic updates: */ 109 uint32_t pending_crtcs; 110 wait_queue_head_t pending_crtcs_event; 111 112 /* registered MMUs: */ 113 unsigned int num_mmus; 114 struct msm_mmu *mmus[NUM_DOMAINS]; 115 116 unsigned int num_planes; 117 struct drm_plane *planes[8]; 118 119 unsigned int num_crtcs; 120 struct drm_crtc *crtcs[8]; 121 122 unsigned int num_encoders; 123 struct drm_encoder *encoders[8]; 124 125 unsigned int num_bridges; 126 struct drm_bridge *bridges[8]; 127 128 unsigned int num_connectors; 129 struct drm_connector *connectors[8]; 130 131 /* VRAM carveout, used when no IOMMU: */ 132 struct { 133 unsigned long size; 134 dma_addr_t paddr; 135 /* NOTE: mm managed at the page level, size is in # of pages 136 * and position mm_node->start is in # of pages: 137 */ 138 struct drm_mm mm; 139 } vram; 140}; 141 142struct msm_format { 143 uint32_t pixel_format; 144}; 145 146/* callback from wq once fence has passed: */ 147struct msm_fence_cb { 148 struct work_struct work; 149 uint32_t fence; 150 void (*func)(struct msm_fence_cb *cb); 151}; 152 153void __msm_fence_worker(struct work_struct *work); 154 155#define INIT_FENCE_CB(_cb, _func) do { \ 156 INIT_WORK(&(_cb)->work, __msm_fence_worker); \ 157 (_cb)->func = _func; \ 158 } while (0) 159 160int msm_atomic_check(struct drm_device *dev, 161 struct drm_atomic_state *state); 162int msm_atomic_commit(struct drm_device *dev, 163 struct drm_atomic_state *state, bool async); 164 165int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 166 167int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence, 168 struct timespec *timeout); 169int msm_queue_fence_cb(struct drm_device *dev, 170 struct msm_fence_cb *cb, uint32_t fence); 171void msm_update_fence(struct drm_device *dev, uint32_t fence); 172 173int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 174 struct drm_file *file); 175 176int msm_gem_mmap_obj(struct drm_gem_object *obj, 177 struct vm_area_struct *vma); 178int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 179int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 180uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 181int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, 182 uint32_t *iova); 183int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); 184uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); 185struct page **msm_gem_get_pages(struct drm_gem_object *obj); 186void msm_gem_put_pages(struct drm_gem_object *obj); 187void msm_gem_put_iova(struct drm_gem_object *obj, int id); 188int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 189 struct drm_mode_create_dumb *args); 190int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 191 uint32_t handle, uint64_t *offset); 192struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 193void *msm_gem_prime_vmap(struct drm_gem_object *obj); 194void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 195int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 196struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 197 struct dma_buf_attachment *attach, struct sg_table *sg); 198int msm_gem_prime_pin(struct drm_gem_object *obj); 199void msm_gem_prime_unpin(struct drm_gem_object *obj); 200void *msm_gem_vaddr_locked(struct drm_gem_object *obj); 201void *msm_gem_vaddr(struct drm_gem_object *obj); 202int msm_gem_queue_inactive_cb(struct drm_gem_object *obj, 203 struct msm_fence_cb *cb); 204void msm_gem_move_to_active(struct drm_gem_object *obj, 205 struct msm_gpu *gpu, bool write, uint32_t fence); 206void msm_gem_move_to_inactive(struct drm_gem_object *obj); 207int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, 208 struct timespec *timeout); 209int msm_gem_cpu_fini(struct drm_gem_object *obj); 210void msm_gem_free_object(struct drm_gem_object *obj); 211int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 212 uint32_t size, uint32_t flags, uint32_t *handle); 213struct drm_gem_object *msm_gem_new(struct drm_device *dev, 214 uint32_t size, uint32_t flags); 215struct drm_gem_object *msm_gem_import(struct drm_device *dev, 216 uint32_t size, struct sg_table *sgt); 217 218int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); 219void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); 220uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); 221struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 222const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 223struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, 224 struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 225struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 226 struct drm_file *file, struct drm_mode_fb_cmd2 *mode_cmd); 227 228struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 229 230struct hdmi; 231int hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 232 struct drm_encoder *encoder); 233void __init hdmi_register(void); 234void __exit hdmi_unregister(void); 235 236struct msm_edp; 237void __init msm_edp_register(void); 238void __exit msm_edp_unregister(void); 239int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 240 struct drm_encoder *encoder); 241 242struct msm_dsi; 243enum msm_dsi_encoder_id { 244 MSM_DSI_VIDEO_ENCODER_ID = 0, 245 MSM_DSI_CMD_ENCODER_ID = 1, 246 MSM_DSI_ENCODER_NUM = 2 247}; 248#ifdef CONFIG_DRM_MSM_DSI 249void __init msm_dsi_register(void); 250void __exit msm_dsi_unregister(void); 251int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 252 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]); 253#else 254static inline void __init msm_dsi_register(void) 255{ 256} 257static inline void __exit msm_dsi_unregister(void) 258{ 259} 260static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 261 struct drm_device *dev, 262 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]) 263{ 264 return -EINVAL; 265} 266#endif 267 268#ifdef CONFIG_DEBUG_FS 269void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 270void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 271void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 272int msm_debugfs_late_init(struct drm_device *dev); 273int msm_rd_debugfs_init(struct drm_minor *minor); 274void msm_rd_debugfs_cleanup(struct drm_minor *minor); 275void msm_rd_dump_submit(struct msm_gem_submit *submit); 276int msm_perf_debugfs_init(struct drm_minor *minor); 277void msm_perf_debugfs_cleanup(struct drm_minor *minor); 278#else 279static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 280static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} 281#endif 282 283void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 284 const char *dbgname); 285void msm_writel(u32 data, void __iomem *addr); 286u32 msm_readl(const void __iomem *addr); 287 288#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 289#define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 290 291static inline bool fence_completed(struct drm_device *dev, uint32_t fence) 292{ 293 struct msm_drm_private *priv = dev->dev_private; 294 return priv->completed_fence >= fence; 295} 296 297static inline int align_pitch(int width, int bpp) 298{ 299 int bytespp = (bpp + 7) / 8; 300 /* adreno needs pitch aligned to 32 pixels: */ 301 return bytespp * ALIGN(width, 32); 302} 303 304/* for the generated headers: */ 305#define INVALID_IDX(idx) ({BUG(); 0;}) 306#define fui(x) ({BUG(); 0;}) 307#define util_float_to_half(x) ({BUG(); 0;}) 308 309 310#define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 311 312/* for conditionally setting boolean flag(s): */ 313#define COND(bool, val) ((bool) ? (val) : 0) 314 315 316#endif /* __MSM_DRV_H__ */ 317