1/*
2 * TI Multiplexer Clock
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/ti.h>
24#include "clock.h"
25
26#undef pr_fmt
27#define pr_fmt(fmt) "%s: " fmt, __func__
28
29#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
30
31static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
32{
33	struct clk_mux *mux = to_clk_mux(hw);
34	int num_parents = __clk_get_num_parents(hw->clk);
35	u32 val;
36
37	/*
38	 * FIXME need a mux-specific flag to determine if val is bitwise or
39	 * numeric. e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges
40	 * from 0x1 to 0x7 (index starts at one)
41	 * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
42	 * val = 0x4 really means "bit 2, index starts at bit 0"
43	 */
44	val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift;
45	val &= mux->mask;
46
47	if (mux->table) {
48		int i;
49
50		for (i = 0; i < num_parents; i++)
51			if (mux->table[i] == val)
52				return i;
53		return -EINVAL;
54	}
55
56	if (val && (mux->flags & CLK_MUX_INDEX_BIT))
57		val = ffs(val) - 1;
58
59	if (val && (mux->flags & CLK_MUX_INDEX_ONE))
60		val--;
61
62	if (val >= num_parents)
63		return -EINVAL;
64
65	return val;
66}
67
68static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
69{
70	struct clk_mux *mux = to_clk_mux(hw);
71	u32 val;
72	unsigned long flags = 0;
73
74	if (mux->table) {
75		index = mux->table[index];
76	} else {
77		if (mux->flags & CLK_MUX_INDEX_BIT)
78			index = (1 << ffs(index));
79
80		if (mux->flags & CLK_MUX_INDEX_ONE)
81			index++;
82	}
83
84	if (mux->lock)
85		spin_lock_irqsave(mux->lock, flags);
86
87	if (mux->flags & CLK_MUX_HIWORD_MASK) {
88		val = mux->mask << (mux->shift + 16);
89	} else {
90		val = ti_clk_ll_ops->clk_readl(mux->reg);
91		val &= ~(mux->mask << mux->shift);
92	}
93	val |= index << mux->shift;
94	ti_clk_ll_ops->clk_writel(val, mux->reg);
95
96	if (mux->lock)
97		spin_unlock_irqrestore(mux->lock, flags);
98
99	return 0;
100}
101
102const struct clk_ops ti_clk_mux_ops = {
103	.get_parent = ti_clk_mux_get_parent,
104	.set_parent = ti_clk_mux_set_parent,
105	.determine_rate = __clk_mux_determine_rate,
106};
107
108static struct clk *_register_mux(struct device *dev, const char *name,
109				 const char **parent_names, u8 num_parents,
110				 unsigned long flags, void __iomem *reg,
111				 u8 shift, u32 mask, u8 clk_mux_flags,
112				 u32 *table, spinlock_t *lock)
113{
114	struct clk_mux *mux;
115	struct clk *clk;
116	struct clk_init_data init;
117
118	/* allocate the mux */
119	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
120	if (!mux) {
121		pr_err("%s: could not allocate mux clk\n", __func__);
122		return ERR_PTR(-ENOMEM);
123	}
124
125	init.name = name;
126	init.ops = &ti_clk_mux_ops;
127	init.flags = flags | CLK_IS_BASIC;
128	init.parent_names = parent_names;
129	init.num_parents = num_parents;
130
131	/* struct clk_mux assignments */
132	mux->reg = reg;
133	mux->shift = shift;
134	mux->mask = mask;
135	mux->flags = clk_mux_flags;
136	mux->lock = lock;
137	mux->table = table;
138	mux->hw.init = &init;
139
140	clk = clk_register(dev, &mux->hw);
141
142	if (IS_ERR(clk))
143		kfree(mux);
144
145	return clk;
146}
147
148struct clk *ti_clk_register_mux(struct ti_clk *setup)
149{
150	struct ti_clk_mux *mux;
151	u32 flags;
152	u8 mux_flags = 0;
153	struct clk_omap_reg *reg_setup;
154	u32 reg;
155	u32 mask;
156
157	reg_setup = (struct clk_omap_reg *)&reg;
158
159	mux = setup->data;
160	flags = CLK_SET_RATE_NO_REPARENT;
161
162	mask = mux->num_parents;
163	if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE))
164		mask--;
165
166	mask = (1 << fls(mask)) - 1;
167	reg_setup->index = mux->module;
168	reg_setup->offset = mux->reg;
169
170	if (mux->flags & CLKF_INDEX_STARTS_AT_ONE)
171		mux_flags |= CLK_MUX_INDEX_ONE;
172
173	if (mux->flags & CLKF_SET_RATE_PARENT)
174		flags |= CLK_SET_RATE_PARENT;
175
176	return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
177			     flags, (void __iomem *)reg, mux->bit_shift, mask,
178			     mux_flags, NULL, NULL);
179}
180
181/**
182 * of_mux_clk_setup - Setup function for simple mux rate clock
183 * @node: DT node for the clock
184 *
185 * Sets up a basic clock multiplexer.
186 */
187static void of_mux_clk_setup(struct device_node *node)
188{
189	struct clk *clk;
190	void __iomem *reg;
191	int num_parents;
192	const char **parent_names;
193	int i;
194	u8 clk_mux_flags = 0;
195	u32 mask = 0;
196	u32 shift = 0;
197	u32 flags = CLK_SET_RATE_NO_REPARENT;
198
199	num_parents = of_clk_get_parent_count(node);
200	if (num_parents < 2) {
201		pr_err("mux-clock %s must have parents\n", node->name);
202		return;
203	}
204	parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
205	if (!parent_names)
206		goto cleanup;
207
208	for (i = 0; i < num_parents; i++)
209		parent_names[i] = of_clk_get_parent_name(node, i);
210
211	reg = ti_clk_get_reg_addr(node, 0);
212
213	if (IS_ERR(reg))
214		goto cleanup;
215
216	of_property_read_u32(node, "ti,bit-shift", &shift);
217
218	if (of_property_read_bool(node, "ti,index-starts-at-one"))
219		clk_mux_flags |= CLK_MUX_INDEX_ONE;
220
221	if (of_property_read_bool(node, "ti,set-rate-parent"))
222		flags |= CLK_SET_RATE_PARENT;
223
224	/* Generate bit-mask based on parent info */
225	mask = num_parents;
226	if (!(clk_mux_flags & CLK_MUX_INDEX_ONE))
227		mask--;
228
229	mask = (1 << fls(mask)) - 1;
230
231	clk = _register_mux(NULL, node->name, parent_names, num_parents,
232			    flags, reg, shift, mask, clk_mux_flags, NULL,
233			    NULL);
234
235	if (!IS_ERR(clk))
236		of_clk_add_provider(node, of_clk_src_simple_get, clk);
237
238cleanup:
239	kfree(parent_names);
240}
241CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
242
243struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup)
244{
245	struct clk_mux *mux;
246	struct clk_omap_reg *reg;
247	int num_parents;
248
249	if (!setup)
250		return NULL;
251
252	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
253	if (!mux)
254		return ERR_PTR(-ENOMEM);
255
256	reg = (struct clk_omap_reg *)&mux->reg;
257
258	mux->shift = setup->bit_shift;
259
260	reg->index = setup->module;
261	reg->offset = setup->reg;
262
263	if (setup->flags & CLKF_INDEX_STARTS_AT_ONE)
264		mux->flags |= CLK_MUX_INDEX_ONE;
265
266	num_parents = setup->num_parents;
267
268	mux->mask = num_parents - 1;
269	mux->mask = (1 << fls(mux->mask)) - 1;
270
271	return &mux->hw;
272}
273
274static void __init of_ti_composite_mux_clk_setup(struct device_node *node)
275{
276	struct clk_mux *mux;
277	int num_parents;
278	u32 val;
279
280	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
281	if (!mux)
282		return;
283
284	mux->reg = ti_clk_get_reg_addr(node, 0);
285
286	if (IS_ERR(mux->reg))
287		goto cleanup;
288
289	if (!of_property_read_u32(node, "ti,bit-shift", &val))
290		mux->shift = val;
291
292	if (of_property_read_bool(node, "ti,index-starts-at-one"))
293		mux->flags |= CLK_MUX_INDEX_ONE;
294
295	num_parents = of_clk_get_parent_count(node);
296
297	if (num_parents < 2) {
298		pr_err("%s must have parents\n", node->name);
299		goto cleanup;
300	}
301
302	mux->mask = num_parents - 1;
303	mux->mask = (1 << fls(mux->mask)) - 1;
304
305	if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX))
306		return;
307
308cleanup:
309	kfree(mux);
310}
311CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
312	       of_ti_composite_mux_clk_setup);
313