1/*
2 * Copyright 2013 Emilio López
3 *
4 * Emilio López <emilio@elopez.com.ar>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
19#include <linux/of_address.h>
20#include <linux/platform_device.h>
21
22#include "clk-factors.h"
23
24/**
25 * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
26 * MOD0 rate is calculated as follows
27 * rate = (parent_rate >> p) / (m + 1);
28 */
29
30static void sun4i_a10_get_mod0_factors(u32 *freq, u32 parent_rate,
31				       u8 *n, u8 *k, u8 *m, u8 *p)
32{
33	u8 div, calcm, calcp;
34
35	/* These clocks can only divide, so we will never be able to achieve
36	 * frequencies higher than the parent frequency */
37	if (*freq > parent_rate)
38		*freq = parent_rate;
39
40	div = DIV_ROUND_UP(parent_rate, *freq);
41
42	if (div < 16)
43		calcp = 0;
44	else if (div / 2 < 16)
45		calcp = 1;
46	else if (div / 4 < 16)
47		calcp = 2;
48	else
49		calcp = 3;
50
51	calcm = DIV_ROUND_UP(div, 1 << calcp);
52
53	*freq = (parent_rate >> calcp) / calcm;
54
55	/* we were called to round the frequency, we can now return */
56	if (n == NULL)
57		return;
58
59	*m = calcm - 1;
60	*p = calcp;
61}
62
63/* user manual says "n" but it's really "p" */
64static struct clk_factors_config sun4i_a10_mod0_config = {
65	.mshift = 0,
66	.mwidth = 4,
67	.pshift = 16,
68	.pwidth = 2,
69};
70
71static const struct factors_data sun4i_a10_mod0_data = {
72	.enable = 31,
73	.mux = 24,
74	.muxmask = BIT(1) | BIT(0),
75	.table = &sun4i_a10_mod0_config,
76	.getter = sun4i_a10_get_mod0_factors,
77};
78
79static DEFINE_SPINLOCK(sun4i_a10_mod0_lock);
80
81static void __init sun4i_a10_mod0_setup(struct device_node *node)
82{
83	void __iomem *reg;
84
85	reg = of_iomap(node, 0);
86	if (!reg) {
87		/*
88		 * This happens with mod0 clk nodes instantiated through
89		 * mfd, as those do not have their resources assigned at
90		 * CLK_OF_DECLARE time yet, so do not print an error.
91		 */
92		return;
93	}
94
95	sunxi_factors_register(node, &sun4i_a10_mod0_data,
96			       &sun4i_a10_mod0_lock, reg);
97}
98CLK_OF_DECLARE(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk", sun4i_a10_mod0_setup);
99
100static int sun4i_a10_mod0_clk_probe(struct platform_device *pdev)
101{
102	struct device_node *np = pdev->dev.of_node;
103	struct resource *r;
104	void __iomem *reg;
105
106	if (!np)
107		return -ENODEV;
108
109	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110	reg = devm_ioremap_resource(&pdev->dev, r);
111	if (IS_ERR(reg))
112		return PTR_ERR(reg);
113
114	sunxi_factors_register(np, &sun4i_a10_mod0_data,
115			       &sun4i_a10_mod0_lock, reg);
116	return 0;
117}
118
119static const struct of_device_id sun4i_a10_mod0_clk_dt_ids[] = {
120	{ .compatible = "allwinner,sun4i-a10-mod0-clk" },
121	{ /* sentinel */ }
122};
123
124static struct platform_driver sun4i_a10_mod0_clk_driver = {
125	.driver = {
126		.name = "sun4i-a10-mod0-clk",
127		.of_match_table = sun4i_a10_mod0_clk_dt_ids,
128	},
129	.probe = sun4i_a10_mod0_clk_probe,
130};
131module_platform_driver(sun4i_a10_mod0_clk_driver);
132
133static const struct factors_data sun9i_a80_mod0_data __initconst = {
134	.enable = 31,
135	.mux = 24,
136	.muxmask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
137	.table = &sun4i_a10_mod0_config,
138	.getter = sun4i_a10_get_mod0_factors,
139};
140
141static void __init sun9i_a80_mod0_setup(struct device_node *node)
142{
143	void __iomem *reg;
144
145	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
146	if (IS_ERR(reg)) {
147		pr_err("Could not get registers for mod0-clk: %s\n",
148		       node->name);
149		return;
150	}
151
152	sunxi_factors_register(node, &sun9i_a80_mod0_data,
153			       &sun4i_a10_mod0_lock, reg);
154}
155CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
156
157static DEFINE_SPINLOCK(sun5i_a13_mbus_lock);
158
159static void __init sun5i_a13_mbus_setup(struct device_node *node)
160{
161	struct clk *mbus;
162	void __iomem *reg;
163
164	reg = of_iomap(node, 0);
165	if (!reg) {
166		pr_err("Could not get registers for a13-mbus-clk\n");
167		return;
168	}
169
170	mbus = sunxi_factors_register(node, &sun4i_a10_mod0_data,
171				      &sun5i_a13_mbus_lock, reg);
172
173	/* The MBUS clocks needs to be always enabled */
174	__clk_get(mbus);
175	clk_prepare_enable(mbus);
176}
177CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
178
179struct mmc_phase {
180	struct clk_hw		hw;
181	u8			offset;
182	void __iomem		*reg;
183	spinlock_t		*lock;
184};
185
186#define to_mmc_phase(_hw) container_of(_hw, struct mmc_phase, hw)
187
188static int mmc_get_phase(struct clk_hw *hw)
189{
190	struct clk *mmc, *mmc_parent, *clk = hw->clk;
191	struct mmc_phase *phase = to_mmc_phase(hw);
192	unsigned int mmc_rate, mmc_parent_rate;
193	u16 step, mmc_div;
194	u32 value;
195	u8 delay;
196
197	value = readl(phase->reg);
198	delay = (value >> phase->offset) & 0x3;
199
200	if (!delay)
201		return 180;
202
203	/* Get the main MMC clock */
204	mmc = clk_get_parent(clk);
205	if (!mmc)
206		return -EINVAL;
207
208	/* And its rate */
209	mmc_rate = clk_get_rate(mmc);
210	if (!mmc_rate)
211		return -EINVAL;
212
213	/* Now, get the MMC parent (most likely some PLL) */
214	mmc_parent = clk_get_parent(mmc);
215	if (!mmc_parent)
216		return -EINVAL;
217
218	/* And its rate */
219	mmc_parent_rate = clk_get_rate(mmc_parent);
220	if (!mmc_parent_rate)
221		return -EINVAL;
222
223	/* Get MMC clock divider */
224	mmc_div = mmc_parent_rate / mmc_rate;
225
226	step = DIV_ROUND_CLOSEST(360, mmc_div);
227	return delay * step;
228}
229
230static int mmc_set_phase(struct clk_hw *hw, int degrees)
231{
232	struct clk *mmc, *mmc_parent, *clk = hw->clk;
233	struct mmc_phase *phase = to_mmc_phase(hw);
234	unsigned int mmc_rate, mmc_parent_rate;
235	unsigned long flags;
236	u32 value;
237	u8 delay;
238
239	/* Get the main MMC clock */
240	mmc = clk_get_parent(clk);
241	if (!mmc)
242		return -EINVAL;
243
244	/* And its rate */
245	mmc_rate = clk_get_rate(mmc);
246	if (!mmc_rate)
247		return -EINVAL;
248
249	/* Now, get the MMC parent (most likely some PLL) */
250	mmc_parent = clk_get_parent(mmc);
251	if (!mmc_parent)
252		return -EINVAL;
253
254	/* And its rate */
255	mmc_parent_rate = clk_get_rate(mmc_parent);
256	if (!mmc_parent_rate)
257		return -EINVAL;
258
259	if (degrees != 180) {
260		u16 step, mmc_div;
261
262		/* Get MMC clock divider */
263		mmc_div = mmc_parent_rate / mmc_rate;
264
265		/*
266		 * We can only outphase the clocks by multiple of the
267		 * PLL's period.
268		 *
269		 * Since the MMC clock in only a divider, and the
270		 * formula to get the outphasing in degrees is deg =
271		 * 360 * delta / period
272		 *
273		 * If we simplify this formula, we can see that the
274		 * only thing that we're concerned about is the number
275		 * of period we want to outphase our clock from, and
276		 * the divider set by the MMC clock.
277		 */
278		step = DIV_ROUND_CLOSEST(360, mmc_div);
279		delay = DIV_ROUND_CLOSEST(degrees, step);
280	} else {
281		delay = 0;
282	}
283
284	spin_lock_irqsave(phase->lock, flags);
285	value = readl(phase->reg);
286	value &= ~GENMASK(phase->offset + 3, phase->offset);
287	value |= delay << phase->offset;
288	writel(value, phase->reg);
289	spin_unlock_irqrestore(phase->lock, flags);
290
291	return 0;
292}
293
294static const struct clk_ops mmc_clk_ops = {
295	.get_phase	= mmc_get_phase,
296	.set_phase	= mmc_set_phase,
297};
298
299/*
300 * sunxi_mmc_setup - Common setup function for mmc module clocks
301 *
302 * The only difference between module clocks on different platforms is the
303 * width of the mux register bits and the valid values, which are passed in
304 * through struct factors_data. The phase clocks parts are identical.
305 */
306static void __init sunxi_mmc_setup(struct device_node *node,
307				   const struct factors_data *data,
308				   spinlock_t *lock)
309{
310	struct clk_onecell_data *clk_data;
311	const char *parent;
312	void __iomem *reg;
313	int i;
314
315	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
316	if (IS_ERR(reg)) {
317		pr_err("Couldn't map the %s clock registers\n", node->name);
318		return;
319	}
320
321	clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
322	if (!clk_data)
323		return;
324
325	clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
326	if (!clk_data->clks)
327		goto err_free_data;
328
329	clk_data->clk_num = 3;
330	clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
331	if (!clk_data->clks[0])
332		goto err_free_clks;
333
334	parent = __clk_get_name(clk_data->clks[0]);
335
336	for (i = 1; i < 3; i++) {
337		struct clk_init_data init = {
338			.num_parents	= 1,
339			.parent_names	= &parent,
340			.ops		= &mmc_clk_ops,
341		};
342		struct mmc_phase *phase;
343
344		phase = kmalloc(sizeof(*phase), GFP_KERNEL);
345		if (!phase)
346			continue;
347
348		phase->hw.init = &init;
349		phase->reg = reg;
350		phase->lock = lock;
351
352		if (i == 1)
353			phase->offset = 8;
354		else
355			phase->offset = 20;
356
357		if (of_property_read_string_index(node, "clock-output-names",
358						  i, &init.name))
359			init.name = node->name;
360
361		clk_data->clks[i] = clk_register(NULL, &phase->hw);
362		if (IS_ERR(clk_data->clks[i])) {
363			kfree(phase);
364			continue;
365		}
366	}
367
368	of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
369
370	return;
371
372err_free_clks:
373	kfree(clk_data->clks);
374err_free_data:
375	kfree(clk_data);
376}
377
378static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);
379
380static void __init sun4i_a10_mmc_setup(struct device_node *node)
381{
382	sunxi_mmc_setup(node, &sun4i_a10_mod0_data, &sun4i_a10_mmc_lock);
383}
384CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
385
386static DEFINE_SPINLOCK(sun9i_a80_mmc_lock);
387
388static void __init sun9i_a80_mmc_setup(struct device_node *node)
389{
390	sunxi_mmc_setup(node, &sun9i_a80_mod0_data, &sun9i_a80_mmc_lock);
391}
392CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);
393