1/* 2 * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of version 2.1 of the GNU Lesser General Public 6 * License as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it would be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 11 * 12 * Further, this software is distributed without any warranty that it is 13 * free of the rightful claim of any third person regarding infringement 14 * or the like. Any license provided herein, whether implied or 15 * otherwise, applies only to this software file. Patent licenses, if 16 * any, provided herein do not apply to combinations of this program with 17 * other software, or any other product whatsoever. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this program; if not, write the Free Software 21 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, 22 * USA. 23 */ 24 25#ifndef _XTENSA_REGS_H 26#define _XTENSA_REGS_H 27 28/* Special registers. */ 29 30#define SREG_MR 32 31#define SREG_IBREAKA 128 32#define SREG_DBREAKA 144 33#define SREG_DBREAKC 160 34#define SREG_EPC 176 35#define SREG_EPS 192 36#define SREG_EXCSAVE 208 37#define SREG_CCOMPARE 240 38#define SREG_MISC 244 39 40/* EXCCAUSE register fields */ 41 42#define EXCCAUSE_EXCCAUSE_SHIFT 0 43#define EXCCAUSE_EXCCAUSE_MASK 0x3F 44 45#define EXCCAUSE_ILLEGAL_INSTRUCTION 0 46#define EXCCAUSE_SYSTEM_CALL 1 47#define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 48#define EXCCAUSE_LOAD_STORE_ERROR 3 49#define EXCCAUSE_LEVEL1_INTERRUPT 4 50#define EXCCAUSE_ALLOCA 5 51#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 52#define EXCCAUSE_SPECULATION 7 53#define EXCCAUSE_PRIVILEGED 8 54#define EXCCAUSE_UNALIGNED 9 55#define EXCCAUSE_INSTR_DATA_ERROR 12 56#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 57#define EXCCAUSE_INSTR_ADDR_ERROR 14 58#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 59#define EXCCAUSE_ITLB_MISS 16 60#define EXCCAUSE_ITLB_MULTIHIT 17 61#define EXCCAUSE_ITLB_PRIVILEGE 18 62#define EXCCAUSE_ITLB_SIZE_RESTRICTION 19 63#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 64#define EXCCAUSE_DTLB_MISS 24 65#define EXCCAUSE_DTLB_MULTIHIT 25 66#define EXCCAUSE_DTLB_PRIVILEGE 26 67#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27 68#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 69#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 70#define EXCCAUSE_COPROCESSOR0_DISABLED 32 71#define EXCCAUSE_COPROCESSOR1_DISABLED 33 72#define EXCCAUSE_COPROCESSOR2_DISABLED 34 73#define EXCCAUSE_COPROCESSOR3_DISABLED 35 74#define EXCCAUSE_COPROCESSOR4_DISABLED 36 75#define EXCCAUSE_COPROCESSOR5_DISABLED 37 76#define EXCCAUSE_COPROCESSOR6_DISABLED 38 77#define EXCCAUSE_COPROCESSOR7_DISABLED 39 78 79/* PS register fields. */ 80 81#define PS_WOE_BIT 18 82#define PS_CALLINC_SHIFT 16 83#define PS_CALLINC_MASK 0x00030000 84#define PS_OWB_SHIFT 8 85#define PS_OWB_WIDTH 4 86#define PS_OWB_MASK 0x00000F00 87#define PS_RING_SHIFT 6 88#define PS_RING_MASK 0x000000C0 89#define PS_UM_BIT 5 90#define PS_EXCM_BIT 4 91#define PS_INTLEVEL_SHIFT 0 92#define PS_INTLEVEL_WIDTH 4 93#define PS_INTLEVEL_MASK 0x0000000F 94 95/* DBREAKCn register fields. */ 96 97#define DBREAKC_MASK_BIT 0 98#define DBREAKC_MASK_MASK 0x0000003F 99#define DBREAKC_LOAD_BIT 30 100#define DBREAKC_LOAD_MASK 0x40000000 101#define DBREAKC_STOR_BIT 31 102#define DBREAKC_STOR_MASK 0x80000000 103 104/* DEBUGCAUSE register fields. */ 105 106#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */ 107#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */ 108#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */ 109#define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */ 110#define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */ 111#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */ 112 113#endif /* _XTENSA_SPECREG_H */ 114