1/* 2 * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and 3 * initial domain support. We also handle the DSDT _PRT callbacks for GSI's 4 * used in HVM and initial domain mode (PV does not parse ACPI, so it has no 5 * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and 6 * 0xcf8 PCI configuration read/write. 7 * 8 * Author: Ryan Wilson <hap9@epoch.ncsc.mil> 9 * Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> 10 * Stefano Stabellini <stefano.stabellini@eu.citrix.com> 11 */ 12#include <linux/module.h> 13#include <linux/init.h> 14#include <linux/pci.h> 15#include <linux/acpi.h> 16 17#include <linux/io.h> 18#include <asm/io_apic.h> 19#include <asm/pci_x86.h> 20 21#include <asm/xen/hypervisor.h> 22 23#include <xen/features.h> 24#include <xen/events.h> 25#include <asm/xen/pci.h> 26#include <asm/xen/cpuid.h> 27#include <asm/apic.h> 28#include <asm/i8259.h> 29 30static int xen_pcifront_enable_irq(struct pci_dev *dev) 31{ 32 int rc; 33 int share = 1; 34 int pirq; 35 u8 gsi; 36 37 rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi); 38 if (rc < 0) { 39 dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n", 40 rc); 41 return rc; 42 } 43 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/ 44 pirq = gsi; 45 46 if (gsi < nr_legacy_irqs()) 47 share = 0; 48 49 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront"); 50 if (rc < 0) { 51 dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n", 52 gsi, pirq, rc); 53 return rc; 54 } 55 56 dev->irq = rc; 57 dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq); 58 return 0; 59} 60 61#ifdef CONFIG_ACPI 62static int xen_register_pirq(u32 gsi, int gsi_override, int triggering, 63 bool set_pirq) 64{ 65 int rc, pirq = -1, irq = -1; 66 struct physdev_map_pirq map_irq; 67 int shareable = 0; 68 char *name; 69 70 irq = xen_irq_from_gsi(gsi); 71 if (irq > 0) 72 return irq; 73 74 if (set_pirq) 75 pirq = gsi; 76 77 map_irq.domid = DOMID_SELF; 78 map_irq.type = MAP_PIRQ_TYPE_GSI; 79 map_irq.index = gsi; 80 map_irq.pirq = pirq; 81 82 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq); 83 if (rc) { 84 printk(KERN_WARNING "xen map irq failed %d\n", rc); 85 return -1; 86 } 87 88 if (triggering == ACPI_EDGE_SENSITIVE) { 89 shareable = 0; 90 name = "ioapic-edge"; 91 } else { 92 shareable = 1; 93 name = "ioapic-level"; 94 } 95 96 if (gsi_override >= 0) 97 gsi = gsi_override; 98 99 irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name); 100 if (irq < 0) 101 goto out; 102 103 printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi); 104out: 105 return irq; 106} 107 108static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi, 109 int trigger, int polarity) 110{ 111 if (!xen_hvm_domain()) 112 return -1; 113 114 return xen_register_pirq(gsi, -1 /* no GSI override */, trigger, 115 false /* no mapping of GSI to PIRQ */); 116} 117 118#ifdef CONFIG_XEN_DOM0 119static int xen_register_gsi(u32 gsi, int gsi_override, int triggering, int polarity) 120{ 121 int rc, irq; 122 struct physdev_setup_gsi setup_gsi; 123 124 if (!xen_pv_domain()) 125 return -1; 126 127 printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n", 128 gsi, triggering, polarity); 129 130 irq = xen_register_pirq(gsi, gsi_override, triggering, true); 131 132 setup_gsi.gsi = gsi; 133 setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1); 134 setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1); 135 136 rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi); 137 if (rc == -EEXIST) 138 printk(KERN_INFO "Already setup the GSI :%d\n", gsi); 139 else if (rc) { 140 printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n", 141 gsi, rc); 142 } 143 144 return irq; 145} 146 147static int acpi_register_gsi_xen(struct device *dev, u32 gsi, 148 int trigger, int polarity) 149{ 150 return xen_register_gsi(gsi, -1 /* no GSI override */, trigger, polarity); 151} 152#endif 153#endif 154 155#if defined(CONFIG_PCI_MSI) 156#include <linux/msi.h> 157#include <asm/msidef.h> 158 159struct xen_pci_frontend_ops *xen_pci_frontend; 160EXPORT_SYMBOL_GPL(xen_pci_frontend); 161 162static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 163{ 164 int irq, ret, i; 165 struct msi_desc *msidesc; 166 int *v; 167 168 if (type == PCI_CAP_ID_MSI && nvec > 1) 169 return 1; 170 171 v = kzalloc(sizeof(int) * max(1, nvec), GFP_KERNEL); 172 if (!v) 173 return -ENOMEM; 174 175 if (type == PCI_CAP_ID_MSIX) 176 ret = xen_pci_frontend_enable_msix(dev, v, nvec); 177 else 178 ret = xen_pci_frontend_enable_msi(dev, v); 179 if (ret) 180 goto error; 181 i = 0; 182 list_for_each_entry(msidesc, &dev->msi_list, list) { 183 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i], 184 (type == PCI_CAP_ID_MSI) ? nvec : 1, 185 (type == PCI_CAP_ID_MSIX) ? 186 "pcifront-msi-x" : 187 "pcifront-msi", 188 DOMID_SELF); 189 if (irq < 0) { 190 ret = irq; 191 goto free; 192 } 193 i++; 194 } 195 kfree(v); 196 return 0; 197 198error: 199 dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n"); 200free: 201 kfree(v); 202 return ret; 203} 204 205#define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE | \ 206 MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0)) 207 208static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq, 209 struct msi_msg *msg) 210{ 211 /* We set vector == 0 to tell the hypervisor we don't care about it, 212 * but we want a pirq setup instead. 213 * We use the dest_id field to pass the pirq that we want. */ 214 msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq); 215 msg->address_lo = 216 MSI_ADDR_BASE_LO | 217 MSI_ADDR_DEST_MODE_PHYSICAL | 218 MSI_ADDR_REDIRECTION_CPU | 219 MSI_ADDR_DEST_ID(pirq); 220 221 msg->data = XEN_PIRQ_MSI_DATA; 222} 223 224static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 225{ 226 int irq, pirq; 227 struct msi_desc *msidesc; 228 struct msi_msg msg; 229 230 if (type == PCI_CAP_ID_MSI && nvec > 1) 231 return 1; 232 233 list_for_each_entry(msidesc, &dev->msi_list, list) { 234 __pci_read_msi_msg(msidesc, &msg); 235 pirq = MSI_ADDR_EXT_DEST_ID(msg.address_hi) | 236 ((msg.address_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xff); 237 if (msg.data != XEN_PIRQ_MSI_DATA || 238 xen_irq_from_pirq(pirq) < 0) { 239 pirq = xen_allocate_pirq_msi(dev, msidesc); 240 if (pirq < 0) { 241 irq = -ENODEV; 242 goto error; 243 } 244 xen_msi_compose_msg(dev, pirq, &msg); 245 __pci_write_msi_msg(msidesc, &msg); 246 dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq); 247 } else { 248 dev_dbg(&dev->dev, 249 "xen: msi already bound to pirq=%d\n", pirq); 250 } 251 irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq, 252 (type == PCI_CAP_ID_MSI) ? nvec : 1, 253 (type == PCI_CAP_ID_MSIX) ? 254 "msi-x" : "msi", 255 DOMID_SELF); 256 if (irq < 0) 257 goto error; 258 dev_dbg(&dev->dev, 259 "xen: msi --> pirq=%d --> irq=%d\n", pirq, irq); 260 } 261 return 0; 262 263error: 264 dev_err(&dev->dev, 265 "Xen PCI frontend has not registered MSI/MSI-X support!\n"); 266 return irq; 267} 268 269#ifdef CONFIG_XEN_DOM0 270static bool __read_mostly pci_seg_supported = true; 271 272static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 273{ 274 int ret = 0; 275 struct msi_desc *msidesc; 276 277 list_for_each_entry(msidesc, &dev->msi_list, list) { 278 struct physdev_map_pirq map_irq; 279 domid_t domid; 280 281 domid = ret = xen_find_device_domain_owner(dev); 282 /* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED, 283 * hence check ret value for < 0. */ 284 if (ret < 0) 285 domid = DOMID_SELF; 286 287 memset(&map_irq, 0, sizeof(map_irq)); 288 map_irq.domid = domid; 289 map_irq.type = MAP_PIRQ_TYPE_MSI_SEG; 290 map_irq.index = -1; 291 map_irq.pirq = -1; 292 map_irq.bus = dev->bus->number | 293 (pci_domain_nr(dev->bus) << 16); 294 map_irq.devfn = dev->devfn; 295 296 if (type == PCI_CAP_ID_MSI && nvec > 1) { 297 map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI; 298 map_irq.entry_nr = nvec; 299 } else if (type == PCI_CAP_ID_MSIX) { 300 int pos; 301 unsigned long flags; 302 u32 table_offset, bir; 303 304 pos = dev->msix_cap; 305 pci_read_config_dword(dev, pos + PCI_MSIX_TABLE, 306 &table_offset); 307 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR); 308 flags = pci_resource_flags(dev, bir); 309 if (!flags || (flags & IORESOURCE_UNSET)) 310 return -EINVAL; 311 312 map_irq.table_base = pci_resource_start(dev, bir); 313 map_irq.entry_nr = msidesc->msi_attrib.entry_nr; 314 } 315 316 ret = -EINVAL; 317 if (pci_seg_supported) 318 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, 319 &map_irq); 320 if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) { 321 /* 322 * If MAP_PIRQ_TYPE_MULTI_MSI is not available 323 * there's nothing else we can do in this case. 324 * Just set ret > 0 so driver can retry with 325 * single MSI. 326 */ 327 ret = 1; 328 goto out; 329 } 330 if (ret == -EINVAL && !pci_domain_nr(dev->bus)) { 331 map_irq.type = MAP_PIRQ_TYPE_MSI; 332 map_irq.index = -1; 333 map_irq.pirq = -1; 334 map_irq.bus = dev->bus->number; 335 ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, 336 &map_irq); 337 if (ret != -EINVAL) 338 pci_seg_supported = false; 339 } 340 if (ret) { 341 dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n", 342 ret, domid); 343 goto out; 344 } 345 346 ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq, 347 (type == PCI_CAP_ID_MSI) ? nvec : 1, 348 (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi", 349 domid); 350 if (ret < 0) 351 goto out; 352 } 353 ret = 0; 354out: 355 return ret; 356} 357 358static void xen_initdom_restore_msi_irqs(struct pci_dev *dev) 359{ 360 int ret = 0; 361 362 if (pci_seg_supported) { 363 struct physdev_pci_device restore_ext; 364 365 restore_ext.seg = pci_domain_nr(dev->bus); 366 restore_ext.bus = dev->bus->number; 367 restore_ext.devfn = dev->devfn; 368 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext, 369 &restore_ext); 370 if (ret == -ENOSYS) 371 pci_seg_supported = false; 372 WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret); 373 } 374 if (!pci_seg_supported) { 375 struct physdev_restore_msi restore; 376 377 restore.bus = dev->bus->number; 378 restore.devfn = dev->devfn; 379 ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore); 380 WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret); 381 } 382} 383#endif 384 385static void xen_teardown_msi_irqs(struct pci_dev *dev) 386{ 387 struct msi_desc *msidesc; 388 389 msidesc = list_entry(dev->msi_list.next, struct msi_desc, list); 390 if (msidesc->msi_attrib.is_msix) 391 xen_pci_frontend_disable_msix(dev); 392 else 393 xen_pci_frontend_disable_msi(dev); 394 395 /* Free the IRQ's and the msidesc using the generic code. */ 396 default_teardown_msi_irqs(dev); 397} 398 399static void xen_teardown_msi_irq(unsigned int irq) 400{ 401 xen_destroy_irq(irq); 402} 403 404#endif 405 406int __init pci_xen_init(void) 407{ 408 if (!xen_pv_domain() || xen_initial_domain()) 409 return -ENODEV; 410 411 printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n"); 412 413 pcibios_set_cache_line_size(); 414 415 pcibios_enable_irq = xen_pcifront_enable_irq; 416 pcibios_disable_irq = NULL; 417 418#ifdef CONFIG_ACPI 419 /* Keep ACPI out of the picture */ 420 acpi_noirq = 1; 421#endif 422 423#ifdef CONFIG_PCI_MSI 424 x86_msi.setup_msi_irqs = xen_setup_msi_irqs; 425 x86_msi.teardown_msi_irq = xen_teardown_msi_irq; 426 x86_msi.teardown_msi_irqs = xen_teardown_msi_irqs; 427 pci_msi_ignore_mask = 1; 428#endif 429 return 0; 430} 431 432#ifdef CONFIG_PCI_MSI 433void __init xen_msi_init(void) 434{ 435 if (!disable_apic) { 436 /* 437 * If hardware supports (x2)APIC virtualization (as indicated 438 * by hypervisor's leaf 4) then we don't need to use pirqs/ 439 * event channels for MSI handling and instead use regular 440 * APIC processing 441 */ 442 uint32_t eax = cpuid_eax(xen_cpuid_base() + 4); 443 444 if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) || 445 ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && cpu_has_apic)) 446 return; 447 } 448 449 x86_msi.setup_msi_irqs = xen_hvm_setup_msi_irqs; 450 x86_msi.teardown_msi_irq = xen_teardown_msi_irq; 451} 452#endif 453 454int __init pci_xen_hvm_init(void) 455{ 456 if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs)) 457 return 0; 458 459#ifdef CONFIG_ACPI 460 /* 461 * We don't want to change the actual ACPI delivery model, 462 * just how GSIs get registered. 463 */ 464 __acpi_register_gsi = acpi_register_gsi_xen_hvm; 465 __acpi_unregister_gsi = NULL; 466#endif 467 468#ifdef CONFIG_PCI_MSI 469 /* 470 * We need to wait until after x2apic is initialized 471 * before we can set MSI IRQ ops. 472 */ 473 x86_platform.apic_post_init = xen_msi_init; 474#endif 475 return 0; 476} 477 478#ifdef CONFIG_XEN_DOM0 479int __init pci_xen_initial_domain(void) 480{ 481 int irq; 482 483#ifdef CONFIG_PCI_MSI 484 x86_msi.setup_msi_irqs = xen_initdom_setup_msi_irqs; 485 x86_msi.teardown_msi_irq = xen_teardown_msi_irq; 486 x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs; 487 pci_msi_ignore_mask = 1; 488#endif 489 __acpi_register_gsi = acpi_register_gsi_xen; 490 __acpi_unregister_gsi = NULL; 491 /* 492 * Pre-allocate the legacy IRQs. Use NR_LEGACY_IRQS here 493 * because we don't have a PIC and thus nr_legacy_irqs() is zero. 494 */ 495 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) { 496 int trigger, polarity; 497 498 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1) 499 continue; 500 501 xen_register_pirq(irq, -1 /* no GSI override */, 502 trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE, 503 true /* Map GSI to PIRQ */); 504 } 505 if (0 == nr_ioapics) { 506 for (irq = 0; irq < nr_legacy_irqs(); irq++) 507 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic"); 508 } 509 return 0; 510} 511 512struct xen_device_domain_owner { 513 domid_t domain; 514 struct pci_dev *dev; 515 struct list_head list; 516}; 517 518static DEFINE_SPINLOCK(dev_domain_list_spinlock); 519static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list); 520 521static struct xen_device_domain_owner *find_device(struct pci_dev *dev) 522{ 523 struct xen_device_domain_owner *owner; 524 525 list_for_each_entry(owner, &dev_domain_list, list) { 526 if (owner->dev == dev) 527 return owner; 528 } 529 return NULL; 530} 531 532int xen_find_device_domain_owner(struct pci_dev *dev) 533{ 534 struct xen_device_domain_owner *owner; 535 int domain = -ENODEV; 536 537 spin_lock(&dev_domain_list_spinlock); 538 owner = find_device(dev); 539 if (owner) 540 domain = owner->domain; 541 spin_unlock(&dev_domain_list_spinlock); 542 return domain; 543} 544EXPORT_SYMBOL_GPL(xen_find_device_domain_owner); 545 546int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain) 547{ 548 struct xen_device_domain_owner *owner; 549 550 owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL); 551 if (!owner) 552 return -ENODEV; 553 554 spin_lock(&dev_domain_list_spinlock); 555 if (find_device(dev)) { 556 spin_unlock(&dev_domain_list_spinlock); 557 kfree(owner); 558 return -EEXIST; 559 } 560 owner->domain = domain; 561 owner->dev = dev; 562 list_add_tail(&owner->list, &dev_domain_list); 563 spin_unlock(&dev_domain_list_spinlock); 564 return 0; 565} 566EXPORT_SYMBOL_GPL(xen_register_device_domain_owner); 567 568int xen_unregister_device_domain_owner(struct pci_dev *dev) 569{ 570 struct xen_device_domain_owner *owner; 571 572 spin_lock(&dev_domain_list_spinlock); 573 owner = find_device(dev); 574 if (!owner) { 575 spin_unlock(&dev_domain_list_spinlock); 576 return -ENODEV; 577 } 578 list_del(&owner->list); 579 spin_unlock(&dev_domain_list_spinlock); 580 kfree(owner); 581 return 0; 582} 583EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner); 584#endif 585