1 /*
2 * Intel Atom SOC Power Management Controller Driver
3 * Copyright (c) 2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/pci.h>
21 #include <linux/device.h>
22 #include <linux/debugfs.h>
23 #include <linux/seq_file.h>
24 #include <linux/io.h>
25
26 #include <asm/pmc_atom.h>
27
28 struct pmc_dev {
29 u32 base_addr;
30 void __iomem *regmap;
31 #ifdef CONFIG_DEBUG_FS
32 struct dentry *dbgfs_dir;
33 #endif /* CONFIG_DEBUG_FS */
34 };
35
36 static struct pmc_dev pmc_device;
37 static u32 acpi_base_addr;
38
39 struct pmc_bit_map {
40 const char *name;
41 u32 bit_mask;
42 };
43
44 static const struct pmc_bit_map dev_map[] = {
45 {"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
46 {"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
47 {"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
48 {"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
49 {"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
50 {"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
51 {"6 - LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
52 {"7 - LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
53 {"8 - SCC_EMMC", BIT_SCC_EMMC},
54 {"9 - SCC_SDIO", BIT_SCC_SDIO},
55 {"10 - SCC_SDCARD", BIT_SCC_SDCARD},
56 {"11 - SCC_MIPI", BIT_SCC_MIPI},
57 {"12 - HDA", BIT_HDA},
58 {"13 - LPE", BIT_LPE},
59 {"14 - OTG", BIT_OTG},
60 {"15 - USH", BIT_USH},
61 {"16 - GBE", BIT_GBE},
62 {"17 - SATA", BIT_SATA},
63 {"18 - USB_EHCI", BIT_USB_EHCI},
64 {"19 - SEC", BIT_SEC},
65 {"20 - PCIE_PORT0", BIT_PCIE_PORT0},
66 {"21 - PCIE_PORT1", BIT_PCIE_PORT1},
67 {"22 - PCIE_PORT2", BIT_PCIE_PORT2},
68 {"23 - PCIE_PORT3", BIT_PCIE_PORT3},
69 {"24 - LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
70 {"25 - LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
71 {"26 - LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
72 {"27 - LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
73 {"28 - LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
74 {"29 - LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
75 {"30 - LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
76 {"31 - LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
77 {"32 - SMB", BIT_SMB},
78 {"33 - OTG_SS_PHY", BIT_OTG_SS_PHY},
79 {"34 - USH_SS_PHY", BIT_USH_SS_PHY},
80 {"35 - DFX", BIT_DFX},
81 };
82
83 static const struct pmc_bit_map pss_map[] = {
84 {"0 - GBE", PMC_PSS_BIT_GBE},
85 {"1 - SATA", PMC_PSS_BIT_SATA},
86 {"2 - HDA", PMC_PSS_BIT_HDA},
87 {"3 - SEC", PMC_PSS_BIT_SEC},
88 {"4 - PCIE", PMC_PSS_BIT_PCIE},
89 {"5 - LPSS", PMC_PSS_BIT_LPSS},
90 {"6 - LPE", PMC_PSS_BIT_LPE},
91 {"7 - DFX", PMC_PSS_BIT_DFX},
92 {"8 - USH_CTRL", PMC_PSS_BIT_USH_CTRL},
93 {"9 - USH_SUS", PMC_PSS_BIT_USH_SUS},
94 {"10 - USH_VCCS", PMC_PSS_BIT_USH_VCCS},
95 {"11 - USH_VCCA", PMC_PSS_BIT_USH_VCCA},
96 {"12 - OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
97 {"13 - OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
98 {"14 - OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
99 {"15 - OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
100 {"16 - USB", PMC_PSS_BIT_USB},
101 {"17 - USB_SUS", PMC_PSS_BIT_USB_SUS},
102 };
103
pmc_reg_read(struct pmc_dev * pmc,int reg_offset)104 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
105 {
106 return readl(pmc->regmap + reg_offset);
107 }
108
pmc_reg_write(struct pmc_dev * pmc,int reg_offset,u32 val)109 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
110 {
111 writel(val, pmc->regmap + reg_offset);
112 }
113
pmc_power_off(void)114 static void pmc_power_off(void)
115 {
116 u16 pm1_cnt_port;
117 u32 pm1_cnt_value;
118
119 pr_info("Preparing to enter system sleep state S5\n");
120
121 pm1_cnt_port = acpi_base_addr + PM1_CNT;
122
123 pm1_cnt_value = inl(pm1_cnt_port);
124 pm1_cnt_value &= SLEEP_TYPE_MASK;
125 pm1_cnt_value |= SLEEP_TYPE_S5;
126 pm1_cnt_value |= SLEEP_ENABLE;
127
128 outl(pm1_cnt_value, pm1_cnt_port);
129 }
130
pmc_hw_reg_setup(struct pmc_dev * pmc)131 static void pmc_hw_reg_setup(struct pmc_dev *pmc)
132 {
133 /*
134 * Disable PMC S0IX_WAKE_EN events coming from:
135 * - LPC clock run
136 * - GPIO_SUS ored dedicated IRQs
137 * - GPIO_SCORE ored dedicated IRQs
138 * - GPIO_SUS shared IRQ
139 * - GPIO_SCORE shared IRQ
140 */
141 pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
142 }
143
144 #ifdef CONFIG_DEBUG_FS
pmc_dev_state_show(struct seq_file * s,void * unused)145 static int pmc_dev_state_show(struct seq_file *s, void *unused)
146 {
147 struct pmc_dev *pmc = s->private;
148 u32 func_dis, func_dis_2, func_dis_index;
149 u32 d3_sts_0, d3_sts_1, d3_sts_index;
150 int dev_num, dev_index, reg_index;
151
152 func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
153 func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
154 d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
155 d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
156
157 dev_num = ARRAY_SIZE(dev_map);
158
159 for (dev_index = 0; dev_index < dev_num; dev_index++) {
160 reg_index = dev_index / PMC_REG_BIT_WIDTH;
161 if (reg_index) {
162 func_dis_index = func_dis_2;
163 d3_sts_index = d3_sts_1;
164 } else {
165 func_dis_index = func_dis;
166 d3_sts_index = d3_sts_0;
167 }
168
169 seq_printf(s, "Dev: %-32s\tState: %s [%s]\n",
170 dev_map[dev_index].name,
171 dev_map[dev_index].bit_mask & func_dis_index ?
172 "Disabled" : "Enabled ",
173 dev_map[dev_index].bit_mask & d3_sts_index ?
174 "D3" : "D0");
175 }
176 return 0;
177 }
178
pmc_dev_state_open(struct inode * inode,struct file * file)179 static int pmc_dev_state_open(struct inode *inode, struct file *file)
180 {
181 return single_open(file, pmc_dev_state_show, inode->i_private);
182 }
183
184 static const struct file_operations pmc_dev_state_ops = {
185 .open = pmc_dev_state_open,
186 .read = seq_read,
187 .llseek = seq_lseek,
188 .release = single_release,
189 };
190
pmc_pss_state_show(struct seq_file * s,void * unused)191 static int pmc_pss_state_show(struct seq_file *s, void *unused)
192 {
193 struct pmc_dev *pmc = s->private;
194 u32 pss = pmc_reg_read(pmc, PMC_PSS);
195 int pss_index;
196
197 for (pss_index = 0; pss_index < ARRAY_SIZE(pss_map); pss_index++) {
198 seq_printf(s, "Island: %-32s\tState: %s\n",
199 pss_map[pss_index].name,
200 pss_map[pss_index].bit_mask & pss ? "Off" : "On");
201 }
202 return 0;
203 }
204
pmc_pss_state_open(struct inode * inode,struct file * file)205 static int pmc_pss_state_open(struct inode *inode, struct file *file)
206 {
207 return single_open(file, pmc_pss_state_show, inode->i_private);
208 }
209
210 static const struct file_operations pmc_pss_state_ops = {
211 .open = pmc_pss_state_open,
212 .read = seq_read,
213 .llseek = seq_lseek,
214 .release = single_release,
215 };
216
pmc_sleep_tmr_show(struct seq_file * s,void * unused)217 static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
218 {
219 struct pmc_dev *pmc = s->private;
220 u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
221
222 s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
223 s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
224 s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
225 s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
226 s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
227
228 seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
229 seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
230 seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
231 seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
232 seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
233 return 0;
234 }
235
pmc_sleep_tmr_open(struct inode * inode,struct file * file)236 static int pmc_sleep_tmr_open(struct inode *inode, struct file *file)
237 {
238 return single_open(file, pmc_sleep_tmr_show, inode->i_private);
239 }
240
241 static const struct file_operations pmc_sleep_tmr_ops = {
242 .open = pmc_sleep_tmr_open,
243 .read = seq_read,
244 .llseek = seq_lseek,
245 .release = single_release,
246 };
247
pmc_dbgfs_unregister(struct pmc_dev * pmc)248 static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
249 {
250 debugfs_remove_recursive(pmc->dbgfs_dir);
251 }
252
pmc_dbgfs_register(struct pmc_dev * pmc,struct pci_dev * pdev)253 static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
254 {
255 struct dentry *dir, *f;
256
257 dir = debugfs_create_dir("pmc_atom", NULL);
258 if (!dir)
259 return -ENOMEM;
260
261 pmc->dbgfs_dir = dir;
262
263 f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
264 dir, pmc, &pmc_dev_state_ops);
265 if (!f) {
266 dev_err(&pdev->dev, "dev_state register failed\n");
267 goto err;
268 }
269
270 f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
271 dir, pmc, &pmc_pss_state_ops);
272 if (!f) {
273 dev_err(&pdev->dev, "pss_state register failed\n");
274 goto err;
275 }
276
277 f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
278 dir, pmc, &pmc_sleep_tmr_ops);
279 if (!f) {
280 dev_err(&pdev->dev, "sleep_state register failed\n");
281 goto err;
282 }
283
284 return 0;
285 err:
286 pmc_dbgfs_unregister(pmc);
287 return -ENODEV;
288 }
289 #else
pmc_dbgfs_register(struct pmc_dev * pmc,struct pci_dev * pdev)290 static int pmc_dbgfs_register(struct pmc_dev *pmc, struct pci_dev *pdev)
291 {
292 return 0;
293 }
294 #endif /* CONFIG_DEBUG_FS */
295
pmc_setup_dev(struct pci_dev * pdev)296 static int pmc_setup_dev(struct pci_dev *pdev)
297 {
298 struct pmc_dev *pmc = &pmc_device;
299 int ret;
300
301 /* Obtain ACPI base address */
302 pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
303 acpi_base_addr &= ACPI_BASE_ADDR_MASK;
304
305 /* Install power off function */
306 if (acpi_base_addr != 0 && pm_power_off == NULL)
307 pm_power_off = pmc_power_off;
308
309 pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
310 pmc->base_addr &= PMC_BASE_ADDR_MASK;
311
312 pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
313 if (!pmc->regmap) {
314 dev_err(&pdev->dev, "error: ioremap failed\n");
315 return -ENOMEM;
316 }
317
318 /* PMC hardware registers setup */
319 pmc_hw_reg_setup(pmc);
320
321 ret = pmc_dbgfs_register(pmc, pdev);
322 if (ret) {
323 iounmap(pmc->regmap);
324 }
325
326 return ret;
327 }
328
329 /*
330 * Data for PCI driver interface
331 *
332 * This data only exists for exporting the supported
333 * PCI ids via MODULE_DEVICE_TABLE. We do not actually
334 * register a pci_driver, because lpc_ich will register
335 * a driver on the same PCI id.
336 */
337 static const struct pci_device_id pmc_pci_ids[] = {
338 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_VLV_PMC) },
339 { 0, },
340 };
341
342 MODULE_DEVICE_TABLE(pci, pmc_pci_ids);
343
pmc_atom_init(void)344 static int __init pmc_atom_init(void)
345 {
346 struct pci_dev *pdev = NULL;
347 const struct pci_device_id *ent;
348
349 /* We look for our device - PCU PMC
350 * we assume that there is max. one device.
351 *
352 * We can't use plain pci_driver mechanism,
353 * as the device is really a multiple function device,
354 * main driver that binds to the pci_device is lpc_ich
355 * and have to find & bind to the device this way.
356 */
357 for_each_pci_dev(pdev) {
358 ent = pci_match_id(pmc_pci_ids, pdev);
359 if (ent)
360 return pmc_setup_dev(pdev);
361 }
362 /* Device not found. */
363 return -ENODEV;
364 }
365
366 module_init(pmc_atom_init);
367 /* no module_exit, this driver shouldn't be unloaded */
368
369 MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
370 MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
371 MODULE_LICENSE("GPL v2");
372