1#ifndef __SVM_H 2#define __SVM_H 3 4#include <uapi/asm/svm.h> 5 6 7enum { 8 INTERCEPT_INTR, 9 INTERCEPT_NMI, 10 INTERCEPT_SMI, 11 INTERCEPT_INIT, 12 INTERCEPT_VINTR, 13 INTERCEPT_SELECTIVE_CR0, 14 INTERCEPT_STORE_IDTR, 15 INTERCEPT_STORE_GDTR, 16 INTERCEPT_STORE_LDTR, 17 INTERCEPT_STORE_TR, 18 INTERCEPT_LOAD_IDTR, 19 INTERCEPT_LOAD_GDTR, 20 INTERCEPT_LOAD_LDTR, 21 INTERCEPT_LOAD_TR, 22 INTERCEPT_RDTSC, 23 INTERCEPT_RDPMC, 24 INTERCEPT_PUSHF, 25 INTERCEPT_POPF, 26 INTERCEPT_CPUID, 27 INTERCEPT_RSM, 28 INTERCEPT_IRET, 29 INTERCEPT_INTn, 30 INTERCEPT_INVD, 31 INTERCEPT_PAUSE, 32 INTERCEPT_HLT, 33 INTERCEPT_INVLPG, 34 INTERCEPT_INVLPGA, 35 INTERCEPT_IOIO_PROT, 36 INTERCEPT_MSR_PROT, 37 INTERCEPT_TASK_SWITCH, 38 INTERCEPT_FERR_FREEZE, 39 INTERCEPT_SHUTDOWN, 40 INTERCEPT_VMRUN, 41 INTERCEPT_VMMCALL, 42 INTERCEPT_VMLOAD, 43 INTERCEPT_VMSAVE, 44 INTERCEPT_STGI, 45 INTERCEPT_CLGI, 46 INTERCEPT_SKINIT, 47 INTERCEPT_RDTSCP, 48 INTERCEPT_ICEBP, 49 INTERCEPT_WBINVD, 50 INTERCEPT_MONITOR, 51 INTERCEPT_MWAIT, 52 INTERCEPT_MWAIT_COND, 53 INTERCEPT_XSETBV, 54}; 55 56 57struct __attribute__ ((__packed__)) vmcb_control_area { 58 u32 intercept_cr; 59 u32 intercept_dr; 60 u32 intercept_exceptions; 61 u64 intercept; 62 u8 reserved_1[42]; 63 u16 pause_filter_count; 64 u64 iopm_base_pa; 65 u64 msrpm_base_pa; 66 u64 tsc_offset; 67 u32 asid; 68 u8 tlb_ctl; 69 u8 reserved_2[3]; 70 u32 int_ctl; 71 u32 int_vector; 72 u32 int_state; 73 u8 reserved_3[4]; 74 u32 exit_code; 75 u32 exit_code_hi; 76 u64 exit_info_1; 77 u64 exit_info_2; 78 u32 exit_int_info; 79 u32 exit_int_info_err; 80 u64 nested_ctl; 81 u8 reserved_4[16]; 82 u32 event_inj; 83 u32 event_inj_err; 84 u64 nested_cr3; 85 u64 lbr_ctl; 86 u32 clean; 87 u32 reserved_5; 88 u64 next_rip; 89 u8 insn_len; 90 u8 insn_bytes[15]; 91 u8 reserved_6[800]; 92}; 93 94 95#define TLB_CONTROL_DO_NOTHING 0 96#define TLB_CONTROL_FLUSH_ALL_ASID 1 97#define TLB_CONTROL_FLUSH_ASID 3 98#define TLB_CONTROL_FLUSH_ASID_LOCAL 7 99 100#define V_TPR_MASK 0x0f 101 102#define V_IRQ_SHIFT 8 103#define V_IRQ_MASK (1 << V_IRQ_SHIFT) 104 105#define V_INTR_PRIO_SHIFT 16 106#define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT) 107 108#define V_IGN_TPR_SHIFT 20 109#define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT) 110 111#define V_INTR_MASKING_SHIFT 24 112#define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT) 113 114#define SVM_INTERRUPT_SHADOW_MASK 1 115 116#define SVM_IOIO_STR_SHIFT 2 117#define SVM_IOIO_REP_SHIFT 3 118#define SVM_IOIO_SIZE_SHIFT 4 119#define SVM_IOIO_ASIZE_SHIFT 7 120 121#define SVM_IOIO_TYPE_MASK 1 122#define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT) 123#define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT) 124#define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT) 125#define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT) 126 127#define SVM_VM_CR_VALID_MASK 0x001fULL 128#define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL 129#define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL 130 131struct __attribute__ ((__packed__)) vmcb_seg { 132 u16 selector; 133 u16 attrib; 134 u32 limit; 135 u64 base; 136}; 137 138struct __attribute__ ((__packed__)) vmcb_save_area { 139 struct vmcb_seg es; 140 struct vmcb_seg cs; 141 struct vmcb_seg ss; 142 struct vmcb_seg ds; 143 struct vmcb_seg fs; 144 struct vmcb_seg gs; 145 struct vmcb_seg gdtr; 146 struct vmcb_seg ldtr; 147 struct vmcb_seg idtr; 148 struct vmcb_seg tr; 149 u8 reserved_1[43]; 150 u8 cpl; 151 u8 reserved_2[4]; 152 u64 efer; 153 u8 reserved_3[112]; 154 u64 cr4; 155 u64 cr3; 156 u64 cr0; 157 u64 dr7; 158 u64 dr6; 159 u64 rflags; 160 u64 rip; 161 u8 reserved_4[88]; 162 u64 rsp; 163 u8 reserved_5[24]; 164 u64 rax; 165 u64 star; 166 u64 lstar; 167 u64 cstar; 168 u64 sfmask; 169 u64 kernel_gs_base; 170 u64 sysenter_cs; 171 u64 sysenter_esp; 172 u64 sysenter_eip; 173 u64 cr2; 174 u8 reserved_6[32]; 175 u64 g_pat; 176 u64 dbgctl; 177 u64 br_from; 178 u64 br_to; 179 u64 last_excp_from; 180 u64 last_excp_to; 181}; 182 183struct __attribute__ ((__packed__)) vmcb { 184 struct vmcb_control_area control; 185 struct vmcb_save_area save; 186}; 187 188#define SVM_CPUID_FEATURE_SHIFT 2 189#define SVM_CPUID_FUNC 0x8000000a 190 191#define SVM_VM_CR_SVM_DISABLE 4 192 193#define SVM_SELECTOR_S_SHIFT 4 194#define SVM_SELECTOR_DPL_SHIFT 5 195#define SVM_SELECTOR_P_SHIFT 7 196#define SVM_SELECTOR_AVL_SHIFT 8 197#define SVM_SELECTOR_L_SHIFT 9 198#define SVM_SELECTOR_DB_SHIFT 10 199#define SVM_SELECTOR_G_SHIFT 11 200 201#define SVM_SELECTOR_TYPE_MASK (0xf) 202#define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT) 203#define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT) 204#define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT) 205#define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT) 206#define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT) 207#define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT) 208#define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT) 209 210#define SVM_SELECTOR_WRITE_MASK (1 << 1) 211#define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK 212#define SVM_SELECTOR_CODE_MASK (1 << 3) 213 214#define INTERCEPT_CR0_READ 0 215#define INTERCEPT_CR3_READ 3 216#define INTERCEPT_CR4_READ 4 217#define INTERCEPT_CR8_READ 8 218#define INTERCEPT_CR0_WRITE (16 + 0) 219#define INTERCEPT_CR3_WRITE (16 + 3) 220#define INTERCEPT_CR4_WRITE (16 + 4) 221#define INTERCEPT_CR8_WRITE (16 + 8) 222 223#define INTERCEPT_DR0_READ 0 224#define INTERCEPT_DR1_READ 1 225#define INTERCEPT_DR2_READ 2 226#define INTERCEPT_DR3_READ 3 227#define INTERCEPT_DR4_READ 4 228#define INTERCEPT_DR5_READ 5 229#define INTERCEPT_DR6_READ 6 230#define INTERCEPT_DR7_READ 7 231#define INTERCEPT_DR0_WRITE (16 + 0) 232#define INTERCEPT_DR1_WRITE (16 + 1) 233#define INTERCEPT_DR2_WRITE (16 + 2) 234#define INTERCEPT_DR3_WRITE (16 + 3) 235#define INTERCEPT_DR4_WRITE (16 + 4) 236#define INTERCEPT_DR5_WRITE (16 + 5) 237#define INTERCEPT_DR6_WRITE (16 + 6) 238#define INTERCEPT_DR7_WRITE (16 + 7) 239 240#define SVM_EVTINJ_VEC_MASK 0xff 241 242#define SVM_EVTINJ_TYPE_SHIFT 8 243#define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT) 244 245#define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT) 246#define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT) 247#define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT) 248#define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT) 249 250#define SVM_EVTINJ_VALID (1 << 31) 251#define SVM_EVTINJ_VALID_ERR (1 << 11) 252 253#define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK 254#define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK 255 256#define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR 257#define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI 258#define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT 259#define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT 260 261#define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID 262#define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR 263 264#define SVM_EXITINFOSHIFT_TS_REASON_IRET 36 265#define SVM_EXITINFOSHIFT_TS_REASON_JMP 38 266#define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44 267 268#define SVM_EXITINFO_REG_MASK 0x0F 269 270#define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP) 271 272#define SVM_VMLOAD ".byte 0x0f, 0x01, 0xda" 273#define SVM_VMRUN ".byte 0x0f, 0x01, 0xd8" 274#define SVM_VMSAVE ".byte 0x0f, 0x01, 0xdb" 275#define SVM_CLGI ".byte 0x0f, 0x01, 0xdd" 276#define SVM_STGI ".byte 0x0f, 0x01, 0xdc" 277#define SVM_INVLPGA ".byte 0x0f, 0x01, 0xdf" 278 279#endif 280