1/*
2 * Copyright 2013 Tilera Corporation. All Rights Reserved.
3 *
4 *   This program is free software; you can redistribute it and/or
5 *   modify it under the terms of the GNU General Public License
6 *   as published by the Free Software Foundation, version 2.
7 *
8 *   This program is distributed in the hope that it will be useful, but
9 *   WITHOUT ANY WARRANTY; without even the implied warranty of
10 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 *   NON INFRINGEMENT.  See the GNU General Public License for
12 *   more details.
13 */
14
15/* Machine-generated file; do not edit. */
16
17#ifndef __ARCH_UART_H__
18#define __ARCH_UART_H__
19
20#include <arch/abi.h>
21#include <arch/uart_def.h>
22
23#ifndef __ASSEMBLER__
24
25/* Divisor. */
26
27__extension__
28typedef union
29{
30  struct
31  {
32#ifndef __BIG_ENDIAN__
33    /*
34     * Baud Rate Divisor.  Desired_baud_rate = REF_CLK frequency / (baud *
35     * 16).
36     *                       Note: REF_CLK is always 125 MHz, the default
37     * divisor = 68, baud rate = 125M/(68*16) = 115200 baud.
38     */
39    uint_reg_t divisor    : 12;
40    /* Reserved. */
41    uint_reg_t __reserved : 52;
42#else   /* __BIG_ENDIAN__ */
43    uint_reg_t __reserved : 52;
44    uint_reg_t divisor    : 12;
45#endif
46  };
47
48  uint_reg_t word;
49} UART_DIVISOR_t;
50
51/* FIFO Count. */
52
53__extension__
54typedef union
55{
56  struct
57  {
58#ifndef __BIG_ENDIAN__
59    /*
60     * n: n active entries in the receive FIFO (max is 2**8). Each entry has
61     * 8 bits.
62     * 0: no active entry in the receive FIFO (that is empty).
63     */
64    uint_reg_t rfifo_count  : 9;
65    /* Reserved. */
66    uint_reg_t __reserved_0 : 7;
67    /*
68     * n: n active entries in the transmit FIFO (max is 2**8). Each entry has
69     * 8 bits.
70     * 0: no active entry in the transmit FIFO (that is empty).
71     */
72    uint_reg_t tfifo_count  : 9;
73    /* Reserved. */
74    uint_reg_t __reserved_1 : 7;
75    /*
76     * n: n active entries in the write FIFO (max is 2**2). Each entry has 8
77     * bits.
78     * 0: no active entry in the write FIFO (that is empty).
79     */
80    uint_reg_t wfifo_count  : 3;
81    /* Reserved. */
82    uint_reg_t __reserved_2 : 29;
83#else   /* __BIG_ENDIAN__ */
84    uint_reg_t __reserved_2 : 29;
85    uint_reg_t wfifo_count  : 3;
86    uint_reg_t __reserved_1 : 7;
87    uint_reg_t tfifo_count  : 9;
88    uint_reg_t __reserved_0 : 7;
89    uint_reg_t rfifo_count  : 9;
90#endif
91  };
92
93  uint_reg_t word;
94} UART_FIFO_COUNT_t;
95
96/* FLAG. */
97
98__extension__
99typedef union
100{
101  struct
102  {
103#ifndef __BIG_ENDIAN__
104    /* Reserved. */
105    uint_reg_t __reserved_0 : 1;
106    /* 1: receive FIFO is empty */
107    uint_reg_t rfifo_empty  : 1;
108    /* 1: write FIFO is empty. */
109    uint_reg_t wfifo_empty  : 1;
110    /* 1: transmit FIFO is empty. */
111    uint_reg_t tfifo_empty  : 1;
112    /* 1: receive FIFO is full. */
113    uint_reg_t rfifo_full   : 1;
114    /* 1: write FIFO is full. */
115    uint_reg_t wfifo_full   : 1;
116    /* 1: transmit FIFO is full. */
117    uint_reg_t tfifo_full   : 1;
118    /* Reserved. */
119    uint_reg_t __reserved_1 : 57;
120#else   /* __BIG_ENDIAN__ */
121    uint_reg_t __reserved_1 : 57;
122    uint_reg_t tfifo_full   : 1;
123    uint_reg_t wfifo_full   : 1;
124    uint_reg_t rfifo_full   : 1;
125    uint_reg_t tfifo_empty  : 1;
126    uint_reg_t wfifo_empty  : 1;
127    uint_reg_t rfifo_empty  : 1;
128    uint_reg_t __reserved_0 : 1;
129#endif
130  };
131
132  uint_reg_t word;
133} UART_FLAG_t;
134
135/*
136 * Interrupt Vector Mask.
137 * Each bit in this register corresponds to a specific interrupt. When set,
138 * the associated interrupt will not be dispatched.
139 */
140
141__extension__
142typedef union
143{
144  struct
145  {
146#ifndef __BIG_ENDIAN__
147    /* Read data FIFO read and no data available */
148    uint_reg_t rdat_err       : 1;
149    /* Write FIFO was written but it was full */
150    uint_reg_t wdat_err       : 1;
151    /* Stop bit not found when current data was received */
152    uint_reg_t frame_err      : 1;
153    /* Parity error was detected when current data was received */
154    uint_reg_t parity_err     : 1;
155    /* Data was received but the receive FIFO was full */
156    uint_reg_t rfifo_overflow : 1;
157    /*
158     * An almost full event is reached when data is to be written to the
159     * receive FIFO, and the receive FIFO has more than or equal to
160     * BUFFER_THRESHOLD.RFIFO_AFULL bytes.
161     */
162    uint_reg_t rfifo_afull    : 1;
163    /* Reserved. */
164    uint_reg_t __reserved_0   : 1;
165    /* An entry in the transmit FIFO was popped */
166    uint_reg_t tfifo_re       : 1;
167    /* An entry has been pushed into the receive FIFO */
168    uint_reg_t rfifo_we       : 1;
169    /* An entry of the write FIFO has been popped */
170    uint_reg_t wfifo_re       : 1;
171    /* Rshim read receive FIFO in protocol mode */
172    uint_reg_t rfifo_err      : 1;
173    /*
174     * An almost empty event is reached when data is to be read from the
175     * transmit FIFO, and the transmit FIFO has less than or equal to
176     * BUFFER_THRESHOLD.TFIFO_AEMPTY bytes.
177     */
178    uint_reg_t tfifo_aempty   : 1;
179    /* Reserved. */
180    uint_reg_t __reserved_1   : 52;
181#else   /* __BIG_ENDIAN__ */
182    uint_reg_t __reserved_1   : 52;
183    uint_reg_t tfifo_aempty   : 1;
184    uint_reg_t rfifo_err      : 1;
185    uint_reg_t wfifo_re       : 1;
186    uint_reg_t rfifo_we       : 1;
187    uint_reg_t tfifo_re       : 1;
188    uint_reg_t __reserved_0   : 1;
189    uint_reg_t rfifo_afull    : 1;
190    uint_reg_t rfifo_overflow : 1;
191    uint_reg_t parity_err     : 1;
192    uint_reg_t frame_err      : 1;
193    uint_reg_t wdat_err       : 1;
194    uint_reg_t rdat_err       : 1;
195#endif
196  };
197
198  uint_reg_t word;
199} UART_INTERRUPT_MASK_t;
200
201/*
202 * Interrupt vector, write-one-to-clear.
203 * Each bit in this register corresponds to a specific interrupt. Hardware
204 * sets the bit when the associated condition has occurred. Writing a 1
205 * clears the status bit.
206 */
207
208__extension__
209typedef union
210{
211  struct
212  {
213#ifndef __BIG_ENDIAN__
214    /* Read data FIFO read and no data available */
215    uint_reg_t rdat_err       : 1;
216    /* Write FIFO was written but it was full */
217    uint_reg_t wdat_err       : 1;
218    /* Stop bit not found when current data was received */
219    uint_reg_t frame_err      : 1;
220    /* Parity error was detected when current data was received */
221    uint_reg_t parity_err     : 1;
222    /* Data was received but the receive FIFO was full */
223    uint_reg_t rfifo_overflow : 1;
224    /*
225     * Data was received and the receive FIFO is now almost full (more than
226     * BUFFER_THRESHOLD.RFIFO_AFULL bytes in it)
227     */
228    uint_reg_t rfifo_afull    : 1;
229    /* Reserved. */
230    uint_reg_t __reserved_0   : 1;
231    /* An entry in the transmit FIFO was popped */
232    uint_reg_t tfifo_re       : 1;
233    /* An entry has been pushed into the receive FIFO */
234    uint_reg_t rfifo_we       : 1;
235    /* An entry of the write FIFO has been popped */
236    uint_reg_t wfifo_re       : 1;
237    /* Rshim read receive FIFO in protocol mode */
238    uint_reg_t rfifo_err      : 1;
239    /*
240     * Data was read from the transmit FIFO and now it is almost empty (less
241     * than or equal to BUFFER_THRESHOLD.TFIFO_AEMPTY bytes in it).
242     */
243    uint_reg_t tfifo_aempty   : 1;
244    /* Reserved. */
245    uint_reg_t __reserved_1   : 52;
246#else   /* __BIG_ENDIAN__ */
247    uint_reg_t __reserved_1   : 52;
248    uint_reg_t tfifo_aempty   : 1;
249    uint_reg_t rfifo_err      : 1;
250    uint_reg_t wfifo_re       : 1;
251    uint_reg_t rfifo_we       : 1;
252    uint_reg_t tfifo_re       : 1;
253    uint_reg_t __reserved_0   : 1;
254    uint_reg_t rfifo_afull    : 1;
255    uint_reg_t rfifo_overflow : 1;
256    uint_reg_t parity_err     : 1;
257    uint_reg_t frame_err      : 1;
258    uint_reg_t wdat_err       : 1;
259    uint_reg_t rdat_err       : 1;
260#endif
261  };
262
263  uint_reg_t word;
264} UART_INTERRUPT_STATUS_t;
265
266/* Type. */
267
268__extension__
269typedef union
270{
271  struct
272  {
273#ifndef __BIG_ENDIAN__
274    /* Number of stop bits, rx and tx */
275    uint_reg_t sbits        : 1;
276    /* Reserved. */
277    uint_reg_t __reserved_0 : 1;
278    /* Data word size, rx and tx */
279    uint_reg_t dbits        : 1;
280    /* Reserved. */
281    uint_reg_t __reserved_1 : 1;
282    /* Parity selection, rx and tx */
283    uint_reg_t ptype        : 3;
284    /* Reserved. */
285    uint_reg_t __reserved_2 : 57;
286#else   /* __BIG_ENDIAN__ */
287    uint_reg_t __reserved_2 : 57;
288    uint_reg_t ptype        : 3;
289    uint_reg_t __reserved_1 : 1;
290    uint_reg_t dbits        : 1;
291    uint_reg_t __reserved_0 : 1;
292    uint_reg_t sbits        : 1;
293#endif
294  };
295
296  uint_reg_t word;
297} UART_TYPE_t;
298#endif /* !defined(__ASSEMBLER__) */
299
300#endif /* !defined(__ARCH_UART_H__) */
301