1/* 2 * SH7201 setup 3 * 4 * Copyright (C) 2008 Peter Griffin pgriffin@mpc-data.co.uk 5 * Copyright (C) 2009 Paul Mundt 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11#include <linux/platform_device.h> 12#include <linux/init.h> 13#include <linux/serial.h> 14#include <linux/serial_sci.h> 15#include <linux/sh_timer.h> 16#include <linux/io.h> 17 18enum { 19 UNUSED = 0, 20 21 /* interrupt sources */ 22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, 23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7, 24 25 ADC_ADI, 26 27 MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU, 28 MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V, 29 30 RTC, WDT, 31 32 IIC30, IIC31, IIC32, 33 34 DMAC0_DMINT0, DMAC1_DMINT1, 35 DMAC2_DMINT2, DMAC3_DMINT3, 36 37 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7, 38 39 DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6, 40 DMAC7_DMINT7, 41 42 RCAN0, RCAN1, 43 44 SSI0_SSII, SSI1_SSII, 45 46 TMR0, TMR1, 47 48 /* interrupt groups */ 49 PINT, 50}; 51 52static struct intc_vect vectors[] __initdata = { 53 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65), 54 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67), 55 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69), 56 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71), 57 58 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81), 59 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83), 60 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85), 61 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87), 62 63 INTC_IRQ(ADC_ADI, 92), 64 65 INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109), 66 INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111), 67 68 INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113), 69 INTC_IRQ(MTU20_VEF, 114), 70 71 INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117), 72 INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121), 73 74 INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125), 75 INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129), 76 77 INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133), 78 INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135), 79 80 INTC_IRQ(MTU2_TCI3V, 136), 81 82 INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141), 83 INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143), 84 85 INTC_IRQ(MTU2_TCI4V, 144), 86 87 INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149), 88 INTC_IRQ(MTU25_UVW, 150), 89 90 INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153), 91 INTC_IRQ(RTC, 154), 92 93 INTC_IRQ(WDT, 156), 94 95 INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158), 96 INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160), 97 INTC_IRQ(IIC30, 161), 98 99 INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165), 100 INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167), 101 INTC_IRQ(IIC31, 168), 102 103 INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171), 104 INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173), 105 INTC_IRQ(IIC32, 174), 106 107 INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177), 108 INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179), 109 110 INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181), 111 INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183), 112 INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185), 113 INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187), 114 INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189), 115 INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191), 116 INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193), 117 INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195), 118 INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197), 119 INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199), 120 INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201), 121 INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203), 122 INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205), 123 INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207), 124 INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209), 125 INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211), 126 127 INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216), 128 INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218), 129 INTC_IRQ(DMAC7_DMINT7, 219), 130 131 INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229), 132 INTC_IRQ(RCAN0, 230), 133 INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232), 134 135 INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235), 136 INTC_IRQ(RCAN1, 236), 137 INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238), 138 139 INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245), 140 141 INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247), 142 INTC_IRQ(TMR0, 248), 143 144 INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253), 145 INTC_IRQ(TMR1, 254), 146}; 147 148static struct intc_group groups[] __initdata = { 149 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3, 150 PINT4, PINT5, PINT6, PINT7), 151}; 152 153static struct intc_prio_reg prio_registers[] __initdata = { 154 { 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, 155 { 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } }, 156 { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } }, 157 { 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } }, 158 { 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU, MTU23_ABCD } }, 159 { 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } }, 160 161 { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } }, 162 { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } }, 163 { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } }, 164 { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } }, 165 { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4 } }, 166 { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } }, 167 { 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } }, 168 { 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } }, 169}; 170 171static struct intc_mask_reg mask_registers[] __initdata = { 172 { 0xfffe9408, 0, 16, /* PINTER */ 173 { 0, 0, 0, 0, 0, 0, 0, 0, 174 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } }, 175}; 176 177static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, 178 mask_registers, prio_registers, NULL); 179 180static struct plat_sci_port scif0_platform_data = { 181 .flags = UPF_BOOT_AUTOCONF, 182 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 183 .type = PORT_SCIF, 184}; 185 186static struct resource scif0_resources[] = { 187 DEFINE_RES_MEM(0xfffe8000, 0x100), 188 DEFINE_RES_IRQ(180), 189}; 190 191static struct platform_device scif0_device = { 192 .name = "sh-sci", 193 .id = 0, 194 .resource = scif0_resources, 195 .num_resources = ARRAY_SIZE(scif0_resources), 196 .dev = { 197 .platform_data = &scif0_platform_data, 198 }, 199}; 200 201static struct plat_sci_port scif1_platform_data = { 202 .flags = UPF_BOOT_AUTOCONF, 203 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 204 .type = PORT_SCIF, 205}; 206 207static struct resource scif1_resources[] = { 208 DEFINE_RES_MEM(0xfffe8800, 0x100), 209 DEFINE_RES_IRQ(184), 210}; 211 212static struct platform_device scif1_device = { 213 .name = "sh-sci", 214 .id = 1, 215 .resource = scif1_resources, 216 .num_resources = ARRAY_SIZE(scif1_resources), 217 .dev = { 218 .platform_data = &scif1_platform_data, 219 }, 220}; 221 222static struct plat_sci_port scif2_platform_data = { 223 .flags = UPF_BOOT_AUTOCONF, 224 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 225 .type = PORT_SCIF, 226}; 227 228static struct resource scif2_resources[] = { 229 DEFINE_RES_MEM(0xfffe9000, 0x100), 230 DEFINE_RES_IRQ(188), 231}; 232 233static struct platform_device scif2_device = { 234 .name = "sh-sci", 235 .id = 2, 236 .resource = scif2_resources, 237 .num_resources = ARRAY_SIZE(scif2_resources), 238 .dev = { 239 .platform_data = &scif2_platform_data, 240 }, 241}; 242 243static struct plat_sci_port scif3_platform_data = { 244 .flags = UPF_BOOT_AUTOCONF, 245 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 246 .type = PORT_SCIF, 247}; 248 249static struct resource scif3_resources[] = { 250 DEFINE_RES_MEM(0xfffe9800, 0x100), 251 DEFINE_RES_IRQ(192), 252}; 253 254static struct platform_device scif3_device = { 255 .name = "sh-sci", 256 .id = 3, 257 .resource = scif3_resources, 258 .num_resources = ARRAY_SIZE(scif3_resources), 259 .dev = { 260 .platform_data = &scif3_platform_data, 261 }, 262}; 263 264static struct plat_sci_port scif4_platform_data = { 265 .flags = UPF_BOOT_AUTOCONF, 266 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 267 .type = PORT_SCIF, 268}; 269 270static struct resource scif4_resources[] = { 271 DEFINE_RES_MEM(0xfffea000, 0x100), 272 DEFINE_RES_IRQ(196), 273}; 274 275static struct platform_device scif4_device = { 276 .name = "sh-sci", 277 .id = 4, 278 .resource = scif4_resources, 279 .num_resources = ARRAY_SIZE(scif4_resources), 280 .dev = { 281 .platform_data = &scif4_platform_data, 282 }, 283}; 284 285static struct plat_sci_port scif5_platform_data = { 286 .flags = UPF_BOOT_AUTOCONF, 287 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 288 .type = PORT_SCIF, 289}; 290 291static struct resource scif5_resources[] = { 292 DEFINE_RES_MEM(0xfffea800, 0x100), 293 DEFINE_RES_IRQ(200), 294}; 295 296static struct platform_device scif5_device = { 297 .name = "sh-sci", 298 .id = 5, 299 .resource = scif5_resources, 300 .num_resources = ARRAY_SIZE(scif5_resources), 301 .dev = { 302 .platform_data = &scif5_platform_data, 303 }, 304}; 305 306static struct plat_sci_port scif6_platform_data = { 307 .flags = UPF_BOOT_AUTOCONF, 308 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 309 .type = PORT_SCIF, 310}; 311 312static struct resource scif6_resources[] = { 313 DEFINE_RES_MEM(0xfffeb000, 0x100), 314 DEFINE_RES_IRQ(204), 315}; 316 317static struct platform_device scif6_device = { 318 .name = "sh-sci", 319 .id = 6, 320 .resource = scif6_resources, 321 .num_resources = ARRAY_SIZE(scif6_resources), 322 .dev = { 323 .platform_data = &scif6_platform_data, 324 }, 325}; 326 327static struct plat_sci_port scif7_platform_data = { 328 .flags = UPF_BOOT_AUTOCONF, 329 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 330 .type = PORT_SCIF, 331}; 332 333static struct resource scif7_resources[] = { 334 DEFINE_RES_MEM(0xfffeb800, 0x100), 335 DEFINE_RES_IRQ(208), 336}; 337 338static struct platform_device scif7_device = { 339 .name = "sh-sci", 340 .id = 7, 341 .resource = scif7_resources, 342 .num_resources = ARRAY_SIZE(scif7_resources), 343 .dev = { 344 .platform_data = &scif7_platform_data, 345 }, 346}; 347 348static struct resource rtc_resources[] = { 349 [0] = { 350 .start = 0xffff0800, 351 .end = 0xffff2000 + 0x58 - 1, 352 .flags = IORESOURCE_IO, 353 }, 354 [1] = { 355 /* Shared Period/Carry/Alarm IRQ */ 356 .start = 152, 357 .flags = IORESOURCE_IRQ, 358 }, 359}; 360 361static struct platform_device rtc_device = { 362 .name = "sh-rtc", 363 .id = -1, 364 .num_resources = ARRAY_SIZE(rtc_resources), 365 .resource = rtc_resources, 366}; 367 368static struct resource mtu2_resources[] = { 369 DEFINE_RES_MEM(0xfffe4000, 0x400), 370 DEFINE_RES_IRQ_NAMED(108, "tgi0a"), 371 DEFINE_RES_IRQ_NAMED(116, "tgi1a"), 372 DEFINE_RES_IRQ_NAMED(124, "tgi1b"), 373}; 374 375static struct platform_device mtu2_device = { 376 .name = "sh-mtu2", 377 .id = -1, 378 .resource = mtu2_resources, 379 .num_resources = ARRAY_SIZE(mtu2_resources), 380}; 381 382static struct platform_device *sh7201_devices[] __initdata = { 383 &scif0_device, 384 &scif1_device, 385 &scif2_device, 386 &scif3_device, 387 &scif4_device, 388 &scif5_device, 389 &scif6_device, 390 &scif7_device, 391 &rtc_device, 392 &mtu2_device, 393}; 394 395static int __init sh7201_devices_setup(void) 396{ 397 return platform_add_devices(sh7201_devices, 398 ARRAY_SIZE(sh7201_devices)); 399} 400arch_initcall(sh7201_devices_setup); 401 402void __init plat_irq_setup(void) 403{ 404 register_intc_controller(&intc_desc); 405} 406 407static struct platform_device *sh7201_early_devices[] __initdata = { 408 &scif0_device, 409 &scif1_device, 410 &scif2_device, 411 &scif3_device, 412 &scif4_device, 413 &scif5_device, 414 &scif6_device, 415 &scif7_device, 416 &mtu2_device, 417}; 418 419#define STBCR3 0xfffe0408 420 421void __init plat_early_device_setup(void) 422{ 423 /* enable MTU2 clock */ 424 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3); 425 426 early_platform_add_devices(sh7201_early_devices, 427 ARRAY_SIZE(sh7201_early_devices)); 428} 429