1/* 2 * BPF Jit compiler for s390. 3 * 4 * Minimum build requirements: 5 * 6 * - HAVE_MARCH_Z196_FEATURES: laal, laalg 7 * - HAVE_MARCH_Z10_FEATURES: msfi, cgrj, clgrj 8 * - HAVE_MARCH_Z9_109_FEATURES: alfi, llilf, clfi, oilf, nilf 9 * - PACK_STACK 10 * - 64BIT 11 * 12 * Copyright IBM Corp. 2012,2015 13 * 14 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com> 15 * Michael Holzheu <holzheu@linux.vnet.ibm.com> 16 */ 17 18#define KMSG_COMPONENT "bpf_jit" 19#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt 20 21#include <linux/netdevice.h> 22#include <linux/filter.h> 23#include <linux/init.h> 24#include <asm/cacheflush.h> 25#include <asm/dis.h> 26#include "bpf_jit.h" 27 28int bpf_jit_enable __read_mostly; 29 30struct bpf_jit { 31 u32 seen; /* Flags to remember seen eBPF instructions */ 32 u32 seen_reg[16]; /* Array to remember which registers are used */ 33 u32 *addrs; /* Array with relative instruction addresses */ 34 u8 *prg_buf; /* Start of program */ 35 int size; /* Size of program and literal pool */ 36 int size_prg; /* Size of program */ 37 int prg; /* Current position in program */ 38 int lit_start; /* Start of literal pool */ 39 int lit; /* Current position in literal pool */ 40 int base_ip; /* Base address for literal pool */ 41 int ret0_ip; /* Address of return 0 */ 42 int exit_ip; /* Address of exit */ 43}; 44 45#define BPF_SIZE_MAX 4096 /* Max size for program */ 46 47#define SEEN_SKB 1 /* skb access */ 48#define SEEN_MEM 2 /* use mem[] for temporary storage */ 49#define SEEN_RET0 4 /* ret0_ip points to a valid return 0 */ 50#define SEEN_LITERAL 8 /* code uses literals */ 51#define SEEN_FUNC 16 /* calls C functions */ 52#define SEEN_STACK (SEEN_FUNC | SEEN_MEM | SEEN_SKB) 53 54/* 55 * s390 registers 56 */ 57#define REG_W0 (__MAX_BPF_REG+0) /* Work register 1 (even) */ 58#define REG_W1 (__MAX_BPF_REG+1) /* Work register 2 (odd) */ 59#define REG_SKB_DATA (__MAX_BPF_REG+2) /* SKB data register */ 60#define REG_L (__MAX_BPF_REG+3) /* Literal pool register */ 61#define REG_15 (__MAX_BPF_REG+4) /* Register 15 */ 62#define REG_0 REG_W0 /* Register 0 */ 63#define REG_2 BPF_REG_1 /* Register 2 */ 64#define REG_14 BPF_REG_0 /* Register 14 */ 65 66/* 67 * Mapping of BPF registers to s390 registers 68 */ 69static const int reg2hex[] = { 70 /* Return code */ 71 [BPF_REG_0] = 14, 72 /* Function parameters */ 73 [BPF_REG_1] = 2, 74 [BPF_REG_2] = 3, 75 [BPF_REG_3] = 4, 76 [BPF_REG_4] = 5, 77 [BPF_REG_5] = 6, 78 /* Call saved registers */ 79 [BPF_REG_6] = 7, 80 [BPF_REG_7] = 8, 81 [BPF_REG_8] = 9, 82 [BPF_REG_9] = 10, 83 /* BPF stack pointer */ 84 [BPF_REG_FP] = 13, 85 /* SKB data pointer */ 86 [REG_SKB_DATA] = 12, 87 /* Work registers for s390x backend */ 88 [REG_W0] = 0, 89 [REG_W1] = 1, 90 [REG_L] = 11, 91 [REG_15] = 15, 92}; 93 94static inline u32 reg(u32 dst_reg, u32 src_reg) 95{ 96 return reg2hex[dst_reg] << 4 | reg2hex[src_reg]; 97} 98 99static inline u32 reg_high(u32 reg) 100{ 101 return reg2hex[reg] << 4; 102} 103 104static inline void reg_set_seen(struct bpf_jit *jit, u32 b1) 105{ 106 u32 r1 = reg2hex[b1]; 107 108 if (!jit->seen_reg[r1] && r1 >= 6 && r1 <= 15) 109 jit->seen_reg[r1] = 1; 110} 111 112#define REG_SET_SEEN(b1) \ 113({ \ 114 reg_set_seen(jit, b1); \ 115}) 116 117#define REG_SEEN(b1) jit->seen_reg[reg2hex[(b1)]] 118 119/* 120 * EMIT macros for code generation 121 */ 122 123#define _EMIT2(op) \ 124({ \ 125 if (jit->prg_buf) \ 126 *(u16 *) (jit->prg_buf + jit->prg) = op; \ 127 jit->prg += 2; \ 128}) 129 130#define EMIT2(op, b1, b2) \ 131({ \ 132 _EMIT2(op | reg(b1, b2)); \ 133 REG_SET_SEEN(b1); \ 134 REG_SET_SEEN(b2); \ 135}) 136 137#define _EMIT4(op) \ 138({ \ 139 if (jit->prg_buf) \ 140 *(u32 *) (jit->prg_buf + jit->prg) = op; \ 141 jit->prg += 4; \ 142}) 143 144#define EMIT4(op, b1, b2) \ 145({ \ 146 _EMIT4(op | reg(b1, b2)); \ 147 REG_SET_SEEN(b1); \ 148 REG_SET_SEEN(b2); \ 149}) 150 151#define EMIT4_RRF(op, b1, b2, b3) \ 152({ \ 153 _EMIT4(op | reg_high(b3) << 8 | reg(b1, b2)); \ 154 REG_SET_SEEN(b1); \ 155 REG_SET_SEEN(b2); \ 156 REG_SET_SEEN(b3); \ 157}) 158 159#define _EMIT4_DISP(op, disp) \ 160({ \ 161 unsigned int __disp = (disp) & 0xfff; \ 162 _EMIT4(op | __disp); \ 163}) 164 165#define EMIT4_DISP(op, b1, b2, disp) \ 166({ \ 167 _EMIT4_DISP(op | reg_high(b1) << 16 | \ 168 reg_high(b2) << 8, disp); \ 169 REG_SET_SEEN(b1); \ 170 REG_SET_SEEN(b2); \ 171}) 172 173#define EMIT4_IMM(op, b1, imm) \ 174({ \ 175 unsigned int __imm = (imm) & 0xffff; \ 176 _EMIT4(op | reg_high(b1) << 16 | __imm); \ 177 REG_SET_SEEN(b1); \ 178}) 179 180#define EMIT4_PCREL(op, pcrel) \ 181({ \ 182 long __pcrel = ((pcrel) >> 1) & 0xffff; \ 183 _EMIT4(op | __pcrel); \ 184}) 185 186#define _EMIT6(op1, op2) \ 187({ \ 188 if (jit->prg_buf) { \ 189 *(u32 *) (jit->prg_buf + jit->prg) = op1; \ 190 *(u16 *) (jit->prg_buf + jit->prg + 4) = op2; \ 191 } \ 192 jit->prg += 6; \ 193}) 194 195#define _EMIT6_DISP(op1, op2, disp) \ 196({ \ 197 unsigned int __disp = (disp) & 0xfff; \ 198 _EMIT6(op1 | __disp, op2); \ 199}) 200 201#define EMIT6_DISP(op1, op2, b1, b2, b3, disp) \ 202({ \ 203 _EMIT6_DISP(op1 | reg(b1, b2) << 16 | \ 204 reg_high(b3) << 8, op2, disp); \ 205 REG_SET_SEEN(b1); \ 206 REG_SET_SEEN(b2); \ 207 REG_SET_SEEN(b3); \ 208}) 209 210#define _EMIT6_DISP_LH(op1, op2, disp) \ 211({ \ 212 unsigned int __disp_h = ((u32)disp) & 0xff000; \ 213 unsigned int __disp_l = ((u32)disp) & 0x00fff; \ 214 _EMIT6(op1 | __disp_l, op2 | __disp_h >> 4); \ 215}) 216 217#define EMIT6_DISP_LH(op1, op2, b1, b2, b3, disp) \ 218({ \ 219 _EMIT6_DISP_LH(op1 | reg(b1, b2) << 16 | \ 220 reg_high(b3) << 8, op2, disp); \ 221 REG_SET_SEEN(b1); \ 222 REG_SET_SEEN(b2); \ 223 REG_SET_SEEN(b3); \ 224}) 225 226#define EMIT6_PCREL(op1, op2, b1, b2, i, off, mask) \ 227({ \ 228 /* Branch instruction needs 6 bytes */ \ 229 int rel = (addrs[i + off + 1] - (addrs[i + 1] - 6)) / 2;\ 230 _EMIT6(op1 | reg(b1, b2) << 16 | (rel & 0xffff), op2 | mask); \ 231 REG_SET_SEEN(b1); \ 232 REG_SET_SEEN(b2); \ 233}) 234 235#define _EMIT6_IMM(op, imm) \ 236({ \ 237 unsigned int __imm = (imm); \ 238 _EMIT6(op | (__imm >> 16), __imm & 0xffff); \ 239}) 240 241#define EMIT6_IMM(op, b1, imm) \ 242({ \ 243 _EMIT6_IMM(op | reg_high(b1) << 16, imm); \ 244 REG_SET_SEEN(b1); \ 245}) 246 247#define EMIT_CONST_U32(val) \ 248({ \ 249 unsigned int ret; \ 250 ret = jit->lit - jit->base_ip; \ 251 jit->seen |= SEEN_LITERAL; \ 252 if (jit->prg_buf) \ 253 *(u32 *) (jit->prg_buf + jit->lit) = (u32) val; \ 254 jit->lit += 4; \ 255 ret; \ 256}) 257 258#define EMIT_CONST_U64(val) \ 259({ \ 260 unsigned int ret; \ 261 ret = jit->lit - jit->base_ip; \ 262 jit->seen |= SEEN_LITERAL; \ 263 if (jit->prg_buf) \ 264 *(u64 *) (jit->prg_buf + jit->lit) = (u64) val; \ 265 jit->lit += 8; \ 266 ret; \ 267}) 268 269#define EMIT_ZERO(b1) \ 270({ \ 271 /* llgfr %dst,%dst (zero extend to 64 bit) */ \ 272 EMIT4(0xb9160000, b1, b1); \ 273 REG_SET_SEEN(b1); \ 274}) 275 276/* 277 * Fill whole space with illegal instructions 278 */ 279static void jit_fill_hole(void *area, unsigned int size) 280{ 281 memset(area, 0, size); 282} 283 284/* 285 * Save registers from "rs" (register start) to "re" (register end) on stack 286 */ 287static void save_regs(struct bpf_jit *jit, u32 rs, u32 re) 288{ 289 u32 off = 72 + (rs - 6) * 8; 290 291 if (rs == re) 292 /* stg %rs,off(%r15) */ 293 _EMIT6(0xe300f000 | rs << 20 | off, 0x0024); 294 else 295 /* stmg %rs,%re,off(%r15) */ 296 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0024, off); 297} 298 299/* 300 * Restore registers from "rs" (register start) to "re" (register end) on stack 301 */ 302static void restore_regs(struct bpf_jit *jit, u32 rs, u32 re) 303{ 304 u32 off = 72 + (rs - 6) * 8; 305 306 if (jit->seen & SEEN_STACK) 307 off += STK_OFF; 308 309 if (rs == re) 310 /* lg %rs,off(%r15) */ 311 _EMIT6(0xe300f000 | rs << 20 | off, 0x0004); 312 else 313 /* lmg %rs,%re,off(%r15) */ 314 _EMIT6_DISP(0xeb00f000 | rs << 20 | re << 16, 0x0004, off); 315} 316 317/* 318 * Return first seen register (from start) 319 */ 320static int get_start(struct bpf_jit *jit, int start) 321{ 322 int i; 323 324 for (i = start; i <= 15; i++) { 325 if (jit->seen_reg[i]) 326 return i; 327 } 328 return 0; 329} 330 331/* 332 * Return last seen register (from start) (gap >= 2) 333 */ 334static int get_end(struct bpf_jit *jit, int start) 335{ 336 int i; 337 338 for (i = start; i < 15; i++) { 339 if (!jit->seen_reg[i] && !jit->seen_reg[i + 1]) 340 return i - 1; 341 } 342 return jit->seen_reg[15] ? 15 : 14; 343} 344 345#define REGS_SAVE 1 346#define REGS_RESTORE 0 347/* 348 * Save and restore clobbered registers (6-15) on stack. 349 * We save/restore registers in chunks with gap >= 2 registers. 350 */ 351static void save_restore_regs(struct bpf_jit *jit, int op) 352{ 353 354 int re = 6, rs; 355 356 do { 357 rs = get_start(jit, re); 358 if (!rs) 359 break; 360 re = get_end(jit, rs + 1); 361 if (op == REGS_SAVE) 362 save_regs(jit, rs, re); 363 else 364 restore_regs(jit, rs, re); 365 re++; 366 } while (re <= 15); 367} 368 369/* 370 * Emit function prologue 371 * 372 * Save registers and create stack frame if necessary. 373 * See stack frame layout desription in "bpf_jit.h"! 374 */ 375static void bpf_jit_prologue(struct bpf_jit *jit) 376{ 377 /* Save registers */ 378 save_restore_regs(jit, REGS_SAVE); 379 /* Setup literal pool */ 380 if (jit->seen & SEEN_LITERAL) { 381 /* basr %r13,0 */ 382 EMIT2(0x0d00, REG_L, REG_0); 383 jit->base_ip = jit->prg; 384 } 385 /* Setup stack and backchain */ 386 if (jit->seen & SEEN_STACK) { 387 if (jit->seen & SEEN_FUNC) 388 /* lgr %w1,%r15 (backchain) */ 389 EMIT4(0xb9040000, REG_W1, REG_15); 390 /* la %bfp,STK_160_UNUSED(%r15) (BPF frame pointer) */ 391 EMIT4_DISP(0x41000000, BPF_REG_FP, REG_15, STK_160_UNUSED); 392 /* aghi %r15,-STK_OFF */ 393 EMIT4_IMM(0xa70b0000, REG_15, -STK_OFF); 394 if (jit->seen & SEEN_FUNC) 395 /* stg %w1,152(%r15) (backchain) */ 396 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, 397 REG_15, 152); 398 } 399 /* 400 * For SKB access %b1 contains the SKB pointer. For "bpf_jit.S" 401 * we store the SKB header length on the stack and the SKB data 402 * pointer in REG_SKB_DATA. 403 */ 404 if (jit->seen & SEEN_SKB) { 405 /* Header length: llgf %w1,<len>(%b1) */ 406 EMIT6_DISP_LH(0xe3000000, 0x0016, REG_W1, REG_0, BPF_REG_1, 407 offsetof(struct sk_buff, len)); 408 /* s %w1,<data_len>(%b1) */ 409 EMIT4_DISP(0x5b000000, REG_W1, BPF_REG_1, 410 offsetof(struct sk_buff, data_len)); 411 /* stg %w1,ST_OFF_HLEN(%r0,%r15) */ 412 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W1, REG_0, REG_15, 413 STK_OFF_HLEN); 414 /* lg %skb_data,data_off(%b1) */ 415 EMIT6_DISP_LH(0xe3000000, 0x0004, REG_SKB_DATA, REG_0, 416 BPF_REG_1, offsetof(struct sk_buff, data)); 417 } 418 /* BPF compatibility: clear A (%b0) and X (%b7) registers */ 419 if (REG_SEEN(BPF_REG_A)) 420 /* lghi %ba,0 */ 421 EMIT4_IMM(0xa7090000, BPF_REG_A, 0); 422 if (REG_SEEN(BPF_REG_X)) 423 /* lghi %bx,0 */ 424 EMIT4_IMM(0xa7090000, BPF_REG_X, 0); 425} 426 427/* 428 * Function epilogue 429 */ 430static void bpf_jit_epilogue(struct bpf_jit *jit) 431{ 432 /* Return 0 */ 433 if (jit->seen & SEEN_RET0) { 434 jit->ret0_ip = jit->prg; 435 /* lghi %b0,0 */ 436 EMIT4_IMM(0xa7090000, BPF_REG_0, 0); 437 } 438 jit->exit_ip = jit->prg; 439 /* Load exit code: lgr %r2,%b0 */ 440 EMIT4(0xb9040000, REG_2, BPF_REG_0); 441 /* Restore registers */ 442 save_restore_regs(jit, REGS_RESTORE); 443 /* br %r14 */ 444 _EMIT2(0x07fe); 445} 446 447/* 448 * Compile one eBPF instruction into s390x code 449 * 450 * NOTE: Use noinline because for gcov (-fprofile-arcs) gcc allocates a lot of 451 * stack space for the large switch statement. 452 */ 453static noinline int bpf_jit_insn(struct bpf_jit *jit, struct bpf_prog *fp, int i) 454{ 455 struct bpf_insn *insn = &fp->insnsi[i]; 456 int jmp_off, last, insn_count = 1; 457 unsigned int func_addr, mask; 458 u32 dst_reg = insn->dst_reg; 459 u32 src_reg = insn->src_reg; 460 u32 *addrs = jit->addrs; 461 s32 imm = insn->imm; 462 s16 off = insn->off; 463 464 switch (insn->code) { 465 /* 466 * BPF_MOV 467 */ 468 case BPF_ALU | BPF_MOV | BPF_X: /* dst = (u32) src */ 469 /* llgfr %dst,%src */ 470 EMIT4(0xb9160000, dst_reg, src_reg); 471 break; 472 case BPF_ALU64 | BPF_MOV | BPF_X: /* dst = src */ 473 /* lgr %dst,%src */ 474 EMIT4(0xb9040000, dst_reg, src_reg); 475 break; 476 case BPF_ALU | BPF_MOV | BPF_K: /* dst = (u32) imm */ 477 /* llilf %dst,imm */ 478 EMIT6_IMM(0xc00f0000, dst_reg, imm); 479 break; 480 case BPF_ALU64 | BPF_MOV | BPF_K: /* dst = imm */ 481 /* lgfi %dst,imm */ 482 EMIT6_IMM(0xc0010000, dst_reg, imm); 483 break; 484 /* 485 * BPF_LD 64 486 */ 487 case BPF_LD | BPF_IMM | BPF_DW: /* dst = (u64) imm */ 488 { 489 /* 16 byte instruction that uses two 'struct bpf_insn' */ 490 u64 imm64; 491 492 imm64 = (u64)(u32) insn[0].imm | ((u64)(u32) insn[1].imm) << 32; 493 /* lg %dst,<d(imm)>(%l) */ 494 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, REG_0, REG_L, 495 EMIT_CONST_U64(imm64)); 496 insn_count = 2; 497 break; 498 } 499 /* 500 * BPF_ADD 501 */ 502 case BPF_ALU | BPF_ADD | BPF_X: /* dst = (u32) dst + (u32) src */ 503 /* ar %dst,%src */ 504 EMIT2(0x1a00, dst_reg, src_reg); 505 EMIT_ZERO(dst_reg); 506 break; 507 case BPF_ALU64 | BPF_ADD | BPF_X: /* dst = dst + src */ 508 /* agr %dst,%src */ 509 EMIT4(0xb9080000, dst_reg, src_reg); 510 break; 511 case BPF_ALU | BPF_ADD | BPF_K: /* dst = (u32) dst + (u32) imm */ 512 if (!imm) 513 break; 514 /* alfi %dst,imm */ 515 EMIT6_IMM(0xc20b0000, dst_reg, imm); 516 EMIT_ZERO(dst_reg); 517 break; 518 case BPF_ALU64 | BPF_ADD | BPF_K: /* dst = dst + imm */ 519 if (!imm) 520 break; 521 /* agfi %dst,imm */ 522 EMIT6_IMM(0xc2080000, dst_reg, imm); 523 break; 524 /* 525 * BPF_SUB 526 */ 527 case BPF_ALU | BPF_SUB | BPF_X: /* dst = (u32) dst - (u32) src */ 528 /* sr %dst,%src */ 529 EMIT2(0x1b00, dst_reg, src_reg); 530 EMIT_ZERO(dst_reg); 531 break; 532 case BPF_ALU64 | BPF_SUB | BPF_X: /* dst = dst - src */ 533 /* sgr %dst,%src */ 534 EMIT4(0xb9090000, dst_reg, src_reg); 535 break; 536 case BPF_ALU | BPF_SUB | BPF_K: /* dst = (u32) dst - (u32) imm */ 537 if (!imm) 538 break; 539 /* alfi %dst,-imm */ 540 EMIT6_IMM(0xc20b0000, dst_reg, -imm); 541 EMIT_ZERO(dst_reg); 542 break; 543 case BPF_ALU64 | BPF_SUB | BPF_K: /* dst = dst - imm */ 544 if (!imm) 545 break; 546 /* agfi %dst,-imm */ 547 EMIT6_IMM(0xc2080000, dst_reg, -imm); 548 break; 549 /* 550 * BPF_MUL 551 */ 552 case BPF_ALU | BPF_MUL | BPF_X: /* dst = (u32) dst * (u32) src */ 553 /* msr %dst,%src */ 554 EMIT4(0xb2520000, dst_reg, src_reg); 555 EMIT_ZERO(dst_reg); 556 break; 557 case BPF_ALU64 | BPF_MUL | BPF_X: /* dst = dst * src */ 558 /* msgr %dst,%src */ 559 EMIT4(0xb90c0000, dst_reg, src_reg); 560 break; 561 case BPF_ALU | BPF_MUL | BPF_K: /* dst = (u32) dst * (u32) imm */ 562 if (imm == 1) 563 break; 564 /* msfi %r5,imm */ 565 EMIT6_IMM(0xc2010000, dst_reg, imm); 566 EMIT_ZERO(dst_reg); 567 break; 568 case BPF_ALU64 | BPF_MUL | BPF_K: /* dst = dst * imm */ 569 if (imm == 1) 570 break; 571 /* msgfi %dst,imm */ 572 EMIT6_IMM(0xc2000000, dst_reg, imm); 573 break; 574 /* 575 * BPF_DIV / BPF_MOD 576 */ 577 case BPF_ALU | BPF_DIV | BPF_X: /* dst = (u32) dst / (u32) src */ 578 case BPF_ALU | BPF_MOD | BPF_X: /* dst = (u32) dst % (u32) src */ 579 { 580 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 581 582 jit->seen |= SEEN_RET0; 583 /* ltr %src,%src (if src == 0 goto fail) */ 584 EMIT2(0x1200, src_reg, src_reg); 585 /* jz <ret0> */ 586 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg); 587 /* lhi %w0,0 */ 588 EMIT4_IMM(0xa7080000, REG_W0, 0); 589 /* lr %w1,%dst */ 590 EMIT2(0x1800, REG_W1, dst_reg); 591 /* dlr %w0,%src */ 592 EMIT4(0xb9970000, REG_W0, src_reg); 593 /* llgfr %dst,%rc */ 594 EMIT4(0xb9160000, dst_reg, rc_reg); 595 break; 596 } 597 case BPF_ALU64 | BPF_DIV | BPF_X: /* dst = dst / src */ 598 case BPF_ALU64 | BPF_MOD | BPF_X: /* dst = dst % src */ 599 { 600 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 601 602 jit->seen |= SEEN_RET0; 603 /* ltgr %src,%src (if src == 0 goto fail) */ 604 EMIT4(0xb9020000, src_reg, src_reg); 605 /* jz <ret0> */ 606 EMIT4_PCREL(0xa7840000, jit->ret0_ip - jit->prg); 607 /* lghi %w0,0 */ 608 EMIT4_IMM(0xa7090000, REG_W0, 0); 609 /* lgr %w1,%dst */ 610 EMIT4(0xb9040000, REG_W1, dst_reg); 611 /* dlgr %w0,%dst */ 612 EMIT4(0xb9870000, REG_W0, src_reg); 613 /* lgr %dst,%rc */ 614 EMIT4(0xb9040000, dst_reg, rc_reg); 615 break; 616 } 617 case BPF_ALU | BPF_DIV | BPF_K: /* dst = (u32) dst / (u32) imm */ 618 case BPF_ALU | BPF_MOD | BPF_K: /* dst = (u32) dst % (u32) imm */ 619 { 620 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 621 622 if (imm == 1) { 623 if (BPF_OP(insn->code) == BPF_MOD) 624 /* lhgi %dst,0 */ 625 EMIT4_IMM(0xa7090000, dst_reg, 0); 626 break; 627 } 628 /* lhi %w0,0 */ 629 EMIT4_IMM(0xa7080000, REG_W0, 0); 630 /* lr %w1,%dst */ 631 EMIT2(0x1800, REG_W1, dst_reg); 632 /* dl %w0,<d(imm)>(%l) */ 633 EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0, REG_L, 634 EMIT_CONST_U32(imm)); 635 /* llgfr %dst,%rc */ 636 EMIT4(0xb9160000, dst_reg, rc_reg); 637 break; 638 } 639 case BPF_ALU64 | BPF_DIV | BPF_K: /* dst = dst / imm */ 640 case BPF_ALU64 | BPF_MOD | BPF_K: /* dst = dst % imm */ 641 { 642 int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0; 643 644 if (imm == 1) { 645 if (BPF_OP(insn->code) == BPF_MOD) 646 /* lhgi %dst,0 */ 647 EMIT4_IMM(0xa7090000, dst_reg, 0); 648 break; 649 } 650 /* lghi %w0,0 */ 651 EMIT4_IMM(0xa7090000, REG_W0, 0); 652 /* lgr %w1,%dst */ 653 EMIT4(0xb9040000, REG_W1, dst_reg); 654 /* dlg %w0,<d(imm)>(%l) */ 655 EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0, REG_L, 656 EMIT_CONST_U64(imm)); 657 /* lgr %dst,%rc */ 658 EMIT4(0xb9040000, dst_reg, rc_reg); 659 break; 660 } 661 /* 662 * BPF_AND 663 */ 664 case BPF_ALU | BPF_AND | BPF_X: /* dst = (u32) dst & (u32) src */ 665 /* nr %dst,%src */ 666 EMIT2(0x1400, dst_reg, src_reg); 667 EMIT_ZERO(dst_reg); 668 break; 669 case BPF_ALU64 | BPF_AND | BPF_X: /* dst = dst & src */ 670 /* ngr %dst,%src */ 671 EMIT4(0xb9800000, dst_reg, src_reg); 672 break; 673 case BPF_ALU | BPF_AND | BPF_K: /* dst = (u32) dst & (u32) imm */ 674 /* nilf %dst,imm */ 675 EMIT6_IMM(0xc00b0000, dst_reg, imm); 676 EMIT_ZERO(dst_reg); 677 break; 678 case BPF_ALU64 | BPF_AND | BPF_K: /* dst = dst & imm */ 679 /* ng %dst,<d(imm)>(%l) */ 680 EMIT6_DISP_LH(0xe3000000, 0x0080, dst_reg, REG_0, REG_L, 681 EMIT_CONST_U64(imm)); 682 break; 683 /* 684 * BPF_OR 685 */ 686 case BPF_ALU | BPF_OR | BPF_X: /* dst = (u32) dst | (u32) src */ 687 /* or %dst,%src */ 688 EMIT2(0x1600, dst_reg, src_reg); 689 EMIT_ZERO(dst_reg); 690 break; 691 case BPF_ALU64 | BPF_OR | BPF_X: /* dst = dst | src */ 692 /* ogr %dst,%src */ 693 EMIT4(0xb9810000, dst_reg, src_reg); 694 break; 695 case BPF_ALU | BPF_OR | BPF_K: /* dst = (u32) dst | (u32) imm */ 696 /* oilf %dst,imm */ 697 EMIT6_IMM(0xc00d0000, dst_reg, imm); 698 EMIT_ZERO(dst_reg); 699 break; 700 case BPF_ALU64 | BPF_OR | BPF_K: /* dst = dst | imm */ 701 /* og %dst,<d(imm)>(%l) */ 702 EMIT6_DISP_LH(0xe3000000, 0x0081, dst_reg, REG_0, REG_L, 703 EMIT_CONST_U64(imm)); 704 break; 705 /* 706 * BPF_XOR 707 */ 708 case BPF_ALU | BPF_XOR | BPF_X: /* dst = (u32) dst ^ (u32) src */ 709 /* xr %dst,%src */ 710 EMIT2(0x1700, dst_reg, src_reg); 711 EMIT_ZERO(dst_reg); 712 break; 713 case BPF_ALU64 | BPF_XOR | BPF_X: /* dst = dst ^ src */ 714 /* xgr %dst,%src */ 715 EMIT4(0xb9820000, dst_reg, src_reg); 716 break; 717 case BPF_ALU | BPF_XOR | BPF_K: /* dst = (u32) dst ^ (u32) imm */ 718 if (!imm) 719 break; 720 /* xilf %dst,imm */ 721 EMIT6_IMM(0xc0070000, dst_reg, imm); 722 EMIT_ZERO(dst_reg); 723 break; 724 case BPF_ALU64 | BPF_XOR | BPF_K: /* dst = dst ^ imm */ 725 /* xg %dst,<d(imm)>(%l) */ 726 EMIT6_DISP_LH(0xe3000000, 0x0082, dst_reg, REG_0, REG_L, 727 EMIT_CONST_U64(imm)); 728 break; 729 /* 730 * BPF_LSH 731 */ 732 case BPF_ALU | BPF_LSH | BPF_X: /* dst = (u32) dst << (u32) src */ 733 /* sll %dst,0(%src) */ 734 EMIT4_DISP(0x89000000, dst_reg, src_reg, 0); 735 EMIT_ZERO(dst_reg); 736 break; 737 case BPF_ALU64 | BPF_LSH | BPF_X: /* dst = dst << src */ 738 /* sllg %dst,%dst,0(%src) */ 739 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, src_reg, 0); 740 break; 741 case BPF_ALU | BPF_LSH | BPF_K: /* dst = (u32) dst << (u32) imm */ 742 if (imm == 0) 743 break; 744 /* sll %dst,imm(%r0) */ 745 EMIT4_DISP(0x89000000, dst_reg, REG_0, imm); 746 EMIT_ZERO(dst_reg); 747 break; 748 case BPF_ALU64 | BPF_LSH | BPF_K: /* dst = dst << imm */ 749 if (imm == 0) 750 break; 751 /* sllg %dst,%dst,imm(%r0) */ 752 EMIT6_DISP_LH(0xeb000000, 0x000d, dst_reg, dst_reg, REG_0, imm); 753 break; 754 /* 755 * BPF_RSH 756 */ 757 case BPF_ALU | BPF_RSH | BPF_X: /* dst = (u32) dst >> (u32) src */ 758 /* srl %dst,0(%src) */ 759 EMIT4_DISP(0x88000000, dst_reg, src_reg, 0); 760 EMIT_ZERO(dst_reg); 761 break; 762 case BPF_ALU64 | BPF_RSH | BPF_X: /* dst = dst >> src */ 763 /* srlg %dst,%dst,0(%src) */ 764 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, src_reg, 0); 765 break; 766 case BPF_ALU | BPF_RSH | BPF_K: /* dst = (u32) dst >> (u32) imm */ 767 if (imm == 0) 768 break; 769 /* srl %dst,imm(%r0) */ 770 EMIT4_DISP(0x88000000, dst_reg, REG_0, imm); 771 EMIT_ZERO(dst_reg); 772 break; 773 case BPF_ALU64 | BPF_RSH | BPF_K: /* dst = dst >> imm */ 774 if (imm == 0) 775 break; 776 /* srlg %dst,%dst,imm(%r0) */ 777 EMIT6_DISP_LH(0xeb000000, 0x000c, dst_reg, dst_reg, REG_0, imm); 778 break; 779 /* 780 * BPF_ARSH 781 */ 782 case BPF_ALU64 | BPF_ARSH | BPF_X: /* ((s64) dst) >>= src */ 783 /* srag %dst,%dst,0(%src) */ 784 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, src_reg, 0); 785 break; 786 case BPF_ALU64 | BPF_ARSH | BPF_K: /* ((s64) dst) >>= imm */ 787 if (imm == 0) 788 break; 789 /* srag %dst,%dst,imm(%r0) */ 790 EMIT6_DISP_LH(0xeb000000, 0x000a, dst_reg, dst_reg, REG_0, imm); 791 break; 792 /* 793 * BPF_NEG 794 */ 795 case BPF_ALU | BPF_NEG: /* dst = (u32) -dst */ 796 /* lcr %dst,%dst */ 797 EMIT2(0x1300, dst_reg, dst_reg); 798 EMIT_ZERO(dst_reg); 799 break; 800 case BPF_ALU64 | BPF_NEG: /* dst = -dst */ 801 /* lcgr %dst,%dst */ 802 EMIT4(0xb9130000, dst_reg, dst_reg); 803 break; 804 /* 805 * BPF_FROM_BE/LE 806 */ 807 case BPF_ALU | BPF_END | BPF_FROM_BE: 808 /* s390 is big endian, therefore only clear high order bytes */ 809 switch (imm) { 810 case 16: /* dst = (u16) cpu_to_be16(dst) */ 811 /* llghr %dst,%dst */ 812 EMIT4(0xb9850000, dst_reg, dst_reg); 813 break; 814 case 32: /* dst = (u32) cpu_to_be32(dst) */ 815 /* llgfr %dst,%dst */ 816 EMIT4(0xb9160000, dst_reg, dst_reg); 817 break; 818 case 64: /* dst = (u64) cpu_to_be64(dst) */ 819 break; 820 } 821 break; 822 case BPF_ALU | BPF_END | BPF_FROM_LE: 823 switch (imm) { 824 case 16: /* dst = (u16) cpu_to_le16(dst) */ 825 /* lrvr %dst,%dst */ 826 EMIT4(0xb91f0000, dst_reg, dst_reg); 827 /* srl %dst,16(%r0) */ 828 EMIT4_DISP(0x88000000, dst_reg, REG_0, 16); 829 /* llghr %dst,%dst */ 830 EMIT4(0xb9850000, dst_reg, dst_reg); 831 break; 832 case 32: /* dst = (u32) cpu_to_le32(dst) */ 833 /* lrvr %dst,%dst */ 834 EMIT4(0xb91f0000, dst_reg, dst_reg); 835 /* llgfr %dst,%dst */ 836 EMIT4(0xb9160000, dst_reg, dst_reg); 837 break; 838 case 64: /* dst = (u64) cpu_to_le64(dst) */ 839 /* lrvgr %dst,%dst */ 840 EMIT4(0xb90f0000, dst_reg, dst_reg); 841 break; 842 } 843 break; 844 /* 845 * BPF_ST(X) 846 */ 847 case BPF_STX | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = src_reg */ 848 /* stcy %src,off(%dst) */ 849 EMIT6_DISP_LH(0xe3000000, 0x0072, src_reg, dst_reg, REG_0, off); 850 jit->seen |= SEEN_MEM; 851 break; 852 case BPF_STX | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = src */ 853 /* sthy %src,off(%dst) */ 854 EMIT6_DISP_LH(0xe3000000, 0x0070, src_reg, dst_reg, REG_0, off); 855 jit->seen |= SEEN_MEM; 856 break; 857 case BPF_STX | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = src */ 858 /* sty %src,off(%dst) */ 859 EMIT6_DISP_LH(0xe3000000, 0x0050, src_reg, dst_reg, REG_0, off); 860 jit->seen |= SEEN_MEM; 861 break; 862 case BPF_STX | BPF_MEM | BPF_DW: /* (u64 *)(dst + off) = src */ 863 /* stg %src,off(%dst) */ 864 EMIT6_DISP_LH(0xe3000000, 0x0024, src_reg, dst_reg, REG_0, off); 865 jit->seen |= SEEN_MEM; 866 break; 867 case BPF_ST | BPF_MEM | BPF_B: /* *(u8 *)(dst + off) = imm */ 868 /* lhi %w0,imm */ 869 EMIT4_IMM(0xa7080000, REG_W0, (u8) imm); 870 /* stcy %w0,off(dst) */ 871 EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg, REG_0, off); 872 jit->seen |= SEEN_MEM; 873 break; 874 case BPF_ST | BPF_MEM | BPF_H: /* (u16 *)(dst + off) = imm */ 875 /* lhi %w0,imm */ 876 EMIT4_IMM(0xa7080000, REG_W0, (u16) imm); 877 /* sthy %w0,off(dst) */ 878 EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg, REG_0, off); 879 jit->seen |= SEEN_MEM; 880 break; 881 case BPF_ST | BPF_MEM | BPF_W: /* *(u32 *)(dst + off) = imm */ 882 /* llilf %w0,imm */ 883 EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm); 884 /* sty %w0,off(%dst) */ 885 EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg, REG_0, off); 886 jit->seen |= SEEN_MEM; 887 break; 888 case BPF_ST | BPF_MEM | BPF_DW: /* *(u64 *)(dst + off) = imm */ 889 /* lgfi %w0,imm */ 890 EMIT6_IMM(0xc0010000, REG_W0, imm); 891 /* stg %w0,off(%dst) */ 892 EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg, REG_0, off); 893 jit->seen |= SEEN_MEM; 894 break; 895 /* 896 * BPF_STX XADD (atomic_add) 897 */ 898 case BPF_STX | BPF_XADD | BPF_W: /* *(u32 *)(dst + off) += src */ 899 /* laal %w0,%src,off(%dst) */ 900 EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W0, src_reg, 901 dst_reg, off); 902 jit->seen |= SEEN_MEM; 903 break; 904 case BPF_STX | BPF_XADD | BPF_DW: /* *(u64 *)(dst + off) += src */ 905 /* laalg %w0,%src,off(%dst) */ 906 EMIT6_DISP_LH(0xeb000000, 0x00ea, REG_W0, src_reg, 907 dst_reg, off); 908 jit->seen |= SEEN_MEM; 909 break; 910 /* 911 * BPF_LDX 912 */ 913 case BPF_LDX | BPF_MEM | BPF_B: /* dst = *(u8 *)(ul) (src + off) */ 914 /* llgc %dst,0(off,%src) */ 915 EMIT6_DISP_LH(0xe3000000, 0x0090, dst_reg, src_reg, REG_0, off); 916 jit->seen |= SEEN_MEM; 917 break; 918 case BPF_LDX | BPF_MEM | BPF_H: /* dst = *(u16 *)(ul) (src + off) */ 919 /* llgh %dst,0(off,%src) */ 920 EMIT6_DISP_LH(0xe3000000, 0x0091, dst_reg, src_reg, REG_0, off); 921 jit->seen |= SEEN_MEM; 922 break; 923 case BPF_LDX | BPF_MEM | BPF_W: /* dst = *(u32 *)(ul) (src + off) */ 924 /* llgf %dst,off(%src) */ 925 jit->seen |= SEEN_MEM; 926 EMIT6_DISP_LH(0xe3000000, 0x0016, dst_reg, src_reg, REG_0, off); 927 break; 928 case BPF_LDX | BPF_MEM | BPF_DW: /* dst = *(u64 *)(ul) (src + off) */ 929 /* lg %dst,0(off,%src) */ 930 jit->seen |= SEEN_MEM; 931 EMIT6_DISP_LH(0xe3000000, 0x0004, dst_reg, src_reg, REG_0, off); 932 break; 933 /* 934 * BPF_JMP / CALL 935 */ 936 case BPF_JMP | BPF_CALL: 937 { 938 /* 939 * b0 = (__bpf_call_base + imm)(b1, b2, b3, b4, b5) 940 */ 941 const u64 func = (u64)__bpf_call_base + imm; 942 943 REG_SET_SEEN(BPF_REG_5); 944 jit->seen |= SEEN_FUNC; 945 /* lg %w1,<d(imm)>(%l) */ 946 EMIT6_DISP(0xe3000000, 0x0004, REG_W1, REG_0, REG_L, 947 EMIT_CONST_U64(func)); 948 /* basr %r14,%w1 */ 949 EMIT2(0x0d00, REG_14, REG_W1); 950 /* lgr %b0,%r2: load return value into %b0 */ 951 EMIT4(0xb9040000, BPF_REG_0, REG_2); 952 break; 953 } 954 case BPF_JMP | BPF_EXIT: /* return b0 */ 955 last = (i == fp->len - 1) ? 1 : 0; 956 if (last && !(jit->seen & SEEN_RET0)) 957 break; 958 /* j <exit> */ 959 EMIT4_PCREL(0xa7f40000, jit->exit_ip - jit->prg); 960 break; 961 /* 962 * Branch relative (number of skipped instructions) to offset on 963 * condition. 964 * 965 * Condition code to mask mapping: 966 * 967 * CC | Description | Mask 968 * ------------------------------ 969 * 0 | Operands equal | 8 970 * 1 | First operand low | 4 971 * 2 | First operand high | 2 972 * 3 | Unused | 1 973 * 974 * For s390x relative branches: ip = ip + off_bytes 975 * For BPF relative branches: insn = insn + off_insns + 1 976 * 977 * For example for s390x with offset 0 we jump to the branch 978 * instruction itself (loop) and for BPF with offset 0 we 979 * branch to the instruction behind the branch. 980 */ 981 case BPF_JMP | BPF_JA: /* if (true) */ 982 mask = 0xf000; /* j */ 983 goto branch_oc; 984 case BPF_JMP | BPF_JSGT | BPF_K: /* ((s64) dst > (s64) imm) */ 985 mask = 0x2000; /* jh */ 986 goto branch_ks; 987 case BPF_JMP | BPF_JSGE | BPF_K: /* ((s64) dst >= (s64) imm) */ 988 mask = 0xa000; /* jhe */ 989 goto branch_ks; 990 case BPF_JMP | BPF_JGT | BPF_K: /* (dst_reg > imm) */ 991 mask = 0x2000; /* jh */ 992 goto branch_ku; 993 case BPF_JMP | BPF_JGE | BPF_K: /* (dst_reg >= imm) */ 994 mask = 0xa000; /* jhe */ 995 goto branch_ku; 996 case BPF_JMP | BPF_JNE | BPF_K: /* (dst_reg != imm) */ 997 mask = 0x7000; /* jne */ 998 goto branch_ku; 999 case BPF_JMP | BPF_JEQ | BPF_K: /* (dst_reg == imm) */ 1000 mask = 0x8000; /* je */ 1001 goto branch_ku; 1002 case BPF_JMP | BPF_JSET | BPF_K: /* (dst_reg & imm) */ 1003 mask = 0x7000; /* jnz */ 1004 /* lgfi %w1,imm (load sign extend imm) */ 1005 EMIT6_IMM(0xc0010000, REG_W1, imm); 1006 /* ngr %w1,%dst */ 1007 EMIT4(0xb9800000, REG_W1, dst_reg); 1008 goto branch_oc; 1009 1010 case BPF_JMP | BPF_JSGT | BPF_X: /* ((s64) dst > (s64) src) */ 1011 mask = 0x2000; /* jh */ 1012 goto branch_xs; 1013 case BPF_JMP | BPF_JSGE | BPF_X: /* ((s64) dst >= (s64) src) */ 1014 mask = 0xa000; /* jhe */ 1015 goto branch_xs; 1016 case BPF_JMP | BPF_JGT | BPF_X: /* (dst > src) */ 1017 mask = 0x2000; /* jh */ 1018 goto branch_xu; 1019 case BPF_JMP | BPF_JGE | BPF_X: /* (dst >= src) */ 1020 mask = 0xa000; /* jhe */ 1021 goto branch_xu; 1022 case BPF_JMP | BPF_JNE | BPF_X: /* (dst != src) */ 1023 mask = 0x7000; /* jne */ 1024 goto branch_xu; 1025 case BPF_JMP | BPF_JEQ | BPF_X: /* (dst == src) */ 1026 mask = 0x8000; /* je */ 1027 goto branch_xu; 1028 case BPF_JMP | BPF_JSET | BPF_X: /* (dst & src) */ 1029 mask = 0x7000; /* jnz */ 1030 /* ngrk %w1,%dst,%src */ 1031 EMIT4_RRF(0xb9e40000, REG_W1, dst_reg, src_reg); 1032 goto branch_oc; 1033branch_ks: 1034 /* lgfi %w1,imm (load sign extend imm) */ 1035 EMIT6_IMM(0xc0010000, REG_W1, imm); 1036 /* cgrj %dst,%w1,mask,off */ 1037 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, REG_W1, i, off, mask); 1038 break; 1039branch_ku: 1040 /* lgfi %w1,imm (load sign extend imm) */ 1041 EMIT6_IMM(0xc0010000, REG_W1, imm); 1042 /* clgrj %dst,%w1,mask,off */ 1043 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, REG_W1, i, off, mask); 1044 break; 1045branch_xs: 1046 /* cgrj %dst,%src,mask,off */ 1047 EMIT6_PCREL(0xec000000, 0x0064, dst_reg, src_reg, i, off, mask); 1048 break; 1049branch_xu: 1050 /* clgrj %dst,%src,mask,off */ 1051 EMIT6_PCREL(0xec000000, 0x0065, dst_reg, src_reg, i, off, mask); 1052 break; 1053branch_oc: 1054 /* brc mask,jmp_off (branch instruction needs 4 bytes) */ 1055 jmp_off = addrs[i + off + 1] - (addrs[i + 1] - 4); 1056 EMIT4_PCREL(0xa7040000 | mask << 8, jmp_off); 1057 break; 1058 /* 1059 * BPF_LD 1060 */ 1061 case BPF_LD | BPF_ABS | BPF_B: /* b0 = *(u8 *) (skb->data+imm) */ 1062 case BPF_LD | BPF_IND | BPF_B: /* b0 = *(u8 *) (skb->data+imm+src) */ 1063 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1064 func_addr = __pa(sk_load_byte_pos); 1065 else 1066 func_addr = __pa(sk_load_byte); 1067 goto call_fn; 1068 case BPF_LD | BPF_ABS | BPF_H: /* b0 = *(u16 *) (skb->data+imm) */ 1069 case BPF_LD | BPF_IND | BPF_H: /* b0 = *(u16 *) (skb->data+imm+src) */ 1070 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1071 func_addr = __pa(sk_load_half_pos); 1072 else 1073 func_addr = __pa(sk_load_half); 1074 goto call_fn; 1075 case BPF_LD | BPF_ABS | BPF_W: /* b0 = *(u32 *) (skb->data+imm) */ 1076 case BPF_LD | BPF_IND | BPF_W: /* b0 = *(u32 *) (skb->data+imm+src) */ 1077 if ((BPF_MODE(insn->code) == BPF_ABS) && (imm >= 0)) 1078 func_addr = __pa(sk_load_word_pos); 1079 else 1080 func_addr = __pa(sk_load_word); 1081 goto call_fn; 1082call_fn: 1083 jit->seen |= SEEN_SKB | SEEN_RET0 | SEEN_FUNC; 1084 REG_SET_SEEN(REG_14); /* Return address of possible func call */ 1085 1086 /* 1087 * Implicit input: 1088 * BPF_REG_6 (R7) : skb pointer 1089 * REG_SKB_DATA (R12): skb data pointer 1090 * 1091 * Calculated input: 1092 * BPF_REG_2 (R3) : offset of byte(s) to fetch in skb 1093 * BPF_REG_5 (R6) : return address 1094 * 1095 * Output: 1096 * BPF_REG_0 (R14): data read from skb 1097 * 1098 * Scratch registers (BPF_REG_1-5) 1099 */ 1100 1101 /* Call function: llilf %w1,func_addr */ 1102 EMIT6_IMM(0xc00f0000, REG_W1, func_addr); 1103 1104 /* Offset: lgfi %b2,imm */ 1105 EMIT6_IMM(0xc0010000, BPF_REG_2, imm); 1106 if (BPF_MODE(insn->code) == BPF_IND) 1107 /* agfr %b2,%src (%src is s32 here) */ 1108 EMIT4(0xb9180000, BPF_REG_2, src_reg); 1109 1110 /* basr %b5,%w1 (%b5 is call saved) */ 1111 EMIT2(0x0d00, BPF_REG_5, REG_W1); 1112 1113 /* 1114 * Note: For fast access we jump directly after the 1115 * jnz instruction from bpf_jit.S 1116 */ 1117 /* jnz <ret0> */ 1118 EMIT4_PCREL(0xa7740000, jit->ret0_ip - jit->prg); 1119 break; 1120 default: /* too complex, give up */ 1121 pr_err("Unknown opcode %02x\n", insn->code); 1122 return -1; 1123 } 1124 return insn_count; 1125} 1126 1127/* 1128 * Compile eBPF program into s390x code 1129 */ 1130static int bpf_jit_prog(struct bpf_jit *jit, struct bpf_prog *fp) 1131{ 1132 int i, insn_count; 1133 1134 jit->lit = jit->lit_start; 1135 jit->prg = 0; 1136 1137 bpf_jit_prologue(jit); 1138 for (i = 0; i < fp->len; i += insn_count) { 1139 insn_count = bpf_jit_insn(jit, fp, i); 1140 if (insn_count < 0) 1141 return -1; 1142 jit->addrs[i + 1] = jit->prg; /* Next instruction address */ 1143 } 1144 bpf_jit_epilogue(jit); 1145 1146 jit->lit_start = jit->prg; 1147 jit->size = jit->lit; 1148 jit->size_prg = jit->prg; 1149 return 0; 1150} 1151 1152/* 1153 * Classic BPF function stub. BPF programs will be converted into 1154 * eBPF and then bpf_int_jit_compile() will be called. 1155 */ 1156void bpf_jit_compile(struct bpf_prog *fp) 1157{ 1158} 1159 1160/* 1161 * Compile eBPF program "fp" 1162 */ 1163void bpf_int_jit_compile(struct bpf_prog *fp) 1164{ 1165 struct bpf_binary_header *header; 1166 struct bpf_jit jit; 1167 int pass; 1168 1169 if (!bpf_jit_enable) 1170 return; 1171 memset(&jit, 0, sizeof(jit)); 1172 jit.addrs = kcalloc(fp->len + 1, sizeof(*jit.addrs), GFP_KERNEL); 1173 if (jit.addrs == NULL) 1174 return; 1175 /* 1176 * Three initial passes: 1177 * - 1/2: Determine clobbered registers 1178 * - 3: Calculate program size and addrs arrray 1179 */ 1180 for (pass = 1; pass <= 3; pass++) { 1181 if (bpf_jit_prog(&jit, fp)) 1182 goto free_addrs; 1183 } 1184 /* 1185 * Final pass: Allocate and generate program 1186 */ 1187 if (jit.size >= BPF_SIZE_MAX) 1188 goto free_addrs; 1189 header = bpf_jit_binary_alloc(jit.size, &jit.prg_buf, 2, jit_fill_hole); 1190 if (!header) 1191 goto free_addrs; 1192 if (bpf_jit_prog(&jit, fp)) 1193 goto free_addrs; 1194 if (bpf_jit_enable > 1) { 1195 bpf_jit_dump(fp->len, jit.size, pass, jit.prg_buf); 1196 if (jit.prg_buf) 1197 print_fn_code(jit.prg_buf, jit.size_prg); 1198 } 1199 if (jit.prg_buf) { 1200 set_memory_ro((unsigned long)header, header->pages); 1201 fp->bpf_func = (void *) jit.prg_buf; 1202 fp->jited = true; 1203 } 1204free_addrs: 1205 kfree(jit.addrs); 1206} 1207 1208/* 1209 * Free eBPF program 1210 */ 1211void bpf_jit_free(struct bpf_prog *fp) 1212{ 1213 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK; 1214 struct bpf_binary_header *header = (void *)addr; 1215 1216 if (!fp->jited) 1217 goto free_filter; 1218 1219 set_memory_rw(addr, header->pages); 1220 bpf_jit_binary_free(header); 1221 1222free_filter: 1223 bpf_prog_unlock_free(fp); 1224} 1225