1/* 2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 3 * 4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc. 6 * 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 8 * Recode: ZHANG WEI <wei.zhang@freescale.com> 9 * Rewrite the routing for Frescale PCI and PCI Express 10 * Roy Zang <tie-fei.zang@freescale.com> 11 * MPC83xx PCI-Express support: 12 * Tony Li <tony.li@freescale.com> 13 * Anton Vorontsov <avorontsov@ru.mvista.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 */ 20#include <linux/kernel.h> 21#include <linux/pci.h> 22#include <linux/delay.h> 23#include <linux/string.h> 24#include <linux/init.h> 25#include <linux/interrupt.h> 26#include <linux/memblock.h> 27#include <linux/log2.h> 28#include <linux/slab.h> 29#include <linux/suspend.h> 30#include <linux/syscore_ops.h> 31#include <linux/uaccess.h> 32 33#include <asm/io.h> 34#include <asm/prom.h> 35#include <asm/pci-bridge.h> 36#include <asm/ppc-pci.h> 37#include <asm/machdep.h> 38#include <asm/disassemble.h> 39#include <asm/ppc-opcode.h> 40#include <sysdev/fsl_soc.h> 41#include <sysdev/fsl_pci.h> 42 43static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 44 45static void quirk_fsl_pcie_early(struct pci_dev *dev) 46{ 47 u8 hdr_type; 48 49 /* if we aren't a PCIe don't bother */ 50 if (!pci_is_pcie(dev)) 51 return; 52 53 /* if we aren't in host mode don't bother */ 54 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 55 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 56 return; 57 58 dev->class = PCI_CLASS_BRIDGE_PCI << 8; 59 fsl_pcie_bus_fixup = 1; 60 return; 61} 62 63static int fsl_indirect_read_config(struct pci_bus *, unsigned int, 64 int, int, u32 *); 65 66static int fsl_pcie_check_link(struct pci_controller *hose) 67{ 68 u32 val = 0; 69 70 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) { 71 if (hose->ops->read == fsl_indirect_read_config) 72 __indirect_read_config(hose, hose->first_busno, 0, 73 PCIE_LTSSM, 4, &val); 74 else 75 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val); 76 if (val < PCIE_LTSSM_L0) 77 return 1; 78 } else { 79 struct ccsr_pci __iomem *pci = hose->private_data; 80 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */ 81 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) 82 >> PEX_CSR0_LTSSM_SHIFT; 83 if (val != PEX_CSR0_LTSSM_L0) 84 return 1; 85 } 86 87 return 0; 88} 89 90static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn, 91 int offset, int len, u32 *val) 92{ 93 struct pci_controller *hose = pci_bus_to_host(bus); 94 95 if (fsl_pcie_check_link(hose)) 96 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 97 else 98 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK; 99 100 return indirect_read_config(bus, devfn, offset, len, val); 101} 102 103#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 104 105static struct pci_ops fsl_indirect_pcie_ops = 106{ 107 .read = fsl_indirect_read_config, 108 .write = indirect_write_config, 109}; 110 111#define MAX_PHYS_ADDR_BITS 40 112static u64 pci64_dma_offset = 1ull << MAX_PHYS_ADDR_BITS; 113 114#ifdef CONFIG_SWIOTLB 115static void setup_swiotlb_ops(struct pci_controller *hose) 116{ 117 if (ppc_swiotlb_enable) { 118 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb; 119 set_pci_dma_ops(&swiotlb_dma_ops); 120 } 121} 122#else 123static inline void setup_swiotlb_ops(struct pci_controller *hose) {} 124#endif 125 126static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask) 127{ 128 if (!dev->dma_mask || !dma_supported(dev, dma_mask)) 129 return -EIO; 130 131 /* 132 * Fixup PCI devices that are able to DMA to above the physical 133 * address width of the SoC such that we can address any internal 134 * SoC address from across PCI if needed 135 */ 136 if ((dev_is_pci(dev)) && 137 dma_mask >= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS)) { 138 set_dma_ops(dev, &dma_direct_ops); 139 set_dma_offset(dev, pci64_dma_offset); 140 } 141 142 *dev->dma_mask = dma_mask; 143 return 0; 144} 145 146static int setup_one_atmu(struct ccsr_pci __iomem *pci, 147 unsigned int index, const struct resource *res, 148 resource_size_t offset) 149{ 150 resource_size_t pci_addr = res->start - offset; 151 resource_size_t phys_addr = res->start; 152 resource_size_t size = resource_size(res); 153 u32 flags = 0x80044000; /* enable & mem R/W */ 154 unsigned int i; 155 156 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n", 157 (u64)res->start, (u64)size); 158 159 if (res->flags & IORESOURCE_PREFETCH) 160 flags |= 0x10000000; /* enable relaxed ordering */ 161 162 for (i = 0; size > 0; i++) { 163 unsigned int bits = min_t(u32, ilog2(size), 164 __ffs(pci_addr | phys_addr)); 165 166 if (index + i >= 5) 167 return -1; 168 169 out_be32(&pci->pow[index + i].potar, pci_addr >> 12); 170 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44); 171 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12); 172 out_be32(&pci->pow[index + i].powar, flags | (bits - 1)); 173 174 pci_addr += (resource_size_t)1U << bits; 175 phys_addr += (resource_size_t)1U << bits; 176 size -= (resource_size_t)1U << bits; 177 } 178 179 return i; 180} 181 182/* atmu setup for fsl pci/pcie controller */ 183static void setup_pci_atmu(struct pci_controller *hose) 184{ 185 struct ccsr_pci __iomem *pci = hose->private_data; 186 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 187 u64 mem, sz, paddr_hi = 0; 188 u64 offset = 0, paddr_lo = ULLONG_MAX; 189 u32 pcicsrbar = 0, pcicsrbar_sz; 190 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL | 191 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; 192 const char *name = hose->dn->full_name; 193 const u64 *reg; 194 int len; 195 196 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 197 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 198 win_idx = 2; 199 start_idx = 0; 200 end_idx = 3; 201 } 202 } 203 204 /* Disable all windows (except powar0 since it's ignored) */ 205 for(i = 1; i < 5; i++) 206 out_be32(&pci->pow[i].powar, 0); 207 for (i = start_idx; i < end_idx; i++) 208 out_be32(&pci->piw[i].piwar, 0); 209 210 /* Setup outbound MEM window */ 211 for(i = 0, j = 1; i < 3; i++) { 212 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM)) 213 continue; 214 215 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start); 216 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end); 217 218 /* We assume all memory resources have the same offset */ 219 offset = hose->mem_offset[i]; 220 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset); 221 222 if (n < 0 || j >= 5) { 223 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i); 224 hose->mem_resources[i].flags |= IORESOURCE_DISABLED; 225 } else 226 j += n; 227 } 228 229 /* Setup outbound IO window */ 230 if (hose->io_resource.flags & IORESOURCE_IO) { 231 if (j >= 5) { 232 pr_err("Ran out of outbound PCI ATMUs for IO resource\n"); 233 } else { 234 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, " 235 "phy base 0x%016llx.\n", 236 (u64)hose->io_resource.start, 237 (u64)resource_size(&hose->io_resource), 238 (u64)hose->io_base_phys); 239 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12)); 240 out_be32(&pci->pow[j].potear, 0); 241 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 242 /* Enable, IO R/W */ 243 out_be32(&pci->pow[j].powar, 0x80088000 244 | (ilog2(hose->io_resource.end 245 - hose->io_resource.start + 1) - 1)); 246 } 247 } 248 249 /* convert to pci address space */ 250 paddr_hi -= offset; 251 paddr_lo -= offset; 252 253 if (paddr_hi == paddr_lo) { 254 pr_err("%s: No outbound window space\n", name); 255 return; 256 } 257 258 if (paddr_lo == 0) { 259 pr_err("%s: No space for inbound window\n", name); 260 return; 261 } 262 263 /* setup PCSRBAR/PEXCSRBAR */ 264 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff); 265 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz); 266 pcicsrbar_sz = ~pcicsrbar_sz + 1; 267 268 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) || 269 (paddr_lo > 0x100000000ull)) 270 pcicsrbar = 0x100000000ull - pcicsrbar_sz; 271 else 272 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz; 273 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar); 274 275 paddr_lo = min(paddr_lo, (u64)pcicsrbar); 276 277 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar); 278 279 /* Setup inbound mem window */ 280 mem = memblock_end_of_DRAM(); 281 282 /* 283 * The msi-address-64 property, if it exists, indicates the physical 284 * address of the MSIIR register. Normally, this register is located 285 * inside CCSR, so the ATMU that covers all of CCSR is used. But if 286 * this property exists, then we normally need to create a new ATMU 287 * for it. For now, however, we cheat. The only entity that creates 288 * this property is the Freescale hypervisor, and the address is 289 * specified in the partition configuration. Typically, the address 290 * is located in the page immediately after the end of DDR. If so, we 291 * can avoid allocating a new ATMU by extending the DDR ATMU by one 292 * page. 293 */ 294 reg = of_get_property(hose->dn, "msi-address-64", &len); 295 if (reg && (len == sizeof(u64))) { 296 u64 address = be64_to_cpup(reg); 297 298 if ((address >= mem) && (address < (mem + PAGE_SIZE))) { 299 pr_info("%s: extending DDR ATMU to cover MSIIR", name); 300 mem += PAGE_SIZE; 301 } else { 302 /* TODO: Create a new ATMU for MSIIR */ 303 pr_warn("%s: msi-address-64 address of %llx is " 304 "unsupported\n", name, address); 305 } 306 } 307 308 sz = min(mem, paddr_lo); 309 mem_log = ilog2(sz); 310 311 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 312 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 313 /* Size window to exact size if power-of-two or one size up */ 314 if ((1ull << mem_log) != mem) { 315 mem_log++; 316 if ((1ull << mem_log) > mem) 317 pr_info("%s: Setting PCI inbound window " 318 "greater than memory size\n", name); 319 } 320 321 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK); 322 323 /* Setup inbound memory window */ 324 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 325 out_be32(&pci->piw[win_idx].piwbar, 0x00000000); 326 out_be32(&pci->piw[win_idx].piwar, piwar); 327 win_idx--; 328 329 hose->dma_window_base_cur = 0x00000000; 330 hose->dma_window_size = (resource_size_t)sz; 331 332 /* 333 * if we have >4G of memory setup second PCI inbound window to 334 * let devices that are 64-bit address capable to work w/o 335 * SWIOTLB and access the full range of memory 336 */ 337 if (sz != mem) { 338 mem_log = ilog2(mem); 339 340 /* Size window up if we dont fit in exact power-of-2 */ 341 if ((1ull << mem_log) != mem) 342 mem_log++; 343 344 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1); 345 346 /* Setup inbound memory window */ 347 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 348 out_be32(&pci->piw[win_idx].piwbear, 349 pci64_dma_offset >> 44); 350 out_be32(&pci->piw[win_idx].piwbar, 351 pci64_dma_offset >> 12); 352 out_be32(&pci->piw[win_idx].piwar, piwar); 353 354 /* 355 * install our own dma_set_mask handler to fixup dma_ops 356 * and dma_offset 357 */ 358 ppc_md.dma_set_mask = fsl_pci_dma_set_mask; 359 360 pr_info("%s: Setup 64-bit PCI DMA window\n", name); 361 } 362 } else { 363 u64 paddr = 0; 364 365 /* Setup inbound memory window */ 366 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 367 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 368 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1))); 369 win_idx--; 370 371 paddr += 1ull << mem_log; 372 sz -= 1ull << mem_log; 373 374 if (sz) { 375 mem_log = ilog2(sz); 376 piwar |= (mem_log - 1); 377 378 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 379 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12); 380 out_be32(&pci->piw[win_idx].piwar, piwar); 381 win_idx--; 382 383 paddr += 1ull << mem_log; 384 } 385 386 hose->dma_window_base_cur = 0x00000000; 387 hose->dma_window_size = (resource_size_t)paddr; 388 } 389 390 if (hose->dma_window_size < mem) { 391#ifdef CONFIG_SWIOTLB 392 ppc_swiotlb_enable = 1; 393#else 394 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to " 395 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n", 396 name); 397#endif 398 /* adjusting outbound windows could reclaim space in mem map */ 399 if (paddr_hi < 0xffffffffull) 400 pr_warning("%s: WARNING: Outbound window cfg leaves " 401 "gaps in memory map. Adjusting the memory map " 402 "could reduce unnecessary bounce buffering.\n", 403 name); 404 405 pr_info("%s: DMA window size is 0x%llx\n", name, 406 (u64)hose->dma_window_size); 407 } 408} 409 410static void __init setup_pci_cmd(struct pci_controller *hose) 411{ 412 u16 cmd; 413 int cap_x; 414 415 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 416 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 417 | PCI_COMMAND_IO; 418 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 419 420 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX); 421 if (cap_x) { 422 int pci_x_cmd = cap_x + PCI_X_CMD; 423 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ 424 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; 425 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd); 426 } else { 427 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 428 } 429} 430 431void fsl_pcibios_fixup_bus(struct pci_bus *bus) 432{ 433 struct pci_controller *hose = pci_bus_to_host(bus); 434 int i, is_pcie = 0, no_link; 435 436 /* The root complex bridge comes up with bogus resources, 437 * we copy the PHB ones in. 438 * 439 * With the current generic PCI code, the PHB bus no longer 440 * has bus->resource[0..4] set, so things are a bit more 441 * tricky. 442 */ 443 444 if (fsl_pcie_bus_fixup) 445 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 446 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); 447 448 if (bus->parent == hose->bus && (is_pcie || no_link)) { 449 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { 450 struct resource *res = bus->resource[i]; 451 struct resource *par; 452 453 if (!res) 454 continue; 455 if (i == 0) 456 par = &hose->io_resource; 457 else if (i < 4) 458 par = &hose->mem_resources[i-1]; 459 else par = NULL; 460 461 res->start = par ? par->start : 0; 462 res->end = par ? par->end : 0; 463 res->flags = par ? par->flags : 0; 464 } 465 } 466} 467 468int fsl_add_bridge(struct platform_device *pdev, int is_primary) 469{ 470 int len; 471 struct pci_controller *hose; 472 struct resource rsrc; 473 const int *bus_range; 474 u8 hdr_type, progif; 475 struct device_node *dev; 476 struct ccsr_pci __iomem *pci; 477 478 dev = pdev->dev.of_node; 479 480 if (!of_device_is_available(dev)) { 481 pr_warning("%s: disabled\n", dev->full_name); 482 return -ENODEV; 483 } 484 485 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 486 487 /* Fetch host bridge registers address */ 488 if (of_address_to_resource(dev, 0, &rsrc)) { 489 printk(KERN_WARNING "Can't get pci register base!"); 490 return -ENOMEM; 491 } 492 493 /* Get bus range if any */ 494 bus_range = of_get_property(dev, "bus-range", &len); 495 if (bus_range == NULL || len < 2 * sizeof(int)) 496 printk(KERN_WARNING "Can't get bus-range for %s, assume" 497 " bus 0\n", dev->full_name); 498 499 pci_add_flags(PCI_REASSIGN_ALL_BUS); 500 hose = pcibios_alloc_controller(dev); 501 if (!hose) 502 return -ENOMEM; 503 504 /* set platform device as the parent */ 505 hose->parent = &pdev->dev; 506 hose->first_busno = bus_range ? bus_range[0] : 0x0; 507 hose->last_busno = bus_range ? bus_range[1] : 0xff; 508 509 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 510 (u64)rsrc.start, (u64)resource_size(&rsrc)); 511 512 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc)); 513 if (!hose->private_data) 514 goto no_bridge; 515 516 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 517 PPC_INDIRECT_TYPE_BIG_ENDIAN); 518 519 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) 520 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 521 522 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 523 /* use fsl_indirect_read_config for PCIe */ 524 hose->ops = &fsl_indirect_pcie_ops; 525 /* For PCIE read HEADER_TYPE to identify controler mode */ 526 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type); 527 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) 528 goto no_bridge; 529 530 } else { 531 /* For PCI read PROG to identify controller mode */ 532 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 533 if ((progif & 1) && 534 !of_property_read_bool(dev, "fsl,pci-agent-force-enum")) 535 goto no_bridge; 536 } 537 538 setup_pci_cmd(hose); 539 540 /* check PCI express link status */ 541 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 542 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG | 543 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS; 544 if (fsl_pcie_check_link(hose)) 545 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 546 } 547 548 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 549 "Firmware bus number: %d->%d\n", 550 (unsigned long long)rsrc.start, hose->first_busno, 551 hose->last_busno); 552 553 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 554 hose, hose->cfg_addr, hose->cfg_data); 555 556 /* Interpret the "ranges" property */ 557 /* This also maps the I/O region and sets isa_io/mem_base */ 558 pci_process_bridge_OF_ranges(hose, dev, is_primary); 559 560 /* Setup PEX window registers */ 561 setup_pci_atmu(hose); 562 563 /* Set up controller operations */ 564 setup_swiotlb_ops(hose); 565 566 return 0; 567 568no_bridge: 569 iounmap(hose->private_data); 570 /* unmap cfg_data & cfg_addr separately if not on same page */ 571 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 572 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 573 iounmap(hose->cfg_data); 574 iounmap(hose->cfg_addr); 575 pcibios_free_controller(hose); 576 return -ENODEV; 577} 578#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 579 580DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, 581 quirk_fsl_pcie_early); 582 583#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 584struct mpc83xx_pcie_priv { 585 void __iomem *cfg_type0; 586 void __iomem *cfg_type1; 587 u32 dev_base; 588}; 589 590struct pex_inbound_window { 591 u32 ar; 592 u32 tar; 593 u32 barl; 594 u32 barh; 595}; 596 597/* 598 * With the convention of u-boot, the PCIE outbound window 0 serves 599 * as configuration transactions outbound. 600 */ 601#define PEX_OUTWIN0_BAR 0xCA4 602#define PEX_OUTWIN0_TAL 0xCA8 603#define PEX_OUTWIN0_TAH 0xCAC 604#define PEX_RC_INWIN_BASE 0xE60 605#define PEX_RCIWARn_EN 0x1 606 607static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn) 608{ 609 struct pci_controller *hose = pci_bus_to_host(bus); 610 611 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) 612 return PCIBIOS_DEVICE_NOT_FOUND; 613 /* 614 * Workaround for the HW bug: for Type 0 configure transactions the 615 * PCI-E controller does not check the device number bits and just 616 * assumes that the device number bits are 0. 617 */ 618 if (bus->number == hose->first_busno || 619 bus->primary == hose->first_busno) { 620 if (devfn & 0xf8) 621 return PCIBIOS_DEVICE_NOT_FOUND; 622 } 623 624 if (ppc_md.pci_exclude_device) { 625 if (ppc_md.pci_exclude_device(hose, bus->number, devfn)) 626 return PCIBIOS_DEVICE_NOT_FOUND; 627 } 628 629 return PCIBIOS_SUCCESSFUL; 630} 631 632static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus, 633 unsigned int devfn, int offset) 634{ 635 struct pci_controller *hose = pci_bus_to_host(bus); 636 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 637 u32 dev_base = bus->number << 24 | devfn << 16; 638 int ret; 639 640 ret = mpc83xx_pcie_exclude_device(bus, devfn); 641 if (ret) 642 return NULL; 643 644 offset &= 0xfff; 645 646 /* Type 0 */ 647 if (bus->number == hose->first_busno) 648 return pcie->cfg_type0 + offset; 649 650 if (pcie->dev_base == dev_base) 651 goto mapped; 652 653 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base); 654 655 pcie->dev_base = dev_base; 656mapped: 657 return pcie->cfg_type1 + offset; 658} 659 660static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, 661 int offset, int len, u32 val) 662{ 663 struct pci_controller *hose = pci_bus_to_host(bus); 664 665 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */ 666 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno) 667 val &= 0xffffff00; 668 669 return pci_generic_config_write(bus, devfn, offset, len, val); 670} 671 672static struct pci_ops mpc83xx_pcie_ops = { 673 .map_bus = mpc83xx_pcie_remap_cfg, 674 .read = pci_generic_config_read, 675 .write = mpc83xx_pcie_write_config, 676}; 677 678static int __init mpc83xx_pcie_setup(struct pci_controller *hose, 679 struct resource *reg) 680{ 681 struct mpc83xx_pcie_priv *pcie; 682 u32 cfg_bar; 683 int ret = -ENOMEM; 684 685 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL); 686 if (!pcie) 687 return ret; 688 689 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg)); 690 if (!pcie->cfg_type0) 691 goto err0; 692 693 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR); 694 if (!cfg_bar) { 695 /* PCI-E isn't configured. */ 696 ret = -ENODEV; 697 goto err1; 698 } 699 700 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000); 701 if (!pcie->cfg_type1) 702 goto err1; 703 704 WARN_ON(hose->dn->data); 705 hose->dn->data = pcie; 706 hose->ops = &mpc83xx_pcie_ops; 707 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK; 708 709 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 710 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 711 712 if (fsl_pcie_check_link(hose)) 713 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK; 714 715 return 0; 716err1: 717 iounmap(pcie->cfg_type0); 718err0: 719 kfree(pcie); 720 return ret; 721 722} 723 724int __init mpc83xx_add_bridge(struct device_node *dev) 725{ 726 int ret; 727 int len; 728 struct pci_controller *hose; 729 struct resource rsrc_reg; 730 struct resource rsrc_cfg; 731 const int *bus_range; 732 int primary; 733 734 is_mpc83xx_pci = 1; 735 736 if (!of_device_is_available(dev)) { 737 pr_warning("%s: disabled by the firmware.\n", 738 dev->full_name); 739 return -ENODEV; 740 } 741 pr_debug("Adding PCI host bridge %s\n", dev->full_name); 742 743 /* Fetch host bridge registers address */ 744 if (of_address_to_resource(dev, 0, &rsrc_reg)) { 745 printk(KERN_WARNING "Can't get pci register base!\n"); 746 return -ENOMEM; 747 } 748 749 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg)); 750 751 if (of_address_to_resource(dev, 1, &rsrc_cfg)) { 752 printk(KERN_WARNING 753 "No pci config register base in dev tree, " 754 "using default\n"); 755 /* 756 * MPC83xx supports up to two host controllers 757 * one at 0x8500 has config space registers at 0x8300 758 * one at 0x8600 has config space registers at 0x8380 759 */ 760 if ((rsrc_reg.start & 0xfffff) == 0x8500) 761 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300; 762 else if ((rsrc_reg.start & 0xfffff) == 0x8600) 763 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380; 764 } 765 /* 766 * Controller at offset 0x8500 is primary 767 */ 768 if ((rsrc_reg.start & 0xfffff) == 0x8500) 769 primary = 1; 770 else 771 primary = 0; 772 773 /* Get bus range if any */ 774 bus_range = of_get_property(dev, "bus-range", &len); 775 if (bus_range == NULL || len < 2 * sizeof(int)) { 776 printk(KERN_WARNING "Can't get bus-range for %s, assume" 777 " bus 0\n", dev->full_name); 778 } 779 780 pci_add_flags(PCI_REASSIGN_ALL_BUS); 781 hose = pcibios_alloc_controller(dev); 782 if (!hose) 783 return -ENOMEM; 784 785 hose->first_busno = bus_range ? bus_range[0] : 0; 786 hose->last_busno = bus_range ? bus_range[1] : 0xff; 787 788 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) { 789 ret = mpc83xx_pcie_setup(hose, &rsrc_reg); 790 if (ret) 791 goto err0; 792 } else { 793 setup_indirect_pci(hose, rsrc_cfg.start, 794 rsrc_cfg.start + 4, 0); 795 } 796 797 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 798 "Firmware bus number: %d->%d\n", 799 (unsigned long long)rsrc_reg.start, hose->first_busno, 800 hose->last_busno); 801 802 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 803 hose, hose->cfg_addr, hose->cfg_data); 804 805 /* Interpret the "ranges" property */ 806 /* This also maps the I/O region and sets isa_io/mem_base */ 807 pci_process_bridge_OF_ranges(hose, dev, primary); 808 809 return 0; 810err0: 811 pcibios_free_controller(hose); 812 return ret; 813} 814#endif /* CONFIG_PPC_83xx */ 815 816u64 fsl_pci_immrbar_base(struct pci_controller *hose) 817{ 818#ifdef CONFIG_PPC_83xx 819 if (is_mpc83xx_pci) { 820 struct mpc83xx_pcie_priv *pcie = hose->dn->data; 821 struct pex_inbound_window *in; 822 int i; 823 824 /* Walk the Root Complex Inbound windows to match IMMR base */ 825 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE; 826 for (i = 0; i < 4; i++) { 827 /* not enabled, skip */ 828 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN)) 829 continue; 830 831 if (get_immrbase() == in_le32(&in[i].tar)) 832 return (u64)in_le32(&in[i].barh) << 32 | 833 in_le32(&in[i].barl); 834 } 835 836 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n"); 837 } 838#endif 839 840#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 841 if (!is_mpc83xx_pci) { 842 u32 base; 843 844 pci_bus_read_config_dword(hose->bus, 845 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base); 846 847 /* 848 * For PEXCSRBAR, bit 3-0 indicate prefetchable and 849 * address type. So when getting base address, these 850 * bits should be masked 851 */ 852 base &= PCI_BASE_ADDRESS_MEM_MASK; 853 854 return base; 855 } 856#endif 857 858 return 0; 859} 860 861#ifdef CONFIG_E500 862static int mcheck_handle_load(struct pt_regs *regs, u32 inst) 863{ 864 unsigned int rd, ra, rb, d; 865 866 rd = get_rt(inst); 867 ra = get_ra(inst); 868 rb = get_rb(inst); 869 d = get_d(inst); 870 871 switch (get_op(inst)) { 872 case 31: 873 switch (get_xop(inst)) { 874 case OP_31_XOP_LWZX: 875 case OP_31_XOP_LWBRX: 876 regs->gpr[rd] = 0xffffffff; 877 break; 878 879 case OP_31_XOP_LWZUX: 880 regs->gpr[rd] = 0xffffffff; 881 regs->gpr[ra] += regs->gpr[rb]; 882 break; 883 884 case OP_31_XOP_LBZX: 885 regs->gpr[rd] = 0xff; 886 break; 887 888 case OP_31_XOP_LBZUX: 889 regs->gpr[rd] = 0xff; 890 regs->gpr[ra] += regs->gpr[rb]; 891 break; 892 893 case OP_31_XOP_LHZX: 894 case OP_31_XOP_LHBRX: 895 regs->gpr[rd] = 0xffff; 896 break; 897 898 case OP_31_XOP_LHZUX: 899 regs->gpr[rd] = 0xffff; 900 regs->gpr[ra] += regs->gpr[rb]; 901 break; 902 903 case OP_31_XOP_LHAX: 904 regs->gpr[rd] = ~0UL; 905 break; 906 907 case OP_31_XOP_LHAUX: 908 regs->gpr[rd] = ~0UL; 909 regs->gpr[ra] += regs->gpr[rb]; 910 break; 911 912 default: 913 return 0; 914 } 915 break; 916 917 case OP_LWZ: 918 regs->gpr[rd] = 0xffffffff; 919 break; 920 921 case OP_LWZU: 922 regs->gpr[rd] = 0xffffffff; 923 regs->gpr[ra] += (s16)d; 924 break; 925 926 case OP_LBZ: 927 regs->gpr[rd] = 0xff; 928 break; 929 930 case OP_LBZU: 931 regs->gpr[rd] = 0xff; 932 regs->gpr[ra] += (s16)d; 933 break; 934 935 case OP_LHZ: 936 regs->gpr[rd] = 0xffff; 937 break; 938 939 case OP_LHZU: 940 regs->gpr[rd] = 0xffff; 941 regs->gpr[ra] += (s16)d; 942 break; 943 944 case OP_LHA: 945 regs->gpr[rd] = ~0UL; 946 break; 947 948 case OP_LHAU: 949 regs->gpr[rd] = ~0UL; 950 regs->gpr[ra] += (s16)d; 951 break; 952 953 default: 954 return 0; 955 } 956 957 return 1; 958} 959 960static int is_in_pci_mem_space(phys_addr_t addr) 961{ 962 struct pci_controller *hose; 963 struct resource *res; 964 int i; 965 966 list_for_each_entry(hose, &hose_list, list_node) { 967 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)) 968 continue; 969 970 for (i = 0; i < 3; i++) { 971 res = &hose->mem_resources[i]; 972 if ((res->flags & IORESOURCE_MEM) && 973 addr >= res->start && addr <= res->end) 974 return 1; 975 } 976 } 977 return 0; 978} 979 980int fsl_pci_mcheck_exception(struct pt_regs *regs) 981{ 982 u32 inst; 983 int ret; 984 phys_addr_t addr = 0; 985 986 /* Let KVM/QEMU deal with the exception */ 987 if (regs->msr & MSR_GS) 988 return 0; 989 990#ifdef CONFIG_PHYS_64BIT 991 addr = mfspr(SPRN_MCARU); 992 addr <<= 32; 993#endif 994 addr += mfspr(SPRN_MCAR); 995 996 if (is_in_pci_mem_space(addr)) { 997 if (user_mode(regs)) { 998 pagefault_disable(); 999 ret = get_user(regs->nip, &inst); 1000 pagefault_enable(); 1001 } else { 1002 ret = probe_kernel_address(regs->nip, inst); 1003 } 1004 1005 if (mcheck_handle_load(regs, inst)) { 1006 regs->nip += 4; 1007 return 1; 1008 } 1009 } 1010 1011 return 0; 1012} 1013#endif 1014 1015#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 1016static const struct of_device_id pci_ids[] = { 1017 { .compatible = "fsl,mpc8540-pci", }, 1018 { .compatible = "fsl,mpc8548-pcie", }, 1019 { .compatible = "fsl,mpc8610-pci", }, 1020 { .compatible = "fsl,mpc8641-pcie", }, 1021 { .compatible = "fsl,qoriq-pcie", }, 1022 { .compatible = "fsl,qoriq-pcie-v2.1", }, 1023 { .compatible = "fsl,qoriq-pcie-v2.2", }, 1024 { .compatible = "fsl,qoriq-pcie-v2.3", }, 1025 { .compatible = "fsl,qoriq-pcie-v2.4", }, 1026 { .compatible = "fsl,qoriq-pcie-v3.0", }, 1027 1028 /* 1029 * The following entries are for compatibility with older device 1030 * trees. 1031 */ 1032 { .compatible = "fsl,p1022-pcie", }, 1033 { .compatible = "fsl,p4080-pcie", }, 1034 1035 {}, 1036}; 1037 1038struct device_node *fsl_pci_primary; 1039 1040void fsl_pci_assign_primary(void) 1041{ 1042 struct device_node *np; 1043 1044 /* Callers can specify the primary bus using other means. */ 1045 if (fsl_pci_primary) 1046 return; 1047 1048 /* If a PCI host bridge contains an ISA node, it's primary. */ 1049 np = of_find_node_by_type(NULL, "isa"); 1050 while ((fsl_pci_primary = of_get_parent(np))) { 1051 of_node_put(np); 1052 np = fsl_pci_primary; 1053 1054 if (of_match_node(pci_ids, np) && of_device_is_available(np)) 1055 return; 1056 } 1057 1058 /* 1059 * If there's no PCI host bridge with ISA, arbitrarily 1060 * designate one as primary. This can go away once 1061 * various bugs with primary-less systems are fixed. 1062 */ 1063 for_each_matching_node(np, pci_ids) { 1064 if (of_device_is_available(np)) { 1065 fsl_pci_primary = np; 1066 of_node_put(np); 1067 return; 1068 } 1069 } 1070} 1071 1072#ifdef CONFIG_PM_SLEEP 1073static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id) 1074{ 1075 struct pci_controller *hose = dev_id; 1076 struct ccsr_pci __iomem *pci = hose->private_data; 1077 u32 dr; 1078 1079 dr = in_be32(&pci->pex_pme_mes_dr); 1080 if (!dr) 1081 return IRQ_NONE; 1082 1083 out_be32(&pci->pex_pme_mes_dr, dr); 1084 1085 return IRQ_HANDLED; 1086} 1087 1088static int fsl_pci_pme_probe(struct pci_controller *hose) 1089{ 1090 struct ccsr_pci __iomem *pci; 1091 struct pci_dev *dev; 1092 int pme_irq; 1093 int res; 1094 u16 pms; 1095 1096 /* Get hose's pci_dev */ 1097 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list); 1098 1099 /* PME Disable */ 1100 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1101 pms &= ~PCI_PM_CTRL_PME_ENABLE; 1102 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1103 1104 pme_irq = irq_of_parse_and_map(hose->dn, 0); 1105 if (!pme_irq) { 1106 dev_err(&dev->dev, "Failed to map PME interrupt.\n"); 1107 1108 return -ENXIO; 1109 } 1110 1111 res = devm_request_irq(hose->parent, pme_irq, 1112 fsl_pci_pme_handle, 1113 IRQF_SHARED, 1114 "[PCI] PME", hose); 1115 if (res < 0) { 1116 dev_err(&dev->dev, "Unable to requiest irq %d for PME\n", pme_irq); 1117 irq_dispose_mapping(pme_irq); 1118 1119 return -ENODEV; 1120 } 1121 1122 pci = hose->private_data; 1123 1124 /* Enable PTOD, ENL23D & EXL23D */ 1125 clrbits32(&pci->pex_pme_mes_disr, 1126 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1127 1128 out_be32(&pci->pex_pme_mes_ier, 0); 1129 setbits32(&pci->pex_pme_mes_ier, 1130 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D); 1131 1132 /* PME Enable */ 1133 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms); 1134 pms |= PCI_PM_CTRL_PME_ENABLE; 1135 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms); 1136 1137 return 0; 1138} 1139 1140static void send_pme_turnoff_message(struct pci_controller *hose) 1141{ 1142 struct ccsr_pci __iomem *pci = hose->private_data; 1143 u32 dr; 1144 int i; 1145 1146 /* Send PME_Turn_Off Message Request */ 1147 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR); 1148 1149 /* Wait trun off done */ 1150 for (i = 0; i < 150; i++) { 1151 dr = in_be32(&pci->pex_pme_mes_dr); 1152 if (dr) { 1153 out_be32(&pci->pex_pme_mes_dr, dr); 1154 break; 1155 } 1156 1157 udelay(1000); 1158 } 1159} 1160 1161static void fsl_pci_syscore_do_suspend(struct pci_controller *hose) 1162{ 1163 send_pme_turnoff_message(hose); 1164} 1165 1166static int fsl_pci_syscore_suspend(void) 1167{ 1168 struct pci_controller *hose, *tmp; 1169 1170 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1171 fsl_pci_syscore_do_suspend(hose); 1172 1173 return 0; 1174} 1175 1176static void fsl_pci_syscore_do_resume(struct pci_controller *hose) 1177{ 1178 struct ccsr_pci __iomem *pci = hose->private_data; 1179 u32 dr; 1180 int i; 1181 1182 /* Send Exit L2 State Message */ 1183 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S); 1184 1185 /* Wait exit done */ 1186 for (i = 0; i < 150; i++) { 1187 dr = in_be32(&pci->pex_pme_mes_dr); 1188 if (dr) { 1189 out_be32(&pci->pex_pme_mes_dr, dr); 1190 break; 1191 } 1192 1193 udelay(1000); 1194 } 1195 1196 setup_pci_atmu(hose); 1197} 1198 1199static void fsl_pci_syscore_resume(void) 1200{ 1201 struct pci_controller *hose, *tmp; 1202 1203 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 1204 fsl_pci_syscore_do_resume(hose); 1205} 1206 1207static struct syscore_ops pci_syscore_pm_ops = { 1208 .suspend = fsl_pci_syscore_suspend, 1209 .resume = fsl_pci_syscore_resume, 1210}; 1211#endif 1212 1213void fsl_pcibios_fixup_phb(struct pci_controller *phb) 1214{ 1215#ifdef CONFIG_PM_SLEEP 1216 fsl_pci_pme_probe(phb); 1217#endif 1218} 1219 1220static int fsl_pci_probe(struct platform_device *pdev) 1221{ 1222 struct device_node *node; 1223 int ret; 1224 1225 node = pdev->dev.of_node; 1226 ret = fsl_add_bridge(pdev, fsl_pci_primary == node); 1227 1228 mpc85xx_pci_err_probe(pdev); 1229 1230 return 0; 1231} 1232 1233static struct platform_driver fsl_pci_driver = { 1234 .driver = { 1235 .name = "fsl-pci", 1236 .of_match_table = pci_ids, 1237 }, 1238 .probe = fsl_pci_probe, 1239}; 1240 1241static int __init fsl_pci_init(void) 1242{ 1243#ifdef CONFIG_PM_SLEEP 1244 register_syscore_ops(&pci_syscore_pm_ops); 1245#endif 1246 return platform_driver_register(&fsl_pci_driver); 1247} 1248arch_initcall(fsl_pci_init); 1249#endif 1250