1/* 2 * Contains common pci routines for ALL ppc platform 3 * (based on pci_32.c and pci_64.c) 4 * 5 * Port for PPC64 David Engebretsen, IBM Corp. 6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 7 * 8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 9 * Rework, based on alpha PCI code. 10 * 11 * Common pmac/prep/chrp pci routines. -- Cort 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License 15 * as published by the Free Software Foundation; either version 16 * 2 of the License, or (at your option) any later version. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/pci.h> 21#include <linux/string.h> 22#include <linux/init.h> 23#include <linux/delay.h> 24#include <linux/export.h> 25#include <linux/of_address.h> 26#include <linux/of_pci.h> 27#include <linux/mm.h> 28#include <linux/list.h> 29#include <linux/syscalls.h> 30#include <linux/irq.h> 31#include <linux/vmalloc.h> 32#include <linux/slab.h> 33#include <linux/vgaarb.h> 34 35#include <asm/processor.h> 36#include <asm/io.h> 37#include <asm/prom.h> 38#include <asm/pci-bridge.h> 39#include <asm/byteorder.h> 40#include <asm/machdep.h> 41#include <asm/ppc-pci.h> 42#include <asm/eeh.h> 43 44static DEFINE_SPINLOCK(hose_spinlock); 45LIST_HEAD(hose_list); 46 47/* XXX kill that some day ... */ 48static int global_phb_number; /* Global phb counter */ 49 50/* ISA Memory physical address */ 51resource_size_t isa_mem_base; 52 53 54static struct dma_map_ops *pci_dma_ops = &dma_direct_ops; 55 56void set_pci_dma_ops(struct dma_map_ops *dma_ops) 57{ 58 pci_dma_ops = dma_ops; 59} 60 61struct dma_map_ops *get_pci_dma_ops(void) 62{ 63 return pci_dma_ops; 64} 65EXPORT_SYMBOL(get_pci_dma_ops); 66 67struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 68{ 69 struct pci_controller *phb; 70 71 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); 72 if (phb == NULL) 73 return NULL; 74 spin_lock(&hose_spinlock); 75 phb->global_number = global_phb_number++; 76 list_add_tail(&phb->list_node, &hose_list); 77 spin_unlock(&hose_spinlock); 78 phb->dn = dev; 79 phb->is_dynamic = slab_is_available(); 80#ifdef CONFIG_PPC64 81 if (dev) { 82 int nid = of_node_to_nid(dev); 83 84 if (nid < 0 || !node_online(nid)) 85 nid = -1; 86 87 PHB_SET_NODE(phb, nid); 88 } 89#endif 90 return phb; 91} 92 93void pcibios_free_controller(struct pci_controller *phb) 94{ 95 spin_lock(&hose_spinlock); 96 list_del(&phb->list_node); 97 spin_unlock(&hose_spinlock); 98 99 if (phb->is_dynamic) 100 kfree(phb); 101} 102 103/* 104 * The function is used to return the minimal alignment 105 * for memory or I/O windows of the associated P2P bridge. 106 * By default, 4KiB alignment for I/O windows and 1MiB for 107 * memory windows. 108 */ 109resource_size_t pcibios_window_alignment(struct pci_bus *bus, 110 unsigned long type) 111{ 112 struct pci_controller *phb = pci_bus_to_host(bus); 113 114 if (phb->controller_ops.window_alignment) 115 return phb->controller_ops.window_alignment(bus, type); 116 117 /* 118 * PCI core will figure out the default 119 * alignment: 4KiB for I/O and 1MiB for 120 * memory window. 121 */ 122 return 1; 123} 124 125void pcibios_reset_secondary_bus(struct pci_dev *dev) 126{ 127 struct pci_controller *phb = pci_bus_to_host(dev->bus); 128 129 if (phb->controller_ops.reset_secondary_bus) { 130 phb->controller_ops.reset_secondary_bus(dev); 131 return; 132 } 133 134 pci_reset_secondary_bus(dev); 135} 136 137#ifdef CONFIG_PCI_IOV 138resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) 139{ 140 if (ppc_md.pcibios_iov_resource_alignment) 141 return ppc_md.pcibios_iov_resource_alignment(pdev, resno); 142 143 return pci_iov_resource_size(pdev, resno); 144} 145#endif /* CONFIG_PCI_IOV */ 146 147static resource_size_t pcibios_io_size(const struct pci_controller *hose) 148{ 149#ifdef CONFIG_PPC64 150 return hose->pci_io_size; 151#else 152 return resource_size(&hose->io_resource); 153#endif 154} 155 156int pcibios_vaddr_is_ioport(void __iomem *address) 157{ 158 int ret = 0; 159 struct pci_controller *hose; 160 resource_size_t size; 161 162 spin_lock(&hose_spinlock); 163 list_for_each_entry(hose, &hose_list, list_node) { 164 size = pcibios_io_size(hose); 165 if (address >= hose->io_base_virt && 166 address < (hose->io_base_virt + size)) { 167 ret = 1; 168 break; 169 } 170 } 171 spin_unlock(&hose_spinlock); 172 return ret; 173} 174 175unsigned long pci_address_to_pio(phys_addr_t address) 176{ 177 struct pci_controller *hose; 178 resource_size_t size; 179 unsigned long ret = ~0; 180 181 spin_lock(&hose_spinlock); 182 list_for_each_entry(hose, &hose_list, list_node) { 183 size = pcibios_io_size(hose); 184 if (address >= hose->io_base_phys && 185 address < (hose->io_base_phys + size)) { 186 unsigned long base = 187 (unsigned long)hose->io_base_virt - _IO_BASE; 188 ret = base + (address - hose->io_base_phys); 189 break; 190 } 191 } 192 spin_unlock(&hose_spinlock); 193 194 return ret; 195} 196EXPORT_SYMBOL_GPL(pci_address_to_pio); 197 198/* 199 * Return the domain number for this bus. 200 */ 201int pci_domain_nr(struct pci_bus *bus) 202{ 203 struct pci_controller *hose = pci_bus_to_host(bus); 204 205 return hose->global_number; 206} 207EXPORT_SYMBOL(pci_domain_nr); 208 209/* This routine is meant to be used early during boot, when the 210 * PCI bus numbers have not yet been assigned, and you need to 211 * issue PCI config cycles to an OF device. 212 * It could also be used to "fix" RTAS config cycles if you want 213 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 214 * config cycles. 215 */ 216struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 217{ 218 while(node) { 219 struct pci_controller *hose, *tmp; 220 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 221 if (hose->dn == node) 222 return hose; 223 node = node->parent; 224 } 225 return NULL; 226} 227 228/* 229 * Reads the interrupt pin to determine if interrupt is use by card. 230 * If the interrupt is used, then gets the interrupt line from the 231 * openfirmware and sets it in the pci_dev and pci_config line. 232 */ 233static int pci_read_irq_line(struct pci_dev *pci_dev) 234{ 235 struct of_phandle_args oirq; 236 unsigned int virq; 237 238 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 239 240#ifdef DEBUG 241 memset(&oirq, 0xff, sizeof(oirq)); 242#endif 243 /* Try to get a mapping from the device-tree */ 244 if (of_irq_parse_pci(pci_dev, &oirq)) { 245 u8 line, pin; 246 247 /* If that fails, lets fallback to what is in the config 248 * space and map that through the default controller. We 249 * also set the type to level low since that's what PCI 250 * interrupts are. If your platform does differently, then 251 * either provide a proper interrupt tree or don't use this 252 * function. 253 */ 254 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 255 return -1; 256 if (pin == 0) 257 return -1; 258 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 259 line == 0xff || line == 0) { 260 return -1; 261 } 262 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 263 line, pin); 264 265 virq = irq_create_mapping(NULL, line); 266 if (virq != NO_IRQ) 267 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 268 } else { 269 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n", 270 oirq.args_count, oirq.args[0], oirq.args[1], 271 of_node_full_name(oirq.np)); 272 273 virq = irq_create_of_mapping(&oirq); 274 } 275 if(virq == NO_IRQ) { 276 pr_debug(" Failed to map !\n"); 277 return -1; 278 } 279 280 pr_debug(" Mapped to linux irq %d\n", virq); 281 282 pci_dev->irq = virq; 283 284 return 0; 285} 286 287/* 288 * Platform support for /proc/bus/pci/X/Y mmap()s, 289 * modelled on the sparc64 implementation by Dave Miller. 290 * -- paulus. 291 */ 292 293/* 294 * Adjust vm_pgoff of VMA such that it is the physical page offset 295 * corresponding to the 32-bit pci bus offset for DEV requested by the user. 296 * 297 * Basically, the user finds the base address for his device which he wishes 298 * to mmap. They read the 32-bit value from the config space base register, 299 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the 300 * offset parameter of mmap on /proc/bus/pci/XXX for that device. 301 * 302 * Returns negative error code on failure, zero on success. 303 */ 304static struct resource *__pci_mmap_make_offset(struct pci_dev *dev, 305 resource_size_t *offset, 306 enum pci_mmap_state mmap_state) 307{ 308 struct pci_controller *hose = pci_bus_to_host(dev->bus); 309 unsigned long io_offset = 0; 310 int i, res_bit; 311 312 if (hose == NULL) 313 return NULL; /* should never happen */ 314 315 /* If memory, add on the PCI bridge address offset */ 316 if (mmap_state == pci_mmap_mem) { 317#if 0 /* See comment in pci_resource_to_user() for why this is disabled */ 318 *offset += hose->pci_mem_offset; 319#endif 320 res_bit = IORESOURCE_MEM; 321 } else { 322 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 323 *offset += io_offset; 324 res_bit = IORESOURCE_IO; 325 } 326 327 /* 328 * Check that the offset requested corresponds to one of the 329 * resources of the device. 330 */ 331 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 332 struct resource *rp = &dev->resource[i]; 333 int flags = rp->flags; 334 335 /* treat ROM as memory (should be already) */ 336 if (i == PCI_ROM_RESOURCE) 337 flags |= IORESOURCE_MEM; 338 339 /* Active and same type? */ 340 if ((flags & res_bit) == 0) 341 continue; 342 343 /* In the range of this resource? */ 344 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end) 345 continue; 346 347 /* found it! construct the final physical address */ 348 if (mmap_state == pci_mmap_io) 349 *offset += hose->io_base_phys - io_offset; 350 return rp; 351 } 352 353 return NULL; 354} 355 356/* 357 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci 358 * device mapping. 359 */ 360static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp, 361 pgprot_t protection, 362 enum pci_mmap_state mmap_state, 363 int write_combine) 364{ 365 366 /* Write combine is always 0 on non-memory space mappings. On 367 * memory space, if the user didn't pass 1, we check for a 368 * "prefetchable" resource. This is a bit hackish, but we use 369 * this to workaround the inability of /sysfs to provide a write 370 * combine bit 371 */ 372 if (mmap_state != pci_mmap_mem) 373 write_combine = 0; 374 else if (write_combine == 0) { 375 if (rp->flags & IORESOURCE_PREFETCH) 376 write_combine = 1; 377 } 378 379 /* XXX would be nice to have a way to ask for write-through */ 380 if (write_combine) 381 return pgprot_noncached_wc(protection); 382 else 383 return pgprot_noncached(protection); 384} 385 386/* 387 * This one is used by /dev/mem and fbdev who have no clue about the 388 * PCI device, it tries to find the PCI device first and calls the 389 * above routine 390 */ 391pgprot_t pci_phys_mem_access_prot(struct file *file, 392 unsigned long pfn, 393 unsigned long size, 394 pgprot_t prot) 395{ 396 struct pci_dev *pdev = NULL; 397 struct resource *found = NULL; 398 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 399 int i; 400 401 if (page_is_ram(pfn)) 402 return prot; 403 404 prot = pgprot_noncached(prot); 405 for_each_pci_dev(pdev) { 406 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 407 struct resource *rp = &pdev->resource[i]; 408 int flags = rp->flags; 409 410 /* Active and same type? */ 411 if ((flags & IORESOURCE_MEM) == 0) 412 continue; 413 /* In the range of this resource? */ 414 if (offset < (rp->start & PAGE_MASK) || 415 offset > rp->end) 416 continue; 417 found = rp; 418 break; 419 } 420 if (found) 421 break; 422 } 423 if (found) { 424 if (found->flags & IORESOURCE_PREFETCH) 425 prot = pgprot_noncached_wc(prot); 426 pci_dev_put(pdev); 427 } 428 429 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 430 (unsigned long long)offset, pgprot_val(prot)); 431 432 return prot; 433} 434 435 436/* 437 * Perform the actual remap of the pages for a PCI device mapping, as 438 * appropriate for this architecture. The region in the process to map 439 * is described by vm_start and vm_end members of VMA, the base physical 440 * address is found in vm_pgoff. 441 * The pci device structure is provided so that architectures may make mapping 442 * decisions on a per-device or per-bus basis. 443 * 444 * Returns a negative error code on failure, zero on success. 445 */ 446int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 447 enum pci_mmap_state mmap_state, int write_combine) 448{ 449 resource_size_t offset = 450 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 451 struct resource *rp; 452 int ret; 453 454 rp = __pci_mmap_make_offset(dev, &offset, mmap_state); 455 if (rp == NULL) 456 return -EINVAL; 457 458 vma->vm_pgoff = offset >> PAGE_SHIFT; 459 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp, 460 vma->vm_page_prot, 461 mmap_state, write_combine); 462 463 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 464 vma->vm_end - vma->vm_start, vma->vm_page_prot); 465 466 return ret; 467} 468 469/* This provides legacy IO read access on a bus */ 470int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 471{ 472 unsigned long offset; 473 struct pci_controller *hose = pci_bus_to_host(bus); 474 struct resource *rp = &hose->io_resource; 475 void __iomem *addr; 476 477 /* Check if port can be supported by that bus. We only check 478 * the ranges of the PHB though, not the bus itself as the rules 479 * for forwarding legacy cycles down bridges are not our problem 480 * here. So if the host bridge supports it, we do it. 481 */ 482 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 483 offset += port; 484 485 if (!(rp->flags & IORESOURCE_IO)) 486 return -ENXIO; 487 if (offset < rp->start || (offset + size) > rp->end) 488 return -ENXIO; 489 addr = hose->io_base_virt + port; 490 491 switch(size) { 492 case 1: 493 *((u8 *)val) = in_8(addr); 494 return 1; 495 case 2: 496 if (port & 1) 497 return -EINVAL; 498 *((u16 *)val) = in_le16(addr); 499 return 2; 500 case 4: 501 if (port & 3) 502 return -EINVAL; 503 *((u32 *)val) = in_le32(addr); 504 return 4; 505 } 506 return -EINVAL; 507} 508 509/* This provides legacy IO write access on a bus */ 510int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 511{ 512 unsigned long offset; 513 struct pci_controller *hose = pci_bus_to_host(bus); 514 struct resource *rp = &hose->io_resource; 515 void __iomem *addr; 516 517 /* Check if port can be supported by that bus. We only check 518 * the ranges of the PHB though, not the bus itself as the rules 519 * for forwarding legacy cycles down bridges are not our problem 520 * here. So if the host bridge supports it, we do it. 521 */ 522 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 523 offset += port; 524 525 if (!(rp->flags & IORESOURCE_IO)) 526 return -ENXIO; 527 if (offset < rp->start || (offset + size) > rp->end) 528 return -ENXIO; 529 addr = hose->io_base_virt + port; 530 531 /* WARNING: The generic code is idiotic. It gets passed a pointer 532 * to what can be a 1, 2 or 4 byte quantity and always reads that 533 * as a u32, which means that we have to correct the location of 534 * the data read within those 32 bits for size 1 and 2 535 */ 536 switch(size) { 537 case 1: 538 out_8(addr, val >> 24); 539 return 1; 540 case 2: 541 if (port & 1) 542 return -EINVAL; 543 out_le16(addr, val >> 16); 544 return 2; 545 case 4: 546 if (port & 3) 547 return -EINVAL; 548 out_le32(addr, val); 549 return 4; 550 } 551 return -EINVAL; 552} 553 554/* This provides legacy IO or memory mmap access on a bus */ 555int pci_mmap_legacy_page_range(struct pci_bus *bus, 556 struct vm_area_struct *vma, 557 enum pci_mmap_state mmap_state) 558{ 559 struct pci_controller *hose = pci_bus_to_host(bus); 560 resource_size_t offset = 561 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 562 resource_size_t size = vma->vm_end - vma->vm_start; 563 struct resource *rp; 564 565 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 566 pci_domain_nr(bus), bus->number, 567 mmap_state == pci_mmap_mem ? "MEM" : "IO", 568 (unsigned long long)offset, 569 (unsigned long long)(offset + size - 1)); 570 571 if (mmap_state == pci_mmap_mem) { 572 /* Hack alert ! 573 * 574 * Because X is lame and can fail starting if it gets an error trying 575 * to mmap legacy_mem (instead of just moving on without legacy memory 576 * access) we fake it here by giving it anonymous memory, effectively 577 * behaving just like /dev/zero 578 */ 579 if ((offset + size) > hose->isa_mem_size) { 580 printk(KERN_DEBUG 581 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 582 current->comm, current->pid, pci_domain_nr(bus), bus->number); 583 if (vma->vm_flags & VM_SHARED) 584 return shmem_zero_setup(vma); 585 return 0; 586 } 587 offset += hose->isa_mem_phys; 588 } else { 589 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 590 unsigned long roffset = offset + io_offset; 591 rp = &hose->io_resource; 592 if (!(rp->flags & IORESOURCE_IO)) 593 return -ENXIO; 594 if (roffset < rp->start || (roffset + size) > rp->end) 595 return -ENXIO; 596 offset += hose->io_base_phys; 597 } 598 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 599 600 vma->vm_pgoff = offset >> PAGE_SHIFT; 601 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 602 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 603 vma->vm_end - vma->vm_start, 604 vma->vm_page_prot); 605} 606 607void pci_resource_to_user(const struct pci_dev *dev, int bar, 608 const struct resource *rsrc, 609 resource_size_t *start, resource_size_t *end) 610{ 611 struct pci_controller *hose = pci_bus_to_host(dev->bus); 612 resource_size_t offset = 0; 613 614 if (hose == NULL) 615 return; 616 617 if (rsrc->flags & IORESOURCE_IO) 618 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 619 620 /* We pass a fully fixed up address to userland for MMIO instead of 621 * a BAR value because X is lame and expects to be able to use that 622 * to pass to /dev/mem ! 623 * 624 * That means that we'll have potentially 64 bits values where some 625 * userland apps only expect 32 (like X itself since it thinks only 626 * Sparc has 64 bits MMIO) but if we don't do that, we break it on 627 * 32 bits CHRPs :-( 628 * 629 * Hopefully, the sysfs insterface is immune to that gunk. Once X 630 * has been fixed (and the fix spread enough), we can re-enable the 631 * 2 lines below and pass down a BAR value to userland. In that case 632 * we'll also have to re-enable the matching code in 633 * __pci_mmap_make_offset(). 634 * 635 * BenH. 636 */ 637#if 0 638 else if (rsrc->flags & IORESOURCE_MEM) 639 offset = hose->pci_mem_offset; 640#endif 641 642 *start = rsrc->start - offset; 643 *end = rsrc->end - offset; 644} 645 646/** 647 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 648 * @hose: newly allocated pci_controller to be setup 649 * @dev: device node of the host bridge 650 * @primary: set if primary bus (32 bits only, soon to be deprecated) 651 * 652 * This function will parse the "ranges" property of a PCI host bridge device 653 * node and setup the resource mapping of a pci controller based on its 654 * content. 655 * 656 * Life would be boring if it wasn't for a few issues that we have to deal 657 * with here: 658 * 659 * - We can only cope with one IO space range and up to 3 Memory space 660 * ranges. However, some machines (thanks Apple !) tend to split their 661 * space into lots of small contiguous ranges. So we have to coalesce. 662 * 663 * - Some busses have IO space not starting at 0, which causes trouble with 664 * the way we do our IO resource renumbering. The code somewhat deals with 665 * it for 64 bits but I would expect problems on 32 bits. 666 * 667 * - Some 32 bits platforms such as 4xx can have physical space larger than 668 * 32 bits so we need to use 64 bits values for the parsing 669 */ 670void pci_process_bridge_OF_ranges(struct pci_controller *hose, 671 struct device_node *dev, int primary) 672{ 673 int memno = 0; 674 struct resource *res; 675 struct of_pci_range range; 676 struct of_pci_range_parser parser; 677 678 printk(KERN_INFO "PCI host bridge %s %s ranges:\n", 679 dev->full_name, primary ? "(primary)" : ""); 680 681 /* Check for ranges property */ 682 if (of_pci_range_parser_init(&parser, dev)) 683 return; 684 685 /* Parse it */ 686 for_each_of_pci_range(&parser, &range) { 687 /* If we failed translation or got a zero-sized region 688 * (some FW try to feed us with non sensical zero sized regions 689 * such as power3 which look like some kind of attempt at exposing 690 * the VGA memory hole) 691 */ 692 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 693 continue; 694 695 /* Act based on address space type */ 696 res = NULL; 697 switch (range.flags & IORESOURCE_TYPE_BITS) { 698 case IORESOURCE_IO: 699 printk(KERN_INFO 700 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 701 range.cpu_addr, range.cpu_addr + range.size - 1, 702 range.pci_addr); 703 704 /* We support only one IO range */ 705 if (hose->pci_io_size) { 706 printk(KERN_INFO 707 " \\--> Skipped (too many) !\n"); 708 continue; 709 } 710#ifdef CONFIG_PPC32 711 /* On 32 bits, limit I/O space to 16MB */ 712 if (range.size > 0x01000000) 713 range.size = 0x01000000; 714 715 /* 32 bits needs to map IOs here */ 716 hose->io_base_virt = ioremap(range.cpu_addr, 717 range.size); 718 719 /* Expect trouble if pci_addr is not 0 */ 720 if (primary) 721 isa_io_base = 722 (unsigned long)hose->io_base_virt; 723#endif /* CONFIG_PPC32 */ 724 /* pci_io_size and io_base_phys always represent IO 725 * space starting at 0 so we factor in pci_addr 726 */ 727 hose->pci_io_size = range.pci_addr + range.size; 728 hose->io_base_phys = range.cpu_addr - range.pci_addr; 729 730 /* Build resource */ 731 res = &hose->io_resource; 732 range.cpu_addr = range.pci_addr; 733 break; 734 case IORESOURCE_MEM: 735 printk(KERN_INFO 736 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 737 range.cpu_addr, range.cpu_addr + range.size - 1, 738 range.pci_addr, 739 (range.pci_space & 0x40000000) ? 740 "Prefetch" : ""); 741 742 /* We support only 3 memory ranges */ 743 if (memno >= 3) { 744 printk(KERN_INFO 745 " \\--> Skipped (too many) !\n"); 746 continue; 747 } 748 /* Handles ISA memory hole space here */ 749 if (range.pci_addr == 0) { 750 if (primary || isa_mem_base == 0) 751 isa_mem_base = range.cpu_addr; 752 hose->isa_mem_phys = range.cpu_addr; 753 hose->isa_mem_size = range.size; 754 } 755 756 /* Build resource */ 757 hose->mem_offset[memno] = range.cpu_addr - 758 range.pci_addr; 759 res = &hose->mem_resources[memno++]; 760 break; 761 } 762 if (res != NULL) { 763 res->name = dev->full_name; 764 res->flags = range.flags; 765 res->start = range.cpu_addr; 766 res->end = range.cpu_addr + range.size - 1; 767 res->parent = res->child = res->sibling = NULL; 768 } 769 } 770} 771 772/* Decide whether to display the domain number in /proc */ 773int pci_proc_domain(struct pci_bus *bus) 774{ 775 struct pci_controller *hose = pci_bus_to_host(bus); 776 777 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 778 return 0; 779 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 780 return hose->global_number != 0; 781 return 1; 782} 783 784int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 785{ 786 if (ppc_md.pcibios_root_bridge_prepare) 787 return ppc_md.pcibios_root_bridge_prepare(bridge); 788 789 return 0; 790} 791 792/* This header fixup will do the resource fixup for all devices as they are 793 * probed, but not for bridge ranges 794 */ 795static void pcibios_fixup_resources(struct pci_dev *dev) 796{ 797 struct pci_controller *hose = pci_bus_to_host(dev->bus); 798 int i; 799 800 if (!hose) { 801 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 802 pci_name(dev)); 803 return; 804 } 805 806 if (dev->is_virtfn) 807 return; 808 809 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 810 struct resource *res = dev->resource + i; 811 struct pci_bus_region reg; 812 if (!res->flags) 813 continue; 814 815 /* If we're going to re-assign everything, we mark all resources 816 * as unset (and 0-base them). In addition, we mark BARs starting 817 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 818 * since in that case, we don't want to re-assign anything 819 */ 820 pcibios_resource_to_bus(dev->bus, ®, res); 821 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 822 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 823 /* Only print message if not re-assigning */ 824 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 825 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 826 "is unassigned\n", 827 pci_name(dev), i, 828 (unsigned long long)res->start, 829 (unsigned long long)res->end, 830 (unsigned int)res->flags); 831 res->end -= res->start; 832 res->start = 0; 833 res->flags |= IORESOURCE_UNSET; 834 continue; 835 } 836 837 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", 838 pci_name(dev), i, 839 (unsigned long long)res->start,\ 840 (unsigned long long)res->end, 841 (unsigned int)res->flags); 842 } 843 844 /* Call machine specific resource fixup */ 845 if (ppc_md.pcibios_fixup_resources) 846 ppc_md.pcibios_fixup_resources(dev); 847} 848DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 849 850/* This function tries to figure out if a bridge resource has been initialized 851 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 852 * things go more smoothly when it gets it right. It should covers cases such 853 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 854 */ 855static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 856 struct resource *res) 857{ 858 struct pci_controller *hose = pci_bus_to_host(bus); 859 struct pci_dev *dev = bus->self; 860 resource_size_t offset; 861 struct pci_bus_region region; 862 u16 command; 863 int i; 864 865 /* We don't do anything if PCI_PROBE_ONLY is set */ 866 if (pci_has_flag(PCI_PROBE_ONLY)) 867 return 0; 868 869 /* Job is a bit different between memory and IO */ 870 if (res->flags & IORESOURCE_MEM) { 871 pcibios_resource_to_bus(dev->bus, ®ion, res); 872 873 /* If the BAR is non-0 then it's probably been initialized */ 874 if (region.start != 0) 875 return 0; 876 877 /* The BAR is 0, let's check if memory decoding is enabled on 878 * the bridge. If not, we consider it unassigned 879 */ 880 pci_read_config_word(dev, PCI_COMMAND, &command); 881 if ((command & PCI_COMMAND_MEMORY) == 0) 882 return 1; 883 884 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 885 * resources covers that starting address (0 then it's good enough for 886 * us for memory space) 887 */ 888 for (i = 0; i < 3; i++) { 889 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 890 hose->mem_resources[i].start == hose->mem_offset[i]) 891 return 0; 892 } 893 894 /* Well, it starts at 0 and we know it will collide so we may as 895 * well consider it as unassigned. That covers the Apple case. 896 */ 897 return 1; 898 } else { 899 /* If the BAR is non-0, then we consider it assigned */ 900 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 901 if (((res->start - offset) & 0xfffffffful) != 0) 902 return 0; 903 904 /* Here, we are a bit different than memory as typically IO space 905 * starting at low addresses -is- valid. What we do instead if that 906 * we consider as unassigned anything that doesn't have IO enabled 907 * in the PCI command register, and that's it. 908 */ 909 pci_read_config_word(dev, PCI_COMMAND, &command); 910 if (command & PCI_COMMAND_IO) 911 return 0; 912 913 /* It's starting at 0 and IO is disabled in the bridge, consider 914 * it unassigned 915 */ 916 return 1; 917 } 918} 919 920/* Fixup resources of a PCI<->PCI bridge */ 921static void pcibios_fixup_bridge(struct pci_bus *bus) 922{ 923 struct resource *res; 924 int i; 925 926 struct pci_dev *dev = bus->self; 927 928 pci_bus_for_each_resource(bus, res, i) { 929 if (!res || !res->flags) 930 continue; 931 if (i >= 3 && bus->self->transparent) 932 continue; 933 934 /* If we're going to reassign everything, we can 935 * shrink the P2P resource to have size as being 936 * of 0 in order to save space. 937 */ 938 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 939 res->flags |= IORESOURCE_UNSET; 940 res->start = 0; 941 res->end = -1; 942 continue; 943 } 944 945 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x]\n", 946 pci_name(dev), i, 947 (unsigned long long)res->start,\ 948 (unsigned long long)res->end, 949 (unsigned int)res->flags); 950 951 /* Try to detect uninitialized P2P bridge resources, 952 * and clear them out so they get re-assigned later 953 */ 954 if (pcibios_uninitialized_bridge_resource(bus, res)) { 955 res->flags = 0; 956 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 957 } 958 } 959} 960 961void pcibios_setup_bus_self(struct pci_bus *bus) 962{ 963 struct pci_controller *phb; 964 965 /* Fix up the bus resources for P2P bridges */ 966 if (bus->self != NULL) 967 pcibios_fixup_bridge(bus); 968 969 /* Platform specific bus fixups. This is currently only used 970 * by fsl_pci and I'm hoping to get rid of it at some point 971 */ 972 if (ppc_md.pcibios_fixup_bus) 973 ppc_md.pcibios_fixup_bus(bus); 974 975 /* Setup bus DMA mappings */ 976 phb = pci_bus_to_host(bus); 977 if (phb->controller_ops.dma_bus_setup) 978 phb->controller_ops.dma_bus_setup(bus); 979} 980 981static void pcibios_setup_device(struct pci_dev *dev) 982{ 983 struct pci_controller *phb; 984 /* Fixup NUMA node as it may not be setup yet by the generic 985 * code and is needed by the DMA init 986 */ 987 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 988 989 /* Hook up default DMA ops */ 990 set_dma_ops(&dev->dev, pci_dma_ops); 991 set_dma_offset(&dev->dev, PCI_DRAM_OFFSET); 992 993 /* Additional platform DMA/iommu setup */ 994 phb = pci_bus_to_host(dev->bus); 995 if (phb->controller_ops.dma_dev_setup) 996 phb->controller_ops.dma_dev_setup(dev); 997 998 /* Read default IRQs and fixup if necessary */ 999 pci_read_irq_line(dev); 1000 if (ppc_md.pci_irq_fixup) 1001 ppc_md.pci_irq_fixup(dev); 1002} 1003 1004int pcibios_add_device(struct pci_dev *dev) 1005{ 1006 /* 1007 * We can only call pcibios_setup_device() after bus setup is complete, 1008 * since some of the platform specific DMA setup code depends on it. 1009 */ 1010 if (dev->bus->is_added) 1011 pcibios_setup_device(dev); 1012 1013#ifdef CONFIG_PCI_IOV 1014 if (ppc_md.pcibios_fixup_sriov) 1015 ppc_md.pcibios_fixup_sriov(dev); 1016#endif /* CONFIG_PCI_IOV */ 1017 1018 return 0; 1019} 1020 1021void pcibios_setup_bus_devices(struct pci_bus *bus) 1022{ 1023 struct pci_dev *dev; 1024 1025 pr_debug("PCI: Fixup bus devices %d (%s)\n", 1026 bus->number, bus->self ? pci_name(bus->self) : "PHB"); 1027 1028 list_for_each_entry(dev, &bus->devices, bus_list) { 1029 /* Cardbus can call us to add new devices to a bus, so ignore 1030 * those who are already fully discovered 1031 */ 1032 if (dev->is_added) 1033 continue; 1034 1035 pcibios_setup_device(dev); 1036 } 1037} 1038 1039void pcibios_set_master(struct pci_dev *dev) 1040{ 1041 /* No special bus mastering setup handling */ 1042} 1043 1044void pcibios_fixup_bus(struct pci_bus *bus) 1045{ 1046 /* When called from the generic PCI probe, read PCI<->PCI bridge 1047 * bases. This is -not- called when generating the PCI tree from 1048 * the OF device-tree. 1049 */ 1050 pci_read_bridge_bases(bus); 1051 1052 /* Now fixup the bus bus */ 1053 pcibios_setup_bus_self(bus); 1054 1055 /* Now fixup devices on that bus */ 1056 pcibios_setup_bus_devices(bus); 1057} 1058EXPORT_SYMBOL(pcibios_fixup_bus); 1059 1060void pci_fixup_cardbus(struct pci_bus *bus) 1061{ 1062 /* Now fixup devices on that bus */ 1063 pcibios_setup_bus_devices(bus); 1064} 1065 1066 1067static int skip_isa_ioresource_align(struct pci_dev *dev) 1068{ 1069 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1070 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1071 return 1; 1072 return 0; 1073} 1074 1075/* 1076 * We need to avoid collisions with `mirrored' VGA ports 1077 * and other strange ISA hardware, so we always want the 1078 * addresses to be allocated in the 0x000-0x0ff region 1079 * modulo 0x400. 1080 * 1081 * Why? Because some silly external IO cards only decode 1082 * the low 10 bits of the IO address. The 0x00-0xff region 1083 * is reserved for motherboard devices that decode all 16 1084 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1085 * but we want to try to avoid allocating at 0x2900-0x2bff 1086 * which might have be mirrored at 0x0100-0x03ff.. 1087 */ 1088resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1089 resource_size_t size, resource_size_t align) 1090{ 1091 struct pci_dev *dev = data; 1092 resource_size_t start = res->start; 1093 1094 if (res->flags & IORESOURCE_IO) { 1095 if (skip_isa_ioresource_align(dev)) 1096 return start; 1097 if (start & 0x300) 1098 start = (start + 0x3ff) & ~0x3ff; 1099 } 1100 1101 return start; 1102} 1103EXPORT_SYMBOL(pcibios_align_resource); 1104 1105/* 1106 * Reparent resource children of pr that conflict with res 1107 * under res, and make res replace those children. 1108 */ 1109static int reparent_resources(struct resource *parent, 1110 struct resource *res) 1111{ 1112 struct resource *p, **pp; 1113 struct resource **firstpp = NULL; 1114 1115 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1116 if (p->end < res->start) 1117 continue; 1118 if (res->end < p->start) 1119 break; 1120 if (p->start < res->start || p->end > res->end) 1121 return -1; /* not completely contained */ 1122 if (firstpp == NULL) 1123 firstpp = pp; 1124 } 1125 if (firstpp == NULL) 1126 return -1; /* didn't find any conflicting entries? */ 1127 res->parent = parent; 1128 res->child = *firstpp; 1129 res->sibling = *pp; 1130 *firstpp = res; 1131 *pp = NULL; 1132 for (p = res->child; p != NULL; p = p->sibling) { 1133 p->parent = res; 1134 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", 1135 p->name, 1136 (unsigned long long)p->start, 1137 (unsigned long long)p->end, res->name); 1138 } 1139 return 0; 1140} 1141 1142/* 1143 * Handle resources of PCI devices. If the world were perfect, we could 1144 * just allocate all the resource regions and do nothing more. It isn't. 1145 * On the other hand, we cannot just re-allocate all devices, as it would 1146 * require us to know lots of host bridge internals. So we attempt to 1147 * keep as much of the original configuration as possible, but tweak it 1148 * when it's found to be wrong. 1149 * 1150 * Known BIOS problems we have to work around: 1151 * - I/O or memory regions not configured 1152 * - regions configured, but not enabled in the command register 1153 * - bogus I/O addresses above 64K used 1154 * - expansion ROMs left enabled (this may sound harmless, but given 1155 * the fact the PCI specs explicitly allow address decoders to be 1156 * shared between expansion ROMs and other resource regions, it's 1157 * at least dangerous) 1158 * 1159 * Our solution: 1160 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1161 * This gives us fixed barriers on where we can allocate. 1162 * (2) Allocate resources for all enabled devices. If there is 1163 * a collision, just mark the resource as unallocated. Also 1164 * disable expansion ROMs during this step. 1165 * (3) Try to allocate resources for disabled devices. If the 1166 * resources were assigned correctly, everything goes well, 1167 * if they weren't, they won't disturb allocation of other 1168 * resources. 1169 * (4) Assign new addresses to resources which were either 1170 * not configured at all or misconfigured. If explicitly 1171 * requested by the user, configure expansion ROM address 1172 * as well. 1173 */ 1174 1175static void pcibios_allocate_bus_resources(struct pci_bus *bus) 1176{ 1177 struct pci_bus *b; 1178 int i; 1179 struct resource *res, *pr; 1180 1181 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1182 pci_domain_nr(bus), bus->number); 1183 1184 pci_bus_for_each_resource(bus, res, i) { 1185 if (!res || !res->flags || res->start > res->end || res->parent) 1186 continue; 1187 1188 /* If the resource was left unset at this point, we clear it */ 1189 if (res->flags & IORESOURCE_UNSET) 1190 goto clear_resource; 1191 1192 if (bus->parent == NULL) 1193 pr = (res->flags & IORESOURCE_IO) ? 1194 &ioport_resource : &iomem_resource; 1195 else { 1196 pr = pci_find_parent_resource(bus->self, res); 1197 if (pr == res) { 1198 /* this happens when the generic PCI 1199 * code (wrongly) decides that this 1200 * bridge is transparent -- paulus 1201 */ 1202 continue; 1203 } 1204 } 1205 1206 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx " 1207 "[0x%x], parent %p (%s)\n", 1208 bus->self ? pci_name(bus->self) : "PHB", 1209 bus->number, i, 1210 (unsigned long long)res->start, 1211 (unsigned long long)res->end, 1212 (unsigned int)res->flags, 1213 pr, (pr && pr->name) ? pr->name : "nil"); 1214 1215 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1216 struct pci_dev *dev = bus->self; 1217 1218 if (request_resource(pr, res) == 0) 1219 continue; 1220 /* 1221 * Must be a conflict with an existing entry. 1222 * Move that entry (or entries) under the 1223 * bridge resource and try again. 1224 */ 1225 if (reparent_resources(pr, res) == 0) 1226 continue; 1227 1228 if (dev && i < PCI_BRIDGE_RESOURCE_NUM && 1229 pci_claim_bridge_resource(dev, 1230 i + PCI_BRIDGE_RESOURCES) == 0) 1231 continue; 1232 } 1233 pr_warning("PCI: Cannot allocate resource region " 1234 "%d of PCI bridge %d, will remap\n", i, bus->number); 1235 clear_resource: 1236 /* The resource might be figured out when doing 1237 * reassignment based on the resources required 1238 * by the downstream PCI devices. Here we set 1239 * the size of the resource to be 0 in order to 1240 * save more space. 1241 */ 1242 res->start = 0; 1243 res->end = -1; 1244 res->flags = 0; 1245 } 1246 1247 list_for_each_entry(b, &bus->children, node) 1248 pcibios_allocate_bus_resources(b); 1249} 1250 1251static inline void alloc_resource(struct pci_dev *dev, int idx) 1252{ 1253 struct resource *pr, *r = &dev->resource[idx]; 1254 1255 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", 1256 pci_name(dev), idx, 1257 (unsigned long long)r->start, 1258 (unsigned long long)r->end, 1259 (unsigned int)r->flags); 1260 1261 pr = pci_find_parent_resource(dev, r); 1262 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1263 request_resource(pr, r) < 0) { 1264 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1265 " of device %s, will remap\n", idx, pci_name(dev)); 1266 if (pr) 1267 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", 1268 pr, 1269 (unsigned long long)pr->start, 1270 (unsigned long long)pr->end, 1271 (unsigned int)pr->flags); 1272 /* We'll assign a new address later */ 1273 r->flags |= IORESOURCE_UNSET; 1274 r->end -= r->start; 1275 r->start = 0; 1276 } 1277} 1278 1279static void __init pcibios_allocate_resources(int pass) 1280{ 1281 struct pci_dev *dev = NULL; 1282 int idx, disabled; 1283 u16 command; 1284 struct resource *r; 1285 1286 for_each_pci_dev(dev) { 1287 pci_read_config_word(dev, PCI_COMMAND, &command); 1288 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1289 r = &dev->resource[idx]; 1290 if (r->parent) /* Already allocated */ 1291 continue; 1292 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1293 continue; /* Not assigned at all */ 1294 /* We only allocate ROMs on pass 1 just in case they 1295 * have been screwed up by firmware 1296 */ 1297 if (idx == PCI_ROM_RESOURCE ) 1298 disabled = 1; 1299 if (r->flags & IORESOURCE_IO) 1300 disabled = !(command & PCI_COMMAND_IO); 1301 else 1302 disabled = !(command & PCI_COMMAND_MEMORY); 1303 if (pass == disabled) 1304 alloc_resource(dev, idx); 1305 } 1306 if (pass) 1307 continue; 1308 r = &dev->resource[PCI_ROM_RESOURCE]; 1309 if (r->flags) { 1310 /* Turn the ROM off, leave the resource region, 1311 * but keep it unregistered. 1312 */ 1313 u32 reg; 1314 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1315 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1316 pr_debug("PCI: Switching off ROM of %s\n", 1317 pci_name(dev)); 1318 r->flags &= ~IORESOURCE_ROM_ENABLE; 1319 pci_write_config_dword(dev, dev->rom_base_reg, 1320 reg & ~PCI_ROM_ADDRESS_ENABLE); 1321 } 1322 } 1323 } 1324} 1325 1326static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1327{ 1328 struct pci_controller *hose = pci_bus_to_host(bus); 1329 resource_size_t offset; 1330 struct resource *res, *pres; 1331 int i; 1332 1333 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1334 1335 /* Check for IO */ 1336 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1337 goto no_io; 1338 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1339 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1340 BUG_ON(res == NULL); 1341 res->name = "Legacy IO"; 1342 res->flags = IORESOURCE_IO; 1343 res->start = offset; 1344 res->end = (offset + 0xfff) & 0xfffffffful; 1345 pr_debug("Candidate legacy IO: %pR\n", res); 1346 if (request_resource(&hose->io_resource, res)) { 1347 printk(KERN_DEBUG 1348 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1349 pci_domain_nr(bus), bus->number, res); 1350 kfree(res); 1351 } 1352 1353 no_io: 1354 /* Check for memory */ 1355 for (i = 0; i < 3; i++) { 1356 pres = &hose->mem_resources[i]; 1357 offset = hose->mem_offset[i]; 1358 if (!(pres->flags & IORESOURCE_MEM)) 1359 continue; 1360 pr_debug("hose mem res: %pR\n", pres); 1361 if ((pres->start - offset) <= 0xa0000 && 1362 (pres->end - offset) >= 0xbffff) 1363 break; 1364 } 1365 if (i >= 3) 1366 return; 1367 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1368 BUG_ON(res == NULL); 1369 res->name = "Legacy VGA memory"; 1370 res->flags = IORESOURCE_MEM; 1371 res->start = 0xa0000 + offset; 1372 res->end = 0xbffff + offset; 1373 pr_debug("Candidate VGA memory: %pR\n", res); 1374 if (request_resource(pres, res)) { 1375 printk(KERN_DEBUG 1376 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1377 pci_domain_nr(bus), bus->number, res); 1378 kfree(res); 1379 } 1380} 1381 1382void __init pcibios_resource_survey(void) 1383{ 1384 struct pci_bus *b; 1385 1386 /* Allocate and assign resources */ 1387 list_for_each_entry(b, &pci_root_buses, node) 1388 pcibios_allocate_bus_resources(b); 1389 pcibios_allocate_resources(0); 1390 pcibios_allocate_resources(1); 1391 1392 /* Before we start assigning unassigned resource, we try to reserve 1393 * the low IO area and the VGA memory area if they intersect the 1394 * bus available resources to avoid allocating things on top of them 1395 */ 1396 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1397 list_for_each_entry(b, &pci_root_buses, node) 1398 pcibios_reserve_legacy_regions(b); 1399 } 1400 1401 /* Now, if the platform didn't decide to blindly trust the firmware, 1402 * we proceed to assigning things that were left unassigned 1403 */ 1404 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1405 pr_debug("PCI: Assigning unassigned resources...\n"); 1406 pci_assign_unassigned_resources(); 1407 } 1408 1409 /* Call machine dependent fixup */ 1410 if (ppc_md.pcibios_fixup) 1411 ppc_md.pcibios_fixup(); 1412} 1413 1414/* This is used by the PCI hotplug driver to allocate resource 1415 * of newly plugged busses. We can try to consolidate with the 1416 * rest of the code later, for now, keep it as-is as our main 1417 * resource allocation function doesn't deal with sub-trees yet. 1418 */ 1419void pcibios_claim_one_bus(struct pci_bus *bus) 1420{ 1421 struct pci_dev *dev; 1422 struct pci_bus *child_bus; 1423 1424 list_for_each_entry(dev, &bus->devices, bus_list) { 1425 int i; 1426 1427 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 1428 struct resource *r = &dev->resource[i]; 1429 1430 if (r->parent || !r->start || !r->flags) 1431 continue; 1432 1433 pr_debug("PCI: Claiming %s: " 1434 "Resource %d: %016llx..%016llx [%x]\n", 1435 pci_name(dev), i, 1436 (unsigned long long)r->start, 1437 (unsigned long long)r->end, 1438 (unsigned int)r->flags); 1439 1440 if (pci_claim_resource(dev, i) == 0) 1441 continue; 1442 1443 pci_claim_bridge_resource(dev, i); 1444 } 1445 } 1446 1447 list_for_each_entry(child_bus, &bus->children, node) 1448 pcibios_claim_one_bus(child_bus); 1449} 1450 1451 1452/* pcibios_finish_adding_to_bus 1453 * 1454 * This is to be called by the hotplug code after devices have been 1455 * added to a bus, this include calling it for a PHB that is just 1456 * being added 1457 */ 1458void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1459{ 1460 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1461 pci_domain_nr(bus), bus->number); 1462 1463 /* Allocate bus and devices resources */ 1464 pcibios_allocate_bus_resources(bus); 1465 pcibios_claim_one_bus(bus); 1466 if (!pci_has_flag(PCI_PROBE_ONLY)) 1467 pci_assign_unassigned_bus_resources(bus); 1468 1469 /* Fixup EEH */ 1470 eeh_add_device_tree_late(bus); 1471 1472 /* Add new devices to global lists. Register in proc, sysfs. */ 1473 pci_bus_add_devices(bus); 1474 1475 /* sysfs files should only be added after devices are added */ 1476 eeh_add_sysfs_files(bus); 1477} 1478EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1479 1480int pcibios_enable_device(struct pci_dev *dev, int mask) 1481{ 1482 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1483 1484 if (phb->controller_ops.enable_device_hook) 1485 if (!phb->controller_ops.enable_device_hook(dev)) 1486 return -EINVAL; 1487 1488 return pci_enable_resources(dev, mask); 1489} 1490 1491resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1492{ 1493 return (unsigned long) hose->io_base_virt - _IO_BASE; 1494} 1495 1496static void pcibios_setup_phb_resources(struct pci_controller *hose, 1497 struct list_head *resources) 1498{ 1499 struct resource *res; 1500 resource_size_t offset; 1501 int i; 1502 1503 /* Hookup PHB IO resource */ 1504 res = &hose->io_resource; 1505 1506 if (!res->flags) { 1507 pr_info("PCI: I/O resource not set for host" 1508 " bridge %s (domain %d)\n", 1509 hose->dn->full_name, hose->global_number); 1510 } else { 1511 offset = pcibios_io_space_offset(hose); 1512 1513 pr_debug("PCI: PHB IO resource = %08llx-%08llx [%lx] off 0x%08llx\n", 1514 (unsigned long long)res->start, 1515 (unsigned long long)res->end, 1516 (unsigned long)res->flags, 1517 (unsigned long long)offset); 1518 pci_add_resource_offset(resources, res, offset); 1519 } 1520 1521 /* Hookup PHB Memory resources */ 1522 for (i = 0; i < 3; ++i) { 1523 res = &hose->mem_resources[i]; 1524 if (!res->flags) { 1525 if (i == 0) 1526 printk(KERN_ERR "PCI: Memory resource 0 not set for " 1527 "host bridge %s (domain %d)\n", 1528 hose->dn->full_name, hose->global_number); 1529 continue; 1530 } 1531 offset = hose->mem_offset[i]; 1532 1533 1534 pr_debug("PCI: PHB MEM resource %d = %08llx-%08llx [%lx] off 0x%08llx\n", i, 1535 (unsigned long long)res->start, 1536 (unsigned long long)res->end, 1537 (unsigned long)res->flags, 1538 (unsigned long long)offset); 1539 1540 pci_add_resource_offset(resources, res, offset); 1541 } 1542} 1543 1544/* 1545 * Null PCI config access functions, for the case when we can't 1546 * find a hose. 1547 */ 1548#define NULL_PCI_OP(rw, size, type) \ 1549static int \ 1550null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1551{ \ 1552 return PCIBIOS_DEVICE_NOT_FOUND; \ 1553} 1554 1555static int 1556null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1557 int len, u32 *val) 1558{ 1559 return PCIBIOS_DEVICE_NOT_FOUND; 1560} 1561 1562static int 1563null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1564 int len, u32 val) 1565{ 1566 return PCIBIOS_DEVICE_NOT_FOUND; 1567} 1568 1569static struct pci_ops null_pci_ops = 1570{ 1571 .read = null_read_config, 1572 .write = null_write_config, 1573}; 1574 1575/* 1576 * These functions are used early on before PCI scanning is done 1577 * and all of the pci_dev and pci_bus structures have been created. 1578 */ 1579static struct pci_bus * 1580fake_pci_bus(struct pci_controller *hose, int busnr) 1581{ 1582 static struct pci_bus bus; 1583 1584 if (hose == NULL) { 1585 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1586 } 1587 bus.number = busnr; 1588 bus.sysdata = hose; 1589 bus.ops = hose? hose->ops: &null_pci_ops; 1590 return &bus; 1591} 1592 1593#define EARLY_PCI_OP(rw, size, type) \ 1594int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1595 int devfn, int offset, type value) \ 1596{ \ 1597 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1598 devfn, offset, value); \ 1599} 1600 1601EARLY_PCI_OP(read, byte, u8 *) 1602EARLY_PCI_OP(read, word, u16 *) 1603EARLY_PCI_OP(read, dword, u32 *) 1604EARLY_PCI_OP(write, byte, u8) 1605EARLY_PCI_OP(write, word, u16) 1606EARLY_PCI_OP(write, dword, u32) 1607 1608int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1609 int cap) 1610{ 1611 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1612} 1613 1614struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1615{ 1616 struct pci_controller *hose = bus->sysdata; 1617 1618 return of_node_get(hose->dn); 1619} 1620 1621/** 1622 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1623 * @hose: Pointer to the PCI host controller instance structure 1624 */ 1625void pcibios_scan_phb(struct pci_controller *hose) 1626{ 1627 LIST_HEAD(resources); 1628 struct pci_bus *bus; 1629 struct device_node *node = hose->dn; 1630 int mode; 1631 1632 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node)); 1633 1634 /* Get some IO space for the new PHB */ 1635 pcibios_setup_phb_io_space(hose); 1636 1637 /* Wire up PHB bus resources */ 1638 pcibios_setup_phb_resources(hose, &resources); 1639 1640 hose->busn.start = hose->first_busno; 1641 hose->busn.end = hose->last_busno; 1642 hose->busn.flags = IORESOURCE_BUS; 1643 pci_add_resource(&resources, &hose->busn); 1644 1645 /* Create an empty bus for the toplevel */ 1646 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1647 hose->ops, hose, &resources); 1648 if (bus == NULL) { 1649 pr_err("Failed to create bus for PCI domain %04x\n", 1650 hose->global_number); 1651 pci_free_resource_list(&resources); 1652 return; 1653 } 1654 hose->bus = bus; 1655 1656 /* Get probe mode and perform scan */ 1657 mode = PCI_PROBE_NORMAL; 1658 if (node && hose->controller_ops.probe_mode) 1659 mode = hose->controller_ops.probe_mode(bus); 1660 pr_debug(" probe mode: %d\n", mode); 1661 if (mode == PCI_PROBE_DEVTREE) 1662 of_scan_bus(node, bus); 1663 1664 if (mode == PCI_PROBE_NORMAL) { 1665 pci_bus_update_busn_res_end(bus, 255); 1666 hose->last_busno = pci_scan_child_bus(bus); 1667 pci_bus_update_busn_res_end(bus, hose->last_busno); 1668 } 1669 1670 /* Platform gets a chance to do some global fixups before 1671 * we proceed to resource allocation 1672 */ 1673 if (ppc_md.pcibios_fixup_phb) 1674 ppc_md.pcibios_fixup_phb(hose); 1675 1676 /* Configure PCI Express settings */ 1677 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1678 struct pci_bus *child; 1679 list_for_each_entry(child, &bus->children, node) 1680 pcie_bus_configure_settings(child); 1681 } 1682} 1683 1684static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1685{ 1686 int i, class = dev->class >> 8; 1687 /* When configured as agent, programing interface = 1 */ 1688 int prog_if = dev->class & 0xf; 1689 1690 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1691 class == PCI_CLASS_BRIDGE_OTHER) && 1692 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1693 (prog_if == 0) && 1694 (dev->bus->parent == NULL)) { 1695 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1696 dev->resource[i].start = 0; 1697 dev->resource[i].end = 0; 1698 dev->resource[i].flags = 0; 1699 } 1700 } 1701} 1702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1704 1705static void fixup_vga(struct pci_dev *pdev) 1706{ 1707 u16 cmd; 1708 1709 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 1710 if ((cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) || !vga_default_device()) 1711 vga_set_default_device(pdev); 1712 1713} 1714DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1715 PCI_CLASS_DISPLAY_VGA, 8, fixup_vga); 1716