1#ifndef _ASM_POWERPC_KEYLARGO_H
2#define _ASM_POWERPC_KEYLARGO_H
3#ifdef __KERNEL__
4/*
5 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
6 *
7 */
8
9/* "Pangea" chipset has keylargo device-id 0x25 while core99
10 * has device-id 0x22. The rev. of the pangea one is 0, so we
11 * fake an artificial rev. in keylargo_rev by oring 0x100
12 */
13#define KL_PANGEA_REV		0x100
14
15/* offset from base for feature control registers */
16#define KEYLARGO_MBCR		0x34	/* KL Only, Media bay control/status */
17#define KEYLARGO_FCR0		0x38
18#define KEYLARGO_FCR1		0x3c
19#define KEYLARGO_FCR2		0x40
20#define KEYLARGO_FCR3		0x44
21#define KEYLARGO_FCR4		0x48
22#define KEYLARGO_FCR5		0x4c	/* Pangea only */
23
24/* K2 additional FCRs */
25#define K2_FCR6			0x34
26#define K2_FCR7			0x30
27#define K2_FCR8			0x2c
28#define K2_FCR9			0x28
29#define K2_FCR10		0x24
30
31/* GPIO registers */
32#define KEYLARGO_GPIO_LEVELS0		0x50
33#define KEYLARGO_GPIO_LEVELS1		0x54
34#define KEYLARGO_GPIO_EXTINT_0		0x58
35#define KEYLARGO_GPIO_EXTINT_CNT	18
36#define KEYLARGO_GPIO_0			0x6A
37#define KEYLARGO_GPIO_CNT		17
38#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE	0x80
39#define KEYLARGO_GPIO_OUTPUT_ENABLE	0x04
40#define KEYLARGO_GPIO_OUTOUT_DATA	0x01
41#define KEYLARGO_GPIO_INPUT_DATA	0x02
42
43/* K2 does only extint GPIOs and does 51 of them */
44#define K2_GPIO_EXTINT_0		0x58
45#define K2_GPIO_EXTINT_CNT		51
46
47/* Specific GPIO regs */
48
49#define KL_GPIO_MODEM_RESET		(KEYLARGO_GPIO_0+0x03)
50#define KL_GPIO_MODEM_POWER		(KEYLARGO_GPIO_0+0x02) /* Pangea */
51
52#define KL_GPIO_SOUND_POWER		(KEYLARGO_GPIO_0+0x05)
53
54/* Hrm... this one is only to be used on Pismo. It seems to also
55 * control the timebase enable on other machines. Still to be
56 * experimented... --BenH.
57 */
58#define KL_GPIO_FW_CABLE_POWER		(KEYLARGO_GPIO_0+0x09)
59#define KL_GPIO_TB_ENABLE		(KEYLARGO_GPIO_0+0x09)
60
61#define KL_GPIO_ETH_PHY_RESET		(KEYLARGO_GPIO_0+0x10)
62
63#define KL_GPIO_EXTINT_CPU1		(KEYLARGO_GPIO_0+0x0a)
64#define KL_GPIO_EXTINT_CPU1_ASSERT	0x04
65#define KL_GPIO_EXTINT_CPU1_RELEASE	0x38
66
67#define KL_GPIO_RESET_CPU0		(KEYLARGO_GPIO_EXTINT_0+0x03)
68#define KL_GPIO_RESET_CPU1		(KEYLARGO_GPIO_EXTINT_0+0x04)
69#define KL_GPIO_RESET_CPU2		(KEYLARGO_GPIO_EXTINT_0+0x0f)
70#define KL_GPIO_RESET_CPU3		(KEYLARGO_GPIO_EXTINT_0+0x10)
71
72#define KL_GPIO_PMU_MESSAGE_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x09)
73#define KL_GPIO_PMU_MESSAGE_BIT		KEYLARGO_GPIO_INPUT_DATA
74
75#define KL_GPIO_MEDIABAY_IRQ		(KEYLARGO_GPIO_EXTINT_0+0x0e)
76
77#define KL_GPIO_AIRPORT_0		(KEYLARGO_GPIO_EXTINT_0+0x0a)
78#define KL_GPIO_AIRPORT_1		(KEYLARGO_GPIO_EXTINT_0+0x0d)
79#define KL_GPIO_AIRPORT_2		(KEYLARGO_GPIO_0+0x0d)
80#define KL_GPIO_AIRPORT_3		(KEYLARGO_GPIO_0+0x0e)
81#define KL_GPIO_AIRPORT_4		(KEYLARGO_GPIO_0+0x0f)
82
83/*
84 * Bits in feature control register. Those bits different for K2 are
85 * listed separately
86 */
87#define KL_MBCR_MB0_PCI_ENABLE		0x00000800	/* exist ? */
88#define KL_MBCR_MB0_IDE_ENABLE		0x00001000
89#define KL_MBCR_MB0_FLOPPY_ENABLE	0x00002000	/* exist ? */
90#define KL_MBCR_MB0_SOUND_ENABLE	0x00004000	/* hrm... */
91#define KL_MBCR_MB0_DEV_MASK		0x00007800
92#define KL_MBCR_MB0_DEV_POWER		0x00000400
93#define KL_MBCR_MB0_DEV_RESET		0x00000200
94#define KL_MBCR_MB0_ENABLE		0x00000100
95#define KL_MBCR_MB1_PCI_ENABLE		0x08000000	/* exist ? */
96#define KL_MBCR_MB1_IDE_ENABLE		0x10000000
97#define KL_MBCR_MB1_FLOPPY_ENABLE	0x20000000	/* exist ? */
98#define KL_MBCR_MB1_SOUND_ENABLE	0x40000000	/* hrm... */
99#define KL_MBCR_MB1_DEV_MASK		0x78000000
100#define KL_MBCR_MB1_DEV_POWER		0x04000000
101#define KL_MBCR_MB1_DEV_RESET		0x02000000
102#define KL_MBCR_MB1_ENABLE		0x01000000
103
104#define KL0_SCC_B_INTF_ENABLE		0x00000001	/* (KL Only) */
105#define KL0_SCC_A_INTF_ENABLE		0x00000002
106#define KL0_SCC_SLOWPCLK		0x00000004
107#define KL0_SCC_RESET			0x00000008
108#define KL0_SCCA_ENABLE			0x00000010
109#define KL0_SCCB_ENABLE			0x00000020
110#define KL0_SCC_CELL_ENABLE		0x00000040
111#define KL0_IRDA_HIGH_BAND		0x00000100	/* (KL Only) */
112#define KL0_IRDA_SOURCE2_SEL		0x00000200	/* (KL Only) */
113#define KL0_IRDA_SOURCE1_SEL		0x00000400	/* (KL Only) */
114#define KL0_PG_USB0_PMI_ENABLE		0x00000400	/* (Pangea/Intrepid Only) */
115#define KL0_IRDA_RESET			0x00000800	/* (KL Only) */
116#define KL0_PG_USB0_REF_SUSPEND_SEL	0x00000800	/* (Pangea/Intrepid Only) */
117#define KL0_IRDA_DEFAULT1		0x00001000	/* (KL Only) */
118#define KL0_PG_USB0_REF_SUSPEND		0x00001000	/* (Pangea/Intrepid Only) */
119#define KL0_IRDA_DEFAULT0		0x00002000	/* (KL Only) */
120#define KL0_PG_USB0_PAD_SUSPEND		0x00002000	/* (Pangea/Intrepid Only) */
121#define KL0_IRDA_FAST_CONNECT		0x00004000	/* (KL Only) */
122#define KL0_PG_USB1_PMI_ENABLE		0x00004000	/* (Pangea/Intrepid Only) */
123#define KL0_IRDA_ENABLE			0x00008000	/* (KL Only) */
124#define KL0_PG_USB1_REF_SUSPEND_SEL	0x00008000	/* (Pangea/Intrepid Only) */
125#define KL0_IRDA_CLK32_ENABLE		0x00010000	/* (KL Only) */
126#define KL0_PG_USB1_REF_SUSPEND		0x00010000	/* (Pangea/Intrepid Only) */
127#define KL0_IRDA_CLK19_ENABLE		0x00020000	/* (KL Only) */
128#define KL0_PG_USB1_PAD_SUSPEND		0x00020000	/* (Pangea/Intrepid Only) */
129#define KL0_USB0_PAD_SUSPEND0		0x00040000
130#define KL0_USB0_PAD_SUSPEND1		0x00080000
131#define KL0_USB0_CELL_ENABLE		0x00100000
132#define KL0_USB1_PAD_SUSPEND0		0x00400000
133#define KL0_USB1_PAD_SUSPEND1		0x00800000
134#define KL0_USB1_CELL_ENABLE		0x01000000
135#define KL0_USB_REF_SUSPEND		0x10000000	/* (KL Only) */
136
137#define KL0_SERIAL_ENABLE		(KL0_SCC_B_INTF_ENABLE | \
138					KL0_SCC_SLOWPCLK | \
139					KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
140
141#define KL1_USB2_PMI_ENABLE		0x00000001	/* Intrepid only */
142#define KL1_AUDIO_SEL_22MCLK		0x00000002	/* KL/Pangea only */
143#define KL1_USB2_REF_SUSPEND_SEL	0x00000002	/* Intrepid only */
144#define KL1_USB2_REF_SUSPEND		0x00000004	/* Intrepid only */
145#define KL1_AUDIO_CLK_ENABLE_BIT	0x00000008	/* KL/Pangea only */
146#define KL1_USB2_PAD_SUSPEND_SEL	0x00000008	/* Intrepid only */
147#define KL1_USB2_PAD_SUSPEND0		0x00000010	/* Intrepid only */
148#define KL1_AUDIO_CLK_OUT_ENABLE	0x00000020	/* KL/Pangea only */
149#define KL1_USB2_PAD_SUSPEND1		0x00000020	/* Intrepid only */
150#define KL1_AUDIO_CELL_ENABLE		0x00000040	/* KL/Pangea only */
151#define KL1_USB2_CELL_ENABLE		0x00000040	/* Intrepid only */
152#define KL1_AUDIO_CHOOSE		0x00000080	/* KL/Pangea only */
153#define KL1_I2S0_CHOOSE			0x00000200	/* KL Only */
154#define KL1_I2S0_CELL_ENABLE		0x00000400
155#define KL1_I2S0_CLK_ENABLE_BIT		0x00001000
156#define KL1_I2S0_ENABLE			0x00002000
157#define KL1_I2S1_CELL_ENABLE		0x00020000
158#define KL1_I2S1_CLK_ENABLE_BIT		0x00080000
159#define KL1_I2S1_ENABLE			0x00100000
160#define KL1_EIDE0_ENABLE		0x00800000	/* KL/Intrepid Only */
161#define KL1_EIDE0_RESET_N		0x01000000	/* KL/Intrepid Only */
162#define KL1_EIDE1_ENABLE		0x04000000	/* KL Only */
163#define KL1_EIDE1_RESET_N		0x08000000	/* KL Only */
164#define KL1_UIDE_ENABLE			0x20000000	/* KL/Pangea Only */
165#define KL1_UIDE_RESET_N		0x40000000	/* KL/Pangea Only */
166
167#define KL2_IOBUS_ENABLE		0x00000002
168#define KL2_SLEEP_STATE_BIT		0x00000100	/* KL Only */
169#define KL2_PG_STOP_ALL_CLOCKS		0x00000100	/* Pangea Only */
170#define KL2_MPIC_ENABLE			0x00020000
171#define KL2_CARDSLOT_RESET		0x00040000	/* Pangea/Intrepid Only */
172#define KL2_ALT_DATA_OUT		0x02000000	/* KL Only ??? */
173#define KL2_MEM_IS_BIG			0x04000000
174#define KL2_CARDSEL_16			0x08000000
175
176#define KL3_SHUTDOWN_PLL_TOTAL		0x00000001	/* KL/Pangea only */
177#define KL3_SHUTDOWN_PLLKW6		0x00000002	/* KL/Pangea only */
178#define KL3_IT_SHUTDOWN_PLL3		0x00000002	/* Intrepid only */
179#define KL3_SHUTDOWN_PLLKW4		0x00000004	/* KL/Pangea only */
180#define KL3_IT_SHUTDOWN_PLL2		0x00000004	/* Intrepid only */
181#define KL3_SHUTDOWN_PLLKW35		0x00000008	/* KL/Pangea only */
182#define KL3_IT_SHUTDOWN_PLL1		0x00000008	/* Intrepid only */
183#define KL3_SHUTDOWN_PLLKW12		0x00000010	/* KL Only */
184#define KL3_IT_ENABLE_PLL3_SHUTDOWN	0x00000010	/* Intrepid only */
185#define KL3_PLL_RESET			0x00000020	/* KL/Pangea only */
186#define KL3_IT_ENABLE_PLL2_SHUTDOWN	0x00000020	/* Intrepid only */
187#define KL3_IT_ENABLE_PLL1_SHUTDOWN	0x00000010	/* Intrepid only */
188#define KL3_SHUTDOWN_PLL2X		0x00000080	/* KL Only */
189#define KL3_CLK66_ENABLE		0x00000100	/* KL Only */
190#define KL3_CLK49_ENABLE		0x00000200
191#define KL3_CLK45_ENABLE		0x00000400
192#define KL3_CLK31_ENABLE		0x00000800	/* KL/Pangea only */
193#define KL3_TIMER_CLK18_ENABLE		0x00001000
194#define KL3_I2S1_CLK18_ENABLE		0x00002000
195#define KL3_I2S0_CLK18_ENABLE		0x00004000
196#define KL3_VIA_CLK16_ENABLE		0x00008000	/* KL/Pangea only */
197#define KL3_IT_VIA_CLK32_ENABLE		0x00008000	/* Intrepid only */
198#define KL3_STOPPING33_ENABLED		0x00080000	/* KL Only */
199#define KL3_PG_PLL_ENABLE_TEST		0x00080000	/* Pangea Only */
200
201/* Intrepid USB bus 2, port 0,1 */
202#define KL3_IT_PORT_WAKEUP_ENABLE(p)		(0x00080000 << ((p)<<3))
203#define KL3_IT_PORT_RESUME_WAKE_EN(p)		(0x00040000 << ((p)<<3))
204#define KL3_IT_PORT_CONNECT_WAKE_EN(p)		(0x00020000 << ((p)<<3))
205#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p)	(0x00010000 << ((p)<<3))
206#define KL3_IT_PORT_RESUME_STAT(p)		(0x00300000 << ((p)<<3))
207#define KL3_IT_PORT_CONNECT_STAT(p)		(0x00200000 << ((p)<<3))
208#define KL3_IT_PORT_DISCONNECT_STAT(p)		(0x00100000 << ((p)<<3))
209
210/* Port 0,1 : bus 0, port 2,3 : bus 1 */
211#define KL4_PORT_WAKEUP_ENABLE(p)	(0x00000008 << ((p)<<3))
212#define KL4_PORT_RESUME_WAKE_EN(p)	(0x00000004 << ((p)<<3))
213#define KL4_PORT_CONNECT_WAKE_EN(p)	(0x00000002 << ((p)<<3))
214#define KL4_PORT_DISCONNECT_WAKE_EN(p)	(0x00000001 << ((p)<<3))
215#define KL4_PORT_RESUME_STAT(p)		(0x00000040 << ((p)<<3))
216#define KL4_PORT_CONNECT_STAT(p)	(0x00000020 << ((p)<<3))
217#define KL4_PORT_DISCONNECT_STAT(p)	(0x00000010 << ((p)<<3))
218
219/* Pangea and Intrepid only */
220#define KL5_VIA_USE_CLK31		0000000001	/* Pangea Only */
221#define KL5_SCC_USE_CLK31		0x00000002	/* Pangea Only */
222#define KL5_PWM_CLK32_EN		0x00000004
223#define KL5_CLK3_68_EN			0x00000010
224#define KL5_CLK32_EN			0x00000020
225
226
227/* K2 definitions */
228#define K2_FCR0_USB0_SWRESET		0x00200000
229#define K2_FCR0_USB1_SWRESET		0x02000000
230#define K2_FCR0_RING_PME_DISABLE	0x08000000
231
232#define K2_FCR1_PCI1_BUS_RESET_N	0x00000010
233#define K2_FCR1_PCI1_SLEEP_RESET_EN	0x00000020
234#define K2_FCR1_I2S0_CELL_ENABLE	0x00000400
235#define K2_FCR1_I2S0_RESET		0x00000800
236#define K2_FCR1_I2S0_CLK_ENABLE_BIT	0x00001000
237#define K2_FCR1_I2S0_ENABLE    		0x00002000
238#define K2_FCR1_PCI1_CLK_ENABLE		0x00004000
239#define K2_FCR1_FW_CLK_ENABLE		0x00008000
240#define K2_FCR1_FW_RESET_N		0x00010000
241#define K2_FCR1_I2S1_CELL_ENABLE	0x00020000
242#define K2_FCR1_I2S1_CLK_ENABLE_BIT	0x00080000
243#define K2_FCR1_I2S1_ENABLE		0x00100000
244#define K2_FCR1_GMAC_CLK_ENABLE		0x00400000
245#define K2_FCR1_GMAC_POWER_DOWN		0x00800000
246#define K2_FCR1_GMAC_RESET_N		0x01000000
247#define K2_FCR1_SATA_CLK_ENABLE		0x02000000
248#define K2_FCR1_SATA_POWER_DOWN		0x04000000
249#define K2_FCR1_SATA_RESET_N		0x08000000
250#define K2_FCR1_UATA_CLK_ENABLE		0x10000000
251#define K2_FCR1_UATA_RESET_N		0x40000000
252#define K2_FCR1_UATA_CHOOSE_CLK66	0x80000000
253
254/* Shasta definitions */
255#define SH_FCR1_I2S2_CELL_ENABLE	0x00000010
256#define SH_FCR1_I2S2_CLK_ENABLE_BIT	0x00000040
257#define SH_FCR1_I2S2_ENABLE		0x00000080
258#define SH_FCR3_I2S2_CLK18_ENABLE	0x00008000
259
260#endif /* __KERNEL__ */
261#endif /* _ASM_POWERPC_KEYLARGO_H */
262