1/*
2 * T1040RDB/T1042RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *	 notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *	 notice, this list of conditions and the following disclaimer in the
12 *	 documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *	 names of its contributors may be used to endorse or promote products
15 *	 derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36	reserved-memory {
37		#address-cells = <2>;
38		#size-cells = <2>;
39		ranges;
40
41		bman_fbpr: bman-fbpr {
42			size = <0 0x1000000>;
43			alignment = <0 0x1000000>;
44		};
45	};
46
47	ifc: localbus@ffe124000 {
48		reg = <0xf 0xfe124000 0 0x2000>;
49		ranges = <0 0 0xf 0xe8000000 0x08000000
50			  2 0 0xf 0xff800000 0x00010000
51			  3 0 0xf 0xffdf0000 0x00008000>;
52
53		nor@0,0 {
54			#address-cells = <1>;
55			#size-cells = <1>;
56			compatible = "cfi-flash";
57			reg = <0x0 0x0 0x8000000>;
58			bank-width = <2>;
59			device-width = <1>;
60		};
61
62		nand@2,0 {
63			#address-cells = <1>;
64			#size-cells = <1>;
65			compatible = "fsl,ifc-nand";
66			reg = <0x2 0x0 0x10000>;
67		};
68
69		cpld@3,0 {
70			reg = <3 0 0x300>;
71		};
72	};
73
74	memory {
75		device_type = "memory";
76	};
77
78	dcsr: dcsr@f00000000 {
79		ranges = <0x00000000 0xf 0x00000000 0x01072000>;
80	};
81
82	bportals: bman-portals@ff4000000 {
83		ranges = <0x0 0xf 0xf4000000 0x2000000>;
84	};
85
86	soc: soc@ffe000000 {
87		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
88		reg = <0xf 0xfe000000 0 0x00001000>;
89
90		spi@110000 {
91			flash@0 {
92				#address-cells = <1>;
93				#size-cells = <1>;
94				compatible = "micron,n25q512a";
95				reg = <0>;
96				spi-max-frequency = <10000000>; /* input clock */
97			};
98		};
99
100		i2c@118000 {
101			adt7461@4c {
102				compatible = "adi,adt7461";
103				reg = <0x4c>;
104			};
105		};
106
107		i2c@118100 {
108			pca9546@77 {
109				compatible = "nxp,pca9546";
110				reg = <0x77>;
111				#address-cells = <1>;
112				#size-cells = <0>;
113			};
114		};
115
116	};
117
118	pci0: pcie@ffe240000 {
119		reg = <0xf 0xfe240000 0 0x10000>;
120		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
121			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
122		pcie@0 {
123			ranges = <0x02000000 0 0xe0000000
124				  0x02000000 0 0xe0000000
125				  0 0x10000000
126
127				  0x01000000 0 0x00000000
128				  0x01000000 0 0x00000000
129				  0 0x00010000>;
130		};
131	};
132
133	pci1: pcie@ffe250000 {
134		reg = <0xf 0xfe250000 0 0x10000>;
135		ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
136			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
137		pcie@0 {
138			ranges = <0x02000000 0 0xe0000000
139				  0x02000000 0 0xe0000000
140				  0 0x10000000
141
142				  0x01000000 0 0x00000000
143				  0x01000000 0 0x00000000
144				  0 0x00010000>;
145		};
146	};
147
148	pci2: pcie@ffe260000 {
149		reg = <0xf 0xfe260000 0 0x10000>;
150		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
151			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
152		pcie@0 {
153			ranges = <0x02000000 0 0xe0000000
154				  0x02000000 0 0xe0000000
155				  0 0x10000000
156
157				  0x01000000 0 0x00000000
158				  0x01000000 0 0x00000000
159				  0 0x00010000>;
160		};
161	};
162
163	pci3: pcie@ffe270000 {
164		reg = <0xf 0xfe270000 0 0x10000>;
165		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
166			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
167		pcie@0 {
168			ranges = <0x02000000 0 0xe0000000
169				  0x02000000 0 0xe0000000
170				  0 0x10000000
171
172				  0x01000000 0 0x00000000
173				  0x01000000 0 0x00000000
174				  0 0x00010000>;
175		};
176	};
177};
178