1/*
2 * T104xQDS Device Tree Source
3 *
4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *     * Redistributions of source code must retain the above copyright
9 *	 notice, this list of conditions and the following disclaimer.
10 *     * Redistributions in binary form must reproduce the above copyright
11 *	 notice, this list of conditions and the following disclaimer in the
12 *	 documentation and/or other materials provided with the distribution.
13 *     * Neither the name of Freescale Semiconductor nor the
14 *	 names of its contributors may be used to endorse or promote products
15 *	 derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36	model = "fsl,T1040QDS";
37	#address-cells = <2>;
38	#size-cells = <2>;
39	interrupt-parent = <&mpic>;
40
41	reserved-memory {
42		#address-cells = <2>;
43		#size-cells = <2>;
44		ranges;
45
46		bman_fbpr: bman-fbpr {
47			size = <0 0x1000000>;
48			alignment = <0 0x1000000>;
49		};
50	};
51
52	ifc: localbus@ffe124000 {
53		reg = <0xf 0xfe124000 0 0x2000>;
54		ranges = <0 0 0xf 0xe8000000 0x08000000
55			  2 0 0xf 0xff800000 0x00010000
56			  3 0 0xf 0xffdf0000 0x00008000>;
57
58		nor@0,0 {
59			#address-cells = <1>;
60			#size-cells = <1>;
61			compatible = "cfi-flash";
62			reg = <0x0 0x0 0x8000000>;
63
64			bank-width = <2>;
65			device-width = <1>;
66		};
67
68		nand@2,0 {
69			#address-cells = <1>;
70			#size-cells = <1>;
71			compatible = "fsl,ifc-nand";
72			reg = <0x2 0x0 0x10000>;
73		};
74
75		board-control@3,0 {
76			#address-cells = <1>;
77			#size-cells = <1>;
78			compatible = "fsl,fpga-qixis";
79			reg = <3 0 0x300>;
80		};
81	};
82
83	memory {
84		device_type = "memory";
85	};
86
87	dcsr: dcsr@f00000000 {
88		ranges = <0x00000000 0xf 0x00000000 0x01072000>;
89	};
90
91	bportals: bman-portals@ff4000000 {
92		ranges = <0x0 0xf 0xf4000000 0x2000000>;
93	};
94
95	soc: soc@ffe000000 {
96		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
97		reg = <0xf 0xfe000000 0 0x00001000>;
98
99		spi@110000 {
100			flash@0 {
101				#address-cells = <1>;
102				#size-cells = <1>;
103				compatible = "micron,n25q128a11";
104				reg = <0>;
105				spi-max-frequency = <10000000>; /* input clock */
106			};
107		};
108
109		i2c@118000 {
110			pca9547@77 {
111				compatible = "philips,pca9547";
112				reg = <0x77>;
113			};
114			rtc@68 {
115				compatible = "dallas,ds3232";
116				reg = <0x68>;
117				interrupts = <0x1 0x1 0 0>;
118			};
119		};
120	};
121
122	pci0: pcie@ffe240000 {
123		reg = <0xf 0xfe240000 0 0x10000>;
124		ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
125			  0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
126		pcie@0 {
127			ranges = <0x02000000 0 0xe0000000
128				  0x02000000 0 0xe0000000
129				  0 0x10000000
130
131				  0x01000000 0 0x00000000
132				  0x01000000 0 0x00000000
133				  0 0x00010000>;
134		};
135	};
136
137	pci1: pcie@ffe250000 {
138		reg = <0xf 0xfe250000 0 0x10000>;
139		ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
140			  0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
141		pcie@0 {
142			ranges = <0x02000000 0 0xe0000000
143				  0x02000000 0 0xe0000000
144				  0 0x10000000
145
146				  0x01000000 0 0x00000000
147				  0x01000000 0 0x00000000
148				  0 0x00010000>;
149		};
150	};
151
152	pci2: pcie@ffe260000 {
153		reg = <0xf 0xfe260000 0 0x10000>;
154		ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
155			  0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
156		pcie@0 {
157			ranges = <0x02000000 0 0xe0000000
158				  0x02000000 0 0xe0000000
159				  0 0x10000000
160
161				  0x01000000 0 0x00000000
162				  0x01000000 0 0x00000000
163				  0 0x00010000>;
164		};
165	};
166
167	pci3: pcie@ffe270000 {
168		reg = <0xf 0xfe270000 0 0x10000>;
169		ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
170			  0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
171		pcie@0 {
172			ranges = <0x02000000 0 0xe0000000
173				  0x02000000 0 0xe0000000
174				  0 0x10000000
175
176				  0x01000000 0 0x00000000
177				  0x01000000 0 0x00000000
178				  0 0x00010000>;
179		};
180	};
181};
182