1/* Device Tree Source for Motorola PrPMC2800 2 * 3 * Author: Mark A. Greer <mgreer@mvista.com> 4 * 5 * 2007 (c) MontaVista, Software, Inc. This file is licensed under 6 * the terms of the GNU General Public License version 2. This program 7 * is licensed "as is" without any warranty of any kind, whether express 8 * or implied. 9 * 10 * Property values that are labeled as "Default" will be updated by bootwrapper 11 * if it can determine the exact PrPMC type. 12 */ 13 14/dts-v1/; 15 16/ { 17 #address-cells = <1>; 18 #size-cells = <1>; 19 model = "PrPMC280/PrPMC2800"; /* Default */ 20 compatible = "motorola,PrPMC2800"; 21 coherency-off; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 PowerPC,7447 { 28 device_type = "cpu"; 29 reg = <0>; 30 clock-frequency = <733333333>; /* Default */ 31 bus-frequency = <133333333>; 32 timebase-frequency = <33333333>; 33 i-cache-line-size = <32>; 34 d-cache-line-size = <32>; 35 i-cache-size = <32768>; 36 d-cache-size = <32768>; 37 }; 38 }; 39 40 memory { 41 device_type = "memory"; 42 reg = <0x0 0x20000000>; /* Default (512MB) */ 43 }; 44 45 system-controller@f1000000 { /* Marvell Discovery mv64360 */ 46 #address-cells = <1>; 47 #size-cells = <1>; 48 model = "mv64360"; /* Default */ 49 compatible = "marvell,mv64360"; 50 clock-frequency = <133333333>; 51 reg = <0xf1000000 0x10000>; 52 virtual-reg = <0xf1000000>; 53 ranges = <0x88000000 0x88000000 0x1000000 /* PCI 0 I/O Space */ 54 0x80000000 0x80000000 0x8000000 /* PCI 0 MEM Space */ 55 0xa0000000 0xa0000000 0x4000000 /* User FLASH */ 56 0x00000000 0xf1000000 0x0010000 /* Bridge's regs */ 57 0xf2000000 0xf2000000 0x0040000>;/* Integrated SRAM */ 58 59 flash@a0000000 { 60 device_type = "rom"; 61 compatible = "direct-mapped"; 62 reg = <0xa0000000 0x4000000>; /* Default (64MB) */ 63 probe-type = "CFI"; 64 bank-width = <4>; 65 partitions = <0x00000000 0x00100000 /* RO */ 66 0x00100000 0x00040001 /* RW */ 67 0x00140000 0x00400000 /* RO */ 68 0x00540000 0x039c0000 /* RO */ 69 0x03f00000 0x00100000>; /* RO */ 70 partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B"; 71 }; 72 73 mdio { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 compatible = "marvell,mv64360-mdio"; 77 PHY0: ethernet-phy@1 { 78 compatible = "broadcom,bcm5421"; 79 interrupts = <76>; /* GPP 12 */ 80 interrupt-parent = <&PIC>; 81 reg = <1>; 82 }; 83 PHY1: ethernet-phy@3 { 84 compatible = "broadcom,bcm5421"; 85 interrupts = <76>; /* GPP 12 */ 86 interrupt-parent = <&PIC>; 87 reg = <3>; 88 }; 89 }; 90 91 ethernet-group@2000 { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 compatible = "marvell,mv64360-eth-group"; 95 reg = <0x2000 0x2000>; 96 ethernet@0 { 97 device_type = "network"; 98 compatible = "marvell,mv64360-eth"; 99 reg = <0>; 100 interrupts = <32>; 101 interrupt-parent = <&PIC>; 102 phy = <&PHY0>; 103 local-mac-address = [ 00 00 00 00 00 00 ]; 104 }; 105 ethernet@1 { 106 device_type = "network"; 107 compatible = "marvell,mv64360-eth"; 108 reg = <1>; 109 interrupts = <33>; 110 interrupt-parent = <&PIC>; 111 phy = <&PHY1>; 112 local-mac-address = [ 00 00 00 00 00 00 ]; 113 }; 114 }; 115 116 SDMA0: sdma@4000 { 117 compatible = "marvell,mv64360-sdma"; 118 reg = <0x4000 0xc18>; 119 virtual-reg = <0xf1004000>; 120 interrupts = <36>; 121 interrupt-parent = <&PIC>; 122 }; 123 124 SDMA1: sdma@6000 { 125 compatible = "marvell,mv64360-sdma"; 126 reg = <0x6000 0xc18>; 127 virtual-reg = <0xf1006000>; 128 interrupts = <38>; 129 interrupt-parent = <&PIC>; 130 }; 131 132 BRG0: brg@b200 { 133 compatible = "marvell,mv64360-brg"; 134 reg = <0xb200 0x8>; 135 clock-src = <8>; 136 clock-frequency = <133333333>; 137 current-speed = <9600>; 138 }; 139 140 BRG1: brg@b208 { 141 compatible = "marvell,mv64360-brg"; 142 reg = <0xb208 0x8>; 143 clock-src = <8>; 144 clock-frequency = <133333333>; 145 current-speed = <9600>; 146 }; 147 148 CUNIT: cunit@f200 { 149 reg = <0xf200 0x200>; 150 }; 151 152 MPSCROUTING: mpscrouting@b400 { 153 reg = <0xb400 0xc>; 154 }; 155 156 MPSCINTR: mpscintr@b800 { 157 reg = <0xb800 0x100>; 158 virtual-reg = <0xf100b800>; 159 }; 160 161 MPSC0: mpsc@8000 { 162 compatible = "marvell,mv64360-mpsc"; 163 reg = <0x8000 0x38>; 164 virtual-reg = <0xf1008000>; 165 sdma = <&SDMA0>; 166 brg = <&BRG0>; 167 cunit = <&CUNIT>; 168 mpscrouting = <&MPSCROUTING>; 169 mpscintr = <&MPSCINTR>; 170 cell-index = <0>; 171 interrupts = <40>; 172 interrupt-parent = <&PIC>; 173 }; 174 175 MPSC1: mpsc@9000 { 176 compatible = "marvell,mv64360-mpsc"; 177 reg = <0x9000 0x38>; 178 virtual-reg = <0xf1009000>; 179 sdma = <&SDMA1>; 180 brg = <&BRG1>; 181 cunit = <&CUNIT>; 182 mpscrouting = <&MPSCROUTING>; 183 mpscintr = <&MPSCINTR>; 184 cell-index = <1>; 185 interrupts = <42>; 186 interrupt-parent = <&PIC>; 187 }; 188 189 wdt@b410 { /* watchdog timer */ 190 compatible = "marvell,mv64360-wdt"; 191 reg = <0xb410 0x8>; 192 }; 193 194 i2c@c000 { 195 device_type = "i2c"; 196 compatible = "marvell,mv64360-i2c"; 197 reg = <0xc000 0x20>; 198 virtual-reg = <0xf100c000>; 199 interrupts = <37>; 200 interrupt-parent = <&PIC>; 201 }; 202 203 PIC: pic { 204 #interrupt-cells = <1>; 205 #address-cells = <0>; 206 compatible = "marvell,mv64360-pic"; 207 reg = <0x0 0x88>; 208 interrupt-controller; 209 }; 210 211 mpp@f000 { 212 compatible = "marvell,mv64360-mpp"; 213 reg = <0xf000 0x10>; 214 }; 215 216 gpp@f100 { 217 compatible = "marvell,mv64360-gpp"; 218 reg = <0xf100 0x20>; 219 }; 220 221 pci@80000000 { 222 #address-cells = <3>; 223 #size-cells = <2>; 224 #interrupt-cells = <1>; 225 device_type = "pci"; 226 compatible = "marvell,mv64360-pci"; 227 reg = <0xcf8 0x8>; 228 ranges = <0x01000000 0x0 0x0 229 0x88000000 0x0 0x01000000 230 0x02000000 0x0 0x80000000 231 0x80000000 0x0 0x08000000>; 232 bus-range = <0 255>; 233 clock-frequency = <66000000>; 234 interrupt-pci-iack = <0xc34>; 235 interrupt-parent = <&PIC>; 236 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 237 interrupt-map = < 238 /* IDSEL 0x0a */ 239 0x5000 0 0 1 &PIC 80 240 0x5000 0 0 2 &PIC 81 241 0x5000 0 0 3 &PIC 91 242 0x5000 0 0 4 &PIC 93 243 244 /* IDSEL 0x0b */ 245 0x5800 0 0 1 &PIC 91 246 0x5800 0 0 2 &PIC 93 247 0x5800 0 0 3 &PIC 80 248 0x5800 0 0 4 &PIC 81 249 250 /* IDSEL 0x0c */ 251 0x6000 0 0 1 &PIC 91 252 0x6000 0 0 2 &PIC 93 253 0x6000 0 0 3 &PIC 80 254 0x6000 0 0 4 &PIC 81 255 256 /* IDSEL 0x0d */ 257 0x6800 0 0 1 &PIC 93 258 0x6800 0 0 2 &PIC 80 259 0x6800 0 0 3 &PIC 81 260 0x6800 0 0 4 &PIC 91 261 >; 262 }; 263 264 cpu-error@0070 { 265 compatible = "marvell,mv64360-cpu-error"; 266 reg = <0x70 0x10 0x128 0x28>; 267 interrupts = <3>; 268 interrupt-parent = <&PIC>; 269 }; 270 271 sram-ctrl@0380 { 272 compatible = "marvell,mv64360-sram-ctrl"; 273 reg = <0x380 0x80>; 274 interrupts = <13>; 275 interrupt-parent = <&PIC>; 276 }; 277 278 pci-error@1d40 { 279 compatible = "marvell,mv64360-pci-error"; 280 reg = <0x1d40 0x40 0xc28 0x4>; 281 interrupts = <12>; 282 interrupt-parent = <&PIC>; 283 }; 284 285 mem-ctrl@1400 { 286 compatible = "marvell,mv64360-mem-ctrl"; 287 reg = <0x1400 0x60>; 288 interrupts = <17>; 289 interrupt-parent = <&PIC>; 290 }; 291 }; 292 293 chosen { 294 bootargs = "ip=on"; 295 linux,stdout-path = &MPSC0; 296 }; 297}; 298