1/*
2 * MPC8379E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13
14/ {
15	model = "fsl,mpc8379emds";
16	compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
17	#address-cells = <1>;
18	#size-cells = <1>;
19
20	aliases {
21		ethernet0 = &enet0;
22		ethernet1 = &enet1;
23		serial0 = &serial0;
24		serial1 = &serial1;
25		pci0 = &pci0;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,8379@0 {
33			device_type = "cpu";
34			reg = <0x0>;
35			d-cache-line-size = <32>;
36			i-cache-line-size = <32>;
37			d-cache-size = <32768>;
38			i-cache-size = <32768>;
39			timebase-frequency = <0>;
40			bus-frequency = <0>;
41			clock-frequency = <0>;
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x20000000>;	// 512MB at 0
48	};
49
50	localbus@e0005000 {
51		#address-cells = <2>;
52		#size-cells = <1>;
53		compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
54		reg = <0xe0005000 0x1000>;
55		interrupts = <77 0x8>;
56		interrupt-parent = <&ipic>;
57
58		// booting from NOR flash
59		ranges = <0 0x0 0xfe000000 0x02000000
60		          1 0x0 0xf8000000 0x00008000
61		          3 0x0 0xe0600000 0x00008000>;
62
63		flash@0,0 {
64			#address-cells = <1>;
65			#size-cells = <1>;
66			compatible = "cfi-flash";
67			reg = <0 0x0 0x2000000>;
68			bank-width = <2>;
69			device-width = <1>;
70
71			u-boot@0 {
72				reg = <0x0 0x100000>;
73				read-only;
74			};
75
76			fs@100000 {
77				reg = <0x100000 0x800000>;
78			};
79
80			kernel@1d00000 {
81				reg = <0x1d00000 0x200000>;
82			};
83
84			dtb@1f00000 {
85				reg = <0x1f00000 0x100000>;
86			};
87		};
88
89		bcsr@1,0 {
90			reg = <1 0x0 0x8000>;
91			compatible = "fsl,mpc837xmds-bcsr";
92		};
93
94		nand@3,0 {
95			#address-cells = <1>;
96			#size-cells = <1>;
97			compatible = "fsl,mpc8379-fcm-nand",
98			             "fsl,elbc-fcm-nand";
99			reg = <3 0x0 0x8000>;
100
101			u-boot@0 {
102				reg = <0x0 0x100000>;
103				read-only;
104			};
105
106			kernel@100000 {
107				reg = <0x100000 0x300000>;
108			};
109
110			fs@400000 {
111				reg = <0x400000 0x1c00000>;
112			};
113		};
114	};
115
116	soc@e0000000 {
117		#address-cells = <1>;
118		#size-cells = <1>;
119		device_type = "soc";
120		compatible = "simple-bus";
121		ranges = <0x0 0xe0000000 0x00100000>;
122		reg = <0xe0000000 0x00000200>;
123		bus-frequency = <0>;
124
125		wdt@200 {
126			compatible = "mpc83xx_wdt";
127			reg = <0x200 0x100>;
128		};
129
130		sleep-nexus {
131			#address-cells = <1>;
132			#size-cells = <1>;
133			compatible = "simple-bus";
134			sleep = <&pmc 0x0c000000>;
135			ranges;
136
137			i2c@3000 {
138				#address-cells = <1>;
139				#size-cells = <0>;
140				cell-index = <0>;
141				compatible = "fsl-i2c";
142				reg = <0x3000 0x100>;
143				interrupts = <14 0x8>;
144				interrupt-parent = <&ipic>;
145				dfsrr;
146
147				rtc@68 {
148					compatible = "dallas,ds1374";
149					reg = <0x68>;
150					interrupts = <19 0x8>;
151					interrupt-parent = <&ipic>;
152				};
153			};
154
155			sdhci@2e000 {
156				compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
157				reg = <0x2e000 0x1000>;
158				interrupts = <42 0x8>;
159				interrupt-parent = <&ipic>;
160				sdhci,wp-inverted;
161				/* Filled in by U-Boot */
162				clock-frequency = <0>;
163			};
164		};
165
166		i2c@3100 {
167			#address-cells = <1>;
168			#size-cells = <0>;
169			cell-index = <1>;
170			compatible = "fsl-i2c";
171			reg = <0x3100 0x100>;
172			interrupts = <15 0x8>;
173			interrupt-parent = <&ipic>;
174			dfsrr;
175		};
176
177		spi@7000 {
178			cell-index = <0>;
179			compatible = "fsl,spi";
180			reg = <0x7000 0x1000>;
181			interrupts = <16 0x8>;
182			interrupt-parent = <&ipic>;
183			mode = "cpu";
184		};
185
186		dma@82a8 {
187			#address-cells = <1>;
188			#size-cells = <1>;
189			compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
190			reg = <0x82a8 4>;
191			ranges = <0 0x8100 0x1a8>;
192			interrupt-parent = <&ipic>;
193			interrupts = <71 8>;
194			cell-index = <0>;
195			dma-channel@0 {
196				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
197				reg = <0 0x80>;
198				cell-index = <0>;
199				interrupt-parent = <&ipic>;
200				interrupts = <71 8>;
201			};
202			dma-channel@80 {
203				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
204				reg = <0x80 0x80>;
205				cell-index = <1>;
206				interrupt-parent = <&ipic>;
207				interrupts = <71 8>;
208			};
209			dma-channel@100 {
210				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
211				reg = <0x100 0x80>;
212				cell-index = <2>;
213				interrupt-parent = <&ipic>;
214				interrupts = <71 8>;
215			};
216			dma-channel@180 {
217				compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
218				reg = <0x180 0x28>;
219				cell-index = <3>;
220				interrupt-parent = <&ipic>;
221				interrupts = <71 8>;
222			};
223		};
224
225		usb@23000 {
226			compatible = "fsl-usb2-dr";
227			reg = <0x23000 0x1000>;
228			#address-cells = <1>;
229			#size-cells = <0>;
230			interrupt-parent = <&ipic>;
231			interrupts = <38 0x8>;
232			dr_mode = "host";
233			phy_type = "ulpi";
234			sleep = <&pmc 0x00c00000>;
235		};
236
237		enet0: ethernet@24000 {
238			#address-cells = <1>;
239			#size-cells = <1>;
240			cell-index = <0>;
241			device_type = "network";
242			model = "eTSEC";
243			compatible = "gianfar";
244			reg = <0x24000 0x1000>;
245			ranges = <0x0 0x24000 0x1000>;
246			local-mac-address = [ 00 00 00 00 00 00 ];
247			interrupts = <32 0x8 33 0x8 34 0x8>;
248			phy-connection-type = "mii";
249			interrupt-parent = <&ipic>;
250			tbi-handle = <&tbi0>;
251			phy-handle = <&phy2>;
252			sleep = <&pmc 0xc0000000>;
253			fsl,magic-packet;
254
255			mdio@520 {
256				#address-cells = <1>;
257				#size-cells = <0>;
258				compatible = "fsl,gianfar-mdio";
259				reg = <0x520 0x20>;
260
261				phy2: ethernet-phy@2 {
262					interrupt-parent = <&ipic>;
263					interrupts = <17 0x8>;
264					reg = <0x2>;
265				};
266
267				phy3: ethernet-phy@3 {
268					interrupt-parent = <&ipic>;
269					interrupts = <18 0x8>;
270					reg = <0x3>;
271				};
272
273				tbi0: tbi-phy@11 {
274					reg = <0x11>;
275					device_type = "tbi-phy";
276				};
277			};
278		};
279
280		enet1: ethernet@25000 {
281			#address-cells = <1>;
282			#size-cells = <1>;
283			cell-index = <1>;
284			device_type = "network";
285			model = "eTSEC";
286			compatible = "gianfar";
287			reg = <0x25000 0x1000>;
288			ranges = <0x0 0x25000 0x1000>;
289			local-mac-address = [ 00 00 00 00 00 00 ];
290			interrupts = <35 0x8 36 0x8 37 0x8>;
291			phy-connection-type = "mii";
292			interrupt-parent = <&ipic>;
293			tbi-handle = <&tbi1>;
294			phy-handle = <&phy3>;
295			sleep = <&pmc 0x30000000>;
296			fsl,magic-packet;
297
298			mdio@520 {
299				#address-cells = <1>;
300				#size-cells = <0>;
301				compatible = "fsl,gianfar-tbi";
302				reg = <0x520 0x20>;
303
304				tbi1: tbi-phy@11 {
305					reg = <0x11>;
306					device_type = "tbi-phy";
307				};
308			};
309		};
310
311		serial0: serial@4500 {
312			cell-index = <0>;
313			device_type = "serial";
314			compatible = "fsl,ns16550", "ns16550";
315			reg = <0x4500 0x100>;
316			clock-frequency = <0>;
317			interrupts = <9 0x8>;
318			interrupt-parent = <&ipic>;
319		};
320
321		serial1: serial@4600 {
322			cell-index = <1>;
323			device_type = "serial";
324			compatible = "fsl,ns16550", "ns16550";
325			reg = <0x4600 0x100>;
326			clock-frequency = <0>;
327			interrupts = <10 0x8>;
328			interrupt-parent = <&ipic>;
329		};
330
331		crypto@30000 {
332			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
333				     "fsl,sec2.1", "fsl,sec2.0";
334			reg = <0x30000 0x10000>;
335			interrupts = <11 0x8>;
336			interrupt-parent = <&ipic>;
337			fsl,num-channels = <4>;
338			fsl,channel-fifo-len = <24>;
339			fsl,exec-units-mask = <0x9fe>;
340			fsl,descriptor-types-mask = <0x3ab0ebf>;
341			sleep = <&pmc 0x03000000>;
342		};
343
344		sata@18000 {
345			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
346			reg = <0x18000 0x1000>;
347			interrupts = <44 0x8>;
348			interrupt-parent = <&ipic>;
349			sleep = <&pmc 0x000000c0>;
350		};
351
352		sata@19000 {
353			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
354			reg = <0x19000 0x1000>;
355			interrupts = <45 0x8>;
356			interrupt-parent = <&ipic>;
357			sleep = <&pmc 0x00000030>;
358		};
359
360		sata@1a000 {
361			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
362			reg = <0x1a000 0x1000>;
363			interrupts = <46 0x8>;
364			interrupt-parent = <&ipic>;
365			sleep = <&pmc 0x0000000c>;
366		};
367
368		sata@1b000 {
369			compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
370			reg = <0x1b000 0x1000>;
371			interrupts = <47 0x8>;
372			interrupt-parent = <&ipic>;
373			sleep = <&pmc 0x00000003>;
374		};
375
376		/* IPIC
377		 * interrupts cell = <intr #, sense>
378		 * sense values match linux IORESOURCE_IRQ_* defines:
379		 * sense == 8: Level, low assertion
380		 * sense == 2: Edge, high-to-low change
381		 */
382		ipic: pic@700 {
383			compatible = "fsl,ipic";
384			interrupt-controller;
385			#address-cells = <0>;
386			#interrupt-cells = <2>;
387			reg = <0x700 0x100>;
388		};
389
390		pmc: power@b00 {
391			compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
392			reg = <0xb00 0x100 0xa00 0x100>;
393			interrupts = <80 0x8>;
394			interrupt-parent = <&ipic>;
395		};
396	};
397
398	pci0: pci@e0008500 {
399		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
400		interrupt-map = <
401
402				/* IDSEL 0x11 */
403				 0x8800 0x0 0x0 0x1 &ipic 20 0x8
404				 0x8800 0x0 0x0 0x2 &ipic 21 0x8
405				 0x8800 0x0 0x0 0x3 &ipic 22 0x8
406				 0x8800 0x0 0x0 0x4 &ipic 23 0x8
407
408				/* IDSEL 0x12 */
409				 0x9000 0x0 0x0 0x1 &ipic 22 0x8
410				 0x9000 0x0 0x0 0x2 &ipic 23 0x8
411				 0x9000 0x0 0x0 0x3 &ipic 20 0x8
412				 0x9000 0x0 0x0 0x4 &ipic 21 0x8
413
414				/* IDSEL 0x13 */
415				 0x9800 0x0 0x0 0x1 &ipic 23 0x8
416				 0x9800 0x0 0x0 0x2 &ipic 20 0x8
417				 0x9800 0x0 0x0 0x3 &ipic 21 0x8
418				 0x9800 0x0 0x0 0x4 &ipic 22 0x8
419
420				/* IDSEL 0x15 */
421				 0xa800 0x0 0x0 0x1 &ipic 20 0x8
422				 0xa800 0x0 0x0 0x2 &ipic 21 0x8
423				 0xa800 0x0 0x0 0x3 &ipic 22 0x8
424				 0xa800 0x0 0x0 0x4 &ipic 23 0x8
425
426				/* IDSEL 0x16 */
427				 0xb000 0x0 0x0 0x1 &ipic 23 0x8
428				 0xb000 0x0 0x0 0x2 &ipic 20 0x8
429				 0xb000 0x0 0x0 0x3 &ipic 21 0x8
430				 0xb000 0x0 0x0 0x4 &ipic 22 0x8
431
432				/* IDSEL 0x17 */
433				 0xb800 0x0 0x0 0x1 &ipic 22 0x8
434				 0xb800 0x0 0x0 0x2 &ipic 23 0x8
435				 0xb800 0x0 0x0 0x3 &ipic 20 0x8
436				 0xb800 0x0 0x0 0x4 &ipic 21 0x8
437
438				/* IDSEL 0x18 */
439				 0xc000 0x0 0x0 0x1 &ipic 21 0x8
440				 0xc000 0x0 0x0 0x2 &ipic 22 0x8
441				 0xc000 0x0 0x0 0x3 &ipic 23 0x8
442				 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
443		interrupt-parent = <&ipic>;
444		interrupts = <66 0x8>;
445		bus-range = <0x0 0x0>;
446		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
447		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
448		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
449		sleep = <&pmc 0x00010000>;
450		clock-frequency = <0>;
451		#interrupt-cells = <1>;
452		#size-cells = <2>;
453		#address-cells = <3>;
454		reg = <0xe0008500 0x100		/* internal registers */
455		       0xe0008300 0x8>;		/* config space access registers */
456		compatible = "fsl,mpc8349-pci";
457		device_type = "pci";
458	};
459};
460