1/*
2 * base MPC5121 Device Tree Source
3 *
4 * Copyright 2007-2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute  it and/or modify it
7 * under  the terms of  the GNU General  Public License as published by the
8 * Free Software Foundation;  either version 2 of the  License, or (at your
9 * option) any later version.
10 */
11
12#include <dt-bindings/clock/mpc512x-clock.h>
13
14/dts-v1/;
15
16/ {
17	model = "mpc5121";
18	compatible = "fsl,mpc5121";
19	#address-cells = <1>;
20	#size-cells = <1>;
21        interrupt-parent = <&ipic>;
22
23	aliases {
24		ethernet0 = &eth0;
25		pci = &pci;
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		PowerPC,5121@0 {
33			device_type = "cpu";
34			reg = <0>;
35			d-cache-line-size = <0x20>;	/* 32 bytes */
36			i-cache-line-size = <0x20>;	/* 32 bytes */
37			d-cache-size = <0x8000>;	/* L1, 32K */
38			i-cache-size = <0x8000>;	/* L1, 32K */
39			timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */
40			bus-frequency = <198000000>;	/* 198 MHz csb bus */
41			clock-frequency = <396000000>;	/* 396 MHz ppc core */
42		};
43	};
44
45	memory {
46		device_type = "memory";
47		reg = <0x00000000 0x10000000>;	/* 256MB at 0 */
48	};
49
50	mbx@20000000 {
51		compatible = "fsl,mpc5121-mbx";
52		reg = <0x20000000 0x4000>;
53		interrupts = <66 0x8>;
54		clocks = <&clks MPC512x_CLK_MBX_BUS>,
55			 <&clks MPC512x_CLK_MBX_3D>,
56			 <&clks MPC512x_CLK_MBX>;
57		clock-names = "mbx-bus", "mbx-3d", "mbx";
58	};
59
60	sram@30000000 {
61		compatible = "fsl,mpc5121-sram";
62		reg = <0x30000000 0x20000>;	/* 128K at 0x30000000 */
63	};
64
65	nfc@40000000 {
66		compatible = "fsl,mpc5121-nfc";
67		reg = <0x40000000 0x100000>;	/* 1M at 0x40000000 */
68		interrupts = <6 8>;
69		#address-cells = <1>;
70		#size-cells = <1>;
71		clocks = <&clks MPC512x_CLK_NFC>;
72		clock-names = "ipg";
73	};
74
75	localbus@80000020 {
76		compatible = "fsl,mpc5121-localbus";
77		#address-cells = <2>;
78		#size-cells = <1>;
79		reg = <0x80000020 0x40>;
80		interrupts = <7 0x8>;
81		ranges = <0x0 0x0 0xfc000000 0x04000000>;
82	};
83
84	clocks {
85		#address-cells = <1>;
86		#size-cells = <0>;
87
88		osc: osc {
89			compatible = "fixed-clock";
90			#clock-cells = <0>;
91			clock-frequency = <33000000>;
92		};
93	};
94
95	soc@80000000 {
96		compatible = "fsl,mpc5121-immr";
97		#address-cells = <1>;
98		#size-cells = <1>;
99		ranges = <0x0 0x80000000 0x400000>;
100		reg = <0x80000000 0x400000>;
101		bus-frequency = <66000000>;	/* 66 MHz ips bus */
102
103
104		/*
105		 * IPIC
106		 * interrupts cell = <intr #, sense>
107		 * sense values match linux IORESOURCE_IRQ_* defines:
108		 * sense == 8: Level, low assertion
109		 * sense == 2: Edge, high-to-low change
110		 */
111		ipic: interrupt-controller@c00 {
112			compatible = "fsl,mpc5121-ipic", "fsl,ipic";
113			interrupt-controller;
114			#address-cells = <0>;
115			#interrupt-cells = <2>;
116			reg = <0xc00 0x100>;
117		};
118
119		/* Watchdog timer */
120		wdt@900 {
121			compatible = "fsl,mpc5121-wdt";
122			reg = <0x900 0x100>;
123		};
124
125		/* Real time clock */
126		rtc@a00 {
127			compatible = "fsl,mpc5121-rtc";
128			reg = <0xa00 0x100>;
129			interrupts = <79 0x8 80 0x8>;
130		};
131
132		/* Reset module */
133		reset@e00 {
134			compatible = "fsl,mpc5121-reset";
135			reg = <0xe00 0x100>;
136		};
137
138		/* Clock control */
139		clks: clock@f00 {
140			compatible = "fsl,mpc5121-clock";
141			reg = <0xf00 0x100>;
142			#clock-cells = <1>;
143			clocks = <&osc>;
144			clock-names = "osc";
145		};
146
147		/* Power Management Controller */
148		pmc@1000{
149			compatible = "fsl,mpc5121-pmc";
150			reg = <0x1000 0x100>;
151			interrupts = <83 0x8>;
152		};
153
154		gpio@1100 {
155			compatible = "fsl,mpc5121-gpio";
156			reg = <0x1100 0x100>;
157			interrupts = <78 0x8>;
158		};
159
160		can@1300 {
161			compatible = "fsl,mpc5121-mscan";
162			reg = <0x1300 0x80>;
163			interrupts = <12 0x8>;
164			clocks = <&clks MPC512x_CLK_BDLC>,
165				 <&clks MPC512x_CLK_IPS>,
166				 <&clks MPC512x_CLK_SYS>,
167				 <&clks MPC512x_CLK_REF>,
168				 <&clks MPC512x_CLK_MSCAN0_MCLK>;
169			clock-names = "ipg", "ips", "sys", "ref", "mclk";
170		};
171
172		can@1380 {
173			compatible = "fsl,mpc5121-mscan";
174			reg = <0x1380 0x80>;
175			interrupts = <13 0x8>;
176			clocks = <&clks MPC512x_CLK_BDLC>,
177				 <&clks MPC512x_CLK_IPS>,
178				 <&clks MPC512x_CLK_SYS>,
179				 <&clks MPC512x_CLK_REF>,
180				 <&clks MPC512x_CLK_MSCAN1_MCLK>;
181			clock-names = "ipg", "ips", "sys", "ref", "mclk";
182		};
183
184		sdhc@1500 {
185			compatible = "fsl,mpc5121-sdhc";
186			reg = <0x1500 0x100>;
187			interrupts = <8 0x8>;
188			dmas = <&dma0 30>;
189			dma-names = "rx-tx";
190			clocks = <&clks MPC512x_CLK_IPS>,
191				 <&clks MPC512x_CLK_SDHC>;
192			clock-names = "ipg", "per";
193		};
194
195		i2c@1700 {
196			#address-cells = <1>;
197			#size-cells = <0>;
198			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
199			reg = <0x1700 0x20>;
200			interrupts = <9 0x8>;
201			clocks = <&clks MPC512x_CLK_I2C>;
202			clock-names = "ipg";
203		};
204
205		i2c@1720 {
206			#address-cells = <1>;
207			#size-cells = <0>;
208			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
209			reg = <0x1720 0x20>;
210			interrupts = <10 0x8>;
211			clocks = <&clks MPC512x_CLK_I2C>;
212			clock-names = "ipg";
213		};
214
215		i2c@1740 {
216			#address-cells = <1>;
217			#size-cells = <0>;
218			compatible = "fsl,mpc5121-i2c", "fsl-i2c";
219			reg = <0x1740 0x20>;
220			interrupts = <11 0x8>;
221			clocks = <&clks MPC512x_CLK_I2C>;
222			clock-names = "ipg";
223		};
224
225		i2ccontrol@1760 {
226			compatible = "fsl,mpc5121-i2c-ctrl";
227			reg = <0x1760 0x8>;
228		};
229
230		axe@2000 {
231			compatible = "fsl,mpc5121-axe";
232			reg = <0x2000 0x100>;
233			interrupts = <42 0x8>;
234			clocks = <&clks MPC512x_CLK_AXE>;
235			clock-names = "ipg";
236		};
237
238		display@2100 {
239			compatible = "fsl,mpc5121-diu";
240			reg = <0x2100 0x100>;
241			interrupts = <64 0x8>;
242			clocks = <&clks MPC512x_CLK_DIU>;
243			clock-names = "ipg";
244		};
245
246		can@2300 {
247			compatible = "fsl,mpc5121-mscan";
248			reg = <0x2300 0x80>;
249			interrupts = <90 0x8>;
250			clocks = <&clks MPC512x_CLK_BDLC>,
251				 <&clks MPC512x_CLK_IPS>,
252				 <&clks MPC512x_CLK_SYS>,
253				 <&clks MPC512x_CLK_REF>,
254				 <&clks MPC512x_CLK_MSCAN2_MCLK>;
255			clock-names = "ipg", "ips", "sys", "ref", "mclk";
256		};
257
258		can@2380 {
259			compatible = "fsl,mpc5121-mscan";
260			reg = <0x2380 0x80>;
261			interrupts = <91 0x8>;
262			clocks = <&clks MPC512x_CLK_BDLC>,
263				 <&clks MPC512x_CLK_IPS>,
264				 <&clks MPC512x_CLK_SYS>,
265				 <&clks MPC512x_CLK_REF>,
266				 <&clks MPC512x_CLK_MSCAN3_MCLK>;
267			clock-names = "ipg", "ips", "sys", "ref", "mclk";
268		};
269
270		viu@2400 {
271			compatible = "fsl,mpc5121-viu";
272			reg = <0x2400 0x400>;
273			interrupts = <67 0x8>;
274			clocks = <&clks MPC512x_CLK_VIU>;
275			clock-names = "ipg";
276		};
277
278		mdio@2800 {
279			compatible = "fsl,mpc5121-fec-mdio";
280			reg = <0x2800 0x800>;
281			#address-cells = <1>;
282			#size-cells = <0>;
283			clocks = <&clks MPC512x_CLK_FEC>;
284			clock-names = "per";
285		};
286
287		eth0: ethernet@2800 {
288			device_type = "network";
289			compatible = "fsl,mpc5121-fec";
290			reg = <0x2800 0x800>;
291			local-mac-address = [ 00 00 00 00 00 00 ];
292			interrupts = <4 0x8>;
293			clocks = <&clks MPC512x_CLK_FEC>;
294			clock-names = "per";
295		};
296
297		/* USB1 using external ULPI PHY */
298		usb@3000 {
299			compatible = "fsl,mpc5121-usb2-dr";
300			reg = <0x3000 0x600>;
301			#address-cells = <1>;
302			#size-cells = <0>;
303			interrupts = <43 0x8>;
304			dr_mode = "otg";
305			phy_type = "ulpi";
306			clocks = <&clks MPC512x_CLK_USB1>;
307			clock-names = "ipg";
308		};
309
310		/* USB0 using internal UTMI PHY */
311		usb@4000 {
312			compatible = "fsl,mpc5121-usb2-dr";
313			reg = <0x4000 0x600>;
314			#address-cells = <1>;
315			#size-cells = <0>;
316			interrupts = <44 0x8>;
317			dr_mode = "otg";
318			phy_type = "utmi_wide";
319			clocks = <&clks MPC512x_CLK_USB2>;
320			clock-names = "ipg";
321		};
322
323		/* IO control */
324		ioctl@a000 {
325			compatible = "fsl,mpc5121-ioctl";
326			reg = <0xA000 0x1000>;
327		};
328
329		/* LocalPlus controller */
330		lpc@10000 {
331			compatible = "fsl,mpc5121-lpc";
332			reg = <0x10000 0x200>;
333		};
334
335		pata@10200 {
336			compatible = "fsl,mpc5121-pata";
337			reg = <0x10200 0x100>;
338			interrupts = <5 0x8>;
339			clocks = <&clks MPC512x_CLK_PATA>;
340			clock-names = "ipg";
341		};
342
343		/* 512x PSCs are not 52xx PSC compatible */
344
345		/* PSC0 */
346		psc@11000 {
347			compatible = "fsl,mpc5121-psc";
348			reg = <0x11000 0x100>;
349			interrupts = <40 0x8>;
350			fsl,rx-fifo-size = <16>;
351			fsl,tx-fifo-size = <16>;
352			clocks = <&clks MPC512x_CLK_PSC0>,
353				 <&clks MPC512x_CLK_PSC0_MCLK>;
354			clock-names = "ipg", "mclk";
355		};
356
357		/* PSC1 */
358		psc@11100 {
359			compatible = "fsl,mpc5121-psc";
360			reg = <0x11100 0x100>;
361			interrupts = <40 0x8>;
362			fsl,rx-fifo-size = <16>;
363			fsl,tx-fifo-size = <16>;
364			clocks = <&clks MPC512x_CLK_PSC1>,
365				 <&clks MPC512x_CLK_PSC1_MCLK>;
366			clock-names = "ipg", "mclk";
367		};
368
369		/* PSC2 */
370		psc@11200 {
371			compatible = "fsl,mpc5121-psc";
372			reg = <0x11200 0x100>;
373			interrupts = <40 0x8>;
374			fsl,rx-fifo-size = <16>;
375			fsl,tx-fifo-size = <16>;
376			clocks = <&clks MPC512x_CLK_PSC2>,
377				 <&clks MPC512x_CLK_PSC2_MCLK>;
378			clock-names = "ipg", "mclk";
379		};
380
381		/* PSC3 */
382		psc@11300 {
383			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
384			reg = <0x11300 0x100>;
385			interrupts = <40 0x8>;
386			fsl,rx-fifo-size = <16>;
387			fsl,tx-fifo-size = <16>;
388			clocks = <&clks MPC512x_CLK_PSC3>,
389				 <&clks MPC512x_CLK_PSC3_MCLK>;
390			clock-names = "ipg", "mclk";
391		};
392
393		/* PSC4 */
394		psc@11400 {
395			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
396			reg = <0x11400 0x100>;
397			interrupts = <40 0x8>;
398			fsl,rx-fifo-size = <16>;
399			fsl,tx-fifo-size = <16>;
400			clocks = <&clks MPC512x_CLK_PSC4>,
401				 <&clks MPC512x_CLK_PSC4_MCLK>;
402			clock-names = "ipg", "mclk";
403		};
404
405		/* PSC5 */
406		psc@11500 {
407			compatible = "fsl,mpc5121-psc";
408			reg = <0x11500 0x100>;
409			interrupts = <40 0x8>;
410			fsl,rx-fifo-size = <16>;
411			fsl,tx-fifo-size = <16>;
412			clocks = <&clks MPC512x_CLK_PSC5>,
413				 <&clks MPC512x_CLK_PSC5_MCLK>;
414			clock-names = "ipg", "mclk";
415		};
416
417		/* PSC6 */
418		psc@11600 {
419			compatible = "fsl,mpc5121-psc";
420			reg = <0x11600 0x100>;
421			interrupts = <40 0x8>;
422			fsl,rx-fifo-size = <16>;
423			fsl,tx-fifo-size = <16>;
424			clocks = <&clks MPC512x_CLK_PSC6>,
425				 <&clks MPC512x_CLK_PSC6_MCLK>;
426			clock-names = "ipg", "mclk";
427		};
428
429		/* PSC7 */
430		psc@11700 {
431			compatible = "fsl,mpc5121-psc";
432			reg = <0x11700 0x100>;
433			interrupts = <40 0x8>;
434			fsl,rx-fifo-size = <16>;
435			fsl,tx-fifo-size = <16>;
436			clocks = <&clks MPC512x_CLK_PSC7>,
437				 <&clks MPC512x_CLK_PSC7_MCLK>;
438			clock-names = "ipg", "mclk";
439		};
440
441		/* PSC8 */
442		psc@11800 {
443			compatible = "fsl,mpc5121-psc";
444			reg = <0x11800 0x100>;
445			interrupts = <40 0x8>;
446			fsl,rx-fifo-size = <16>;
447			fsl,tx-fifo-size = <16>;
448			clocks = <&clks MPC512x_CLK_PSC8>,
449				 <&clks MPC512x_CLK_PSC8_MCLK>;
450			clock-names = "ipg", "mclk";
451		};
452
453		/* PSC9 */
454		psc@11900 {
455			compatible = "fsl,mpc5121-psc";
456			reg = <0x11900 0x100>;
457			interrupts = <40 0x8>;
458			fsl,rx-fifo-size = <16>;
459			fsl,tx-fifo-size = <16>;
460			clocks = <&clks MPC512x_CLK_PSC9>,
461				 <&clks MPC512x_CLK_PSC9_MCLK>;
462			clock-names = "ipg", "mclk";
463		};
464
465		/* PSC10 */
466		psc@11a00 {
467			compatible = "fsl,mpc5121-psc";
468			reg = <0x11a00 0x100>;
469			interrupts = <40 0x8>;
470			fsl,rx-fifo-size = <16>;
471			fsl,tx-fifo-size = <16>;
472			clocks = <&clks MPC512x_CLK_PSC10>,
473				 <&clks MPC512x_CLK_PSC10_MCLK>;
474			clock-names = "ipg", "mclk";
475		};
476
477		/* PSC11 */
478		psc@11b00 {
479			compatible = "fsl,mpc5121-psc";
480			reg = <0x11b00 0x100>;
481			interrupts = <40 0x8>;
482			fsl,rx-fifo-size = <16>;
483			fsl,tx-fifo-size = <16>;
484			clocks = <&clks MPC512x_CLK_PSC11>,
485				 <&clks MPC512x_CLK_PSC11_MCLK>;
486			clock-names = "ipg", "mclk";
487		};
488
489		pscfifo@11f00 {
490			compatible = "fsl,mpc5121-psc-fifo";
491			reg = <0x11f00 0x100>;
492			interrupts = <40 0x8>;
493			clocks = <&clks MPC512x_CLK_PSC_FIFO>;
494			clock-names = "ipg";
495		};
496
497		dma0: dma@14000 {
498			compatible = "fsl,mpc5121-dma";
499			reg = <0x14000 0x1800>;
500			interrupts = <65 0x8>;
501			#dma-cells = <1>;
502		};
503	};
504
505	pci: pci@80008500 {
506		compatible = "fsl,mpc5121-pci";
507		device_type = "pci";
508		interrupts = <1 0x8>;
509		clock-frequency = <0>;
510		#address-cells = <3>;
511		#size-cells = <2>;
512		#interrupt-cells = <1>;
513		clocks = <&clks MPC512x_CLK_PCI>;
514		clock-names = "ipg";
515
516		reg = <0x80008500 0x100	/* internal registers */
517		       0x80008300 0x8>;	/* config space access registers */
518		bus-range = <0x0 0x0>;
519		ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
520			  0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
521			  0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;
522	};
523};
524