1#ifndef __DTS_MARVELL_MMP2_CLOCK_H 2#define __DTS_MARVELL_MMP2_CLOCK_H 3 4/* fixed clocks and plls */ 5#define MMP2_CLK_CLK32 1 6#define MMP2_CLK_VCTCXO 2 7#define MMP2_CLK_PLL1 3 8#define MMP2_CLK_PLL1_2 8 9#define MMP2_CLK_PLL1_4 9 10#define MMP2_CLK_PLL1_8 10 11#define MMP2_CLK_PLL1_16 11 12#define MMP2_CLK_PLL1_3 12 13#define MMP2_CLK_PLL1_6 13 14#define MMP2_CLK_PLL1_12 14 15#define MMP2_CLK_PLL1_20 15 16#define MMP2_CLK_PLL2 16 17#define MMP2_CLK_PLL2_2 17 18#define MMP2_CLK_PLL2_4 18 19#define MMP2_CLK_PLL2_8 19 20#define MMP2_CLK_PLL2_16 20 21#define MMP2_CLK_PLL2_3 21 22#define MMP2_CLK_PLL2_6 22 23#define MMP2_CLK_PLL2_12 23 24#define MMP2_CLK_VCTCXO_2 24 25#define MMP2_CLK_VCTCXO_4 25 26#define MMP2_CLK_UART_PLL 26 27#define MMP2_CLK_USB_PLL 27 28 29/* apb periphrals */ 30#define MMP2_CLK_TWSI0 60 31#define MMP2_CLK_TWSI1 61 32#define MMP2_CLK_TWSI2 62 33#define MMP2_CLK_TWSI3 63 34#define MMP2_CLK_TWSI4 64 35#define MMP2_CLK_TWSI5 65 36#define MMP2_CLK_GPIO 66 37#define MMP2_CLK_KPC 67 38#define MMP2_CLK_RTC 68 39#define MMP2_CLK_PWM0 69 40#define MMP2_CLK_PWM1 70 41#define MMP2_CLK_PWM2 71 42#define MMP2_CLK_PWM3 72 43#define MMP2_CLK_UART0 73 44#define MMP2_CLK_UART1 74 45#define MMP2_CLK_UART2 75 46#define MMP2_CLK_UART3 76 47#define MMP2_CLK_SSP0 77 48#define MMP2_CLK_SSP1 78 49#define MMP2_CLK_SSP2 79 50#define MMP2_CLK_SSP3 80 51 52/* axi periphrals */ 53#define MMP2_CLK_SDH0 101 54#define MMP2_CLK_SDH1 102 55#define MMP2_CLK_SDH2 103 56#define MMP2_CLK_SDH3 104 57#define MMP2_CLK_USB 105 58#define MMP2_CLK_DISP0 106 59#define MMP2_CLK_DISP0_MUX 107 60#define MMP2_CLK_DISP0_SPHY 108 61#define MMP2_CLK_DISP1 109 62#define MMP2_CLK_DISP1_MUX 110 63#define MMP2_CLK_CCIC_ARBITER 111 64#define MMP2_CLK_CCIC0 112 65#define MMP2_CLK_CCIC0_MIX 113 66#define MMP2_CLK_CCIC0_PHY 114 67#define MMP2_CLK_CCIC0_SPHY 115 68#define MMP2_CLK_CCIC1 116 69#define MMP2_CLK_CCIC1_MIX 117 70#define MMP2_CLK_CCIC1_PHY 118 71#define MMP2_CLK_CCIC1_SPHY 119 72 73#define MMP2_NR_CLKS 200 74#endif 75