1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Synthesize TLB refill handlers at runtime. 7 * 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 11 * Copyright (C) 2008, 2009 Cavium Networks, Inc. 12 * Copyright (C) 2011 MIPS Technologies, Inc. 13 * 14 * ... and the days got worse and worse and now you see 15 * I've gone completly out of my mind. 16 * 17 * They're coming to take me a away haha 18 * they're coming to take me a away hoho hihi haha 19 * to the funny farm where code is beautiful all the time ... 20 * 21 * (Condolences to Napoleon XIV) 22 */ 23 24#include <linux/bug.h> 25#include <linux/kernel.h> 26#include <linux/types.h> 27#include <linux/smp.h> 28#include <linux/string.h> 29#include <linux/cache.h> 30 31#include <asm/cacheflush.h> 32#include <asm/cpu-type.h> 33#include <asm/pgtable.h> 34#include <asm/war.h> 35#include <asm/uasm.h> 36#include <asm/setup.h> 37 38static int __cpuinitdata mips_xpa_disabled; 39 40static int __init xpa_disable(char *s) 41{ 42 mips_xpa_disabled = 1; 43 44 return 1; 45} 46 47__setup("noxpa", xpa_disable); 48 49/* 50 * TLB load/store/modify handlers. 51 * 52 * Only the fastpath gets synthesized at runtime, the slowpath for 53 * do_page_fault remains normal asm. 54 */ 55extern void tlb_do_page_fault_0(void); 56extern void tlb_do_page_fault_1(void); 57 58struct work_registers { 59 int r1; 60 int r2; 61 int r3; 62}; 63 64struct tlb_reg_save { 65 unsigned long a; 66 unsigned long b; 67} ____cacheline_aligned_in_smp; 68 69static struct tlb_reg_save handler_reg_save[NR_CPUS]; 70 71static inline int r45k_bvahwbug(void) 72{ 73 /* XXX: We should probe for the presence of this bug, but we don't. */ 74 return 0; 75} 76 77static inline int r4k_250MHZhwbug(void) 78{ 79 /* XXX: We should probe for the presence of this bug, but we don't. */ 80 return 0; 81} 82 83static inline int __maybe_unused bcm1250_m3_war(void) 84{ 85 return BCM1250_M3_WAR; 86} 87 88static inline int __maybe_unused r10000_llsc_war(void) 89{ 90 return R10000_LLSC_WAR; 91} 92 93static int use_bbit_insns(void) 94{ 95 switch (current_cpu_type()) { 96 case CPU_CAVIUM_OCTEON: 97 case CPU_CAVIUM_OCTEON_PLUS: 98 case CPU_CAVIUM_OCTEON2: 99 case CPU_CAVIUM_OCTEON3: 100 return 1; 101 default: 102 return 0; 103 } 104} 105 106static int use_lwx_insns(void) 107{ 108 switch (current_cpu_type()) { 109 case CPU_CAVIUM_OCTEON2: 110 case CPU_CAVIUM_OCTEON3: 111 return 1; 112 default: 113 return 0; 114 } 115} 116#if defined(CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE) && \ 117 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 118static bool scratchpad_available(void) 119{ 120 return true; 121} 122static int scratchpad_offset(int i) 123{ 124 /* 125 * CVMSEG starts at address -32768 and extends for 126 * CAVIUM_OCTEON_CVMSEG_SIZE 128 byte cache lines. 127 */ 128 i += 1; /* Kernel use starts at the top and works down. */ 129 return CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128 - (8 * i) - 32768; 130} 131#else 132static bool scratchpad_available(void) 133{ 134 return false; 135} 136static int scratchpad_offset(int i) 137{ 138 BUG(); 139 /* Really unreachable, but evidently some GCC want this. */ 140 return 0; 141} 142#endif 143/* 144 * Found by experiment: At least some revisions of the 4kc throw under 145 * some circumstances a machine check exception, triggered by invalid 146 * values in the index register. Delaying the tlbp instruction until 147 * after the next branch, plus adding an additional nop in front of 148 * tlbwi/tlbwr avoids the invalid index register values. Nobody knows 149 * why; it's not an issue caused by the core RTL. 150 * 151 */ 152static int m4kc_tlbp_war(void) 153{ 154 return (current_cpu_data.processor_id & 0xffff00) == 155 (PRID_COMP_MIPS | PRID_IMP_4KC); 156} 157 158/* Handle labels (which must be positive integers). */ 159enum label_id { 160 label_second_part = 1, 161 label_leave, 162 label_vmalloc, 163 label_vmalloc_done, 164 label_tlbw_hazard_0, 165 label_split = label_tlbw_hazard_0 + 8, 166 label_tlbl_goaround1, 167 label_tlbl_goaround2, 168 label_nopage_tlbl, 169 label_nopage_tlbs, 170 label_nopage_tlbm, 171 label_smp_pgtable_change, 172 label_r3000_write_probe_fail, 173 label_large_segbits_fault, 174#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 175 label_tlb_huge_update, 176#endif 177}; 178 179UASM_L_LA(_second_part) 180UASM_L_LA(_leave) 181UASM_L_LA(_vmalloc) 182UASM_L_LA(_vmalloc_done) 183/* _tlbw_hazard_x is handled differently. */ 184UASM_L_LA(_split) 185UASM_L_LA(_tlbl_goaround1) 186UASM_L_LA(_tlbl_goaround2) 187UASM_L_LA(_nopage_tlbl) 188UASM_L_LA(_nopage_tlbs) 189UASM_L_LA(_nopage_tlbm) 190UASM_L_LA(_smp_pgtable_change) 191UASM_L_LA(_r3000_write_probe_fail) 192UASM_L_LA(_large_segbits_fault) 193#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 194UASM_L_LA(_tlb_huge_update) 195#endif 196 197static int hazard_instance; 198 199static void uasm_bgezl_hazard(u32 **p, struct uasm_reloc **r, int instance) 200{ 201 switch (instance) { 202 case 0 ... 7: 203 uasm_il_bgezl(p, r, 0, label_tlbw_hazard_0 + instance); 204 return; 205 default: 206 BUG(); 207 } 208} 209 210static void uasm_bgezl_label(struct uasm_label **l, u32 **p, int instance) 211{ 212 switch (instance) { 213 case 0 ... 7: 214 uasm_build_label(l, *p, label_tlbw_hazard_0 + instance); 215 break; 216 default: 217 BUG(); 218 } 219} 220 221/* 222 * pgtable bits are assigned dynamically depending on processor feature 223 * and statically based on kernel configuration. This spits out the actual 224 * values the kernel is using. Required to make sense from disassembled 225 * TLB exception handlers. 226 */ 227static void output_pgtable_bits_defines(void) 228{ 229#define pr_define(fmt, ...) \ 230 pr_debug("#define " fmt, ##__VA_ARGS__) 231 232 pr_debug("#include <asm/asm.h>\n"); 233 pr_debug("#include <asm/regdef.h>\n"); 234 pr_debug("\n"); 235 236 pr_define("_PAGE_PRESENT_SHIFT %d\n", _PAGE_PRESENT_SHIFT); 237 pr_define("_PAGE_READ_SHIFT %d\n", _PAGE_READ_SHIFT); 238 pr_define("_PAGE_WRITE_SHIFT %d\n", _PAGE_WRITE_SHIFT); 239 pr_define("_PAGE_ACCESSED_SHIFT %d\n", _PAGE_ACCESSED_SHIFT); 240 pr_define("_PAGE_MODIFIED_SHIFT %d\n", _PAGE_MODIFIED_SHIFT); 241#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 242 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 243 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); 244#endif 245#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) 246 if (cpu_has_rixi) { 247#ifdef _PAGE_NO_EXEC_SHIFT 248 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 249 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 250#endif 251 } 252#endif 253 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 254 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 255 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); 256 pr_define("_PFN_SHIFT %d\n", _PFN_SHIFT); 257 pr_debug("\n"); 258} 259 260static inline void dump_handler(const char *symbol, const u32 *handler, int count) 261{ 262 int i; 263 264 pr_debug("LEAF(%s)\n", symbol); 265 266 pr_debug("\t.set push\n"); 267 pr_debug("\t.set noreorder\n"); 268 269 for (i = 0; i < count; i++) 270 pr_debug("\t.word\t0x%08x\t\t# %p\n", handler[i], &handler[i]); 271 272 pr_debug("\t.set\tpop\n"); 273 274 pr_debug("\tEND(%s)\n", symbol); 275} 276 277/* The only general purpose registers allowed in TLB handlers. */ 278#define K0 26 279#define K1 27 280 281/* Some CP0 registers */ 282#define C0_INDEX 0, 0 283#define C0_ENTRYLO0 2, 0 284#define C0_TCBIND 2, 2 285#define C0_ENTRYLO1 3, 0 286#define C0_CONTEXT 4, 0 287#define C0_PAGEMASK 5, 0 288#define C0_BADVADDR 8, 0 289#define C0_ENTRYHI 10, 0 290#define C0_EPC 14, 0 291#define C0_XCONTEXT 20, 0 292 293#ifdef CONFIG_64BIT 294# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_XCONTEXT) 295#else 296# define GET_CONTEXT(buf, reg) UASM_i_MFC0(buf, reg, C0_CONTEXT) 297#endif 298 299/* The worst case length of the handler is around 18 instructions for 300 * R3000-style TLBs and up to 63 instructions for R4000-style TLBs. 301 * Maximum space available is 32 instructions for R3000 and 64 302 * instructions for R4000. 303 * 304 * We deliberately chose a buffer size of 128, so we won't scribble 305 * over anything important on overflow before we panic. 306 */ 307static u32 tlb_handler[128]; 308 309/* simply assume worst case size for labels and relocs */ 310static struct uasm_label labels[128]; 311static struct uasm_reloc relocs[128]; 312 313static int check_for_high_segbits; 314 315static unsigned int kscratch_used_mask; 316 317static inline int __maybe_unused c0_kscratch(void) 318{ 319 switch (current_cpu_type()) { 320 case CPU_XLP: 321 case CPU_XLR: 322 return 22; 323 default: 324 return 31; 325 } 326} 327 328static int allocate_kscratch(void) 329{ 330 int r; 331 unsigned int a = cpu_data[0].kscratch_mask & ~kscratch_used_mask; 332 333 r = ffs(a); 334 335 if (r == 0) 336 return -1; 337 338 r--; /* make it zero based */ 339 340 kscratch_used_mask |= (1 << r); 341 342 return r; 343} 344 345static int scratch_reg; 346static int pgd_reg; 347enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch}; 348 349static struct work_registers build_get_work_registers(u32 **p) 350{ 351 struct work_registers r; 352 353 if (scratch_reg >= 0) { 354 /* Save in CPU local C0_KScratch? */ 355 UASM_i_MTC0(p, 1, c0_kscratch(), scratch_reg); 356 r.r1 = K0; 357 r.r2 = K1; 358 r.r3 = 1; 359 return r; 360 } 361 362 if (num_possible_cpus() > 1) { 363 /* Get smp_processor_id */ 364 UASM_i_CPUID_MFC0(p, K0, SMP_CPUID_REG); 365 UASM_i_SRL_SAFE(p, K0, K0, SMP_CPUID_REGSHIFT); 366 367 /* handler_reg_save index in K0 */ 368 UASM_i_SLL(p, K0, K0, ilog2(sizeof(struct tlb_reg_save))); 369 370 UASM_i_LA(p, K1, (long)&handler_reg_save); 371 UASM_i_ADDU(p, K0, K0, K1); 372 } else { 373 UASM_i_LA(p, K0, (long)&handler_reg_save); 374 } 375 /* K0 now points to save area, save $1 and $2 */ 376 UASM_i_SW(p, 1, offsetof(struct tlb_reg_save, a), K0); 377 UASM_i_SW(p, 2, offsetof(struct tlb_reg_save, b), K0); 378 379 r.r1 = K1; 380 r.r2 = 1; 381 r.r3 = 2; 382 return r; 383} 384 385static void build_restore_work_registers(u32 **p) 386{ 387 if (scratch_reg >= 0) { 388 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 389 return; 390 } 391 /* K0 already points to save area, restore $1 and $2 */ 392 UASM_i_LW(p, 1, offsetof(struct tlb_reg_save, a), K0); 393 UASM_i_LW(p, 2, offsetof(struct tlb_reg_save, b), K0); 394} 395 396#ifndef CONFIG_MIPS_PGD_C0_CONTEXT 397 398/* 399 * CONFIG_MIPS_PGD_C0_CONTEXT implies 64 bit and lack of pgd_current, 400 * we cannot do r3000 under these circumstances. 401 * 402 * Declare pgd_current here instead of including mmu_context.h to avoid type 403 * conflicts for tlbmiss_handler_setup_pgd 404 */ 405extern unsigned long pgd_current[]; 406 407/* 408 * The R3000 TLB handler is simple. 409 */ 410static void build_r3000_tlb_refill_handler(void) 411{ 412 long pgdc = (long)pgd_current; 413 u32 *p; 414 415 memset(tlb_handler, 0, sizeof(tlb_handler)); 416 p = tlb_handler; 417 418 uasm_i_mfc0(&p, K0, C0_BADVADDR); 419 uasm_i_lui(&p, K1, uasm_rel_hi(pgdc)); /* cp0 delay */ 420 uasm_i_lw(&p, K1, uasm_rel_lo(pgdc), K1); 421 uasm_i_srl(&p, K0, K0, 22); /* load delay */ 422 uasm_i_sll(&p, K0, K0, 2); 423 uasm_i_addu(&p, K1, K1, K0); 424 uasm_i_mfc0(&p, K0, C0_CONTEXT); 425 uasm_i_lw(&p, K1, 0, K1); /* cp0 delay */ 426 uasm_i_andi(&p, K0, K0, 0xffc); /* load delay */ 427 uasm_i_addu(&p, K1, K1, K0); 428 uasm_i_lw(&p, K0, 0, K1); 429 uasm_i_nop(&p); /* load delay */ 430 uasm_i_mtc0(&p, K0, C0_ENTRYLO0); 431 uasm_i_mfc0(&p, K1, C0_EPC); /* cp0 delay */ 432 uasm_i_tlbwr(&p); /* cp0 delay */ 433 uasm_i_jr(&p, K1); 434 uasm_i_rfe(&p); /* branch delay */ 435 436 if (p > tlb_handler + 32) 437 panic("TLB refill handler space exceeded"); 438 439 pr_debug("Wrote TLB refill handler (%u instructions).\n", 440 (unsigned int)(p - tlb_handler)); 441 442 memcpy((void *)ebase, tlb_handler, 0x80); 443 local_flush_icache_range(ebase, ebase + 0x80); 444 445 dump_handler("r3000_tlb_refill", (u32 *)ebase, 32); 446} 447#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 448 449/* 450 * The R4000 TLB handler is much more complicated. We have two 451 * consecutive handler areas with 32 instructions space each. 452 * Since they aren't used at the same time, we can overflow in the 453 * other one.To keep things simple, we first assume linear space, 454 * then we relocate it to the final handler layout as needed. 455 */ 456static u32 final_handler[64]; 457 458/* 459 * Hazards 460 * 461 * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0: 462 * 2. A timing hazard exists for the TLBP instruction. 463 * 464 * stalling_instruction 465 * TLBP 466 * 467 * The JTLB is being read for the TLBP throughout the stall generated by the 468 * previous instruction. This is not really correct as the stalling instruction 469 * can modify the address used to access the JTLB. The failure symptom is that 470 * the TLBP instruction will use an address created for the stalling instruction 471 * and not the address held in C0_ENHI and thus report the wrong results. 472 * 473 * The software work-around is to not allow the instruction preceding the TLBP 474 * to stall - make it an NOP or some other instruction guaranteed not to stall. 475 * 476 * Errata 2 will not be fixed. This errata is also on the R5000. 477 * 478 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 479 */ 480static void __maybe_unused build_tlb_probe_entry(u32 **p) 481{ 482 switch (current_cpu_type()) { 483 /* Found by experiment: R4600 v2.0/R4700 needs this, too. */ 484 case CPU_R4600: 485 case CPU_R4700: 486 case CPU_R5000: 487 case CPU_NEVADA: 488 uasm_i_nop(p); 489 uasm_i_tlbp(p); 490 break; 491 492 default: 493 uasm_i_tlbp(p); 494 break; 495 } 496} 497 498/* 499 * Write random or indexed TLB entry, and care about the hazards from 500 * the preceding mtc0 and for the following eret. 501 */ 502enum tlb_write_entry { tlb_random, tlb_indexed }; 503 504static void build_tlb_write_entry(u32 **p, struct uasm_label **l, 505 struct uasm_reloc **r, 506 enum tlb_write_entry wmode) 507{ 508 void(*tlbw)(u32 **) = NULL; 509 510 switch (wmode) { 511 case tlb_random: tlbw = uasm_i_tlbwr; break; 512 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 513 } 514 515 if (cpu_has_mips_r2_r6) { 516 if (cpu_has_mips_r2_exec_hazard) 517 uasm_i_ehb(p); 518 tlbw(p); 519 return; 520 } 521 522 switch (current_cpu_type()) { 523 case CPU_R4000PC: 524 case CPU_R4000SC: 525 case CPU_R4000MC: 526 case CPU_R4400PC: 527 case CPU_R4400SC: 528 case CPU_R4400MC: 529 /* 530 * This branch uses up a mtc0 hazard nop slot and saves 531 * two nops after the tlbw instruction. 532 */ 533 uasm_bgezl_hazard(p, r, hazard_instance); 534 tlbw(p); 535 uasm_bgezl_label(l, p, hazard_instance); 536 hazard_instance++; 537 uasm_i_nop(p); 538 break; 539 540 case CPU_R4600: 541 case CPU_R4700: 542 uasm_i_nop(p); 543 tlbw(p); 544 uasm_i_nop(p); 545 break; 546 547 case CPU_R5000: 548 case CPU_NEVADA: 549 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 550 uasm_i_nop(p); /* QED specifies 2 nops hazard */ 551 tlbw(p); 552 break; 553 554 case CPU_R4300: 555 case CPU_5KC: 556 case CPU_TX49XX: 557 case CPU_PR4450: 558 case CPU_XLR: 559 uasm_i_nop(p); 560 tlbw(p); 561 break; 562 563 case CPU_R10000: 564 case CPU_R12000: 565 case CPU_R14000: 566 case CPU_R16000: 567 case CPU_4KC: 568 case CPU_4KEC: 569 case CPU_M14KC: 570 case CPU_M14KEC: 571 case CPU_SB1: 572 case CPU_SB1A: 573 case CPU_4KSC: 574 case CPU_20KC: 575 case CPU_25KF: 576 case CPU_BMIPS32: 577 case CPU_BMIPS3300: 578 case CPU_BMIPS4350: 579 case CPU_BMIPS4380: 580 case CPU_BMIPS5000: 581 case CPU_LOONGSON2: 582 case CPU_LOONGSON3: 583 case CPU_R5500: 584 if (m4kc_tlbp_war()) 585 uasm_i_nop(p); 586 case CPU_ALCHEMY: 587 tlbw(p); 588 break; 589 590 case CPU_RM7000: 591 uasm_i_nop(p); 592 uasm_i_nop(p); 593 uasm_i_nop(p); 594 uasm_i_nop(p); 595 tlbw(p); 596 break; 597 598 case CPU_VR4111: 599 case CPU_VR4121: 600 case CPU_VR4122: 601 case CPU_VR4181: 602 case CPU_VR4181A: 603 uasm_i_nop(p); 604 uasm_i_nop(p); 605 tlbw(p); 606 uasm_i_nop(p); 607 uasm_i_nop(p); 608 break; 609 610 case CPU_VR4131: 611 case CPU_VR4133: 612 case CPU_R5432: 613 uasm_i_nop(p); 614 uasm_i_nop(p); 615 tlbw(p); 616 break; 617 618 case CPU_JZRISC: 619 tlbw(p); 620 uasm_i_nop(p); 621 break; 622 623 default: 624 panic("No TLB refill handler yet (CPU type: %d)", 625 current_cpu_type()); 626 break; 627 } 628} 629 630static __maybe_unused void build_convert_pte_to_entrylo(u32 **p, 631 unsigned int reg) 632{ 633 if (cpu_has_rixi) { 634 UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL)); 635 } else { 636#ifdef CONFIG_PHYS_ADDR_T_64BIT 637 uasm_i_dsrl_safe(p, reg, reg, ilog2(_PAGE_GLOBAL)); 638#else 639 UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); 640#endif 641 } 642} 643 644#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 645 646static void build_restore_pagemask(u32 **p, struct uasm_reloc **r, 647 unsigned int tmp, enum label_id lid, 648 int restore_scratch) 649{ 650 if (restore_scratch) { 651 /* Reset default page size */ 652 if (PM_DEFAULT_MASK >> 16) { 653 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 654 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 655 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 656 uasm_il_b(p, r, lid); 657 } else if (PM_DEFAULT_MASK) { 658 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 659 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 660 uasm_il_b(p, r, lid); 661 } else { 662 uasm_i_mtc0(p, 0, C0_PAGEMASK); 663 uasm_il_b(p, r, lid); 664 } 665 if (scratch_reg >= 0) 666 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 667 else 668 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 669 } else { 670 /* Reset default page size */ 671 if (PM_DEFAULT_MASK >> 16) { 672 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); 673 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); 674 uasm_il_b(p, r, lid); 675 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 676 } else if (PM_DEFAULT_MASK) { 677 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); 678 uasm_il_b(p, r, lid); 679 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 680 } else { 681 uasm_il_b(p, r, lid); 682 uasm_i_mtc0(p, 0, C0_PAGEMASK); 683 } 684 } 685} 686 687static void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, 688 struct uasm_reloc **r, 689 unsigned int tmp, 690 enum tlb_write_entry wmode, 691 int restore_scratch) 692{ 693 /* Set huge page tlb entry size */ 694 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); 695 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); 696 uasm_i_mtc0(p, tmp, C0_PAGEMASK); 697 698 build_tlb_write_entry(p, l, r, wmode); 699 700 build_restore_pagemask(p, r, tmp, label_leave, restore_scratch); 701} 702 703/* 704 * Check if Huge PTE is present, if so then jump to LABEL. 705 */ 706static void 707build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp, 708 unsigned int pmd, int lid) 709{ 710 UASM_i_LW(p, tmp, 0, pmd); 711 if (use_bbit_insns()) { 712 uasm_il_bbit1(p, r, tmp, ilog2(_PAGE_HUGE), lid); 713 } else { 714 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE); 715 uasm_il_bnez(p, r, tmp, lid); 716 } 717} 718 719static void build_huge_update_entries(u32 **p, unsigned int pte, 720 unsigned int tmp) 721{ 722 int small_sequence; 723 724 /* 725 * A huge PTE describes an area the size of the 726 * configured huge page size. This is twice the 727 * of the large TLB entry size we intend to use. 728 * A TLB entry half the size of the configured 729 * huge page size is configured into entrylo0 730 * and entrylo1 to cover the contiguous huge PTE 731 * address space. 732 */ 733 small_sequence = (HPAGE_SIZE >> 7) < 0x10000; 734 735 /* We can clobber tmp. It isn't used after this.*/ 736 if (!small_sequence) 737 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); 738 739 build_convert_pte_to_entrylo(p, pte); 740 UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ 741 /* convert to entrylo1 */ 742 if (small_sequence) 743 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); 744 else 745 UASM_i_ADDU(p, pte, pte, tmp); 746 747 UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ 748} 749 750static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r, 751 struct uasm_label **l, 752 unsigned int pte, 753 unsigned int ptr) 754{ 755#ifdef CONFIG_SMP 756 UASM_i_SC(p, pte, 0, ptr); 757 uasm_il_beqz(p, r, pte, label_tlb_huge_update); 758 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */ 759#else 760 UASM_i_SW(p, pte, 0, ptr); 761#endif 762 build_huge_update_entries(p, pte, ptr); 763 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed, 0); 764} 765#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 766 767#ifdef CONFIG_64BIT 768/* 769 * TMP and PTR are scratch. 770 * TMP will be clobbered, PTR will hold the pmd entry. 771 */ 772static void 773build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 774 unsigned int tmp, unsigned int ptr) 775{ 776#ifndef CONFIG_MIPS_PGD_C0_CONTEXT 777 long pgdc = (long)pgd_current; 778#endif 779 /* 780 * The vmalloc handling is not in the hotpath. 781 */ 782 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 783 784 if (check_for_high_segbits) { 785 /* 786 * The kernel currently implicitely assumes that the 787 * MIPS SEGBITS parameter for the processor is 788 * (PGDIR_SHIFT+PGDIR_BITS) or less, and will never 789 * allocate virtual addresses outside the maximum 790 * range for SEGBITS = (PGDIR_SHIFT+PGDIR_BITS). But 791 * that doesn't prevent user code from accessing the 792 * higher xuseg addresses. Here, we make sure that 793 * everything but the lower xuseg addresses goes down 794 * the module_alloc/vmalloc path. 795 */ 796 uasm_i_dsrl_safe(p, ptr, tmp, PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 797 uasm_il_bnez(p, r, ptr, label_vmalloc); 798 } else { 799 uasm_il_bltz(p, r, tmp, label_vmalloc); 800 } 801 /* No uasm_i_nop needed here, since the next insn doesn't touch TMP. */ 802 803 if (pgd_reg != -1) { 804 /* pgd is in pgd_reg */ 805 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 806 } else { 807#if defined(CONFIG_MIPS_PGD_C0_CONTEXT) 808 /* 809 * &pgd << 11 stored in CONTEXT [23..63]. 810 */ 811 UASM_i_MFC0(p, ptr, C0_CONTEXT); 812 813 /* Clear lower 23 bits of context. */ 814 uasm_i_dins(p, ptr, 0, 0, 23); 815 816 /* 1 0 1 0 1 << 6 xkphys cached */ 817 uasm_i_ori(p, ptr, ptr, 0x540); 818 uasm_i_drotr(p, ptr, ptr, 11); 819#elif defined(CONFIG_SMP) 820 UASM_i_CPUID_MFC0(p, ptr, SMP_CPUID_REG); 821 uasm_i_dsrl_safe(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 822 UASM_i_LA_mostly(p, tmp, pgdc); 823 uasm_i_daddu(p, ptr, ptr, tmp); 824 uasm_i_dmfc0(p, tmp, C0_BADVADDR); 825 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 826#else 827 UASM_i_LA_mostly(p, ptr, pgdc); 828 uasm_i_ld(p, ptr, uasm_rel_lo(pgdc), ptr); 829#endif 830 } 831 832 uasm_l_vmalloc_done(l, *p); 833 834 /* get pgd offset in bytes */ 835 uasm_i_dsrl_safe(p, tmp, tmp, PGDIR_SHIFT - 3); 836 837 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3); 838 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */ 839#ifndef __PAGETABLE_PMD_FOLDED 840 uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 841 uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */ 842 uasm_i_dsrl_safe(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */ 843 uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3); 844 uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */ 845#endif 846} 847 848/* 849 * BVADDR is the faulting address, PTR is scratch. 850 * PTR will hold the pgd for vmalloc. 851 */ 852static void 853build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 854 unsigned int bvaddr, unsigned int ptr, 855 enum vmalloc64_mode mode) 856{ 857 long swpd = (long)swapper_pg_dir; 858 int single_insn_swpd; 859 int did_vmalloc_branch = 0; 860 861 single_insn_swpd = uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd); 862 863 uasm_l_vmalloc(l, *p); 864 865 if (mode != not_refill && check_for_high_segbits) { 866 if (single_insn_swpd) { 867 uasm_il_bltz(p, r, bvaddr, label_vmalloc_done); 868 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 869 did_vmalloc_branch = 1; 870 /* fall through */ 871 } else { 872 uasm_il_bgez(p, r, bvaddr, label_large_segbits_fault); 873 } 874 } 875 if (!did_vmalloc_branch) { 876 if (uasm_in_compat_space_p(swpd) && !uasm_rel_lo(swpd)) { 877 uasm_il_b(p, r, label_vmalloc_done); 878 uasm_i_lui(p, ptr, uasm_rel_hi(swpd)); 879 } else { 880 UASM_i_LA_mostly(p, ptr, swpd); 881 uasm_il_b(p, r, label_vmalloc_done); 882 if (uasm_in_compat_space_p(swpd)) 883 uasm_i_addiu(p, ptr, ptr, uasm_rel_lo(swpd)); 884 else 885 uasm_i_daddiu(p, ptr, ptr, uasm_rel_lo(swpd)); 886 } 887 } 888 if (mode != not_refill && check_for_high_segbits) { 889 uasm_l_large_segbits_fault(l, *p); 890 /* 891 * We get here if we are an xsseg address, or if we are 892 * an xuseg address above (PGDIR_SHIFT+PGDIR_BITS) boundary. 893 * 894 * Ignoring xsseg (assume disabled so would generate 895 * (address errors?), the only remaining possibility 896 * is the upper xuseg addresses. On processors with 897 * TLB_SEGBITS <= PGDIR_SHIFT+PGDIR_BITS, these 898 * addresses would have taken an address error. We try 899 * to mimic that here by taking a load/istream page 900 * fault. 901 */ 902 UASM_i_LA(p, ptr, (unsigned long)tlb_do_page_fault_0); 903 uasm_i_jr(p, ptr); 904 905 if (mode == refill_scratch) { 906 if (scratch_reg >= 0) 907 UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); 908 else 909 UASM_i_LW(p, 1, scratchpad_offset(0), 0); 910 } else { 911 uasm_i_nop(p); 912 } 913 } 914} 915 916#else /* !CONFIG_64BIT */ 917 918/* 919 * TMP and PTR are scratch. 920 * TMP will be clobbered, PTR will hold the pgd entry. 921 */ 922static void __maybe_unused 923build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 924{ 925 if (pgd_reg != -1) { 926 /* pgd is in pgd_reg */ 927 uasm_i_mfc0(p, ptr, c0_kscratch(), pgd_reg); 928 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 929 } else { 930 long pgdc = (long)pgd_current; 931 932 /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */ 933#ifdef CONFIG_SMP 934 uasm_i_mfc0(p, ptr, SMP_CPUID_REG); 935 UASM_i_LA_mostly(p, tmp, pgdc); 936 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT); 937 uasm_i_addu(p, ptr, tmp, ptr); 938#else 939 UASM_i_LA_mostly(p, ptr, pgdc); 940#endif 941 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */ 942 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 943 } 944 uasm_i_srl(p, tmp, tmp, PGDIR_SHIFT); /* get pgd only bits */ 945 uasm_i_sll(p, tmp, tmp, PGD_T_LOG2); 946 uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */ 947} 948 949#endif /* !CONFIG_64BIT */ 950 951static void build_adjust_context(u32 **p, unsigned int ctx) 952{ 953 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 954 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 955 956 switch (current_cpu_type()) { 957 case CPU_VR41XX: 958 case CPU_VR4111: 959 case CPU_VR4121: 960 case CPU_VR4122: 961 case CPU_VR4131: 962 case CPU_VR4181: 963 case CPU_VR4181A: 964 case CPU_VR4133: 965 shift += 2; 966 break; 967 968 default: 969 break; 970 } 971 972 if (shift) 973 UASM_i_SRL(p, ctx, ctx, shift); 974 uasm_i_andi(p, ctx, ctx, mask); 975} 976 977static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 978{ 979 /* 980 * Bug workaround for the Nevada. It seems as if under certain 981 * circumstances the move from cp0_context might produce a 982 * bogus result when the mfc0 instruction and its consumer are 983 * in a different cacheline or a load instruction, probably any 984 * memory reference, is between them. 985 */ 986 switch (current_cpu_type()) { 987 case CPU_NEVADA: 988 UASM_i_LW(p, ptr, 0, ptr); 989 GET_CONTEXT(p, tmp); /* get context reg */ 990 break; 991 992 default: 993 GET_CONTEXT(p, tmp); /* get context reg */ 994 UASM_i_LW(p, ptr, 0, ptr); 995 break; 996 } 997 998 build_adjust_context(p, tmp); 999 UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1000} 1001 1002static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) 1003{ 1004 /* 1005 * 64bit address support (36bit on a 32bit CPU) in a 32bit 1006 * Kernel is a special case. Only a few CPUs use it. 1007 */ 1008#ifdef CONFIG_PHYS_ADDR_T_64BIT 1009 if (cpu_has_64bits) { 1010 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ 1011 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1012 if (cpu_has_rixi) { 1013 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1014 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1015 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); 1016 } else { 1017 uasm_i_dsrl_safe(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ 1018 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1019 uasm_i_dsrl_safe(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ 1020 } 1021 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1022 } else { 1023 int pte_off_even = sizeof(pte_t) / 2; 1024 int pte_off_odd = pte_off_even + sizeof(pte_t); 1025#ifdef CONFIG_XPA 1026 const int scratch = 1; /* Our extra working register */ 1027 1028 uasm_i_addu(p, scratch, 0, ptep); 1029#endif 1030 uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1031 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* odd pte */ 1032 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1033 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); 1034 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1035 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); 1036#ifdef CONFIG_XPA 1037 uasm_i_lw(p, tmp, 0, scratch); 1038 uasm_i_lw(p, ptep, sizeof(pte_t), scratch); 1039 uasm_i_lui(p, scratch, 0xff); 1040 uasm_i_ori(p, scratch, scratch, 0xffff); 1041 uasm_i_and(p, tmp, scratch, tmp); 1042 uasm_i_and(p, ptep, scratch, ptep); 1043 uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1044 uasm_i_mthc0(p, ptep, C0_ENTRYLO1); 1045#endif 1046 } 1047#else 1048 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ 1049 UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ 1050 if (r45k_bvahwbug()) 1051 build_tlb_probe_entry(p); 1052 if (cpu_has_rixi) { 1053 UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1054 if (r4k_250MHZhwbug()) 1055 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1056 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1057 UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); 1058 } else { 1059 UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ 1060 if (r4k_250MHZhwbug()) 1061 UASM_i_MTC0(p, 0, C0_ENTRYLO0); 1062 UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1063 UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ 1064 if (r45k_bvahwbug()) 1065 uasm_i_mfc0(p, tmp, C0_INDEX); 1066 } 1067 if (r4k_250MHZhwbug()) 1068 UASM_i_MTC0(p, 0, C0_ENTRYLO1); 1069 UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1070#endif 1071} 1072 1073struct mips_huge_tlb_info { 1074 int huge_pte; 1075 int restore_scratch; 1076 bool need_reload_pte; 1077}; 1078 1079static struct mips_huge_tlb_info 1080build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l, 1081 struct uasm_reloc **r, unsigned int tmp, 1082 unsigned int ptr, int c0_scratch_reg) 1083{ 1084 struct mips_huge_tlb_info rv; 1085 unsigned int even, odd; 1086 int vmalloc_branch_delay_filled = 0; 1087 const int scratch = 1; /* Our extra working register */ 1088 1089 rv.huge_pte = scratch; 1090 rv.restore_scratch = 0; 1091 rv.need_reload_pte = false; 1092 1093 if (check_for_high_segbits) { 1094 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1095 1096 if (pgd_reg != -1) 1097 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1098 else 1099 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1100 1101 if (c0_scratch_reg >= 0) 1102 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1103 else 1104 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1105 1106 uasm_i_dsrl_safe(p, scratch, tmp, 1107 PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 1108 uasm_il_bnez(p, r, scratch, label_vmalloc); 1109 1110 if (pgd_reg == -1) { 1111 vmalloc_branch_delay_filled = 1; 1112 /* Clear lower 23 bits of context. */ 1113 uasm_i_dins(p, ptr, 0, 0, 23); 1114 } 1115 } else { 1116 if (pgd_reg != -1) 1117 UASM_i_MFC0(p, ptr, c0_kscratch(), pgd_reg); 1118 else 1119 UASM_i_MFC0(p, ptr, C0_CONTEXT); 1120 1121 UASM_i_MFC0(p, tmp, C0_BADVADDR); 1122 1123 if (c0_scratch_reg >= 0) 1124 UASM_i_MTC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1125 else 1126 UASM_i_SW(p, scratch, scratchpad_offset(0), 0); 1127 1128 if (pgd_reg == -1) 1129 /* Clear lower 23 bits of context. */ 1130 uasm_i_dins(p, ptr, 0, 0, 23); 1131 1132 uasm_il_bltz(p, r, tmp, label_vmalloc); 1133 } 1134 1135 if (pgd_reg == -1) { 1136 vmalloc_branch_delay_filled = 1; 1137 /* 1 0 1 0 1 << 6 xkphys cached */ 1138 uasm_i_ori(p, ptr, ptr, 0x540); 1139 uasm_i_drotr(p, ptr, ptr, 11); 1140 } 1141 1142#ifdef __PAGETABLE_PMD_FOLDED 1143#define LOC_PTEP scratch 1144#else 1145#define LOC_PTEP ptr 1146#endif 1147 1148 if (!vmalloc_branch_delay_filled) 1149 /* get pgd offset in bytes */ 1150 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1151 1152 uasm_l_vmalloc_done(l, *p); 1153 1154 /* 1155 * tmp ptr 1156 * fall-through case = badvaddr *pgd_current 1157 * vmalloc case = badvaddr swapper_pg_dir 1158 */ 1159 1160 if (vmalloc_branch_delay_filled) 1161 /* get pgd offset in bytes */ 1162 uasm_i_dsrl_safe(p, scratch, tmp, PGDIR_SHIFT - 3); 1163 1164#ifdef __PAGETABLE_PMD_FOLDED 1165 GET_CONTEXT(p, tmp); /* get context reg */ 1166#endif 1167 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PGD - 1) << 3); 1168 1169 if (use_lwx_insns()) { 1170 UASM_i_LWX(p, LOC_PTEP, scratch, ptr); 1171 } else { 1172 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pgd offset */ 1173 uasm_i_ld(p, LOC_PTEP, 0, ptr); /* get pmd pointer */ 1174 } 1175 1176#ifndef __PAGETABLE_PMD_FOLDED 1177 /* get pmd offset in bytes */ 1178 uasm_i_dsrl_safe(p, scratch, tmp, PMD_SHIFT - 3); 1179 uasm_i_andi(p, scratch, scratch, (PTRS_PER_PMD - 1) << 3); 1180 GET_CONTEXT(p, tmp); /* get context reg */ 1181 1182 if (use_lwx_insns()) { 1183 UASM_i_LWX(p, scratch, scratch, ptr); 1184 } else { 1185 uasm_i_daddu(p, ptr, ptr, scratch); /* add in pmd offset */ 1186 UASM_i_LW(p, scratch, 0, ptr); 1187 } 1188#endif 1189 /* Adjust the context during the load latency. */ 1190 build_adjust_context(p, tmp); 1191 1192#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1193 uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update); 1194 /* 1195 * The in the LWX case we don't want to do the load in the 1196 * delay slot. It cannot issue in the same cycle and may be 1197 * speculative and unneeded. 1198 */ 1199 if (use_lwx_insns()) 1200 uasm_i_nop(p); 1201#endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */ 1202 1203 1204 /* build_update_entries */ 1205 if (use_lwx_insns()) { 1206 even = ptr; 1207 odd = tmp; 1208 UASM_i_LWX(p, even, scratch, tmp); 1209 UASM_i_ADDIU(p, tmp, tmp, sizeof(pte_t)); 1210 UASM_i_LWX(p, odd, scratch, tmp); 1211 } else { 1212 UASM_i_ADDU(p, ptr, scratch, tmp); /* add in offset */ 1213 even = tmp; 1214 odd = ptr; 1215 UASM_i_LW(p, even, 0, ptr); /* get even pte */ 1216 UASM_i_LW(p, odd, sizeof(pte_t), ptr); /* get odd pte */ 1217 } 1218 if (cpu_has_rixi) { 1219 uasm_i_drotr(p, even, even, ilog2(_PAGE_GLOBAL)); 1220 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1221 uasm_i_drotr(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1222 } else { 1223 uasm_i_dsrl_safe(p, even, even, ilog2(_PAGE_GLOBAL)); 1224 UASM_i_MTC0(p, even, C0_ENTRYLO0); /* load it */ 1225 uasm_i_dsrl_safe(p, odd, odd, ilog2(_PAGE_GLOBAL)); 1226 } 1227 UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ 1228 1229 if (c0_scratch_reg >= 0) { 1230 UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); 1231 build_tlb_write_entry(p, l, r, tlb_random); 1232 uasm_l_leave(l, *p); 1233 rv.restore_scratch = 1; 1234 } else if (PAGE_SHIFT == 14 || PAGE_SHIFT == 13) { 1235 build_tlb_write_entry(p, l, r, tlb_random); 1236 uasm_l_leave(l, *p); 1237 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1238 } else { 1239 UASM_i_LW(p, scratch, scratchpad_offset(0), 0); 1240 build_tlb_write_entry(p, l, r, tlb_random); 1241 uasm_l_leave(l, *p); 1242 rv.restore_scratch = 1; 1243 } 1244 1245 uasm_i_eret(p); /* return from trap */ 1246 1247 return rv; 1248} 1249 1250/* 1251 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception 1252 * because EXL == 0. If we wrap, we can also use the 32 instruction 1253 * slots before the XTLB refill exception handler which belong to the 1254 * unused TLB refill exception. 1255 */ 1256#define MIPS64_REFILL_INSNS 32 1257 1258static void build_r4000_tlb_refill_handler(void) 1259{ 1260 u32 *p = tlb_handler; 1261 struct uasm_label *l = labels; 1262 struct uasm_reloc *r = relocs; 1263 u32 *f; 1264 unsigned int final_len; 1265 struct mips_huge_tlb_info htlb_info __maybe_unused; 1266 enum vmalloc64_mode vmalloc_mode __maybe_unused; 1267 1268 memset(tlb_handler, 0, sizeof(tlb_handler)); 1269 memset(labels, 0, sizeof(labels)); 1270 memset(relocs, 0, sizeof(relocs)); 1271 memset(final_handler, 0, sizeof(final_handler)); 1272 1273 if (IS_ENABLED(CONFIG_64BIT) && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) { 1274 htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1, 1275 scratch_reg); 1276 vmalloc_mode = refill_scratch; 1277 } else { 1278 htlb_info.huge_pte = K0; 1279 htlb_info.restore_scratch = 0; 1280 htlb_info.need_reload_pte = true; 1281 vmalloc_mode = refill_noscratch; 1282 /* 1283 * create the plain linear handler 1284 */ 1285 if (bcm1250_m3_war()) { 1286 unsigned int segbits = 44; 1287 1288 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1289 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1290 uasm_i_xor(&p, K0, K0, K1); 1291 uasm_i_dsrl_safe(&p, K1, K0, 62); 1292 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1293 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1294 uasm_i_or(&p, K0, K0, K1); 1295 uasm_il_bnez(&p, &r, K0, label_leave); 1296 /* No need for uasm_i_nop */ 1297 } 1298 1299#ifdef CONFIG_64BIT 1300 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */ 1301#else 1302 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 1303#endif 1304 1305#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1306 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update); 1307#endif 1308 1309 build_get_ptep(&p, K0, K1); 1310 build_update_entries(&p, K0, K1); 1311 build_tlb_write_entry(&p, &l, &r, tlb_random); 1312 uasm_l_leave(&l, p); 1313 uasm_i_eret(&p); /* return from trap */ 1314 } 1315#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1316 uasm_l_tlb_huge_update(&l, p); 1317 if (htlb_info.need_reload_pte) 1318 UASM_i_LW(&p, htlb_info.huge_pte, 0, K1); 1319 build_huge_update_entries(&p, htlb_info.huge_pte, K1); 1320 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random, 1321 htlb_info.restore_scratch); 1322#endif 1323 1324#ifdef CONFIG_64BIT 1325 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1, vmalloc_mode); 1326#endif 1327 1328 /* 1329 * Overflow check: For the 64bit handler, we need at least one 1330 * free instruction slot for the wrap-around branch. In worst 1331 * case, if the intended insertion point is a delay slot, we 1332 * need three, with the second nop'ed and the third being 1333 * unused. 1334 */ 1335 switch (boot_cpu_type()) { 1336 default: 1337 if (sizeof(long) == 4) { 1338 case CPU_LOONGSON2: 1339 /* Loongson2 ebase is different than r4k, we have more space */ 1340 if ((p - tlb_handler) > 64) 1341 panic("TLB refill handler space exceeded"); 1342 /* 1343 * Now fold the handler in the TLB refill handler space. 1344 */ 1345 f = final_handler; 1346 /* Simplest case, just copy the handler. */ 1347 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1348 final_len = p - tlb_handler; 1349 break; 1350 } else { 1351 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1) 1352 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3) 1353 && uasm_insn_has_bdelay(relocs, 1354 tlb_handler + MIPS64_REFILL_INSNS - 3))) 1355 panic("TLB refill handler space exceeded"); 1356 /* 1357 * Now fold the handler in the TLB refill handler space. 1358 */ 1359 f = final_handler + MIPS64_REFILL_INSNS; 1360 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) { 1361 /* Just copy the handler. */ 1362 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 1363 final_len = p - tlb_handler; 1364 } else { 1365#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1366 const enum label_id ls = label_tlb_huge_update; 1367#else 1368 const enum label_id ls = label_vmalloc; 1369#endif 1370 u32 *split; 1371 int ov = 0; 1372 int i; 1373 1374 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++) 1375 ; 1376 BUG_ON(i == ARRAY_SIZE(labels)); 1377 split = labels[i].addr; 1378 1379 /* 1380 * See if we have overflown one way or the other. 1381 */ 1382 if (split > tlb_handler + MIPS64_REFILL_INSNS || 1383 split < p - MIPS64_REFILL_INSNS) 1384 ov = 1; 1385 1386 if (ov) { 1387 /* 1388 * Split two instructions before the end. One 1389 * for the branch and one for the instruction 1390 * in the delay slot. 1391 */ 1392 split = tlb_handler + MIPS64_REFILL_INSNS - 2; 1393 1394 /* 1395 * If the branch would fall in a delay slot, 1396 * we must back up an additional instruction 1397 * so that it is no longer in a delay slot. 1398 */ 1399 if (uasm_insn_has_bdelay(relocs, split - 1)) 1400 split--; 1401 } 1402 /* Copy first part of the handler. */ 1403 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 1404 f += split - tlb_handler; 1405 1406 if (ov) { 1407 /* Insert branch. */ 1408 uasm_l_split(&l, final_handler); 1409 uasm_il_b(&f, &r, label_split); 1410 if (uasm_insn_has_bdelay(relocs, split)) 1411 uasm_i_nop(&f); 1412 else { 1413 uasm_copy_handler(relocs, labels, 1414 split, split + 1, f); 1415 uasm_move_labels(labels, f, f + 1, -1); 1416 f++; 1417 split++; 1418 } 1419 } 1420 1421 /* Copy the rest of the handler. */ 1422 uasm_copy_handler(relocs, labels, split, p, final_handler); 1423 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) + 1424 (p - split); 1425 } 1426 } 1427 break; 1428 } 1429 1430 uasm_resolve_relocs(relocs, labels); 1431 pr_debug("Wrote TLB refill handler (%u instructions).\n", 1432 final_len); 1433 1434 memcpy((void *)ebase, final_handler, 0x100); 1435 local_flush_icache_range(ebase, ebase + 0x100); 1436 1437 dump_handler("r4000_tlb_refill", (u32 *)ebase, 64); 1438} 1439 1440extern u32 handle_tlbl[], handle_tlbl_end[]; 1441extern u32 handle_tlbs[], handle_tlbs_end[]; 1442extern u32 handle_tlbm[], handle_tlbm_end[]; 1443extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[]; 1444extern u32 tlbmiss_handler_setup_pgd_end[]; 1445 1446static void build_setup_pgd(void) 1447{ 1448 const int a0 = 4; 1449 const int __maybe_unused a1 = 5; 1450 const int __maybe_unused a2 = 6; 1451 u32 *p = tlbmiss_handler_setup_pgd_start; 1452 const int tlbmiss_handler_setup_pgd_size = 1453 tlbmiss_handler_setup_pgd_end - tlbmiss_handler_setup_pgd_start; 1454#ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1455 long pgdc = (long)pgd_current; 1456#endif 1457 1458 memset(tlbmiss_handler_setup_pgd, 0, tlbmiss_handler_setup_pgd_size * 1459 sizeof(tlbmiss_handler_setup_pgd[0])); 1460 memset(labels, 0, sizeof(labels)); 1461 memset(relocs, 0, sizeof(relocs)); 1462 pgd_reg = allocate_kscratch(); 1463#ifdef CONFIG_MIPS_PGD_C0_CONTEXT 1464 if (pgd_reg == -1) { 1465 struct uasm_label *l = labels; 1466 struct uasm_reloc *r = relocs; 1467 1468 /* PGD << 11 in c0_Context */ 1469 /* 1470 * If it is a ckseg0 address, convert to a physical 1471 * address. Shifting right by 29 and adding 4 will 1472 * result in zero for these addresses. 1473 * 1474 */ 1475 UASM_i_SRA(&p, a1, a0, 29); 1476 UASM_i_ADDIU(&p, a1, a1, 4); 1477 uasm_il_bnez(&p, &r, a1, label_tlbl_goaround1); 1478 uasm_i_nop(&p); 1479 uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); 1480 uasm_l_tlbl_goaround1(&l, p); 1481 UASM_i_SLL(&p, a0, a0, 11); 1482 uasm_i_jr(&p, 31); 1483 UASM_i_MTC0(&p, a0, C0_CONTEXT); 1484 } else { 1485 /* PGD in c0_KScratch */ 1486 uasm_i_jr(&p, 31); 1487 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1488 } 1489#else 1490#ifdef CONFIG_SMP 1491 /* Save PGD to pgd_current[smp_processor_id()] */ 1492 UASM_i_CPUID_MFC0(&p, a1, SMP_CPUID_REG); 1493 UASM_i_SRL_SAFE(&p, a1, a1, SMP_CPUID_PTRSHIFT); 1494 UASM_i_LA_mostly(&p, a2, pgdc); 1495 UASM_i_ADDU(&p, a2, a2, a1); 1496 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1497#else 1498 UASM_i_LA_mostly(&p, a2, pgdc); 1499 UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); 1500#endif /* SMP */ 1501 uasm_i_jr(&p, 31); 1502 1503 /* if pgd_reg is allocated, save PGD also to scratch register */ 1504 if (pgd_reg != -1) 1505 UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); 1506 else 1507 uasm_i_nop(&p); 1508#endif 1509 if (p >= tlbmiss_handler_setup_pgd_end) 1510 panic("tlbmiss_handler_setup_pgd space exceeded"); 1511 1512 uasm_resolve_relocs(relocs, labels); 1513 pr_debug("Wrote tlbmiss_handler_setup_pgd (%u instructions).\n", 1514 (unsigned int)(p - tlbmiss_handler_setup_pgd)); 1515 1516 dump_handler("tlbmiss_handler", tlbmiss_handler_setup_pgd, 1517 tlbmiss_handler_setup_pgd_size); 1518} 1519 1520static void 1521iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr) 1522{ 1523#ifdef CONFIG_SMP 1524# ifdef CONFIG_PHYS_ADDR_T_64BIT 1525 if (cpu_has_64bits) 1526 uasm_i_lld(p, pte, 0, ptr); 1527 else 1528# endif 1529 UASM_i_LL(p, pte, 0, ptr); 1530#else 1531# ifdef CONFIG_PHYS_ADDR_T_64BIT 1532 if (cpu_has_64bits) 1533 uasm_i_ld(p, pte, 0, ptr); 1534 else 1535# endif 1536 UASM_i_LW(p, pte, 0, ptr); 1537#endif 1538} 1539 1540static void 1541iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, 1542 unsigned int mode) 1543{ 1544#ifdef CONFIG_PHYS_ADDR_T_64BIT 1545 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1546 1547 if (!cpu_has_64bits) { 1548 const int scratch = 1; /* Our extra working register */ 1549 1550 uasm_i_lui(p, scratch, (mode >> 16)); 1551 uasm_i_or(p, pte, pte, scratch); 1552 } else 1553#endif 1554 uasm_i_ori(p, pte, pte, mode); 1555#ifdef CONFIG_SMP 1556# ifdef CONFIG_PHYS_ADDR_T_64BIT 1557 if (cpu_has_64bits) 1558 uasm_i_scd(p, pte, 0, ptr); 1559 else 1560# endif 1561 UASM_i_SC(p, pte, 0, ptr); 1562 1563 if (r10000_llsc_war()) 1564 uasm_il_beqzl(p, r, pte, label_smp_pgtable_change); 1565 else 1566 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1567 1568# ifdef CONFIG_PHYS_ADDR_T_64BIT 1569 if (!cpu_has_64bits) { 1570 /* no uasm_i_nop needed */ 1571 uasm_i_ll(p, pte, sizeof(pte_t) / 2, ptr); 1572 uasm_i_ori(p, pte, pte, hwmode); 1573 uasm_i_sc(p, pte, sizeof(pte_t) / 2, ptr); 1574 uasm_il_beqz(p, r, pte, label_smp_pgtable_change); 1575 /* no uasm_i_nop needed */ 1576 uasm_i_lw(p, pte, 0, ptr); 1577 } else 1578 uasm_i_nop(p); 1579# else 1580 uasm_i_nop(p); 1581# endif 1582#else 1583# ifdef CONFIG_PHYS_ADDR_T_64BIT 1584 if (cpu_has_64bits) 1585 uasm_i_sd(p, pte, 0, ptr); 1586 else 1587# endif 1588 UASM_i_SW(p, pte, 0, ptr); 1589 1590# ifdef CONFIG_PHYS_ADDR_T_64BIT 1591 if (!cpu_has_64bits) { 1592 uasm_i_lw(p, pte, sizeof(pte_t) / 2, ptr); 1593 uasm_i_ori(p, pte, pte, hwmode); 1594 uasm_i_sw(p, pte, sizeof(pte_t) / 2, ptr); 1595 uasm_i_lw(p, pte, 0, ptr); 1596 } 1597# endif 1598#endif 1599} 1600 1601/* 1602 * Check if PTE is present, if not then jump to LABEL. PTR points to 1603 * the page table where this PTE is located, PTE will be re-loaded 1604 * with it's original value. 1605 */ 1606static void 1607build_pte_present(u32 **p, struct uasm_reloc **r, 1608 int pte, int ptr, int scratch, enum label_id lid) 1609{ 1610 int t = scratch >= 0 ? scratch : pte; 1611 1612 if (cpu_has_rixi) { 1613 if (use_bbit_insns()) { 1614 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1615 uasm_i_nop(p); 1616 } else { 1617 uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); 1618 uasm_i_andi(p, t, t, 1); 1619 uasm_il_beqz(p, r, t, lid); 1620 if (pte == t) 1621 /* You lose the SMP race :-(*/ 1622 iPTE_LW(p, pte, ptr); 1623 } 1624 } else { 1625 uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); 1626 uasm_i_andi(p, t, t, 3); 1627 uasm_i_xori(p, t, t, 3); 1628 uasm_il_bnez(p, r, t, lid); 1629 if (pte == t) 1630 /* You lose the SMP race :-(*/ 1631 iPTE_LW(p, pte, ptr); 1632 } 1633} 1634 1635/* Make PTE valid, store result in PTR. */ 1636static void 1637build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte, 1638 unsigned int ptr) 1639{ 1640 unsigned int mode = _PAGE_VALID | _PAGE_ACCESSED; 1641 1642 iPTE_SW(p, r, pte, ptr, mode); 1643} 1644 1645/* 1646 * Check if PTE can be written to, if not branch to LABEL. Regardless 1647 * restore PTE with value from PTR when done. 1648 */ 1649static void 1650build_pte_writable(u32 **p, struct uasm_reloc **r, 1651 unsigned int pte, unsigned int ptr, int scratch, 1652 enum label_id lid) 1653{ 1654 int t = scratch >= 0 ? scratch : pte; 1655 1656 uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); 1657 uasm_i_andi(p, t, t, 5); 1658 uasm_i_xori(p, t, t, 5); 1659 uasm_il_bnez(p, r, t, lid); 1660 if (pte == t) 1661 /* You lose the SMP race :-(*/ 1662 iPTE_LW(p, pte, ptr); 1663 else 1664 uasm_i_nop(p); 1665} 1666 1667/* Make PTE writable, update software status bits as well, then store 1668 * at PTR. 1669 */ 1670static void 1671build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte, 1672 unsigned int ptr) 1673{ 1674 unsigned int mode = (_PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID 1675 | _PAGE_DIRTY); 1676 1677 iPTE_SW(p, r, pte, ptr, mode); 1678} 1679 1680/* 1681 * Check if PTE can be modified, if not branch to LABEL. Regardless 1682 * restore PTE with value from PTR when done. 1683 */ 1684static void 1685build_pte_modifiable(u32 **p, struct uasm_reloc **r, 1686 unsigned int pte, unsigned int ptr, int scratch, 1687 enum label_id lid) 1688{ 1689 if (use_bbit_insns()) { 1690 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_WRITE), lid); 1691 uasm_i_nop(p); 1692 } else { 1693 int t = scratch >= 0 ? scratch : pte; 1694 uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1695 uasm_i_andi(p, t, t, 1); 1696 uasm_il_beqz(p, r, t, lid); 1697 if (pte == t) 1698 /* You lose the SMP race :-(*/ 1699 iPTE_LW(p, pte, ptr); 1700 } 1701} 1702 1703#ifndef CONFIG_MIPS_PGD_C0_CONTEXT 1704 1705 1706/* 1707 * R3000 style TLB load/store/modify handlers. 1708 */ 1709 1710/* 1711 * This places the pte into ENTRYLO0 and writes it with tlbwi. 1712 * Then it returns. 1713 */ 1714static void 1715build_r3000_pte_reload_tlbwi(u32 **p, unsigned int pte, unsigned int tmp) 1716{ 1717 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1718 uasm_i_mfc0(p, tmp, C0_EPC); /* cp0 delay */ 1719 uasm_i_tlbwi(p); 1720 uasm_i_jr(p, tmp); 1721 uasm_i_rfe(p); /* branch delay */ 1722} 1723 1724/* 1725 * This places the pte into ENTRYLO0 and writes it with tlbwi 1726 * or tlbwr as appropriate. This is because the index register 1727 * may have the probe fail bit set as a result of a trap on a 1728 * kseg2 access, i.e. without refill. Then it returns. 1729 */ 1730static void 1731build_r3000_tlb_reload_write(u32 **p, struct uasm_label **l, 1732 struct uasm_reloc **r, unsigned int pte, 1733 unsigned int tmp) 1734{ 1735 uasm_i_mfc0(p, tmp, C0_INDEX); 1736 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* cp0 delay */ 1737 uasm_il_bltz(p, r, tmp, label_r3000_write_probe_fail); /* cp0 delay */ 1738 uasm_i_mfc0(p, tmp, C0_EPC); /* branch delay */ 1739 uasm_i_tlbwi(p); /* cp0 delay */ 1740 uasm_i_jr(p, tmp); 1741 uasm_i_rfe(p); /* branch delay */ 1742 uasm_l_r3000_write_probe_fail(l, *p); 1743 uasm_i_tlbwr(p); /* cp0 delay */ 1744 uasm_i_jr(p, tmp); 1745 uasm_i_rfe(p); /* branch delay */ 1746} 1747 1748static void 1749build_r3000_tlbchange_handler_head(u32 **p, unsigned int pte, 1750 unsigned int ptr) 1751{ 1752 long pgdc = (long)pgd_current; 1753 1754 uasm_i_mfc0(p, pte, C0_BADVADDR); 1755 uasm_i_lui(p, ptr, uasm_rel_hi(pgdc)); /* cp0 delay */ 1756 uasm_i_lw(p, ptr, uasm_rel_lo(pgdc), ptr); 1757 uasm_i_srl(p, pte, pte, 22); /* load delay */ 1758 uasm_i_sll(p, pte, pte, 2); 1759 uasm_i_addu(p, ptr, ptr, pte); 1760 uasm_i_mfc0(p, pte, C0_CONTEXT); 1761 uasm_i_lw(p, ptr, 0, ptr); /* cp0 delay */ 1762 uasm_i_andi(p, pte, pte, 0xffc); /* load delay */ 1763 uasm_i_addu(p, ptr, ptr, pte); 1764 uasm_i_lw(p, pte, 0, ptr); 1765 uasm_i_tlbp(p); /* load delay */ 1766} 1767 1768static void build_r3000_tlb_load_handler(void) 1769{ 1770 u32 *p = handle_tlbl; 1771 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1772 struct uasm_label *l = labels; 1773 struct uasm_reloc *r = relocs; 1774 1775 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 1776 memset(labels, 0, sizeof(labels)); 1777 memset(relocs, 0, sizeof(relocs)); 1778 1779 build_r3000_tlbchange_handler_head(&p, K0, K1); 1780 build_pte_present(&p, &r, K0, K1, -1, label_nopage_tlbl); 1781 uasm_i_nop(&p); /* load delay */ 1782 build_make_valid(&p, &r, K0, K1); 1783 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1784 1785 uasm_l_nopage_tlbl(&l, p); 1786 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1787 uasm_i_nop(&p); 1788 1789 if (p >= handle_tlbl_end) 1790 panic("TLB load handler fastpath space exceeded"); 1791 1792 uasm_resolve_relocs(relocs, labels); 1793 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 1794 (unsigned int)(p - handle_tlbl)); 1795 1796 dump_handler("r3000_tlb_load", handle_tlbl, handle_tlbl_size); 1797} 1798 1799static void build_r3000_tlb_store_handler(void) 1800{ 1801 u32 *p = handle_tlbs; 1802 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 1803 struct uasm_label *l = labels; 1804 struct uasm_reloc *r = relocs; 1805 1806 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 1807 memset(labels, 0, sizeof(labels)); 1808 memset(relocs, 0, sizeof(relocs)); 1809 1810 build_r3000_tlbchange_handler_head(&p, K0, K1); 1811 build_pte_writable(&p, &r, K0, K1, -1, label_nopage_tlbs); 1812 uasm_i_nop(&p); /* load delay */ 1813 build_make_write(&p, &r, K0, K1); 1814 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1815 1816 uasm_l_nopage_tlbs(&l, p); 1817 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1818 uasm_i_nop(&p); 1819 1820 if (p >= handle_tlbs_end) 1821 panic("TLB store handler fastpath space exceeded"); 1822 1823 uasm_resolve_relocs(relocs, labels); 1824 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 1825 (unsigned int)(p - handle_tlbs)); 1826 1827 dump_handler("r3000_tlb_store", handle_tlbs, handle_tlbs_size); 1828} 1829 1830static void build_r3000_tlb_modify_handler(void) 1831{ 1832 u32 *p = handle_tlbm; 1833 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 1834 struct uasm_label *l = labels; 1835 struct uasm_reloc *r = relocs; 1836 1837 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 1838 memset(labels, 0, sizeof(labels)); 1839 memset(relocs, 0, sizeof(relocs)); 1840 1841 build_r3000_tlbchange_handler_head(&p, K0, K1); 1842 build_pte_modifiable(&p, &r, K0, K1, -1, label_nopage_tlbm); 1843 uasm_i_nop(&p); /* load delay */ 1844 build_make_write(&p, &r, K0, K1); 1845 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1846 1847 uasm_l_nopage_tlbm(&l, p); 1848 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1849 uasm_i_nop(&p); 1850 1851 if (p >= handle_tlbm_end) 1852 panic("TLB modify handler fastpath space exceeded"); 1853 1854 uasm_resolve_relocs(relocs, labels); 1855 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 1856 (unsigned int)(p - handle_tlbm)); 1857 1858 dump_handler("r3000_tlb_modify", handle_tlbm, handle_tlbm_size); 1859} 1860#endif /* CONFIG_MIPS_PGD_C0_CONTEXT */ 1861 1862/* 1863 * R4000 style TLB load/store/modify handlers. 1864 */ 1865static struct work_registers 1866build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l, 1867 struct uasm_reloc **r) 1868{ 1869 struct work_registers wr = build_get_work_registers(p); 1870 1871#ifdef CONFIG_64BIT 1872 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */ 1873#else 1874 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */ 1875#endif 1876 1877#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 1878 /* 1879 * For huge tlb entries, pmd doesn't contain an address but 1880 * instead contains the tlb pte. Check the PAGE_HUGE bit and 1881 * see if we need to jump to huge tlb processing. 1882 */ 1883 build_is_huge_pte(p, r, wr.r1, wr.r2, label_tlb_huge_update); 1884#endif 1885 1886 UASM_i_MFC0(p, wr.r1, C0_BADVADDR); 1887 UASM_i_LW(p, wr.r2, 0, wr.r2); 1888 UASM_i_SRL(p, wr.r1, wr.r1, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1889 uasm_i_andi(p, wr.r1, wr.r1, (PTRS_PER_PTE - 1) << PTE_T_LOG2); 1890 UASM_i_ADDU(p, wr.r2, wr.r2, wr.r1); 1891 1892#ifdef CONFIG_SMP 1893 uasm_l_smp_pgtable_change(l, *p); 1894#endif 1895 iPTE_LW(p, wr.r1, wr.r2); /* get even pte */ 1896 if (!m4kc_tlbp_war()) { 1897 build_tlb_probe_entry(p); 1898 if (cpu_has_htw) { 1899 /* race condition happens, leaving */ 1900 uasm_i_ehb(p); 1901 uasm_i_mfc0(p, wr.r3, C0_INDEX); 1902 uasm_il_bltz(p, r, wr.r3, label_leave); 1903 uasm_i_nop(p); 1904 } 1905 } 1906 return wr; 1907} 1908 1909static void 1910build_r4000_tlbchange_handler_tail(u32 **p, struct uasm_label **l, 1911 struct uasm_reloc **r, unsigned int tmp, 1912 unsigned int ptr) 1913{ 1914 uasm_i_ori(p, ptr, ptr, sizeof(pte_t)); 1915 uasm_i_xori(p, ptr, ptr, sizeof(pte_t)); 1916 build_update_entries(p, tmp, ptr); 1917 build_tlb_write_entry(p, l, r, tlb_indexed); 1918 uasm_l_leave(l, *p); 1919 build_restore_work_registers(p); 1920 uasm_i_eret(p); /* return from trap */ 1921 1922#ifdef CONFIG_64BIT 1923 build_get_pgd_vmalloc64(p, l, r, tmp, ptr, not_refill); 1924#endif 1925} 1926 1927static void build_r4000_tlb_load_handler(void) 1928{ 1929 u32 *p = handle_tlbl; 1930 const int handle_tlbl_size = handle_tlbl_end - handle_tlbl; 1931 struct uasm_label *l = labels; 1932 struct uasm_reloc *r = relocs; 1933 struct work_registers wr; 1934 1935 memset(handle_tlbl, 0, handle_tlbl_size * sizeof(handle_tlbl[0])); 1936 memset(labels, 0, sizeof(labels)); 1937 memset(relocs, 0, sizeof(relocs)); 1938 1939 if (bcm1250_m3_war()) { 1940 unsigned int segbits = 44; 1941 1942 uasm_i_dmfc0(&p, K0, C0_BADVADDR); 1943 uasm_i_dmfc0(&p, K1, C0_ENTRYHI); 1944 uasm_i_xor(&p, K0, K0, K1); 1945 uasm_i_dsrl_safe(&p, K1, K0, 62); 1946 uasm_i_dsrl_safe(&p, K0, K0, 12 + 1); 1947 uasm_i_dsll_safe(&p, K0, K0, 64 + 12 + 1 - segbits); 1948 uasm_i_or(&p, K0, K0, K1); 1949 uasm_il_bnez(&p, &r, K0, label_leave); 1950 /* No need for uasm_i_nop */ 1951 } 1952 1953 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 1954 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 1955 if (m4kc_tlbp_war()) 1956 build_tlb_probe_entry(&p); 1957 1958 if (cpu_has_rixi && !cpu_has_rixiex) { 1959 /* 1960 * If the page is not _PAGE_VALID, RI or XI could not 1961 * have triggered it. Skip the expensive test.. 1962 */ 1963 if (use_bbit_insns()) { 1964 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 1965 label_tlbl_goaround1); 1966 } else { 1967 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 1968 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround1); 1969 } 1970 uasm_i_nop(&p); 1971 1972 uasm_i_tlbr(&p); 1973 1974 switch (current_cpu_type()) { 1975 default: 1976 if (cpu_has_mips_r2_exec_hazard) { 1977 uasm_i_ehb(&p); 1978 1979 case CPU_CAVIUM_OCTEON: 1980 case CPU_CAVIUM_OCTEON_PLUS: 1981 case CPU_CAVIUM_OCTEON2: 1982 break; 1983 } 1984 } 1985 1986 /* Examine entrylo 0 or 1 based on ptr. */ 1987 if (use_bbit_insns()) { 1988 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 1989 } else { 1990 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 1991 uasm_i_beqz(&p, wr.r3, 8); 1992 } 1993 /* load it in the delay slot*/ 1994 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 1995 /* load it if ptr is odd */ 1996 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 1997 /* 1998 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 1999 * XI must have triggered it. 2000 */ 2001 if (use_bbit_insns()) { 2002 uasm_il_bbit1(&p, &r, wr.r3, 1, label_nopage_tlbl); 2003 uasm_i_nop(&p); 2004 uasm_l_tlbl_goaround1(&l, p); 2005 } else { 2006 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2007 uasm_il_bnez(&p, &r, wr.r3, label_nopage_tlbl); 2008 uasm_i_nop(&p); 2009 } 2010 uasm_l_tlbl_goaround1(&l, p); 2011 } 2012 build_make_valid(&p, &r, wr.r1, wr.r2); 2013 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2014 2015#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2016 /* 2017 * This is the entry point when build_r4000_tlbchange_handler_head 2018 * spots a huge page. 2019 */ 2020 uasm_l_tlb_huge_update(&l, p); 2021 iPTE_LW(&p, wr.r1, wr.r2); 2022 build_pte_present(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbl); 2023 build_tlb_probe_entry(&p); 2024 2025 if (cpu_has_rixi && !cpu_has_rixiex) { 2026 /* 2027 * If the page is not _PAGE_VALID, RI or XI could not 2028 * have triggered it. Skip the expensive test.. 2029 */ 2030 if (use_bbit_insns()) { 2031 uasm_il_bbit0(&p, &r, wr.r1, ilog2(_PAGE_VALID), 2032 label_tlbl_goaround2); 2033 } else { 2034 uasm_i_andi(&p, wr.r3, wr.r1, _PAGE_VALID); 2035 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2036 } 2037 uasm_i_nop(&p); 2038 2039 uasm_i_tlbr(&p); 2040 2041 switch (current_cpu_type()) { 2042 default: 2043 if (cpu_has_mips_r2_exec_hazard) { 2044 uasm_i_ehb(&p); 2045 2046 case CPU_CAVIUM_OCTEON: 2047 case CPU_CAVIUM_OCTEON_PLUS: 2048 case CPU_CAVIUM_OCTEON2: 2049 break; 2050 } 2051 } 2052 2053 /* Examine entrylo 0 or 1 based on ptr. */ 2054 if (use_bbit_insns()) { 2055 uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); 2056 } else { 2057 uasm_i_andi(&p, wr.r3, wr.r2, sizeof(pte_t)); 2058 uasm_i_beqz(&p, wr.r3, 8); 2059 } 2060 /* load it in the delay slot*/ 2061 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO0); 2062 /* load it if ptr is odd */ 2063 UASM_i_MFC0(&p, wr.r3, C0_ENTRYLO1); 2064 /* 2065 * If the entryLo (now in wr.r3) is valid (bit 1), RI or 2066 * XI must have triggered it. 2067 */ 2068 if (use_bbit_insns()) { 2069 uasm_il_bbit0(&p, &r, wr.r3, 1, label_tlbl_goaround2); 2070 } else { 2071 uasm_i_andi(&p, wr.r3, wr.r3, 2); 2072 uasm_il_beqz(&p, &r, wr.r3, label_tlbl_goaround2); 2073 } 2074 if (PM_DEFAULT_MASK == 0) 2075 uasm_i_nop(&p); 2076 /* 2077 * We clobbered C0_PAGEMASK, restore it. On the other branch 2078 * it is restored in build_huge_tlb_write_entry. 2079 */ 2080 build_restore_pagemask(&p, &r, wr.r3, label_nopage_tlbl, 0); 2081 2082 uasm_l_tlbl_goaround2(&l, p); 2083 } 2084 uasm_i_ori(&p, wr.r1, wr.r1, (_PAGE_ACCESSED | _PAGE_VALID)); 2085 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); 2086#endif 2087 2088 uasm_l_nopage_tlbl(&l, p); 2089 build_restore_work_registers(&p); 2090#ifdef CONFIG_CPU_MICROMIPS 2091 if ((unsigned long)tlb_do_page_fault_0 & 1) { 2092 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_0)); 2093 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_0)); 2094 uasm_i_jr(&p, K0); 2095 } else 2096#endif 2097 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 2098 uasm_i_nop(&p); 2099 2100 if (p >= handle_tlbl_end) 2101 panic("TLB load handler fastpath space exceeded"); 2102 2103 uasm_resolve_relocs(relocs, labels); 2104 pr_debug("Wrote TLB load handler fastpath (%u instructions).\n", 2105 (unsigned int)(p - handle_tlbl)); 2106 2107 dump_handler("r4000_tlb_load", handle_tlbl, handle_tlbl_size); 2108} 2109 2110static void build_r4000_tlb_store_handler(void) 2111{ 2112 u32 *p = handle_tlbs; 2113 const int handle_tlbs_size = handle_tlbs_end - handle_tlbs; 2114 struct uasm_label *l = labels; 2115 struct uasm_reloc *r = relocs; 2116 struct work_registers wr; 2117 2118 memset(handle_tlbs, 0, handle_tlbs_size * sizeof(handle_tlbs[0])); 2119 memset(labels, 0, sizeof(labels)); 2120 memset(relocs, 0, sizeof(relocs)); 2121 2122 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2123 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2124 if (m4kc_tlbp_war()) 2125 build_tlb_probe_entry(&p); 2126 build_make_write(&p, &r, wr.r1, wr.r2); 2127 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2128 2129#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2130 /* 2131 * This is the entry point when 2132 * build_r4000_tlbchange_handler_head spots a huge page. 2133 */ 2134 uasm_l_tlb_huge_update(&l, p); 2135 iPTE_LW(&p, wr.r1, wr.r2); 2136 build_pte_writable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbs); 2137 build_tlb_probe_entry(&p); 2138 uasm_i_ori(&p, wr.r1, wr.r1, 2139 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2140 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); 2141#endif 2142 2143 uasm_l_nopage_tlbs(&l, p); 2144 build_restore_work_registers(&p); 2145#ifdef CONFIG_CPU_MICROMIPS 2146 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2147 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2148 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2149 uasm_i_jr(&p, K0); 2150 } else 2151#endif 2152 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2153 uasm_i_nop(&p); 2154 2155 if (p >= handle_tlbs_end) 2156 panic("TLB store handler fastpath space exceeded"); 2157 2158 uasm_resolve_relocs(relocs, labels); 2159 pr_debug("Wrote TLB store handler fastpath (%u instructions).\n", 2160 (unsigned int)(p - handle_tlbs)); 2161 2162 dump_handler("r4000_tlb_store", handle_tlbs, handle_tlbs_size); 2163} 2164 2165static void build_r4000_tlb_modify_handler(void) 2166{ 2167 u32 *p = handle_tlbm; 2168 const int handle_tlbm_size = handle_tlbm_end - handle_tlbm; 2169 struct uasm_label *l = labels; 2170 struct uasm_reloc *r = relocs; 2171 struct work_registers wr; 2172 2173 memset(handle_tlbm, 0, handle_tlbm_size * sizeof(handle_tlbm[0])); 2174 memset(labels, 0, sizeof(labels)); 2175 memset(relocs, 0, sizeof(relocs)); 2176 2177 wr = build_r4000_tlbchange_handler_head(&p, &l, &r); 2178 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2179 if (m4kc_tlbp_war()) 2180 build_tlb_probe_entry(&p); 2181 /* Present and writable bits set, set accessed and dirty bits. */ 2182 build_make_write(&p, &r, wr.r1, wr.r2); 2183 build_r4000_tlbchange_handler_tail(&p, &l, &r, wr.r1, wr.r2); 2184 2185#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 2186 /* 2187 * This is the entry point when 2188 * build_r4000_tlbchange_handler_head spots a huge page. 2189 */ 2190 uasm_l_tlb_huge_update(&l, p); 2191 iPTE_LW(&p, wr.r1, wr.r2); 2192 build_pte_modifiable(&p, &r, wr.r1, wr.r2, wr.r3, label_nopage_tlbm); 2193 build_tlb_probe_entry(&p); 2194 uasm_i_ori(&p, wr.r1, wr.r1, 2195 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY); 2196 build_huge_handler_tail(&p, &r, &l, wr.r1, wr.r2); 2197#endif 2198 2199 uasm_l_nopage_tlbm(&l, p); 2200 build_restore_work_registers(&p); 2201#ifdef CONFIG_CPU_MICROMIPS 2202 if ((unsigned long)tlb_do_page_fault_1 & 1) { 2203 uasm_i_lui(&p, K0, uasm_rel_hi((long)tlb_do_page_fault_1)); 2204 uasm_i_addiu(&p, K0, K0, uasm_rel_lo((long)tlb_do_page_fault_1)); 2205 uasm_i_jr(&p, K0); 2206 } else 2207#endif 2208 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 2209 uasm_i_nop(&p); 2210 2211 if (p >= handle_tlbm_end) 2212 panic("TLB modify handler fastpath space exceeded"); 2213 2214 uasm_resolve_relocs(relocs, labels); 2215 pr_debug("Wrote TLB modify handler fastpath (%u instructions).\n", 2216 (unsigned int)(p - handle_tlbm)); 2217 2218 dump_handler("r4000_tlb_modify", handle_tlbm, handle_tlbm_size); 2219} 2220 2221static void flush_tlb_handlers(void) 2222{ 2223 local_flush_icache_range((unsigned long)handle_tlbl, 2224 (unsigned long)handle_tlbl_end); 2225 local_flush_icache_range((unsigned long)handle_tlbs, 2226 (unsigned long)handle_tlbs_end); 2227 local_flush_icache_range((unsigned long)handle_tlbm, 2228 (unsigned long)handle_tlbm_end); 2229 local_flush_icache_range((unsigned long)tlbmiss_handler_setup_pgd, 2230 (unsigned long)tlbmiss_handler_setup_pgd_end); 2231} 2232 2233static void print_htw_config(void) 2234{ 2235 unsigned long config; 2236 unsigned int pwctl; 2237 const int field = 2 * sizeof(unsigned long); 2238 2239 config = read_c0_pwfield(); 2240 pr_debug("PWField (0x%0*lx): GDI: 0x%02lx UDI: 0x%02lx MDI: 0x%02lx PTI: 0x%02lx PTEI: 0x%02lx\n", 2241 field, config, 2242 (config & MIPS_PWFIELD_GDI_MASK) >> MIPS_PWFIELD_GDI_SHIFT, 2243 (config & MIPS_PWFIELD_UDI_MASK) >> MIPS_PWFIELD_UDI_SHIFT, 2244 (config & MIPS_PWFIELD_MDI_MASK) >> MIPS_PWFIELD_MDI_SHIFT, 2245 (config & MIPS_PWFIELD_PTI_MASK) >> MIPS_PWFIELD_PTI_SHIFT, 2246 (config & MIPS_PWFIELD_PTEI_MASK) >> MIPS_PWFIELD_PTEI_SHIFT); 2247 2248 config = read_c0_pwsize(); 2249 pr_debug("PWSize (0x%0*lx): GDW: 0x%02lx UDW: 0x%02lx MDW: 0x%02lx PTW: 0x%02lx PTEW: 0x%02lx\n", 2250 field, config, 2251 (config & MIPS_PWSIZE_GDW_MASK) >> MIPS_PWSIZE_GDW_SHIFT, 2252 (config & MIPS_PWSIZE_UDW_MASK) >> MIPS_PWSIZE_UDW_SHIFT, 2253 (config & MIPS_PWSIZE_MDW_MASK) >> MIPS_PWSIZE_MDW_SHIFT, 2254 (config & MIPS_PWSIZE_PTW_MASK) >> MIPS_PWSIZE_PTW_SHIFT, 2255 (config & MIPS_PWSIZE_PTEW_MASK) >> MIPS_PWSIZE_PTEW_SHIFT); 2256 2257 pwctl = read_c0_pwctl(); 2258 pr_debug("PWCtl (0x%x): PWEn: 0x%x DPH: 0x%x HugePg: 0x%x Psn: 0x%x\n", 2259 pwctl, 2260 (pwctl & MIPS_PWCTL_PWEN_MASK) >> MIPS_PWCTL_PWEN_SHIFT, 2261 (pwctl & MIPS_PWCTL_DPH_MASK) >> MIPS_PWCTL_DPH_SHIFT, 2262 (pwctl & MIPS_PWCTL_HUGEPG_MASK) >> MIPS_PWCTL_HUGEPG_SHIFT, 2263 (pwctl & MIPS_PWCTL_PSN_MASK) >> MIPS_PWCTL_PSN_SHIFT); 2264} 2265 2266static void config_htw_params(void) 2267{ 2268 unsigned long pwfield, pwsize, ptei; 2269 unsigned int config; 2270 2271 /* 2272 * We are using 2-level page tables, so we only need to 2273 * setup GDW and PTW appropriately. UDW and MDW will remain 0. 2274 * The default value of GDI/UDI/MDI/PTI is 0xc. It is illegal to 2275 * write values less than 0xc in these fields because the entire 2276 * write will be dropped. As a result of which, we must preserve 2277 * the original reset values and overwrite only what we really want. 2278 */ 2279 2280 pwfield = read_c0_pwfield(); 2281 /* re-initialize the GDI field */ 2282 pwfield &= ~MIPS_PWFIELD_GDI_MASK; 2283 pwfield |= PGDIR_SHIFT << MIPS_PWFIELD_GDI_SHIFT; 2284 /* re-initialize the PTI field including the even/odd bit */ 2285 pwfield &= ~MIPS_PWFIELD_PTI_MASK; 2286 pwfield |= PAGE_SHIFT << MIPS_PWFIELD_PTI_SHIFT; 2287 /* Set the PTEI right shift */ 2288 ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT; 2289 pwfield |= ptei; 2290 write_c0_pwfield(pwfield); 2291 /* Check whether the PTEI value is supported */ 2292 back_to_back_c0_hazard(); 2293 pwfield = read_c0_pwfield(); 2294 if (((pwfield & MIPS_PWFIELD_PTEI_MASK) << MIPS_PWFIELD_PTEI_SHIFT) 2295 != ptei) { 2296 pr_warn("Unsupported PTEI field value: 0x%lx. HTW will not be enabled", 2297 ptei); 2298 /* 2299 * Drop option to avoid HTW being enabled via another path 2300 * (eg htw_reset()) 2301 */ 2302 current_cpu_data.options &= ~MIPS_CPU_HTW; 2303 return; 2304 } 2305 2306 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2307 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2308 2309 /* If XPA has been enabled, PTEs are 64-bit in size. */ 2310 if (read_c0_pagegrain() & PG_ELPA) 2311 pwsize |= 1; 2312 2313 write_c0_pwsize(pwsize); 2314 2315 /* Make sure everything is set before we enable the HTW */ 2316 back_to_back_c0_hazard(); 2317 2318 /* Enable HTW and disable the rest of the pwctl fields */ 2319 config = 1 << MIPS_PWCTL_PWEN_SHIFT; 2320 write_c0_pwctl(config); 2321 pr_info("Hardware Page Table Walker enabled\n"); 2322 2323 print_htw_config(); 2324} 2325 2326static void config_xpa_params(void) 2327{ 2328#ifdef CONFIG_XPA 2329 unsigned int pagegrain; 2330 2331 if (mips_xpa_disabled) { 2332 pr_info("Extended Physical Addressing (XPA) disabled\n"); 2333 return; 2334 } 2335 2336 pagegrain = read_c0_pagegrain(); 2337 write_c0_pagegrain(pagegrain | PG_ELPA); 2338 back_to_back_c0_hazard(); 2339 pagegrain = read_c0_pagegrain(); 2340 2341 if (pagegrain & PG_ELPA) 2342 pr_info("Extended Physical Addressing (XPA) enabled\n"); 2343 else 2344 panic("Extended Physical Addressing (XPA) disabled"); 2345#endif 2346} 2347 2348void build_tlb_refill_handler(void) 2349{ 2350 /* 2351 * The refill handler is generated per-CPU, multi-node systems 2352 * may have local storage for it. The other handlers are only 2353 * needed once. 2354 */ 2355 static int run_once = 0; 2356 2357 output_pgtable_bits_defines(); 2358 2359#ifdef CONFIG_64BIT 2360 check_for_high_segbits = current_cpu_data.vmbits > (PGDIR_SHIFT + PGD_ORDER + PAGE_SHIFT - 3); 2361#endif 2362 2363 switch (current_cpu_type()) { 2364 case CPU_R2000: 2365 case CPU_R3000: 2366 case CPU_R3000A: 2367 case CPU_R3081E: 2368 case CPU_TX3912: 2369 case CPU_TX3922: 2370 case CPU_TX3927: 2371#ifndef CONFIG_MIPS_PGD_C0_CONTEXT 2372 if (cpu_has_local_ebase) 2373 build_r3000_tlb_refill_handler(); 2374 if (!run_once) { 2375 if (!cpu_has_local_ebase) 2376 build_r3000_tlb_refill_handler(); 2377 build_setup_pgd(); 2378 build_r3000_tlb_load_handler(); 2379 build_r3000_tlb_store_handler(); 2380 build_r3000_tlb_modify_handler(); 2381 flush_tlb_handlers(); 2382 run_once++; 2383 } 2384#else 2385 panic("No R3000 TLB refill handler"); 2386#endif 2387 break; 2388 2389 case CPU_R6000: 2390 case CPU_R6000A: 2391 panic("No R6000 TLB refill handler yet"); 2392 break; 2393 2394 case CPU_R8000: 2395 panic("No R8000 TLB refill handler yet"); 2396 break; 2397 2398 default: 2399 if (!run_once) { 2400 scratch_reg = allocate_kscratch(); 2401 build_setup_pgd(); 2402 build_r4000_tlb_load_handler(); 2403 build_r4000_tlb_store_handler(); 2404 build_r4000_tlb_modify_handler(); 2405 if (!cpu_has_local_ebase) 2406 build_r4000_tlb_refill_handler(); 2407 flush_tlb_handlers(); 2408 run_once++; 2409 } 2410 if (cpu_has_local_ebase) 2411 build_r4000_tlb_refill_handler(); 2412 if (cpu_has_xpa) 2413 config_xpa_params(); 2414 if (cpu_has_htw) 2415 config_htw_params(); 2416 } 2417} 2418